Michal Simek | 6d5af1a | 2009-03-27 14:25:20 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> |
| 3 | * Copyright (C) 2007-2009 PetaLogix |
| 4 | * Copyright (C) 2006 Atmark Techno, Inc. |
| 5 | * |
Michal Simek | 5846cc6 | 2009-05-26 16:30:09 +0200 | [diff] [blame] | 6 | * MMU code derived from arch/ppc/kernel/head_4xx.S: |
| 7 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> |
| 8 | * Initial PowerPC version. |
| 9 | * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> |
| 10 | * Rewritten for PReP |
| 11 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> |
| 12 | * Low-level exception handers, MMU support, and rewrite. |
| 13 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> |
| 14 | * PowerPC 8xx modifications. |
| 15 | * Copyright (c) 1998-1999 TiVo, Inc. |
| 16 | * PowerPC 403GCX modifications. |
| 17 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> |
| 18 | * PowerPC 403GCX/405GP modifications. |
| 19 | * Copyright 2000 MontaVista Software Inc. |
| 20 | * PPC405 modifications |
| 21 | * PowerPC 403GCX/405GP modifications. |
| 22 | * Author: MontaVista Software, Inc. |
| 23 | * frank_rowand@mvista.com or source@mvista.com |
| 24 | * debbie_chu@mvista.com |
| 25 | * |
Michal Simek | 6d5af1a | 2009-03-27 14:25:20 +0100 | [diff] [blame] | 26 | * This file is subject to the terms and conditions of the GNU General Public |
| 27 | * License. See the file "COPYING" in the main directory of this archive |
| 28 | * for more details. |
| 29 | */ |
| 30 | |
| 31 | #include <linux/linkage.h> |
| 32 | #include <asm/thread_info.h> |
| 33 | #include <asm/page.h> |
Grant Likely | d8678b5 | 2009-10-15 10:57:53 -0600 | [diff] [blame] | 34 | #include <linux/of_fdt.h> /* for OF_DT_HEADER */ |
Michal Simek | 6d5af1a | 2009-03-27 14:25:20 +0100 | [diff] [blame] | 35 | |
Michal Simek | 5846cc6 | 2009-05-26 16:30:09 +0200 | [diff] [blame] | 36 | #ifdef CONFIG_MMU |
| 37 | #include <asm/setup.h> /* COMMAND_LINE_SIZE */ |
| 38 | #include <asm/mmu.h> |
| 39 | #include <asm/processor.h> |
| 40 | |
| 41 | .data |
| 42 | .global empty_zero_page |
| 43 | .align 12 |
| 44 | empty_zero_page: |
| 45 | .space 4096 |
| 46 | .global swapper_pg_dir |
| 47 | swapper_pg_dir: |
| 48 | .space 4096 |
| 49 | |
| 50 | #endif /* CONFIG_MMU */ |
| 51 | |
Michal Simek | 6d5af1a | 2009-03-27 14:25:20 +0100 | [diff] [blame] | 52 | .text |
| 53 | ENTRY(_start) |
Michal Simek | ee68f174 | 2010-03-15 08:48:27 +0100 | [diff] [blame] | 54 | #if CONFIG_KERNEL_BASE_ADDR == 0 |
| 55 | brai TOPHYS(real_start) |
| 56 | .org 0x100 |
| 57 | real_start: |
| 58 | #endif |
| 59 | |
Michal Simek | 6d5af1a | 2009-03-27 14:25:20 +0100 | [diff] [blame] | 60 | mfs r1, rmsr |
| 61 | andi r1, r1, ~2 |
| 62 | mts rmsr, r1 |
Michal Simek | 2622434 | 2009-07-30 14:31:23 +0200 | [diff] [blame] | 63 | /* |
| 64 | * Here is checking mechanism which check if Microblaze has msr instructions |
| 65 | * We load msr and compare it with previous r1 value - if is the same, |
| 66 | * msr instructions works if not - cpu don't have them. |
| 67 | */ |
Michal Simek | 9002062 | 2009-08-31 16:24:56 +0200 | [diff] [blame] | 68 | /* r8=0 - I have msr instr, 1 - I don't have them */ |
| 69 | rsubi r0, r0, 1 /* set the carry bit */ |
| 70 | msrclr r0, 0x4 /* try to clear it */ |
| 71 | /* read the carry bit, r8 will be '0' if msrclr exists */ |
| 72 | addik r8, r0, 0 |
Michal Simek | 2622434 | 2009-07-30 14:31:23 +0200 | [diff] [blame] | 73 | |
John Williams | 909964e | 2009-06-22 14:02:09 +1000 | [diff] [blame] | 74 | /* r7 may point to an FDT, or there may be one linked in. |
| 75 | if it's in r7, we've got to save it away ASAP. |
| 76 | We ensure r7 points to a valid FDT, just in case the bootloader |
| 77 | is broken or non-existent */ |
| 78 | beqi r7, no_fdt_arg /* NULL pointer? don't copy */ |
| 79 | lw r11, r0, r7 /* Does r7 point to a */ |
| 80 | rsubi r11, r11, OF_DT_HEADER /* valid FDT? */ |
Michal Simek | ea3fd14 | 2009-06-22 12:31:55 +0200 | [diff] [blame] | 81 | beqi r11, _prepare_copy_fdt |
| 82 | or r7, r0, r0 /* clear R7 when not valid DTB */ |
John Williams | 909964e | 2009-06-22 14:02:09 +1000 | [diff] [blame] | 83 | bnei r11, no_fdt_arg /* No - get out of here */ |
Michal Simek | ea3fd14 | 2009-06-22 12:31:55 +0200 | [diff] [blame] | 84 | _prepare_copy_fdt: |
Michal Simek | 6d5af1a | 2009-03-27 14:25:20 +0100 | [diff] [blame] | 85 | or r11, r0, r0 /* incremment */ |
John Williams | 909964e | 2009-06-22 14:02:09 +1000 | [diff] [blame] | 86 | ori r4, r0, TOPHYS(_fdt_start) |
Michal Simek | 6d5af1a | 2009-03-27 14:25:20 +0100 | [diff] [blame] | 87 | ori r3, r0, (0x4000 - 4) |
| 88 | _copy_fdt: |
| 89 | lw r12, r7, r11 /* r12 = r7 + r11 */ |
| 90 | sw r12, r4, r11 /* addr[r4 + r11] = r12 */ |
| 91 | addik r11, r11, 4 /* increment counting */ |
| 92 | bgtid r3, _copy_fdt /* loop for all entries */ |
| 93 | addik r3, r3, -4 /* descrement loop */ |
| 94 | no_fdt_arg: |
| 95 | |
Michal Simek | 5846cc6 | 2009-05-26 16:30:09 +0200 | [diff] [blame] | 96 | #ifdef CONFIG_MMU |
| 97 | |
| 98 | #ifndef CONFIG_CMDLINE_BOOL |
| 99 | /* |
| 100 | * handling command line |
| 101 | * copy command line to __init_end. There is space for storing command line. |
| 102 | */ |
| 103 | or r6, r0, r0 /* incremment */ |
| 104 | ori r4, r0, __init_end /* load address of command line */ |
| 105 | tophys(r4,r4) /* convert to phys address */ |
| 106 | ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */ |
| 107 | _copy_command_line: |
Michal Simek | 3f21893 | 2010-03-24 11:06:23 +0100 | [diff] [blame^] | 108 | lbu r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */ |
| 109 | sb r2, r4, r6 /* addr[r4+r6]= r2*/ |
Michal Simek | 5846cc6 | 2009-05-26 16:30:09 +0200 | [diff] [blame] | 110 | addik r6, r6, 1 /* increment counting */ |
| 111 | bgtid r3, _copy_command_line /* loop for all entries */ |
| 112 | addik r3, r3, -1 /* descrement loop */ |
| 113 | addik r5, r4, 0 /* add new space for command line */ |
| 114 | tovirt(r5,r5) |
| 115 | #endif /* CONFIG_CMDLINE_BOOL */ |
| 116 | |
| 117 | #ifdef NOT_COMPILE |
| 118 | /* save bram context */ |
| 119 | or r6, r0, r0 /* incremment */ |
| 120 | ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */ |
| 121 | ori r3, r0, (LMB_SIZE - 4) |
| 122 | _copy_bram: |
| 123 | lw r7, r0, r6 /* r7 = r0 + r6 */ |
| 124 | sw r7, r4, r6 /* addr[r4 + r6] = r7*/ |
| 125 | addik r6, r6, 4 /* increment counting */ |
| 126 | bgtid r3, _copy_bram /* loop for all entries */ |
| 127 | addik r3, r3, -4 /* descrement loop */ |
| 128 | #endif |
| 129 | /* We have to turn on the MMU right away. */ |
| 130 | |
| 131 | /* |
| 132 | * Set up the initial MMU state so we can do the first level of |
| 133 | * kernel initialization. This maps the first 16 MBytes of memory 1:1 |
| 134 | * virtual to physical. |
| 135 | */ |
| 136 | nop |
Michal Simek | 0691c97 | 2010-03-24 10:09:17 +0100 | [diff] [blame] | 137 | addik r3, r0, MICROBLAZE_TLB_SIZE -1 /* Invalidate all TLB entries */ |
Michal Simek | 5846cc6 | 2009-05-26 16:30:09 +0200 | [diff] [blame] | 138 | _invalidate: |
| 139 | mts rtlbx, r3 |
| 140 | mts rtlbhi, r0 /* flush: ensure V is clear */ |
| 141 | bgtid r3, _invalidate /* loop for all entries */ |
| 142 | addik r3, r3, -1 |
| 143 | /* sync */ |
| 144 | |
Michal Simek | 137d079 | 2010-02-04 11:42:24 +0100 | [diff] [blame] | 145 | /* Setup the kernel PID */ |
| 146 | mts rpid,r0 /* Load the kernel PID */ |
| 147 | nop |
| 148 | bri 4 |
| 149 | |
Michal Simek | 5846cc6 | 2009-05-26 16:30:09 +0200 | [diff] [blame] | 150 | /* |
| 151 | * We should still be executing code at physical address area |
| 152 | * RAM_BASEADDR at this point. However, kernel code is at |
| 153 | * a virtual address. So, set up a TLB mapping to cover this once |
| 154 | * translation is enabled. |
| 155 | */ |
| 156 | |
| 157 | addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */ |
| 158 | tophys(r4,r3) /* Load the kernel physical address */ |
| 159 | |
Michal Simek | 5846cc6 | 2009-05-26 16:30:09 +0200 | [diff] [blame] | 160 | /* |
| 161 | * Configure and load two entries into TLB slots 0 and 1. |
| 162 | * In case we are pinning TLBs, these are reserved in by the |
| 163 | * other TLB functions. If not reserving, then it doesn't |
| 164 | * matter where they are loaded. |
| 165 | */ |
| 166 | andi r4,r4,0xfffffc00 /* Mask off the real page number */ |
| 167 | ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ |
| 168 | |
| 169 | andi r3,r3,0xfffffc00 /* Mask off the effective page number */ |
| 170 | ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) |
| 171 | |
| 172 | mts rtlbx,r0 /* TLB slow 0 */ |
| 173 | |
| 174 | mts rtlblo,r4 /* Load the data portion of the entry */ |
| 175 | mts rtlbhi,r3 /* Load the tag portion of the entry */ |
| 176 | |
| 177 | addik r4, r4, 0x01000000 /* Map next 16 M entries */ |
| 178 | addik r3, r3, 0x01000000 |
| 179 | |
| 180 | ori r6,r0,1 /* TLB slot 1 */ |
| 181 | mts rtlbx,r6 |
| 182 | |
| 183 | mts rtlblo,r4 /* Load the data portion of the entry */ |
| 184 | mts rtlbhi,r3 /* Load the tag portion of the entry */ |
| 185 | |
| 186 | /* |
| 187 | * Load a TLB entry for LMB, since we need access to |
| 188 | * the exception vectors, using a 4k real==virtual mapping. |
| 189 | */ |
| 190 | ori r6,r0,3 /* TLB slot 3 */ |
| 191 | mts rtlbx,r6 |
| 192 | |
| 193 | ori r4,r0,(TLB_WR | TLB_EX) |
| 194 | ori r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) |
| 195 | |
| 196 | mts rtlblo,r4 /* Load the data portion of the entry */ |
| 197 | mts rtlbhi,r3 /* Load the tag portion of the entry */ |
| 198 | |
| 199 | /* |
| 200 | * We now have the lower 16 Meg of RAM mapped into TLB entries, and the |
| 201 | * caches ready to work. |
| 202 | */ |
| 203 | turn_on_mmu: |
| 204 | ori r15,r0,start_here |
| 205 | ori r4,r0,MSR_KERNEL_VMS |
| 206 | mts rmsr,r4 |
| 207 | nop |
| 208 | rted r15,0 /* enables MMU */ |
| 209 | nop |
| 210 | |
| 211 | start_here: |
| 212 | #endif /* CONFIG_MMU */ |
| 213 | |
Michal Simek | 6d5af1a | 2009-03-27 14:25:20 +0100 | [diff] [blame] | 214 | /* Initialize small data anchors */ |
| 215 | la r13, r0, _KERNEL_SDA_BASE_ |
| 216 | la r2, r0, _KERNEL_SDA2_BASE_ |
| 217 | |
| 218 | /* Initialize stack pointer */ |
| 219 | la r1, r0, init_thread_union + THREAD_SIZE - 4 |
| 220 | |
| 221 | /* Initialize r31 with current task address */ |
| 222 | la r31, r0, init_task |
| 223 | |
| 224 | /* |
| 225 | * Call platform dependent initialize function. |
| 226 | * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for |
| 227 | * the function. |
| 228 | */ |
Michal Simek | 2622434 | 2009-07-30 14:31:23 +0200 | [diff] [blame] | 229 | la r9, r0, machine_early_init |
| 230 | brald r15, r9 |
Michal Simek | 6d5af1a | 2009-03-27 14:25:20 +0100 | [diff] [blame] | 231 | nop |
| 232 | |
Michal Simek | 5846cc6 | 2009-05-26 16:30:09 +0200 | [diff] [blame] | 233 | #ifndef CONFIG_MMU |
Michal Simek | 6d5af1a | 2009-03-27 14:25:20 +0100 | [diff] [blame] | 234 | la r15, r0, machine_halt |
| 235 | braid start_kernel |
| 236 | nop |
Michal Simek | 5846cc6 | 2009-05-26 16:30:09 +0200 | [diff] [blame] | 237 | #else |
| 238 | /* |
| 239 | * Initialize the MMU. |
| 240 | */ |
| 241 | bralid r15, mmu_init |
| 242 | nop |
| 243 | |
| 244 | /* Go back to running unmapped so we can load up new values |
| 245 | * and change to using our exception vectors. |
| 246 | * On the MicroBlaze, all we invalidate the used TLB entries to clear |
| 247 | * the old 16M byte TLB mappings. |
| 248 | */ |
| 249 | ori r15,r0,TOPHYS(kernel_load_context) |
| 250 | ori r4,r0,MSR_KERNEL |
| 251 | mts rmsr,r4 |
| 252 | nop |
| 253 | bri 4 |
| 254 | rted r15,0 |
| 255 | nop |
| 256 | |
| 257 | /* Load up the kernel context */ |
| 258 | kernel_load_context: |
| 259 | # Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away. |
| 260 | ori r5,r0,3 |
| 261 | mts rtlbx,r5 |
| 262 | nop |
| 263 | mts rtlbhi,r0 |
| 264 | nop |
| 265 | addi r15, r0, machine_halt |
| 266 | ori r17, r0, start_kernel |
| 267 | ori r4, r0, MSR_KERNEL_VMS |
| 268 | mts rmsr, r4 |
| 269 | nop |
| 270 | rted r17, 0 /* enable MMU and jump to start_kernel */ |
| 271 | nop |
| 272 | #endif /* CONFIG_MMU */ |