Vivek Gautam | dc2377d | 2013-03-14 15:59:10 +0530 | [diff] [blame] | 1 | /* linux/drivers/usb/phy/phy-samsung-usb2.c |
| 2 | * |
| 3 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com |
| 5 | * |
| 6 | * Author: Praveen Paneri <p.paneri@samsung.com> |
| 7 | * |
| 8 | * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and |
| 9 | * OHCI-EXYNOS controllers. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/clk.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/device.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/io.h> |
| 28 | #include <linux/of.h> |
| 29 | #include <linux/usb/otg.h> |
| 30 | #include <linux/usb/samsung_usb_phy.h> |
| 31 | #include <linux/platform_data/samsung-usbphy.h> |
| 32 | |
| 33 | #include "phy-samsung-usb.h" |
| 34 | |
| 35 | static int samsung_usbphy_set_host(struct usb_otg *otg, struct usb_bus *host) |
| 36 | { |
| 37 | if (!otg) |
| 38 | return -ENODEV; |
| 39 | |
| 40 | if (!otg->host) |
| 41 | otg->host = host; |
| 42 | |
| 43 | return 0; |
| 44 | } |
| 45 | |
Felipe Balbi | b64a159 | 2013-03-19 10:14:35 +0200 | [diff] [blame] | 46 | static bool exynos5_phyhost_is_on(void __iomem *regs) |
Vivek Gautam | dc2377d | 2013-03-14 15:59:10 +0530 | [diff] [blame] | 47 | { |
| 48 | u32 reg; |
| 49 | |
| 50 | reg = readl(regs + EXYNOS5_PHY_HOST_CTRL0); |
| 51 | |
| 52 | return !(reg & HOST_CTRL0_SIDDQ); |
| 53 | } |
| 54 | |
| 55 | static void samsung_exynos5_usb2phy_enable(struct samsung_usbphy *sphy) |
| 56 | { |
| 57 | void __iomem *regs = sphy->regs; |
| 58 | u32 phyclk = sphy->ref_clk_freq; |
| 59 | u32 phyhost; |
| 60 | u32 phyotg; |
| 61 | u32 phyhsic; |
| 62 | u32 ehcictrl; |
| 63 | u32 ohcictrl; |
| 64 | |
| 65 | /* |
| 66 | * phy_usage helps in keeping usage count for phy |
| 67 | * so that the first consumer enabling the phy is also |
| 68 | * the last consumer to disable it. |
| 69 | */ |
| 70 | |
| 71 | atomic_inc(&sphy->phy_usage); |
| 72 | |
| 73 | if (exynos5_phyhost_is_on(regs)) { |
| 74 | dev_info(sphy->dev, "Already power on PHY\n"); |
| 75 | return; |
| 76 | } |
| 77 | |
| 78 | /* Host configuration */ |
| 79 | phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0); |
| 80 | |
| 81 | /* phy reference clock configuration */ |
| 82 | phyhost &= ~HOST_CTRL0_FSEL_MASK; |
| 83 | phyhost |= HOST_CTRL0_FSEL(phyclk); |
| 84 | |
| 85 | /* host phy reset */ |
| 86 | phyhost &= ~(HOST_CTRL0_PHYSWRST | |
| 87 | HOST_CTRL0_PHYSWRSTALL | |
| 88 | HOST_CTRL0_SIDDQ | |
| 89 | /* Enable normal mode of operation */ |
| 90 | HOST_CTRL0_FORCESUSPEND | |
| 91 | HOST_CTRL0_FORCESLEEP); |
| 92 | |
| 93 | /* Link reset */ |
| 94 | phyhost |= (HOST_CTRL0_LINKSWRST | |
| 95 | HOST_CTRL0_UTMISWRST | |
| 96 | /* COMMON Block configuration during suspend */ |
| 97 | HOST_CTRL0_COMMONON_N); |
| 98 | writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0); |
| 99 | udelay(10); |
| 100 | phyhost &= ~(HOST_CTRL0_LINKSWRST | |
| 101 | HOST_CTRL0_UTMISWRST); |
| 102 | writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0); |
| 103 | |
| 104 | /* OTG configuration */ |
| 105 | phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS); |
| 106 | |
| 107 | /* phy reference clock configuration */ |
| 108 | phyotg &= ~OTG_SYS_FSEL_MASK; |
| 109 | phyotg |= OTG_SYS_FSEL(phyclk); |
| 110 | |
| 111 | /* Enable normal mode of operation */ |
| 112 | phyotg &= ~(OTG_SYS_FORCESUSPEND | |
| 113 | OTG_SYS_SIDDQ_UOTG | |
| 114 | OTG_SYS_FORCESLEEP | |
| 115 | OTG_SYS_REFCLKSEL_MASK | |
| 116 | /* COMMON Block configuration during suspend */ |
| 117 | OTG_SYS_COMMON_ON); |
| 118 | |
| 119 | /* OTG phy & link reset */ |
| 120 | phyotg |= (OTG_SYS_PHY0_SWRST | |
| 121 | OTG_SYS_LINKSWRST_UOTG | |
| 122 | OTG_SYS_PHYLINK_SWRESET | |
| 123 | OTG_SYS_OTGDISABLE | |
| 124 | /* Set phy refclk */ |
| 125 | OTG_SYS_REFCLKSEL_CLKCORE); |
| 126 | |
| 127 | writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS); |
| 128 | udelay(10); |
| 129 | phyotg &= ~(OTG_SYS_PHY0_SWRST | |
| 130 | OTG_SYS_LINKSWRST_UOTG | |
| 131 | OTG_SYS_PHYLINK_SWRESET); |
| 132 | writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS); |
| 133 | |
| 134 | /* HSIC phy configuration */ |
| 135 | phyhsic = (HSIC_CTRL_REFCLKDIV_12 | |
| 136 | HSIC_CTRL_REFCLKSEL | |
| 137 | HSIC_CTRL_PHYSWRST); |
| 138 | writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1); |
| 139 | writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2); |
| 140 | udelay(10); |
| 141 | phyhsic &= ~HSIC_CTRL_PHYSWRST; |
| 142 | writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1); |
| 143 | writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2); |
| 144 | |
| 145 | udelay(80); |
| 146 | |
| 147 | /* enable EHCI DMA burst */ |
| 148 | ehcictrl = readl(regs + EXYNOS5_PHY_HOST_EHCICTRL); |
| 149 | ehcictrl |= (HOST_EHCICTRL_ENAINCRXALIGN | |
| 150 | HOST_EHCICTRL_ENAINCR4 | |
| 151 | HOST_EHCICTRL_ENAINCR8 | |
| 152 | HOST_EHCICTRL_ENAINCR16); |
| 153 | writel(ehcictrl, regs + EXYNOS5_PHY_HOST_EHCICTRL); |
| 154 | |
| 155 | /* set ohci_suspend_on_n */ |
| 156 | ohcictrl = readl(regs + EXYNOS5_PHY_HOST_OHCICTRL); |
| 157 | ohcictrl |= HOST_OHCICTRL_SUSPLGCY; |
| 158 | writel(ohcictrl, regs + EXYNOS5_PHY_HOST_OHCICTRL); |
| 159 | } |
| 160 | |
| 161 | static void samsung_usb2phy_enable(struct samsung_usbphy *sphy) |
| 162 | { |
| 163 | void __iomem *regs = sphy->regs; |
| 164 | u32 phypwr; |
| 165 | u32 phyclk; |
| 166 | u32 rstcon; |
| 167 | |
| 168 | /* set clock frequency for PLL */ |
| 169 | phyclk = sphy->ref_clk_freq; |
| 170 | phypwr = readl(regs + SAMSUNG_PHYPWR); |
| 171 | rstcon = readl(regs + SAMSUNG_RSTCON); |
| 172 | |
| 173 | switch (sphy->drv_data->cpu_type) { |
| 174 | case TYPE_S3C64XX: |
| 175 | phyclk &= ~PHYCLK_COMMON_ON_N; |
| 176 | phypwr &= ~PHYPWR_NORMAL_MASK; |
| 177 | rstcon |= RSTCON_SWRST; |
| 178 | break; |
| 179 | case TYPE_EXYNOS4210: |
| 180 | phypwr &= ~PHYPWR_NORMAL_MASK_PHY0; |
| 181 | rstcon |= RSTCON_SWRST; |
| 182 | default: |
| 183 | break; |
| 184 | } |
| 185 | |
| 186 | writel(phyclk, regs + SAMSUNG_PHYCLK); |
| 187 | /* Configure PHY0 for normal operation*/ |
| 188 | writel(phypwr, regs + SAMSUNG_PHYPWR); |
| 189 | /* reset all ports of PHY and Link */ |
| 190 | writel(rstcon, regs + SAMSUNG_RSTCON); |
| 191 | udelay(10); |
| 192 | rstcon &= ~RSTCON_SWRST; |
| 193 | writel(rstcon, regs + SAMSUNG_RSTCON); |
| 194 | } |
| 195 | |
| 196 | static void samsung_exynos5_usb2phy_disable(struct samsung_usbphy *sphy) |
| 197 | { |
| 198 | void __iomem *regs = sphy->regs; |
| 199 | u32 phyhost; |
| 200 | u32 phyotg; |
| 201 | u32 phyhsic; |
| 202 | |
| 203 | if (atomic_dec_return(&sphy->phy_usage) > 0) { |
| 204 | dev_info(sphy->dev, "still being used\n"); |
| 205 | return; |
| 206 | } |
| 207 | |
| 208 | phyhsic = (HSIC_CTRL_REFCLKDIV_12 | |
| 209 | HSIC_CTRL_REFCLKSEL | |
| 210 | HSIC_CTRL_SIDDQ | |
| 211 | HSIC_CTRL_FORCESLEEP | |
| 212 | HSIC_CTRL_FORCESUSPEND); |
| 213 | writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL1); |
| 214 | writel(phyhsic, regs + EXYNOS5_PHY_HSIC_CTRL2); |
| 215 | |
| 216 | phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0); |
| 217 | phyhost |= (HOST_CTRL0_SIDDQ | |
| 218 | HOST_CTRL0_FORCESUSPEND | |
| 219 | HOST_CTRL0_FORCESLEEP | |
| 220 | HOST_CTRL0_PHYSWRST | |
| 221 | HOST_CTRL0_PHYSWRSTALL); |
| 222 | writel(phyhost, regs + EXYNOS5_PHY_HOST_CTRL0); |
| 223 | |
| 224 | phyotg = readl(regs + EXYNOS5_PHY_OTG_SYS); |
| 225 | phyotg |= (OTG_SYS_FORCESUSPEND | |
| 226 | OTG_SYS_SIDDQ_UOTG | |
| 227 | OTG_SYS_FORCESLEEP); |
| 228 | writel(phyotg, regs + EXYNOS5_PHY_OTG_SYS); |
| 229 | } |
| 230 | |
| 231 | static void samsung_usb2phy_disable(struct samsung_usbphy *sphy) |
| 232 | { |
| 233 | void __iomem *regs = sphy->regs; |
| 234 | u32 phypwr; |
| 235 | |
| 236 | phypwr = readl(regs + SAMSUNG_PHYPWR); |
| 237 | |
| 238 | switch (sphy->drv_data->cpu_type) { |
| 239 | case TYPE_S3C64XX: |
| 240 | phypwr |= PHYPWR_NORMAL_MASK; |
| 241 | break; |
| 242 | case TYPE_EXYNOS4210: |
| 243 | phypwr |= PHYPWR_NORMAL_MASK_PHY0; |
| 244 | default: |
| 245 | break; |
| 246 | } |
| 247 | |
| 248 | /* Disable analog and otg block power */ |
| 249 | writel(phypwr, regs + SAMSUNG_PHYPWR); |
| 250 | } |
| 251 | |
| 252 | /* |
| 253 | * The function passed to the usb driver for phy initialization |
| 254 | */ |
| 255 | static int samsung_usb2phy_init(struct usb_phy *phy) |
| 256 | { |
| 257 | struct samsung_usbphy *sphy; |
| 258 | struct usb_bus *host = NULL; |
| 259 | unsigned long flags; |
| 260 | int ret = 0; |
| 261 | |
| 262 | sphy = phy_to_sphy(phy); |
| 263 | |
| 264 | host = phy->otg->host; |
| 265 | |
| 266 | /* Enable the phy clock */ |
| 267 | ret = clk_prepare_enable(sphy->clk); |
| 268 | if (ret) { |
| 269 | dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__); |
| 270 | return ret; |
| 271 | } |
| 272 | |
| 273 | spin_lock_irqsave(&sphy->lock, flags); |
| 274 | |
| 275 | if (host) { |
| 276 | /* setting default phy-type for USB 2.0 */ |
| 277 | if (!strstr(dev_name(host->controller), "ehci") || |
| 278 | !strstr(dev_name(host->controller), "ohci")) |
| 279 | samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_HOST); |
| 280 | } else { |
| 281 | samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE); |
| 282 | } |
| 283 | |
| 284 | /* Disable phy isolation */ |
| 285 | if (sphy->plat && sphy->plat->pmu_isolation) |
| 286 | sphy->plat->pmu_isolation(false); |
Tomasz Figa | 3f33907 | 2013-05-16 11:57:09 +0200 | [diff] [blame^] | 287 | else if (sphy->drv_data->set_isolation) |
| 288 | sphy->drv_data->set_isolation(sphy, false); |
Vivek Gautam | dc2377d | 2013-03-14 15:59:10 +0530 | [diff] [blame] | 289 | |
| 290 | /* Selecting Host/OTG mode; After reset USB2.0PHY_CFG: HOST */ |
| 291 | samsung_usbphy_cfg_sel(sphy); |
| 292 | |
| 293 | /* Initialize usb phy registers */ |
| 294 | if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250) |
| 295 | samsung_exynos5_usb2phy_enable(sphy); |
| 296 | else |
| 297 | samsung_usb2phy_enable(sphy); |
| 298 | |
| 299 | spin_unlock_irqrestore(&sphy->lock, flags); |
| 300 | |
| 301 | /* Disable the phy clock */ |
| 302 | clk_disable_unprepare(sphy->clk); |
| 303 | |
| 304 | return ret; |
| 305 | } |
| 306 | |
| 307 | /* |
| 308 | * The function passed to the usb driver for phy shutdown |
| 309 | */ |
| 310 | static void samsung_usb2phy_shutdown(struct usb_phy *phy) |
| 311 | { |
| 312 | struct samsung_usbphy *sphy; |
| 313 | struct usb_bus *host = NULL; |
| 314 | unsigned long flags; |
| 315 | |
| 316 | sphy = phy_to_sphy(phy); |
| 317 | |
| 318 | host = phy->otg->host; |
| 319 | |
| 320 | if (clk_prepare_enable(sphy->clk)) { |
| 321 | dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__); |
| 322 | return; |
| 323 | } |
| 324 | |
| 325 | spin_lock_irqsave(&sphy->lock, flags); |
| 326 | |
| 327 | if (host) { |
| 328 | /* setting default phy-type for USB 2.0 */ |
| 329 | if (!strstr(dev_name(host->controller), "ehci") || |
| 330 | !strstr(dev_name(host->controller), "ohci")) |
| 331 | samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_HOST); |
| 332 | } else { |
| 333 | samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE); |
| 334 | } |
| 335 | |
| 336 | /* De-initialize usb phy registers */ |
| 337 | if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250) |
| 338 | samsung_exynos5_usb2phy_disable(sphy); |
| 339 | else |
| 340 | samsung_usb2phy_disable(sphy); |
| 341 | |
| 342 | /* Enable phy isolation */ |
| 343 | if (sphy->plat && sphy->plat->pmu_isolation) |
| 344 | sphy->plat->pmu_isolation(true); |
Tomasz Figa | 3f33907 | 2013-05-16 11:57:09 +0200 | [diff] [blame^] | 345 | else if (sphy->drv_data->set_isolation) |
| 346 | sphy->drv_data->set_isolation(sphy, true); |
Vivek Gautam | dc2377d | 2013-03-14 15:59:10 +0530 | [diff] [blame] | 347 | |
| 348 | spin_unlock_irqrestore(&sphy->lock, flags); |
| 349 | |
| 350 | clk_disable_unprepare(sphy->clk); |
| 351 | } |
| 352 | |
| 353 | static int samsung_usb2phy_probe(struct platform_device *pdev) |
| 354 | { |
| 355 | struct samsung_usbphy *sphy; |
| 356 | struct usb_otg *otg; |
| 357 | struct samsung_usbphy_data *pdata = pdev->dev.platform_data; |
| 358 | const struct samsung_usbphy_drvdata *drv_data; |
| 359 | struct device *dev = &pdev->dev; |
| 360 | struct resource *phy_mem; |
| 361 | void __iomem *phy_base; |
| 362 | struct clk *clk; |
| 363 | int ret; |
| 364 | |
| 365 | phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Vivek Gautam | dc2377d | 2013-03-14 15:59:10 +0530 | [diff] [blame] | 366 | phy_base = devm_ioremap_resource(dev, phy_mem); |
| 367 | if (IS_ERR(phy_base)) |
| 368 | return PTR_ERR(phy_base); |
| 369 | |
| 370 | sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); |
| 371 | if (!sphy) |
| 372 | return -ENOMEM; |
| 373 | |
| 374 | otg = devm_kzalloc(dev, sizeof(*otg), GFP_KERNEL); |
| 375 | if (!otg) |
| 376 | return -ENOMEM; |
| 377 | |
| 378 | drv_data = samsung_usbphy_get_driver_data(pdev); |
| 379 | |
| 380 | if (drv_data->cpu_type == TYPE_EXYNOS5250) |
| 381 | clk = devm_clk_get(dev, "usbhost"); |
| 382 | else |
| 383 | clk = devm_clk_get(dev, "otg"); |
| 384 | |
| 385 | if (IS_ERR(clk)) { |
| 386 | dev_err(dev, "Failed to get otg clock\n"); |
| 387 | return PTR_ERR(clk); |
| 388 | } |
| 389 | |
| 390 | sphy->dev = dev; |
| 391 | |
| 392 | if (dev->of_node) { |
| 393 | ret = samsung_usbphy_parse_dt(sphy); |
| 394 | if (ret < 0) |
| 395 | return ret; |
| 396 | } else { |
| 397 | if (!pdata) { |
| 398 | dev_err(dev, "no platform data specified\n"); |
| 399 | return -EINVAL; |
| 400 | } |
| 401 | } |
| 402 | |
| 403 | sphy->plat = pdata; |
| 404 | sphy->regs = phy_base; |
| 405 | sphy->clk = clk; |
| 406 | sphy->drv_data = drv_data; |
| 407 | sphy->phy.dev = sphy->dev; |
| 408 | sphy->phy.label = "samsung-usb2phy"; |
| 409 | sphy->phy.init = samsung_usb2phy_init; |
| 410 | sphy->phy.shutdown = samsung_usb2phy_shutdown; |
Tomasz Figa | 0aa823a | 2013-05-16 11:57:08 +0200 | [diff] [blame] | 411 | |
| 412 | sphy->ref_clk_freq = samsung_usbphy_get_refclk_freq(sphy); |
| 413 | if (sphy->ref_clk_freq < 0) |
| 414 | return -EINVAL; |
Vivek Gautam | dc2377d | 2013-03-14 15:59:10 +0530 | [diff] [blame] | 415 | |
| 416 | sphy->phy.otg = otg; |
| 417 | sphy->phy.otg->phy = &sphy->phy; |
| 418 | sphy->phy.otg->set_host = samsung_usbphy_set_host; |
| 419 | |
| 420 | spin_lock_init(&sphy->lock); |
| 421 | |
| 422 | platform_set_drvdata(pdev, sphy); |
| 423 | |
| 424 | return usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2); |
| 425 | } |
| 426 | |
| 427 | static int samsung_usb2phy_remove(struct platform_device *pdev) |
| 428 | { |
| 429 | struct samsung_usbphy *sphy = platform_get_drvdata(pdev); |
| 430 | |
| 431 | usb_remove_phy(&sphy->phy); |
| 432 | |
| 433 | if (sphy->pmuregs) |
| 434 | iounmap(sphy->pmuregs); |
| 435 | if (sphy->sysreg) |
| 436 | iounmap(sphy->sysreg); |
| 437 | |
| 438 | return 0; |
| 439 | } |
| 440 | |
| 441 | static const struct samsung_usbphy_drvdata usb2phy_s3c64xx = { |
| 442 | .cpu_type = TYPE_S3C64XX, |
| 443 | .devphy_en_mask = S3C64XX_USBPHY_ENABLE, |
Tomasz Figa | 0aa823a | 2013-05-16 11:57:08 +0200 | [diff] [blame] | 444 | .rate_to_clksel = samsung_usbphy_rate_to_clksel_64xx, |
Tomasz Figa | 3f33907 | 2013-05-16 11:57:09 +0200 | [diff] [blame^] | 445 | .set_isolation = NULL, /* TODO */ |
Vivek Gautam | dc2377d | 2013-03-14 15:59:10 +0530 | [diff] [blame] | 446 | }; |
| 447 | |
| 448 | static const struct samsung_usbphy_drvdata usb2phy_exynos4 = { |
| 449 | .cpu_type = TYPE_EXYNOS4210, |
| 450 | .devphy_en_mask = EXYNOS_USBPHY_ENABLE, |
| 451 | .hostphy_en_mask = EXYNOS_USBPHY_ENABLE, |
Tomasz Figa | 0aa823a | 2013-05-16 11:57:08 +0200 | [diff] [blame] | 452 | .rate_to_clksel = samsung_usbphy_rate_to_clksel_64xx, |
Tomasz Figa | 3f33907 | 2013-05-16 11:57:09 +0200 | [diff] [blame^] | 453 | .set_isolation = samsung_usbphy_set_isolation_4210, |
Vivek Gautam | dc2377d | 2013-03-14 15:59:10 +0530 | [diff] [blame] | 454 | }; |
| 455 | |
| 456 | static struct samsung_usbphy_drvdata usb2phy_exynos5 = { |
| 457 | .cpu_type = TYPE_EXYNOS5250, |
| 458 | .hostphy_en_mask = EXYNOS_USBPHY_ENABLE, |
| 459 | .hostphy_reg_offset = EXYNOS_USBHOST_PHY_CTRL_OFFSET, |
Tomasz Figa | 0aa823a | 2013-05-16 11:57:08 +0200 | [diff] [blame] | 460 | .rate_to_clksel = samsung_usbphy_rate_to_clksel_4x12, |
Tomasz Figa | 3f33907 | 2013-05-16 11:57:09 +0200 | [diff] [blame^] | 461 | .set_isolation = samsung_usbphy_set_isolation_4210, |
Vivek Gautam | dc2377d | 2013-03-14 15:59:10 +0530 | [diff] [blame] | 462 | }; |
| 463 | |
| 464 | #ifdef CONFIG_OF |
| 465 | static const struct of_device_id samsung_usbphy_dt_match[] = { |
| 466 | { |
| 467 | .compatible = "samsung,s3c64xx-usb2phy", |
| 468 | .data = &usb2phy_s3c64xx, |
| 469 | }, { |
| 470 | .compatible = "samsung,exynos4210-usb2phy", |
| 471 | .data = &usb2phy_exynos4, |
| 472 | }, { |
| 473 | .compatible = "samsung,exynos5250-usb2phy", |
| 474 | .data = &usb2phy_exynos5 |
| 475 | }, |
| 476 | {}, |
| 477 | }; |
| 478 | MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match); |
| 479 | #endif |
| 480 | |
| 481 | static struct platform_device_id samsung_usbphy_driver_ids[] = { |
| 482 | { |
| 483 | .name = "s3c64xx-usb2phy", |
| 484 | .driver_data = (unsigned long)&usb2phy_s3c64xx, |
| 485 | }, { |
| 486 | .name = "exynos4210-usb2phy", |
| 487 | .driver_data = (unsigned long)&usb2phy_exynos4, |
| 488 | }, { |
| 489 | .name = "exynos5250-usb2phy", |
| 490 | .driver_data = (unsigned long)&usb2phy_exynos5, |
| 491 | }, |
| 492 | {}, |
| 493 | }; |
| 494 | |
| 495 | MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids); |
| 496 | |
| 497 | static struct platform_driver samsung_usb2phy_driver = { |
| 498 | .probe = samsung_usb2phy_probe, |
| 499 | .remove = samsung_usb2phy_remove, |
| 500 | .id_table = samsung_usbphy_driver_ids, |
| 501 | .driver = { |
| 502 | .name = "samsung-usb2phy", |
| 503 | .owner = THIS_MODULE, |
| 504 | .of_match_table = of_match_ptr(samsung_usbphy_dt_match), |
| 505 | }, |
| 506 | }; |
| 507 | |
| 508 | module_platform_driver(samsung_usb2phy_driver); |
| 509 | |
| 510 | MODULE_DESCRIPTION("Samsung USB 2.0 phy controller"); |
| 511 | MODULE_AUTHOR("Praveen Paneri <p.paneri@samsung.com>"); |
| 512 | MODULE_LICENSE("GPL"); |
| 513 | MODULE_ALIAS("platform:samsung-usb2phy"); |