blob: 96e3ee3460a566a96928eb45b332ced184902fe8 [file] [log] [blame]
Alan Cox806c35f2006-01-18 17:44:08 -08001/*
2 * AMD 76x Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.
9 * http://www.anime.net/~goemon/linux-ecc/
10 *
11 * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
12 *
13 */
14
Alan Cox806c35f2006-01-18 17:44:08 -080015#include <linux/module.h>
16#include <linux/init.h>
Alan Cox806c35f2006-01-18 17:44:08 -080017#include <linux/pci.h>
18#include <linux/pci_ids.h>
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -070019#include <linux/edac.h>
Douglas Thompson20bcb7a2007-07-19 01:49:47 -070020#include "edac_core.h"
Alan Cox806c35f2006-01-18 17:44:08 -080021
Michal Marek152ba392011-04-01 12:41:20 +020022#define AMD76X_REVISION " Ver: 2.0.2"
Doug Thompson929a40e2006-07-01 04:35:45 -070023#define EDAC_MOD_STR "amd76x_edac"
Doug Thompson37f04582006-06-30 01:56:07 -070024
Dave Peterson537fba22006-03-26 01:38:40 -080025#define amd76x_printk(level, fmt, arg...) \
Dave Petersone7ecd892006-03-26 01:38:52 -080026 edac_printk(level, "amd76x", fmt, ##arg)
Dave Peterson537fba22006-03-26 01:38:40 -080027
28#define amd76x_mc_printk(mci, level, fmt, arg...) \
Dave Petersone7ecd892006-03-26 01:38:52 -080029 edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
Dave Peterson537fba22006-03-26 01:38:40 -080030
Alan Cox806c35f2006-01-18 17:44:08 -080031#define AMD76X_NR_CSROWS 8
Alan Cox806c35f2006-01-18 17:44:08 -080032#define AMD76X_NR_DIMMS 4
33
Alan Cox806c35f2006-01-18 17:44:08 -080034/* AMD 76x register addresses - device 0 function 0 - PCI bridge */
Dave Petersone7ecd892006-03-26 01:38:52 -080035
Alan Cox806c35f2006-01-18 17:44:08 -080036#define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b)
37 *
38 * 31:16 reserved
39 * 15:14 SERR enabled: x1=ue 1x=ce
40 * 13 reserved
41 * 12 diag: disabled, enabled
42 * 11:10 mode: dis, EC, ECC, ECC+scrub
43 * 9:8 status: x1=ue 1x=ce
44 * 7:4 UE cs row
45 * 3:0 CE cs row
46 */
Dave Petersone7ecd892006-03-26 01:38:52 -080047
Alan Cox806c35f2006-01-18 17:44:08 -080048#define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b)
49 *
50 * 31:26 clock disable 5 - 0
51 * 25 SDRAM init
52 * 24 reserved
53 * 23 mode register service
54 * 22:21 suspend to RAM
55 * 20 burst refresh enable
56 * 19 refresh disable
57 * 18 reserved
58 * 17:16 cycles-per-refresh
59 * 15:8 reserved
60 * 7:0 x4 mode enable 7 - 0
61 */
Dave Petersone7ecd892006-03-26 01:38:52 -080062
Alan Cox806c35f2006-01-18 17:44:08 -080063#define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
64 *
65 * 31:23 chip-select base
66 * 22:16 reserved
67 * 15:7 chip-select mask
68 * 6:3 reserved
69 * 2:1 address mode
70 * 0 chip-select enable
71 */
72
Alan Cox806c35f2006-01-18 17:44:08 -080073struct amd76x_error_info {
74 u32 ecc_mode_status;
75};
76
Alan Cox806c35f2006-01-18 17:44:08 -080077enum amd76x_chips {
78 AMD761 = 0,
79 AMD762
80};
81
Alan Cox806c35f2006-01-18 17:44:08 -080082struct amd76x_dev_info {
83 const char *ctl_name;
84};
85
Alan Cox806c35f2006-01-18 17:44:08 -080086static const struct amd76x_dev_info amd76x_devs[] = {
Dave Petersone7ecd892006-03-26 01:38:52 -080087 [AMD761] = {
Douglas Thompson052dfb42007-07-19 01:50:13 -070088 .ctl_name = "AMD761"},
Dave Petersone7ecd892006-03-26 01:38:52 -080089 [AMD762] = {
Douglas Thompson052dfb42007-07-19 01:50:13 -070090 .ctl_name = "AMD762"},
Alan Cox806c35f2006-01-18 17:44:08 -080091};
92
Dave Jiang456a2f92007-07-19 01:50:10 -070093static struct edac_pci_ctl_info *amd76x_pci;
94
Alan Cox806c35f2006-01-18 17:44:08 -080095/**
96 * amd76x_get_error_info - fetch error information
97 * @mci: Memory controller
98 * @info: Info to fill in
99 *
100 * Fetch and store the AMD76x ECC status. Clear pending status
101 * on the chip so that further errors will be reported
102 */
Dave Petersone7ecd892006-03-26 01:38:52 -0800103static void amd76x_get_error_info(struct mem_ctl_info *mci,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700104 struct amd76x_error_info *info)
Alan Cox806c35f2006-01-18 17:44:08 -0800105{
Doug Thompson37f04582006-06-30 01:56:07 -0700106 struct pci_dev *pdev;
107
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -0300108 pdev = to_pci_dev(mci->pdev);
Doug Thompson37f04582006-06-30 01:56:07 -0700109 pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700110 &info->ecc_mode_status);
Alan Cox806c35f2006-01-18 17:44:08 -0800111
112 if (info->ecc_mode_status & BIT(8))
Doug Thompson37f04582006-06-30 01:56:07 -0700113 pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
Douglas Thompson67cb2b62007-07-19 01:50:02 -0700114 (u32) BIT(8), (u32) BIT(8));
Alan Cox806c35f2006-01-18 17:44:08 -0800115
116 if (info->ecc_mode_status & BIT(9))
Doug Thompson37f04582006-06-30 01:56:07 -0700117 pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
Douglas Thompson67cb2b62007-07-19 01:50:02 -0700118 (u32) BIT(9), (u32) BIT(9));
Alan Cox806c35f2006-01-18 17:44:08 -0800119}
120
Alan Cox806c35f2006-01-18 17:44:08 -0800121/**
122 * amd76x_process_error_info - Error check
123 * @mci: Memory controller
124 * @info: Previously fetched information from chip
125 * @handle_errors: 1 if we should do recovery
126 *
127 * Process the chip state and decide if an error has occurred.
128 * A return of 1 indicates an error. Also if handle_errors is true
129 * then attempt to handle and clean up after the error
130 */
Dave Petersone7ecd892006-03-26 01:38:52 -0800131static int amd76x_process_error_info(struct mem_ctl_info *mci,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700132 struct amd76x_error_info *info,
133 int handle_errors)
Alan Cox806c35f2006-01-18 17:44:08 -0800134{
135 int error_found;
136 u32 row;
137
138 error_found = 0;
139
140 /*
Douglas Thompson67cb2b62007-07-19 01:50:02 -0700141 * Check for an uncorrectable error
Alan Cox806c35f2006-01-18 17:44:08 -0800142 */
143 if (info->ecc_mode_status & BIT(8)) {
144 error_found = 1;
145
146 if (handle_errors) {
147 row = (info->ecc_mode_status >> 4) & 0xf;
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300148 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
Mauro Carvalho Chehabde3910eb2012-04-24 15:05:43 -0300149 mci->csrows[row]->first_page, 0, 0,
Mauro Carvalho Chehabd8c34af2012-04-16 15:05:27 -0300150 row, 0, -1,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300151 mci->ctl_name, "");
Alan Cox806c35f2006-01-18 17:44:08 -0800152 }
153 }
154
155 /*
Douglas Thompson67cb2b62007-07-19 01:50:02 -0700156 * Check for a correctable error
Alan Cox806c35f2006-01-18 17:44:08 -0800157 */
158 if (info->ecc_mode_status & BIT(9)) {
159 error_found = 1;
160
161 if (handle_errors) {
162 row = info->ecc_mode_status & 0xf;
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300163 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
Mauro Carvalho Chehabde3910eb2012-04-24 15:05:43 -0300164 mci->csrows[row]->first_page, 0, 0,
Mauro Carvalho Chehabd8c34af2012-04-16 15:05:27 -0300165 row, 0, -1,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300166 mci->ctl_name, "");
Alan Cox806c35f2006-01-18 17:44:08 -0800167 }
168 }
Dave Petersone7ecd892006-03-26 01:38:52 -0800169
Alan Cox806c35f2006-01-18 17:44:08 -0800170 return error_found;
171}
172
173/**
174 * amd76x_check - Poll the controller
175 * @mci: Memory controller
176 *
177 * Called by the poll handlers this function reads the status
178 * from the controller and checks for errors.
179 */
Alan Cox806c35f2006-01-18 17:44:08 -0800180static void amd76x_check(struct mem_ctl_info *mci)
181{
182 struct amd76x_error_info info;
Joe Perches956b9ba2012-04-29 17:08:39 -0300183 edac_dbg(3, "\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800184 amd76x_get_error_info(mci, &info);
185 amd76x_process_error_info(mci, &info, 1);
186}
187
Doug Thompson13189522006-06-30 01:56:08 -0700188static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700189 enum edac_type edac_mode)
Alan Cox806c35f2006-01-18 17:44:08 -0800190{
Doug Thompson13189522006-06-30 01:56:08 -0700191 struct csrow_info *csrow;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300192 struct dimm_info *dimm;
Doug Thompson13189522006-06-30 01:56:08 -0700193 u32 mba, mba_base, mba_mask, dms;
Alan Cox806c35f2006-01-18 17:44:08 -0800194 int index;
Alan Cox806c35f2006-01-18 17:44:08 -0800195
196 for (index = 0; index < mci->nr_csrows; index++) {
Mauro Carvalho Chehabde3910eb2012-04-24 15:05:43 -0300197 csrow = mci->csrows[index];
198 dimm = csrow->channels[0]->dimm;
Alan Cox806c35f2006-01-18 17:44:08 -0800199
200 /* find the DRAM Chip Select Base address and mask */
Doug Thompson37f04582006-06-30 01:56:07 -0700201 pci_read_config_dword(pdev,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700202 AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
Alan Cox806c35f2006-01-18 17:44:08 -0800203
204 if (!(mba & BIT(0)))
205 continue;
206
207 mba_base = mba & 0xff800000UL;
208 mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
Doug Thompson37f04582006-06-30 01:56:07 -0700209 pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
Alan Cox806c35f2006-01-18 17:44:08 -0800210 csrow->first_page = mba_base >> PAGE_SHIFT;
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300211 dimm->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
212 csrow->last_page = csrow->first_page + dimm->nr_pages - 1;
Alan Cox806c35f2006-01-18 17:44:08 -0800213 csrow->page_mask = mba_mask >> PAGE_SHIFT;
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300214 dimm->grain = dimm->nr_pages << PAGE_SHIFT;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300215 dimm->mtype = MEM_RDDR;
216 dimm->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
217 dimm->edac_mode = edac_mode;
Doug Thompson13189522006-06-30 01:56:08 -0700218 }
219}
220
221/**
222 * amd76x_probe1 - Perform set up for detected device
223 * @pdev; PCI device detected
224 * @dev_idx: Device type index
225 *
226 * We have found an AMD76x and now need to set up the memory
227 * controller status reporting. We configure and set up the
228 * memory controller reporting and claim the device.
229 */
230static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
231{
232 static const enum edac_type ems_modes[] = {
233 EDAC_NONE,
234 EDAC_EC,
235 EDAC_SECDED,
236 EDAC_SECDED
237 };
Mauro Carvalho Chehabd8c34af2012-04-16 15:05:27 -0300238 struct mem_ctl_info *mci;
239 struct edac_mc_layer layers[2];
Doug Thompson13189522006-06-30 01:56:08 -0700240 u32 ems;
241 u32 ems_mode;
242 struct amd76x_error_info discard;
243
Joe Perches956b9ba2012-04-29 17:08:39 -0300244 edac_dbg(0, "\n");
Doug Thompson13189522006-06-30 01:56:08 -0700245 pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
246 ems_mode = (ems >> 10) & 0x3;
Doug Thompson13189522006-06-30 01:56:08 -0700247
Mauro Carvalho Chehabd8c34af2012-04-16 15:05:27 -0300248 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
249 layers[0].size = AMD76X_NR_CSROWS;
250 layers[0].is_virt_csrow = true;
251 layers[1].type = EDAC_MC_LAYER_CHANNEL;
252 layers[1].size = 1;
253 layers[1].is_virt_csrow = false;
Mauro Carvalho Chehabca0907b2012-05-02 14:37:00 -0300254 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
Mauro Carvalho Chehabd8c34af2012-04-16 15:05:27 -0300255
256 if (mci == NULL)
Doug Thompson13189522006-06-30 01:56:08 -0700257 return -ENOMEM;
Alan Cox806c35f2006-01-18 17:44:08 -0800258
Joe Perches956b9ba2012-04-29 17:08:39 -0300259 edac_dbg(0, "mci = %p\n", mci);
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -0300260 mci->pdev = &pdev->dev;
Doug Thompson13189522006-06-30 01:56:08 -0700261 mci->mtype_cap = MEM_FLAG_RDDR;
262 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
263 mci->edac_cap = ems_mode ?
Douglas Thompson052dfb42007-07-19 01:50:13 -0700264 (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
Doug Thompson13189522006-06-30 01:56:08 -0700265 mci->mod_name = EDAC_MOD_STR;
266 mci->mod_ver = AMD76X_REVISION;
267 mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
Dave Jiangc4192702007-07-19 01:49:47 -0700268 mci->dev_name = pci_name(pdev);
Doug Thompson13189522006-06-30 01:56:08 -0700269 mci->edac_check = amd76x_check;
270 mci->ctl_page_to_phys = NULL;
271
272 amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
Douglas Thompson67cb2b62007-07-19 01:50:02 -0700273 amd76x_get_error_info(mci, &discard); /* clear counters */
Alan Cox806c35f2006-01-18 17:44:08 -0800274
Doug Thompson2d7bbb92006-06-30 01:56:08 -0700275 /* Here we assume that we will never see multiple instances of this
276 * type of memory controller. The ID is therefore hardcoded to 0.
277 */
Doug Thompsonb8f6f972007-07-19 01:50:26 -0700278 if (edac_mc_add_mc(mci)) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300279 edac_dbg(3, "failed edac_mc_add_mc()\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800280 goto fail;
281 }
282
Dave Jiang456a2f92007-07-19 01:50:10 -0700283 /* allocating generic PCI control info */
284 amd76x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
285 if (!amd76x_pci) {
286 printk(KERN_WARNING
287 "%s(): Unable to create PCI control\n",
288 __func__);
289 printk(KERN_WARNING
290 "%s(): PCI error report via EDAC not setup\n",
291 __func__);
292 }
293
Alan Cox806c35f2006-01-18 17:44:08 -0800294 /* get this far and it's successful */
Joe Perches956b9ba2012-04-29 17:08:39 -0300295 edac_dbg(3, "success\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800296 return 0;
297
Douglas Thompson052dfb42007-07-19 01:50:13 -0700298fail:
Doug Thompson13189522006-06-30 01:56:08 -0700299 edac_mc_free(mci);
300 return -ENODEV;
Alan Cox806c35f2006-01-18 17:44:08 -0800301}
302
303/* returns count (>= 0), or negative on error */
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800304static int amd76x_init_one(struct pci_dev *pdev,
305 const struct pci_device_id *ent)
Alan Cox806c35f2006-01-18 17:44:08 -0800306{
Joe Perches956b9ba2012-04-29 17:08:39 -0300307 edac_dbg(0, "\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800308
Roman Fietzeee6583f2010-05-18 14:45:47 +0200309 /* don't need to call pci_enable_device() */
Alan Cox806c35f2006-01-18 17:44:08 -0800310 return amd76x_probe1(pdev, ent->driver_data);
311}
312
Alan Cox806c35f2006-01-18 17:44:08 -0800313/**
314 * amd76x_remove_one - driver shutdown
315 * @pdev: PCI device being handed back
316 *
317 * Called when the driver is unloaded. Find the matching mci
318 * structure for the device then delete the mci and free the
319 * resources.
320 */
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800321static void amd76x_remove_one(struct pci_dev *pdev)
Alan Cox806c35f2006-01-18 17:44:08 -0800322{
323 struct mem_ctl_info *mci;
324
Joe Perches956b9ba2012-04-29 17:08:39 -0300325 edac_dbg(0, "\n");
Alan Cox806c35f2006-01-18 17:44:08 -0800326
Dave Jiang456a2f92007-07-19 01:50:10 -0700327 if (amd76x_pci)
328 edac_pci_release_generic_ctl(amd76x_pci);
329
Doug Thompson37f04582006-06-30 01:56:07 -0700330 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
Alan Cox806c35f2006-01-18 17:44:08 -0800331 return;
Dave Peterson18dbc332006-03-26 01:38:50 -0800332
Alan Cox806c35f2006-01-18 17:44:08 -0800333 edac_mc_free(mci);
334}
335
Lionel Debroux36c46f32012-02-27 07:41:47 +0100336static DEFINE_PCI_DEVICE_TABLE(amd76x_pci_tbl) = {
Dave Petersone7ecd892006-03-26 01:38:52 -0800337 {
Douglas Thompson67cb2b62007-07-19 01:50:02 -0700338 PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
339 AMD762},
Dave Petersone7ecd892006-03-26 01:38:52 -0800340 {
Douglas Thompson67cb2b62007-07-19 01:50:02 -0700341 PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
342 AMD761},
Dave Petersone7ecd892006-03-26 01:38:52 -0800343 {
Douglas Thompson67cb2b62007-07-19 01:50:02 -0700344 0,
345 } /* 0 terminated list. */
Alan Cox806c35f2006-01-18 17:44:08 -0800346};
347
348MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
349
Alan Cox806c35f2006-01-18 17:44:08 -0800350static struct pci_driver amd76x_driver = {
Dave Peterson680cbbb2006-03-26 01:38:41 -0800351 .name = EDAC_MOD_STR,
Alan Cox806c35f2006-01-18 17:44:08 -0800352 .probe = amd76x_init_one,
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800353 .remove = amd76x_remove_one,
Alan Cox806c35f2006-01-18 17:44:08 -0800354 .id_table = amd76x_pci_tbl,
355};
356
Alan Coxda9bb1d2006-01-18 17:44:13 -0800357static int __init amd76x_init(void)
Alan Cox806c35f2006-01-18 17:44:08 -0800358{
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -0700359 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
360 opstate_init();
361
Alan Cox806c35f2006-01-18 17:44:08 -0800362 return pci_register_driver(&amd76x_driver);
363}
364
365static void __exit amd76x_exit(void)
366{
367 pci_unregister_driver(&amd76x_driver);
368}
369
370module_init(amd76x_init);
371module_exit(amd76x_exit);
372
373MODULE_LICENSE("GPL");
374MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
375MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -0700376
377module_param(edac_op_state, int, 0444);
378MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");