Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1 | /* |
Sujith | cee075a | 2009-03-13 09:07:23 +0530 | [diff] [blame] | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
Luis R. Rodriguez | cfe8cba | 2009-09-13 23:39:31 -0700 | [diff] [blame] | 17 | #include "hw.h" |
Felix Fietkau | c16fcb4 | 2010-04-15 17:38:39 -0400 | [diff] [blame] | 18 | #include "hw-ops.h" |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 19 | |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 20 | /* Private to ani.c */ |
| 21 | static inline void ath9k_hw_ani_lower_immunity(struct ath_hw *ah) |
| 22 | { |
| 23 | ath9k_hw_private_ops(ah)->ani_lower_immunity(ah); |
| 24 | } |
| 25 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 26 | static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 27 | struct ath9k_channel *chan) |
| 28 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 29 | int i; |
| 30 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 31 | for (i = 0; i < ARRAY_SIZE(ah->ani); i++) { |
| 32 | if (ah->ani[i].c && |
| 33 | ah->ani[i].c->channel == chan->channel) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 34 | return i; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 35 | if (ah->ani[i].c == NULL) { |
| 36 | ah->ani[i].c = chan; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 37 | return i; |
| 38 | } |
| 39 | } |
| 40 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 41 | ath_print(ath9k_hw_common(ah), ATH_DBG_ANI, |
| 42 | "No more channel states left. Using channel 0\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 43 | |
| 44 | return 0; |
| 45 | } |
| 46 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 47 | static void ath9k_hw_update_mibstats(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 48 | struct ath9k_mib_stats *stats) |
| 49 | { |
| 50 | stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); |
| 51 | stats->rts_bad += REG_READ(ah, AR_RTS_FAIL); |
| 52 | stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL); |
| 53 | stats->rts_good += REG_READ(ah, AR_RTS_OK); |
| 54 | stats->beacons += REG_READ(ah, AR_BEACON_CNT); |
| 55 | } |
| 56 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 57 | static void ath9k_ani_restart(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 58 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 59 | struct ar5416AniState *aniState; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 60 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 61 | |
| 62 | if (!DO_ANI(ah)) |
| 63 | return; |
| 64 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 65 | aniState = ah->curani; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 66 | aniState->listenTime = 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 67 | |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 68 | if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { |
| 69 | aniState->ofdmPhyErrBase = 0; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 70 | ath_print(common, ATH_DBG_ANI, |
| 71 | "OFDM Trigger is too high for hw counters\n"); |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 72 | } else { |
| 73 | aniState->ofdmPhyErrBase = |
| 74 | AR_PHY_COUNTMAX - aniState->ofdmTrigHigh; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 75 | } |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 76 | if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) { |
| 77 | aniState->cckPhyErrBase = 0; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 78 | ath_print(common, ATH_DBG_ANI, |
| 79 | "CCK Trigger is too high for hw counters\n"); |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 80 | } else { |
| 81 | aniState->cckPhyErrBase = |
| 82 | AR_PHY_COUNTMAX - aniState->cckTrigHigh; |
| 83 | } |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 84 | ath_print(common, ATH_DBG_ANI, |
| 85 | "Writing ofdmbase=%u cckbase=%u\n", |
| 86 | aniState->ofdmPhyErrBase, |
| 87 | aniState->cckPhyErrBase); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 88 | |
| 89 | ENABLE_REGWRITE_BUFFER(ah); |
| 90 | |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 91 | REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); |
| 92 | REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); |
| 93 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); |
| 94 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); |
| 95 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 96 | REGWRITE_BUFFER_FLUSH(ah); |
| 97 | DISABLE_REGWRITE_BUFFER(ah); |
| 98 | |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 99 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
| 100 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 101 | aniState->ofdmPhyErrCount = 0; |
| 102 | aniState->cckPhyErrCount = 0; |
| 103 | } |
| 104 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 105 | static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 106 | { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 107 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 108 | struct ar5416AniState *aniState; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 109 | int32_t rssi; |
| 110 | |
| 111 | if (!DO_ANI(ah)) |
| 112 | return; |
| 113 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 114 | aniState = ah->curani; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 115 | |
| 116 | if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { |
| 117 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, |
| 118 | aniState->noiseImmunityLevel + 1)) { |
| 119 | return; |
| 120 | } |
| 121 | } |
| 122 | |
| 123 | if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) { |
| 124 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, |
| 125 | aniState->spurImmunityLevel + 1)) { |
| 126 | return; |
| 127 | } |
| 128 | } |
| 129 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 130 | if (ah->opmode == NL80211_IFTYPE_AP) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 131 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { |
| 132 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, |
| 133 | aniState->firstepLevel + 1); |
| 134 | } |
| 135 | return; |
| 136 | } |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 137 | rssi = BEACON_RSSI(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 138 | if (rssi > aniState->rssiThrHigh) { |
| 139 | if (!aniState->ofdmWeakSigDetectOff) { |
| 140 | if (ath9k_hw_ani_control(ah, |
| 141 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, |
| 142 | false)) { |
| 143 | ath9k_hw_ani_control(ah, |
| 144 | ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); |
| 145 | return; |
| 146 | } |
| 147 | } |
| 148 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { |
| 149 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, |
| 150 | aniState->firstepLevel + 1); |
| 151 | return; |
| 152 | } |
| 153 | } else if (rssi > aniState->rssiThrLow) { |
| 154 | if (aniState->ofdmWeakSigDetectOff) |
| 155 | ath9k_hw_ani_control(ah, |
| 156 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, |
| 157 | true); |
| 158 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) |
| 159 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, |
| 160 | aniState->firstepLevel + 1); |
| 161 | return; |
| 162 | } else { |
Sujith | d37b7da | 2009-09-11 08:30:03 +0530 | [diff] [blame] | 163 | if ((conf->channel->band == IEEE80211_BAND_2GHZ) && |
| 164 | !conf_is_ht(conf)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 165 | if (!aniState->ofdmWeakSigDetectOff) |
| 166 | ath9k_hw_ani_control(ah, |
| 167 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, |
| 168 | false); |
| 169 | if (aniState->firstepLevel > 0) |
| 170 | ath9k_hw_ani_control(ah, |
| 171 | ATH9K_ANI_FIRSTEP_LEVEL, 0); |
| 172 | return; |
| 173 | } |
| 174 | } |
| 175 | } |
| 176 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 177 | static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 178 | { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 179 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 180 | struct ar5416AniState *aniState; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 181 | int32_t rssi; |
| 182 | |
| 183 | if (!DO_ANI(ah)) |
| 184 | return; |
| 185 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 186 | aniState = ah->curani; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 187 | if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { |
| 188 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, |
| 189 | aniState->noiseImmunityLevel + 1)) { |
| 190 | return; |
| 191 | } |
| 192 | } |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 193 | if (ah->opmode == NL80211_IFTYPE_AP) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 194 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { |
| 195 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, |
| 196 | aniState->firstepLevel + 1); |
| 197 | } |
| 198 | return; |
| 199 | } |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 200 | rssi = BEACON_RSSI(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 201 | if (rssi > aniState->rssiThrLow) { |
| 202 | if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) |
| 203 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, |
| 204 | aniState->firstepLevel + 1); |
| 205 | } else { |
Sujith | d37b7da | 2009-09-11 08:30:03 +0530 | [diff] [blame] | 206 | if ((conf->channel->band == IEEE80211_BAND_2GHZ) && |
| 207 | !conf_is_ht(conf)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 208 | if (aniState->firstepLevel > 0) |
| 209 | ath9k_hw_ani_control(ah, |
| 210 | ATH9K_ANI_FIRSTEP_LEVEL, 0); |
| 211 | } |
| 212 | } |
| 213 | } |
| 214 | |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 215 | static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 216 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 217 | struct ar5416AniState *aniState; |
| 218 | int32_t rssi; |
| 219 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 220 | aniState = ah->curani; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 221 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 222 | if (ah->opmode == NL80211_IFTYPE_AP) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 223 | if (aniState->firstepLevel > 0) { |
| 224 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, |
| 225 | aniState->firstepLevel - 1)) |
| 226 | return; |
| 227 | } |
| 228 | } else { |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 229 | rssi = BEACON_RSSI(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 230 | if (rssi > aniState->rssiThrHigh) { |
| 231 | /* XXX: Handle me */ |
| 232 | } else if (rssi > aniState->rssiThrLow) { |
| 233 | if (aniState->ofdmWeakSigDetectOff) { |
| 234 | if (ath9k_hw_ani_control(ah, |
| 235 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, |
| 236 | true) == true) |
| 237 | return; |
| 238 | } |
| 239 | if (aniState->firstepLevel > 0) { |
| 240 | if (ath9k_hw_ani_control(ah, |
| 241 | ATH9K_ANI_FIRSTEP_LEVEL, |
| 242 | aniState->firstepLevel - 1) == true) |
| 243 | return; |
| 244 | } |
| 245 | } else { |
| 246 | if (aniState->firstepLevel > 0) { |
| 247 | if (ath9k_hw_ani_control(ah, |
| 248 | ATH9K_ANI_FIRSTEP_LEVEL, |
| 249 | aniState->firstepLevel - 1) == true) |
| 250 | return; |
| 251 | } |
| 252 | } |
| 253 | } |
| 254 | |
| 255 | if (aniState->spurImmunityLevel > 0) { |
| 256 | if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, |
| 257 | aniState->spurImmunityLevel - 1)) |
| 258 | return; |
| 259 | } |
| 260 | |
| 261 | if (aniState->noiseImmunityLevel > 0) { |
| 262 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, |
| 263 | aniState->noiseImmunityLevel - 1); |
| 264 | return; |
| 265 | } |
| 266 | } |
| 267 | |
Luis R. Rodriguez | 37e5bf6 | 2010-06-12 00:33:40 -0400 | [diff] [blame] | 268 | static u8 ath9k_hw_chan_2_clockrate_mhz(struct ath_hw *ah) |
| 269 | { |
| 270 | struct ath9k_channel *chan = ah->curchan; |
| 271 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
| 272 | u8 clockrate; /* in MHz */ |
| 273 | |
| 274 | if (!ah->curchan) /* should really check for CCK instead */ |
| 275 | clockrate = ATH9K_CLOCK_RATE_CCK; |
| 276 | else if (conf->channel->band == IEEE80211_BAND_2GHZ) |
| 277 | clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; |
| 278 | else if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
| 279 | clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; |
| 280 | else |
| 281 | clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; |
| 282 | |
| 283 | if (conf_is_ht40(conf)) |
| 284 | return clockrate * 2; |
| 285 | |
| 286 | return clockrate * 2; |
| 287 | } |
| 288 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 289 | static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 290 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 291 | struct ar5416AniState *aniState; |
| 292 | u32 txFrameCount, rxFrameCount, cycleCount; |
| 293 | int32_t listenTime; |
| 294 | |
| 295 | txFrameCount = REG_READ(ah, AR_TFCNT); |
| 296 | rxFrameCount = REG_READ(ah, AR_RFCNT); |
| 297 | cycleCount = REG_READ(ah, AR_CCCNT); |
| 298 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 299 | aniState = ah->curani; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 300 | if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) { |
| 301 | |
| 302 | listenTime = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 303 | ah->stats.ast_ani_lzero++; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 304 | } else { |
| 305 | int32_t ccdelta = cycleCount - aniState->cycleCount; |
| 306 | int32_t rfdelta = rxFrameCount - aniState->rxFrameCount; |
| 307 | int32_t tfdelta = txFrameCount - aniState->txFrameCount; |
Luis R. Rodriguez | 37e5bf6 | 2010-06-12 00:33:40 -0400 | [diff] [blame] | 308 | int32_t clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;; |
| 309 | |
| 310 | /* |
| 311 | * convert HW counter values to ms using mode |
| 312 | * specifix clock rate |
| 313 | */ |
| 314 | clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;; |
| 315 | |
| 316 | listenTime = (ccdelta - rfdelta - tfdelta) / clock_rate; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 317 | } |
| 318 | aniState->cycleCount = cycleCount; |
| 319 | aniState->txFrameCount = txFrameCount; |
| 320 | aniState->rxFrameCount = rxFrameCount; |
| 321 | |
| 322 | return listenTime; |
| 323 | } |
| 324 | |
Luis R. Rodriguez | 40346b6 | 2010-06-12 00:33:44 -0400 | [diff] [blame^] | 325 | static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 326 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 327 | struct ar5416AniState *aniState; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 328 | struct ath9k_channel *chan = ah->curchan; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 329 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 330 | int index; |
| 331 | |
| 332 | if (!DO_ANI(ah)) |
| 333 | return; |
| 334 | |
| 335 | index = ath9k_hw_get_ani_channel_idx(ah, chan); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 336 | aniState = &ah->ani[index]; |
| 337 | ah->curani = aniState; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 338 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 339 | if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION |
| 340 | && ah->opmode != NL80211_IFTYPE_ADHOC) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 341 | ath_print(common, ATH_DBG_ANI, |
| 342 | "Reset ANI state opmode %u\n", ah->opmode); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 343 | ah->stats.ast_ani_reset++; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 344 | |
Luis R. Rodriguez | c66284f | 2009-07-16 10:17:35 -0700 | [diff] [blame] | 345 | if (ah->opmode == NL80211_IFTYPE_AP) { |
| 346 | /* |
| 347 | * ath9k_hw_ani_control() will only process items set on |
| 348 | * ah->ani_function |
| 349 | */ |
| 350 | if (IS_CHAN_2GHZ(chan)) |
| 351 | ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | |
| 352 | ATH9K_ANI_FIRSTEP_LEVEL); |
| 353 | else |
| 354 | ah->ani_function = 0; |
| 355 | } |
| 356 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 357 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); |
| 358 | ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); |
| 359 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0); |
| 360 | ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, |
| 361 | !ATH9K_ANI_USE_OFDM_WEAK_SIG); |
| 362 | ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, |
| 363 | ATH9K_ANI_CCK_WEAK_SIG_THR); |
| 364 | |
| 365 | ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) | |
| 366 | ATH9K_RX_FILTER_PHYERR); |
| 367 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 368 | if (ah->opmode == NL80211_IFTYPE_AP) { |
| 369 | ah->curani->ofdmTrigHigh = |
| 370 | ah->config.ofdm_trig_high; |
| 371 | ah->curani->ofdmTrigLow = |
| 372 | ah->config.ofdm_trig_low; |
| 373 | ah->curani->cckTrigHigh = |
| 374 | ah->config.cck_trig_high; |
| 375 | ah->curani->cckTrigLow = |
| 376 | ah->config.cck_trig_low; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 377 | } |
| 378 | ath9k_ani_restart(ah); |
| 379 | return; |
| 380 | } |
| 381 | |
| 382 | if (aniState->noiseImmunityLevel != 0) |
| 383 | ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, |
| 384 | aniState->noiseImmunityLevel); |
| 385 | if (aniState->spurImmunityLevel != 0) |
| 386 | ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, |
| 387 | aniState->spurImmunityLevel); |
| 388 | if (aniState->ofdmWeakSigDetectOff) |
| 389 | ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, |
| 390 | !aniState->ofdmWeakSigDetectOff); |
| 391 | if (aniState->cckWeakSigThreshold) |
| 392 | ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, |
| 393 | aniState->cckWeakSigThreshold); |
| 394 | if (aniState->firstepLevel != 0) |
| 395 | ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, |
| 396 | aniState->firstepLevel); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 397 | |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 398 | ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & |
| 399 | ~ATH9K_RX_FILTER_PHYERR); |
| 400 | ath9k_ani_restart(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 401 | |
| 402 | ENABLE_REGWRITE_BUFFER(ah); |
| 403 | |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 404 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); |
| 405 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 406 | |
| 407 | REGWRITE_BUFFER_FLUSH(ah); |
| 408 | DISABLE_REGWRITE_BUFFER(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 409 | } |
| 410 | |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 411 | static void ath9k_hw_ani_monitor_old(struct ath_hw *ah, |
| 412 | struct ath9k_channel *chan) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 413 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 414 | struct ar5416AniState *aniState; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 415 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 416 | int32_t listenTime; |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 417 | u32 phyCnt1, phyCnt2; |
| 418 | u32 ofdmPhyErrCnt, cckPhyErrCnt; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 419 | |
Gabor Juhos | 9950688 | 2009-01-14 20:17:11 +0100 | [diff] [blame] | 420 | if (!DO_ANI(ah)) |
| 421 | return; |
| 422 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 423 | aniState = ah->curani; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 424 | |
| 425 | listenTime = ath9k_hw_ani_get_listen_time(ah); |
| 426 | if (listenTime < 0) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 427 | ah->stats.ast_ani_lneg++; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 428 | ath9k_ani_restart(ah); |
| 429 | return; |
| 430 | } |
| 431 | |
| 432 | aniState->listenTime += listenTime; |
| 433 | |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 434 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 435 | |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 436 | phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); |
| 437 | phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 438 | |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 439 | if (phyCnt1 < aniState->ofdmPhyErrBase || |
| 440 | phyCnt2 < aniState->cckPhyErrBase) { |
| 441 | if (phyCnt1 < aniState->ofdmPhyErrBase) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 442 | ath_print(common, ATH_DBG_ANI, |
| 443 | "phyCnt1 0x%x, resetting " |
| 444 | "counter value to 0x%x\n", |
| 445 | phyCnt1, |
| 446 | aniState->ofdmPhyErrBase); |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 447 | REG_WRITE(ah, AR_PHY_ERR_1, |
| 448 | aniState->ofdmPhyErrBase); |
| 449 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, |
| 450 | AR_PHY_ERR_OFDM_TIMING); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 451 | } |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 452 | if (phyCnt2 < aniState->cckPhyErrBase) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 453 | ath_print(common, ATH_DBG_ANI, |
| 454 | "phyCnt2 0x%x, resetting " |
| 455 | "counter value to 0x%x\n", |
| 456 | phyCnt2, |
| 457 | aniState->cckPhyErrBase); |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 458 | REG_WRITE(ah, AR_PHY_ERR_2, |
| 459 | aniState->cckPhyErrBase); |
| 460 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, |
| 461 | AR_PHY_ERR_CCK_TIMING); |
| 462 | } |
| 463 | return; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 464 | } |
| 465 | |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 466 | ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; |
| 467 | ah->stats.ast_ani_ofdmerrs += |
| 468 | ofdmPhyErrCnt - aniState->ofdmPhyErrCount; |
| 469 | aniState->ofdmPhyErrCount = ofdmPhyErrCnt; |
| 470 | |
| 471 | cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; |
| 472 | ah->stats.ast_ani_cckerrs += |
| 473 | cckPhyErrCnt - aniState->cckPhyErrCount; |
| 474 | aniState->cckPhyErrCount = cckPhyErrCnt; |
| 475 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 476 | if (aniState->listenTime > 5 * ah->aniperiod) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 477 | if (aniState->ofdmPhyErrCount <= aniState->listenTime * |
| 478 | aniState->ofdmTrigLow / 1000 && |
| 479 | aniState->cckPhyErrCount <= aniState->listenTime * |
| 480 | aniState->cckTrigLow / 1000) |
| 481 | ath9k_hw_ani_lower_immunity(ah); |
| 482 | ath9k_ani_restart(ah); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 483 | } else if (aniState->listenTime > ah->aniperiod) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 484 | if (aniState->ofdmPhyErrCount > aniState->listenTime * |
| 485 | aniState->ofdmTrigHigh / 1000) { |
| 486 | ath9k_hw_ani_ofdm_err_trigger(ah); |
| 487 | ath9k_ani_restart(ah); |
| 488 | } else if (aniState->cckPhyErrCount > |
| 489 | aniState->listenTime * aniState->cckTrigHigh / |
| 490 | 1000) { |
| 491 | ath9k_hw_ani_cck_err_trigger(ah); |
| 492 | ath9k_ani_restart(ah); |
| 493 | } |
| 494 | } |
| 495 | } |
| 496 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 497 | void ath9k_enable_mib_counters(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 498 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 499 | struct ath_common *common = ath9k_hw_common(ah); |
| 500 | |
| 501 | ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 502 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 503 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 504 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 505 | ENABLE_REGWRITE_BUFFER(ah); |
| 506 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 507 | REG_WRITE(ah, AR_FILT_OFDM, 0); |
| 508 | REG_WRITE(ah, AR_FILT_CCK, 0); |
| 509 | REG_WRITE(ah, AR_MIBC, |
| 510 | ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) |
| 511 | & 0x0f); |
| 512 | REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); |
| 513 | REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 514 | |
| 515 | REGWRITE_BUFFER_FLUSH(ah); |
| 516 | DISABLE_REGWRITE_BUFFER(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 517 | } |
| 518 | |
Sujith | 0fd06c9 | 2009-02-12 10:06:51 +0530 | [diff] [blame] | 519 | /* Freeze the MIB counters, get the stats and then clear them */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 520 | void ath9k_hw_disable_mib_counters(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 521 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 522 | struct ath_common *common = ath9k_hw_common(ah); |
| 523 | |
| 524 | ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n"); |
| 525 | |
Sujith | 0fd06c9 | 2009-02-12 10:06:51 +0530 | [diff] [blame] | 526 | REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 527 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
Sujith | 0fd06c9 | 2009-02-12 10:06:51 +0530 | [diff] [blame] | 528 | REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 529 | REG_WRITE(ah, AR_FILT_OFDM, 0); |
| 530 | REG_WRITE(ah, AR_FILT_CCK, 0); |
| 531 | } |
Sujith | 21d5130 | 2010-06-01 15:14:18 +0530 | [diff] [blame] | 532 | EXPORT_SYMBOL(ath9k_hw_disable_mib_counters); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 533 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 534 | u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 535 | u32 *rxc_pcnt, |
| 536 | u32 *rxf_pcnt, |
| 537 | u32 *txf_pcnt) |
| 538 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 539 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 540 | static u32 cycles, rx_clear, rx_frame, tx_frame; |
| 541 | u32 good = 1; |
| 542 | |
| 543 | u32 rc = REG_READ(ah, AR_RCCNT); |
| 544 | u32 rf = REG_READ(ah, AR_RFCNT); |
| 545 | u32 tf = REG_READ(ah, AR_TFCNT); |
| 546 | u32 cc = REG_READ(ah, AR_CCCNT); |
| 547 | |
| 548 | if (cycles == 0 || cycles > cc) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 549 | ath_print(common, ATH_DBG_ANI, |
| 550 | "cycle counter wrap. ExtBusy = 0\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 551 | good = 0; |
| 552 | } else { |
| 553 | u32 cc_d = cc - cycles; |
| 554 | u32 rc_d = rc - rx_clear; |
| 555 | u32 rf_d = rf - rx_frame; |
| 556 | u32 tf_d = tf - tx_frame; |
| 557 | |
| 558 | if (cc_d != 0) { |
| 559 | *rxc_pcnt = rc_d * 100 / cc_d; |
| 560 | *rxf_pcnt = rf_d * 100 / cc_d; |
| 561 | *txf_pcnt = tf_d * 100 / cc_d; |
| 562 | } else { |
| 563 | good = 0; |
| 564 | } |
| 565 | } |
| 566 | |
| 567 | cycles = cc; |
| 568 | rx_frame = rf; |
| 569 | rx_clear = rc; |
| 570 | tx_frame = tf; |
| 571 | |
| 572 | return good; |
| 573 | } |
| 574 | |
| 575 | /* |
| 576 | * Process a MIB interrupt. We may potentially be invoked because |
| 577 | * any of the MIB counters overflow/trigger so don't assume we're |
| 578 | * here because a PHY error counter triggered. |
| 579 | */ |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 580 | static void ath9k_hw_proc_mib_event_old(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 581 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 582 | u32 phyCnt1, phyCnt2; |
| 583 | |
| 584 | /* Reset these counters regardless */ |
| 585 | REG_WRITE(ah, AR_FILT_OFDM, 0); |
| 586 | REG_WRITE(ah, AR_FILT_CCK, 0); |
| 587 | if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING)) |
| 588 | REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); |
| 589 | |
| 590 | /* Clear the mib counters and save them in the stats */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 591 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 592 | |
Luis R. Rodriguez | 6e97f0f | 2010-06-12 00:33:41 -0400 | [diff] [blame] | 593 | if (!DO_ANI(ah)) { |
| 594 | /* |
| 595 | * We must always clear the interrupt cause by |
| 596 | * resetting the phy error regs. |
| 597 | */ |
| 598 | REG_WRITE(ah, AR_PHY_ERR_1, 0); |
| 599 | REG_WRITE(ah, AR_PHY_ERR_2, 0); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 600 | return; |
Luis R. Rodriguez | 6e97f0f | 2010-06-12 00:33:41 -0400 | [diff] [blame] | 601 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 602 | |
| 603 | /* NB: these are not reset-on-read */ |
| 604 | phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); |
| 605 | phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); |
| 606 | if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || |
| 607 | ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 608 | struct ar5416AniState *aniState = ah->curani; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 609 | u32 ofdmPhyErrCnt, cckPhyErrCnt; |
| 610 | |
| 611 | /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ |
| 612 | ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 613 | ah->stats.ast_ani_ofdmerrs += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 614 | ofdmPhyErrCnt - aniState->ofdmPhyErrCount; |
| 615 | aniState->ofdmPhyErrCount = ofdmPhyErrCnt; |
| 616 | |
| 617 | cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 618 | ah->stats.ast_ani_cckerrs += |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 619 | cckPhyErrCnt - aniState->cckPhyErrCount; |
| 620 | aniState->cckPhyErrCount = cckPhyErrCnt; |
| 621 | |
| 622 | /* |
| 623 | * NB: figure out which counter triggered. If both |
| 624 | * trigger we'll only deal with one as the processing |
| 625 | * clobbers the error counter so the trigger threshold |
| 626 | * check will never be true. |
| 627 | */ |
| 628 | if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh) |
| 629 | ath9k_hw_ani_ofdm_err_trigger(ah); |
| 630 | if (aniState->cckPhyErrCount > aniState->cckTrigHigh) |
| 631 | ath9k_hw_ani_cck_err_trigger(ah); |
| 632 | /* NB: always restart to insure the h/w counters are reset */ |
| 633 | ath9k_ani_restart(ah); |
| 634 | } |
| 635 | } |
| 636 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 637 | void ath9k_hw_ani_setup(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 638 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 639 | int i; |
| 640 | |
| 641 | const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; |
| 642 | const int coarseHigh[] = { -14, -14, -14, -14, -12 }; |
| 643 | const int coarseLow[] = { -64, -64, -64, -64, -70 }; |
| 644 | const int firpwr[] = { -78, -78, -78, -78, -80 }; |
| 645 | |
| 646 | for (i = 0; i < 5; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 647 | ah->totalSizeDesired[i] = totalSizeDesired[i]; |
| 648 | ah->coarse_high[i] = coarseHigh[i]; |
| 649 | ah->coarse_low[i] = coarseLow[i]; |
| 650 | ah->firpwr[i] = firpwr[i]; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 651 | } |
| 652 | } |
| 653 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 654 | void ath9k_hw_ani_init(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 655 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 656 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 657 | int i; |
| 658 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 659 | ath_print(common, ATH_DBG_ANI, "Initialize ANI\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 660 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 661 | memset(ah->ani, 0, sizeof(ah->ani)); |
| 662 | for (i = 0; i < ARRAY_SIZE(ah->ani); i++) { |
| 663 | ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; |
| 664 | ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; |
| 665 | ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; |
| 666 | ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; |
| 667 | ah->ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; |
| 668 | ah->ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; |
| 669 | ah->ani[i].ofdmWeakSigDetectOff = |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 670 | !ATH9K_ANI_USE_OFDM_WEAK_SIG; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 671 | ah->ani[i].cckWeakSigThreshold = |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 672 | ATH9K_ANI_CCK_WEAK_SIG_THR; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 673 | ah->ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; |
| 674 | ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 675 | ah->ani[i].ofdmPhyErrBase = |
| 676 | AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; |
| 677 | ah->ani[i].cckPhyErrBase = |
| 678 | AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 679 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 680 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 681 | ath_print(common, ATH_DBG_ANI, |
| 682 | "Setting OfdmErrBase = 0x%08x\n", |
| 683 | ah->ani[0].ofdmPhyErrBase); |
| 684 | ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", |
| 685 | ah->ani[0].cckPhyErrBase); |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 686 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 687 | ENABLE_REGWRITE_BUFFER(ah); |
| 688 | |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 689 | REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase); |
| 690 | REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 691 | |
| 692 | REGWRITE_BUFFER_FLUSH(ah); |
| 693 | DISABLE_REGWRITE_BUFFER(ah); |
| 694 | |
Sujith | 1aa8e84 | 2009-08-13 09:34:25 +0530 | [diff] [blame] | 695 | ath9k_enable_mib_counters(ah); |
| 696 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 697 | ah->aniperiod = ATH9K_ANI_PERIOD; |
| 698 | if (ah->config.enable_ani) |
| 699 | ah->proc_phyerr |= HAL_PROCESS_ANI; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 700 | } |
Luis R. Rodriguez | ac0bb76 | 2010-06-12 00:33:42 -0400 | [diff] [blame] | 701 | |
| 702 | void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah) |
| 703 | { |
| 704 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
| 705 | struct ath_hw_ops *ops = ath9k_hw_ops(ah); |
| 706 | |
| 707 | priv_ops->ani_reset = ath9k_ani_reset_old; |
| 708 | priv_ops->ani_lower_immunity = ath9k_hw_ani_lower_immunity_old; |
| 709 | |
| 710 | ops->ani_proc_mib_event = ath9k_hw_proc_mib_event_old; |
| 711 | ops->ani_monitor = ath9k_hw_ani_monitor_old; |
| 712 | } |