Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1 | /* |
| 2 | * RTL8XXXU mac80211 USB driver - 8723b specific subdriver |
| 3 | * |
| 4 | * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@redhat.com> |
| 5 | * |
| 6 | * Portions, notably calibration code: |
| 7 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. |
| 8 | * |
| 9 | * This driver was written as a replacement for the vendor provided |
| 10 | * rtl8723au driver. As the Realtek 8xxx chips are very similar in |
| 11 | * their programming interface, I have started adding support for |
| 12 | * additional 8xxx chips like the 8192cu, 8188cus, etc. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify it |
| 15 | * under the terms of version 2 of the GNU General Public License as |
| 16 | * published by the Free Software Foundation. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 19 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 21 | * more details. |
| 22 | */ |
| 23 | |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/sched.h> |
| 27 | #include <linux/errno.h> |
| 28 | #include <linux/slab.h> |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/spinlock.h> |
| 31 | #include <linux/list.h> |
| 32 | #include <linux/usb.h> |
| 33 | #include <linux/netdevice.h> |
| 34 | #include <linux/etherdevice.h> |
| 35 | #include <linux/ethtool.h> |
| 36 | #include <linux/wireless.h> |
| 37 | #include <linux/firmware.h> |
| 38 | #include <linux/moduleparam.h> |
| 39 | #include <net/mac80211.h> |
| 40 | #include "rtl8xxxu.h" |
| 41 | #include "rtl8xxxu_regs.h" |
| 42 | |
| 43 | static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = { |
| 44 | {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0}, |
| 45 | {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10}, |
| 46 | {0x430, 0x00}, {0x431, 0x00}, |
| 47 | {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, |
| 48 | {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05}, |
| 49 | {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01}, |
| 50 | {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00}, |
| 51 | {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f}, |
| 52 | {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00}, |
| 53 | {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f}, |
| 54 | {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66}, |
| 55 | {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, |
| 56 | {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, |
| 57 | {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, |
| 58 | {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, |
| 59 | {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, |
| 60 | {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, |
| 61 | {0x516, 0x0a}, {0x525, 0x4f}, |
| 62 | {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, |
| 63 | {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, |
| 64 | {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, |
| 65 | {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, |
| 66 | {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, |
| 67 | {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, |
| 68 | {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, |
| 69 | {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, |
| 70 | {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04}, |
| 71 | {0xffff, 0xff}, |
| 72 | }; |
| 73 | |
| 74 | static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = { |
| 75 | {0x800, 0x80040000}, {0x804, 0x00000003}, |
| 76 | {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, |
| 77 | {0x810, 0x10001331}, {0x814, 0x020c3d10}, |
| 78 | {0x818, 0x02200385}, {0x81c, 0x00000000}, |
| 79 | {0x820, 0x01000100}, {0x824, 0x00190204}, |
| 80 | {0x828, 0x00000000}, {0x82c, 0x00000000}, |
| 81 | {0x830, 0x00000000}, {0x834, 0x00000000}, |
| 82 | {0x838, 0x00000000}, {0x83c, 0x00000000}, |
| 83 | {0x840, 0x00010000}, {0x844, 0x00000000}, |
| 84 | {0x848, 0x00000000}, {0x84c, 0x00000000}, |
| 85 | {0x850, 0x00000000}, {0x854, 0x00000000}, |
| 86 | {0x858, 0x569a11a9}, {0x85c, 0x01000014}, |
| 87 | {0x860, 0x66f60110}, {0x864, 0x061f0649}, |
| 88 | {0x868, 0x00000000}, {0x86c, 0x27272700}, |
| 89 | {0x870, 0x07000760}, {0x874, 0x25004000}, |
| 90 | {0x878, 0x00000808}, {0x87c, 0x00000000}, |
| 91 | {0x880, 0xb0000c1c}, {0x884, 0x00000001}, |
| 92 | {0x888, 0x00000000}, {0x88c, 0xccc000c0}, |
| 93 | {0x890, 0x00000800}, {0x894, 0xfffffffe}, |
| 94 | {0x898, 0x40302010}, {0x89c, 0x00706050}, |
| 95 | {0x900, 0x00000000}, {0x904, 0x00000023}, |
| 96 | {0x908, 0x00000000}, {0x90c, 0x81121111}, |
| 97 | {0x910, 0x00000002}, {0x914, 0x00000201}, |
| 98 | {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c}, |
| 99 | {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f}, |
| 100 | {0xa10, 0x9500bb78}, {0xa14, 0x1114d028}, |
| 101 | {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, |
| 102 | {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, |
| 103 | {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, |
| 104 | {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, |
| 105 | {0xa78, 0x00000900}, {0xa7c, 0x225b0606}, |
| 106 | {0xa80, 0x21806490}, {0xb2c, 0x00000000}, |
| 107 | {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, |
| 108 | {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, |
| 109 | {0xc10, 0x08800000}, {0xc14, 0x40000100}, |
| 110 | {0xc18, 0x08800000}, {0xc1c, 0x40000100}, |
| 111 | {0xc20, 0x00000000}, {0xc24, 0x00000000}, |
| 112 | {0xc28, 0x00000000}, {0xc2c, 0x00000000}, |
| 113 | {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, |
| 114 | {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, |
| 115 | {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, |
| 116 | {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, |
| 117 | {0xc50, 0x69553420}, {0xc54, 0x43bc0094}, |
| 118 | {0xc58, 0x00013149}, {0xc5c, 0x00250492}, |
| 119 | {0xc60, 0x00000000}, {0xc64, 0x7112848b}, |
| 120 | {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, |
| 121 | {0xc70, 0x2c7f000d}, {0xc74, 0x020610db}, |
| 122 | {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, |
| 123 | {0xc80, 0x390000e4}, {0xc84, 0x20f60000}, |
| 124 | {0xc88, 0x40000100}, {0xc8c, 0x20200000}, |
| 125 | {0xc90, 0x00020e1a}, {0xc94, 0x00000000}, |
| 126 | {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f}, |
| 127 | {0xca0, 0x00000000}, {0xca4, 0x000300a0}, |
| 128 | {0xca8, 0x00000000}, {0xcac, 0x00000000}, |
| 129 | {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, |
| 130 | {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, |
| 131 | {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, |
| 132 | {0xcc8, 0x00000000}, {0xccc, 0x00000000}, |
| 133 | {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, |
| 134 | {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, |
| 135 | {0xce0, 0x00222222}, {0xce4, 0x00000000}, |
| 136 | {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, |
| 137 | {0xd00, 0x00000740}, {0xd04, 0x40020401}, |
| 138 | {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, |
| 139 | {0xd10, 0xa0633333}, {0xd14, 0x3333bc53}, |
| 140 | {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975}, |
| 141 | {0xd30, 0x00000000}, {0xd34, 0x80608000}, |
| 142 | {0xd38, 0x00000000}, {0xd3c, 0x00127353}, |
| 143 | {0xd40, 0x00000000}, {0xd44, 0x00000000}, |
| 144 | {0xd48, 0x00000000}, {0xd4c, 0x00000000}, |
| 145 | {0xd50, 0x6437140a}, {0xd54, 0x00000000}, |
| 146 | {0xd58, 0x00000282}, {0xd5c, 0x30032064}, |
| 147 | {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, |
| 148 | {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, |
| 149 | {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, |
| 150 | {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d}, |
| 151 | {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d}, |
| 152 | {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d}, |
| 153 | {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d}, |
| 154 | {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, |
| 155 | {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, |
| 156 | {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, |
| 157 | {0xe44, 0x01004800}, {0xe48, 0xfb000000}, |
| 158 | {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, |
| 159 | {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, |
| 160 | {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, |
| 161 | {0xe68, 0x001b2556}, {0xe6c, 0x00c00096}, |
| 162 | {0xe70, 0x00c00096}, {0xe74, 0x01000056}, |
| 163 | {0xe78, 0x01000014}, {0xe7c, 0x01000056}, |
| 164 | {0xe80, 0x01000014}, {0xe84, 0x00c00096}, |
| 165 | {0xe88, 0x01000056}, {0xe8c, 0x00c00096}, |
| 166 | {0xed0, 0x00c00096}, {0xed4, 0x00c00096}, |
| 167 | {0xed8, 0x00c00096}, {0xedc, 0x000000d6}, |
| 168 | {0xee0, 0x000000d6}, {0xeec, 0x01c00016}, |
| 169 | {0xf14, 0x00000003}, {0xf4c, 0x00000000}, |
| 170 | {0xf00, 0x00000300}, |
| 171 | {0x820, 0x01000100}, {0x800, 0x83040000}, |
| 172 | {0xffff, 0xffffffff}, |
| 173 | }; |
| 174 | |
| 175 | static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = { |
| 176 | {0xc78, 0xfd000001}, {0xc78, 0xfc010001}, |
| 177 | {0xc78, 0xfb020001}, {0xc78, 0xfa030001}, |
| 178 | {0xc78, 0xf9040001}, {0xc78, 0xf8050001}, |
| 179 | {0xc78, 0xf7060001}, {0xc78, 0xf6070001}, |
| 180 | {0xc78, 0xf5080001}, {0xc78, 0xf4090001}, |
| 181 | {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001}, |
| 182 | {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001}, |
| 183 | {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001}, |
| 184 | {0xc78, 0xed100001}, {0xc78, 0xec110001}, |
| 185 | {0xc78, 0xeb120001}, {0xc78, 0xea130001}, |
| 186 | {0xc78, 0xe9140001}, {0xc78, 0xe8150001}, |
| 187 | {0xc78, 0xe7160001}, {0xc78, 0xe6170001}, |
| 188 | {0xc78, 0xe5180001}, {0xc78, 0xe4190001}, |
| 189 | {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001}, |
| 190 | {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001}, |
| 191 | {0xc78, 0x671e0001}, {0xc78, 0x661f0001}, |
| 192 | {0xc78, 0x65200001}, {0xc78, 0x64210001}, |
| 193 | {0xc78, 0x63220001}, {0xc78, 0x4a230001}, |
| 194 | {0xc78, 0x49240001}, {0xc78, 0x48250001}, |
| 195 | {0xc78, 0x47260001}, {0xc78, 0x46270001}, |
| 196 | {0xc78, 0x45280001}, {0xc78, 0x44290001}, |
| 197 | {0xc78, 0x432a0001}, {0xc78, 0x422b0001}, |
| 198 | {0xc78, 0x292c0001}, {0xc78, 0x282d0001}, |
| 199 | {0xc78, 0x272e0001}, {0xc78, 0x262f0001}, |
| 200 | {0xc78, 0x0a300001}, {0xc78, 0x09310001}, |
| 201 | {0xc78, 0x08320001}, {0xc78, 0x07330001}, |
| 202 | {0xc78, 0x06340001}, {0xc78, 0x05350001}, |
| 203 | {0xc78, 0x04360001}, {0xc78, 0x03370001}, |
| 204 | {0xc78, 0x02380001}, {0xc78, 0x01390001}, |
| 205 | {0xc78, 0x013a0001}, {0xc78, 0x013b0001}, |
| 206 | {0xc78, 0x013c0001}, {0xc78, 0x013d0001}, |
| 207 | {0xc78, 0x013e0001}, {0xc78, 0x013f0001}, |
| 208 | {0xc78, 0xfc400001}, {0xc78, 0xfb410001}, |
| 209 | {0xc78, 0xfa420001}, {0xc78, 0xf9430001}, |
| 210 | {0xc78, 0xf8440001}, {0xc78, 0xf7450001}, |
| 211 | {0xc78, 0xf6460001}, {0xc78, 0xf5470001}, |
| 212 | {0xc78, 0xf4480001}, {0xc78, 0xf3490001}, |
| 213 | {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001}, |
| 214 | {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001}, |
| 215 | {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001}, |
| 216 | {0xc78, 0xec500001}, {0xc78, 0xeb510001}, |
| 217 | {0xc78, 0xea520001}, {0xc78, 0xe9530001}, |
| 218 | {0xc78, 0xe8540001}, {0xc78, 0xe7550001}, |
| 219 | {0xc78, 0xe6560001}, {0xc78, 0xe5570001}, |
| 220 | {0xc78, 0xe4580001}, {0xc78, 0xe3590001}, |
| 221 | {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001}, |
| 222 | {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001}, |
| 223 | {0xc78, 0x675e0001}, {0xc78, 0x665f0001}, |
| 224 | {0xc78, 0x65600001}, {0xc78, 0x64610001}, |
| 225 | {0xc78, 0x63620001}, {0xc78, 0x62630001}, |
| 226 | {0xc78, 0x61640001}, {0xc78, 0x48650001}, |
| 227 | {0xc78, 0x47660001}, {0xc78, 0x46670001}, |
| 228 | {0xc78, 0x45680001}, {0xc78, 0x44690001}, |
| 229 | {0xc78, 0x436a0001}, {0xc78, 0x426b0001}, |
| 230 | {0xc78, 0x286c0001}, {0xc78, 0x276d0001}, |
| 231 | {0xc78, 0x266e0001}, {0xc78, 0x256f0001}, |
| 232 | {0xc78, 0x24700001}, {0xc78, 0x09710001}, |
| 233 | {0xc78, 0x08720001}, {0xc78, 0x07730001}, |
| 234 | {0xc78, 0x06740001}, {0xc78, 0x05750001}, |
| 235 | {0xc78, 0x04760001}, {0xc78, 0x03770001}, |
| 236 | {0xc78, 0x02780001}, {0xc78, 0x01790001}, |
| 237 | {0xc78, 0x017a0001}, {0xc78, 0x017b0001}, |
| 238 | {0xc78, 0x017c0001}, {0xc78, 0x017d0001}, |
| 239 | {0xc78, 0x017e0001}, {0xc78, 0x017f0001}, |
| 240 | {0xc50, 0x69553422}, |
| 241 | {0xc50, 0x69553420}, |
| 242 | {0x824, 0x00390204}, |
| 243 | {0xffff, 0xffffffff} |
| 244 | }; |
| 245 | |
| 246 | static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = { |
| 247 | {0x00, 0x00010000}, {0xb0, 0x000dffe0}, |
| 248 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 249 | {0xfe, 0x00000000}, {0xb1, 0x00000018}, |
| 250 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 251 | {0xfe, 0x00000000}, {0xb2, 0x00084c00}, |
| 252 | {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa}, |
| 253 | {0xb7, 0x00000010}, {0xb8, 0x0000907f}, |
| 254 | {0x5c, 0x00000002}, {0x7c, 0x00000002}, |
| 255 | {0x7e, 0x00000005}, {0x8b, 0x0006fc00}, |
| 256 | {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2}, |
| 257 | {0x1e, 0x00000000}, {0xdf, 0x00000780}, |
| 258 | {0x50, 0x00067435}, |
| 259 | /* |
| 260 | * The 8723bu vendor driver indicates that bit 8 should be set in |
| 261 | * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However |
| 262 | * they never actually check the package type - and just default |
| 263 | * to not setting it. |
| 264 | */ |
| 265 | {0x51, 0x0006b04e}, |
| 266 | {0x52, 0x000007d2}, {0x53, 0x00000000}, |
| 267 | {0x54, 0x00050400}, {0x55, 0x0004026e}, |
| 268 | {0xdd, 0x0000004c}, {0x70, 0x00067435}, |
| 269 | /* |
| 270 | * 0x71 has same package type condition as for register 0x51 |
| 271 | */ |
| 272 | {0x71, 0x0006b04e}, |
| 273 | {0x72, 0x000007d2}, {0x73, 0x00000000}, |
| 274 | {0x74, 0x00050400}, {0x75, 0x0004026e}, |
| 275 | {0xef, 0x00000100}, {0x34, 0x0000add7}, |
| 276 | {0x35, 0x00005c00}, {0x34, 0x00009dd4}, |
| 277 | {0x35, 0x00005000}, {0x34, 0x00008dd1}, |
| 278 | {0x35, 0x00004400}, {0x34, 0x00007dce}, |
| 279 | {0x35, 0x00003800}, {0x34, 0x00006cd1}, |
| 280 | {0x35, 0x00004400}, {0x34, 0x00005cce}, |
| 281 | {0x35, 0x00003800}, {0x34, 0x000048ce}, |
| 282 | {0x35, 0x00004400}, {0x34, 0x000034ce}, |
| 283 | {0x35, 0x00003800}, {0x34, 0x00002451}, |
| 284 | {0x35, 0x00004400}, {0x34, 0x0000144e}, |
| 285 | {0x35, 0x00003800}, {0x34, 0x00000051}, |
| 286 | {0x35, 0x00004400}, {0xef, 0x00000000}, |
| 287 | {0xef, 0x00000100}, {0xed, 0x00000010}, |
| 288 | {0x44, 0x0000add7}, {0x44, 0x00009dd4}, |
| 289 | {0x44, 0x00008dd1}, {0x44, 0x00007dce}, |
| 290 | {0x44, 0x00006cc1}, {0x44, 0x00005cce}, |
| 291 | {0x44, 0x000044d1}, {0x44, 0x000034ce}, |
| 292 | {0x44, 0x00002451}, {0x44, 0x0000144e}, |
| 293 | {0x44, 0x00000051}, {0xef, 0x00000000}, |
| 294 | {0xed, 0x00000000}, {0x7f, 0x00020080}, |
| 295 | {0xef, 0x00002000}, {0x3b, 0x000380ef}, |
| 296 | {0x3b, 0x000302fe}, {0x3b, 0x00028ce6}, |
| 297 | {0x3b, 0x000200bc}, {0x3b, 0x000188a5}, |
| 298 | {0x3b, 0x00010fbc}, {0x3b, 0x00008f71}, |
| 299 | {0x3b, 0x00000900}, {0xef, 0x00000000}, |
| 300 | {0xed, 0x00000001}, {0x40, 0x000380ef}, |
| 301 | {0x40, 0x000302fe}, {0x40, 0x00028ce6}, |
| 302 | {0x40, 0x000200bc}, {0x40, 0x000188a5}, |
| 303 | {0x40, 0x00010fbc}, {0x40, 0x00008f71}, |
| 304 | {0x40, 0x00000900}, {0xed, 0x00000000}, |
| 305 | {0x82, 0x00080000}, {0x83, 0x00008000}, |
| 306 | {0x84, 0x00048d80}, {0x85, 0x00068000}, |
| 307 | {0xa2, 0x00080000}, {0xa3, 0x00008000}, |
| 308 | {0xa4, 0x00048d80}, {0xa5, 0x00068000}, |
| 309 | {0xed, 0x00000002}, {0xef, 0x00000002}, |
| 310 | {0x56, 0x00000032}, {0x76, 0x00000032}, |
| 311 | {0x01, 0x00000780}, |
| 312 | {0xff, 0xffffffff} |
| 313 | }; |
| 314 | |
| 315 | static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data) |
| 316 | { |
| 317 | struct h2c_cmd h2c; |
| 318 | int reqnum = 0; |
| 319 | |
| 320 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 321 | h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; |
| 322 | h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); |
| 323 | h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; |
| 324 | h2c.bt_mp_oper.data = data; |
Jes Sorensen | 9c0343d | 2016-04-28 15:19:13 -0400 | [diff] [blame] | 325 | rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 326 | |
| 327 | reqnum++; |
| 328 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 329 | h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; |
| 330 | h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); |
| 331 | h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; |
| 332 | h2c.bt_mp_oper.addr = reg; |
Jes Sorensen | 9c0343d | 2016-04-28 15:19:13 -0400 | [diff] [blame] | 333 | rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 334 | } |
| 335 | |
| 336 | static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv) |
| 337 | { |
| 338 | u8 val8; |
| 339 | u16 sys_func; |
| 340 | |
| 341 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); |
| 342 | val8 &= ~BIT(1); |
| 343 | rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); |
| 344 | |
| 345 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
| 346 | val8 &= ~BIT(0); |
| 347 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); |
| 348 | |
| 349 | sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 350 | sys_func &= ~SYS_FUNC_CPU_ENABLE; |
| 351 | rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); |
| 352 | |
| 353 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); |
| 354 | val8 &= ~BIT(1); |
| 355 | rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); |
| 356 | |
| 357 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
| 358 | val8 |= BIT(0); |
| 359 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); |
| 360 | |
| 361 | sys_func |= SYS_FUNC_CPU_ENABLE; |
| 362 | rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); |
| 363 | } |
| 364 | |
| 365 | static void |
| 366 | rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) |
| 367 | { |
| 368 | u32 val32, ofdm, mcs; |
| 369 | u8 cck, ofdmbase, mcsbase; |
| 370 | int group, tx_idx; |
| 371 | |
| 372 | tx_idx = 0; |
| 373 | group = rtl8xxxu_gen2_channel_to_group(channel); |
| 374 | |
| 375 | cck = priv->cck_tx_power_index_B[group]; |
| 376 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); |
| 377 | val32 &= 0xffff00ff; |
| 378 | val32 |= (cck << 8); |
| 379 | rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); |
| 380 | |
| 381 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); |
| 382 | val32 &= 0xff; |
| 383 | val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); |
| 384 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); |
| 385 | |
| 386 | ofdmbase = priv->ht40_1s_tx_power_index_B[group]; |
| 387 | ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; |
| 388 | ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; |
| 389 | |
| 390 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); |
| 391 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); |
| 392 | |
| 393 | mcsbase = priv->ht40_1s_tx_power_index_B[group]; |
| 394 | if (ht40) |
| 395 | mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; |
| 396 | else |
| 397 | mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; |
| 398 | mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; |
| 399 | |
| 400 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); |
| 401 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); |
| 402 | } |
| 403 | |
| 404 | static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv) |
| 405 | { |
| 406 | struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu; |
| 407 | int i; |
| 408 | |
| 409 | if (efuse->rtl_id != cpu_to_le16(0x8129)) |
| 410 | return -EINVAL; |
| 411 | |
| 412 | ether_addr_copy(priv->mac_addr, efuse->mac_addr); |
| 413 | |
| 414 | memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, |
| 415 | sizeof(efuse->tx_power_index_A.cck_base)); |
| 416 | memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, |
| 417 | sizeof(efuse->tx_power_index_B.cck_base)); |
| 418 | |
| 419 | memcpy(priv->ht40_1s_tx_power_index_A, |
| 420 | efuse->tx_power_index_A.ht40_base, |
| 421 | sizeof(efuse->tx_power_index_A.ht40_base)); |
| 422 | memcpy(priv->ht40_1s_tx_power_index_B, |
| 423 | efuse->tx_power_index_B.ht40_base, |
| 424 | sizeof(efuse->tx_power_index_B.ht40_base)); |
| 425 | |
| 426 | priv->ofdm_tx_power_diff[0].a = |
| 427 | efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; |
| 428 | priv->ofdm_tx_power_diff[0].b = |
| 429 | efuse->tx_power_index_B.ht20_ofdm_1s_diff.a; |
| 430 | |
| 431 | priv->ht20_tx_power_diff[0].a = |
| 432 | efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; |
| 433 | priv->ht20_tx_power_diff[0].b = |
| 434 | efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; |
| 435 | |
| 436 | priv->ht40_tx_power_diff[0].a = 0; |
| 437 | priv->ht40_tx_power_diff[0].b = 0; |
| 438 | |
| 439 | for (i = 1; i < RTL8723B_TX_COUNT; i++) { |
| 440 | priv->ofdm_tx_power_diff[i].a = |
| 441 | efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; |
| 442 | priv->ofdm_tx_power_diff[i].b = |
| 443 | efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; |
| 444 | |
| 445 | priv->ht20_tx_power_diff[i].a = |
| 446 | efuse->tx_power_index_A.pwr_diff[i - 1].ht20; |
| 447 | priv->ht20_tx_power_diff[i].b = |
| 448 | efuse->tx_power_index_B.pwr_diff[i - 1].ht20; |
| 449 | |
| 450 | priv->ht40_tx_power_diff[i].a = |
| 451 | efuse->tx_power_index_A.pwr_diff[i - 1].ht40; |
| 452 | priv->ht40_tx_power_diff[i].b = |
| 453 | efuse->tx_power_index_B.pwr_diff[i - 1].ht40; |
| 454 | } |
| 455 | |
| 456 | priv->has_xtalk = 1; |
| 457 | priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f; |
| 458 | |
| 459 | dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); |
| 460 | dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name); |
| 461 | |
| 462 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) { |
| 463 | int i; |
| 464 | unsigned char *raw = priv->efuse_wifi.raw; |
| 465 | |
| 466 | dev_info(&priv->udev->dev, |
| 467 | "%s: dumping efuse (0x%02zx bytes):\n", |
| 468 | __func__, sizeof(struct rtl8723bu_efuse)); |
Andy Shevchenko | 2b9c9f5 | 2016-06-09 14:38:49 -0400 | [diff] [blame] | 469 | for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) |
| 470 | dev_info(&priv->udev->dev, "%02x: %8ph\n", i, &raw[i]); |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 471 | } |
| 472 | |
| 473 | return 0; |
| 474 | } |
| 475 | |
| 476 | static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv) |
| 477 | { |
| 478 | char *fw_name; |
| 479 | int ret; |
| 480 | |
| 481 | if (priv->enable_bluetooth) |
| 482 | fw_name = "rtlwifi/rtl8723bu_bt.bin"; |
| 483 | else |
| 484 | fw_name = "rtlwifi/rtl8723bu_nic.bin"; |
| 485 | |
| 486 | ret = rtl8xxxu_load_firmware(priv, fw_name); |
| 487 | return ret; |
| 488 | } |
| 489 | |
| 490 | static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv) |
| 491 | { |
| 492 | u8 val8; |
| 493 | u16 val16; |
| 494 | |
| 495 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 496 | val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; |
| 497 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 498 | |
| 499 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); |
| 500 | |
| 501 | /* 6. 0x1f[7:0] = 0x07 */ |
| 502 | val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; |
| 503 | rtl8xxxu_write8(priv, REG_RF_CTRL, val8); |
| 504 | |
| 505 | /* Why? */ |
| 506 | rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3); |
| 507 | rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80); |
| 508 | rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table); |
| 509 | |
| 510 | rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table); |
| 511 | } |
| 512 | |
| 513 | static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv) |
| 514 | { |
| 515 | int ret; |
| 516 | |
| 517 | ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A); |
| 518 | /* |
| 519 | * PHY LCK |
| 520 | */ |
| 521 | rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0); |
| 522 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01); |
| 523 | msleep(200); |
| 524 | rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0); |
| 525 | |
| 526 | return ret; |
| 527 | } |
| 528 | |
| 529 | static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) |
| 530 | { |
| 531 | u32 val32; |
| 532 | |
| 533 | val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); |
| 534 | val32 &= ~(BIT(20) | BIT(24)); |
| 535 | rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); |
| 536 | |
| 537 | val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); |
| 538 | val32 &= ~BIT(4); |
| 539 | rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); |
| 540 | |
| 541 | val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); |
| 542 | val32 |= BIT(3); |
| 543 | rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); |
| 544 | |
| 545 | val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); |
| 546 | val32 |= BIT(24); |
| 547 | rtl8xxxu_write32(priv, REG_LEDCFG0, val32); |
| 548 | |
| 549 | val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); |
| 550 | val32 &= ~BIT(23); |
| 551 | rtl8xxxu_write32(priv, REG_LEDCFG0, val32); |
| 552 | |
| 553 | val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); |
| 554 | val32 |= (BIT(0) | BIT(1)); |
| 555 | rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); |
| 556 | |
| 557 | val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC); |
| 558 | val32 &= 0xffffff00; |
| 559 | val32 |= 0x77; |
| 560 | rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); |
| 561 | |
| 562 | val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); |
| 563 | val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; |
| 564 | rtl8xxxu_write32(priv, REG_PWR_DATA, val32); |
| 565 | } |
| 566 | |
| 567 | static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv) |
| 568 | { |
| 569 | u32 reg_eac, reg_e94, reg_e9c, path_sel, val32; |
| 570 | int result = 0; |
| 571 | |
| 572 | path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); |
| 573 | |
| 574 | /* |
| 575 | * Leave IQK mode |
| 576 | */ |
| 577 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 578 | val32 &= 0x000000ff; |
| 579 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 580 | |
| 581 | /* |
| 582 | * Enable path A PA in TX IQK mode |
| 583 | */ |
| 584 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); |
| 585 | val32 |= 0x80000; |
| 586 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); |
| 587 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); |
| 588 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f); |
| 589 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87); |
| 590 | |
| 591 | /* |
| 592 | * Tx IQK setting |
| 593 | */ |
| 594 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); |
| 595 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 596 | |
| 597 | /* path-A IQK setting */ |
| 598 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); |
| 599 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); |
| 600 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); |
| 601 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); |
| 602 | |
| 603 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea); |
| 604 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); |
| 605 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); |
| 606 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); |
| 607 | |
| 608 | /* LO calibration setting */ |
| 609 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); |
| 610 | |
| 611 | /* |
| 612 | * Enter IQK mode |
| 613 | */ |
| 614 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 615 | val32 &= 0x000000ff; |
| 616 | val32 |= 0x80800000; |
| 617 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 618 | |
| 619 | /* |
| 620 | * The vendor driver indicates the USB module is always using |
| 621 | * S0S1 path 1 for the 8723bu. This may be different for 8192eu |
| 622 | */ |
| 623 | if (priv->rf_paths > 1) |
| 624 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); |
| 625 | else |
| 626 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); |
| 627 | |
| 628 | /* |
| 629 | * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. |
| 630 | * No trace of this in the 8192eu or 8188eu vendor drivers. |
| 631 | */ |
| 632 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); |
| 633 | |
| 634 | /* One shot, path A LOK & IQK */ |
| 635 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); |
| 636 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 637 | |
| 638 | mdelay(1); |
| 639 | |
| 640 | /* Restore Ant Path */ |
| 641 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); |
| 642 | #ifdef RTL8723BU_BT |
| 643 | /* GNT_BT = 1 */ |
| 644 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); |
| 645 | #endif |
| 646 | |
| 647 | /* |
| 648 | * Leave IQK mode |
| 649 | */ |
| 650 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 651 | val32 &= 0x000000ff; |
| 652 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 653 | |
| 654 | /* Check failed */ |
| 655 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 656 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
| 657 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
| 658 | |
| 659 | val32 = (reg_e9c >> 16) & 0x3ff; |
| 660 | if (val32 & 0x200) |
| 661 | val32 = 0x400 - val32; |
| 662 | |
| 663 | if (!(reg_eac & BIT(28)) && |
| 664 | ((reg_e94 & 0x03ff0000) != 0x01420000) && |
| 665 | ((reg_e9c & 0x03ff0000) != 0x00420000) && |
| 666 | ((reg_e94 & 0x03ff0000) < 0x01100000) && |
| 667 | ((reg_e94 & 0x03ff0000) > 0x00f00000) && |
| 668 | val32 < 0xf) |
| 669 | result |= 0x01; |
| 670 | else /* If TX not OK, ignore RX */ |
| 671 | goto out; |
| 672 | |
| 673 | out: |
| 674 | return result; |
| 675 | } |
| 676 | |
| 677 | static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) |
| 678 | { |
| 679 | u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32; |
| 680 | int result = 0; |
| 681 | |
| 682 | path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); |
| 683 | |
| 684 | /* |
| 685 | * Leave IQK mode |
| 686 | */ |
| 687 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 688 | val32 &= 0x000000ff; |
| 689 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 690 | |
| 691 | /* |
| 692 | * Enable path A PA in TX IQK mode |
| 693 | */ |
| 694 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); |
| 695 | val32 |= 0x80000; |
| 696 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); |
| 697 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); |
| 698 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); |
| 699 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); |
| 700 | |
| 701 | /* |
| 702 | * Tx IQK setting |
| 703 | */ |
| 704 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); |
| 705 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 706 | |
| 707 | /* path-A IQK setting */ |
| 708 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); |
| 709 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); |
| 710 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); |
| 711 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); |
| 712 | |
| 713 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0); |
| 714 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); |
| 715 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); |
| 716 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); |
| 717 | |
| 718 | /* LO calibration setting */ |
| 719 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); |
| 720 | |
| 721 | /* |
| 722 | * Enter IQK mode |
| 723 | */ |
| 724 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 725 | val32 &= 0x000000ff; |
| 726 | val32 |= 0x80800000; |
| 727 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 728 | |
| 729 | /* |
| 730 | * The vendor driver indicates the USB module is always using |
| 731 | * S0S1 path 1 for the 8723bu. This may be different for 8192eu |
| 732 | */ |
| 733 | if (priv->rf_paths > 1) |
| 734 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); |
| 735 | else |
| 736 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); |
| 737 | |
| 738 | /* |
| 739 | * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. |
| 740 | * No trace of this in the 8192eu or 8188eu vendor drivers. |
| 741 | */ |
| 742 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); |
| 743 | |
| 744 | /* One shot, path A LOK & IQK */ |
| 745 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); |
| 746 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 747 | |
| 748 | mdelay(1); |
| 749 | |
| 750 | /* Restore Ant Path */ |
| 751 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); |
| 752 | #ifdef RTL8723BU_BT |
| 753 | /* GNT_BT = 1 */ |
| 754 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); |
| 755 | #endif |
| 756 | |
| 757 | /* |
| 758 | * Leave IQK mode |
| 759 | */ |
| 760 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 761 | val32 &= 0x000000ff; |
| 762 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 763 | |
| 764 | /* Check failed */ |
| 765 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 766 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
| 767 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
| 768 | |
| 769 | val32 = (reg_e9c >> 16) & 0x3ff; |
| 770 | if (val32 & 0x200) |
| 771 | val32 = 0x400 - val32; |
| 772 | |
| 773 | if (!(reg_eac & BIT(28)) && |
| 774 | ((reg_e94 & 0x03ff0000) != 0x01420000) && |
| 775 | ((reg_e9c & 0x03ff0000) != 0x00420000) && |
| 776 | ((reg_e94 & 0x03ff0000) < 0x01100000) && |
| 777 | ((reg_e94 & 0x03ff0000) > 0x00f00000) && |
| 778 | val32 < 0xf) |
| 779 | result |= 0x01; |
| 780 | else /* If TX not OK, ignore RX */ |
| 781 | goto out; |
| 782 | |
| 783 | val32 = 0x80007c00 | (reg_e94 &0x3ff0000) | |
| 784 | ((reg_e9c & 0x3ff0000) >> 16); |
| 785 | rtl8xxxu_write32(priv, REG_TX_IQK, val32); |
| 786 | |
| 787 | /* |
| 788 | * Modify RX IQK mode |
| 789 | */ |
| 790 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 791 | val32 &= 0x000000ff; |
| 792 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 793 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); |
| 794 | val32 |= 0x80000; |
| 795 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); |
| 796 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); |
| 797 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); |
| 798 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77); |
| 799 | |
| 800 | /* |
| 801 | * PA, PAD setting |
| 802 | */ |
| 803 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80); |
| 804 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f); |
| 805 | |
| 806 | /* |
| 807 | * RX IQK setting |
| 808 | */ |
| 809 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 810 | |
| 811 | /* path-A IQK setting */ |
| 812 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); |
| 813 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); |
| 814 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); |
| 815 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); |
| 816 | |
| 817 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000); |
| 818 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f); |
| 819 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); |
| 820 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); |
| 821 | |
| 822 | /* LO calibration setting */ |
| 823 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); |
| 824 | |
| 825 | /* |
| 826 | * Enter IQK mode |
| 827 | */ |
| 828 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 829 | val32 &= 0x000000ff; |
| 830 | val32 |= 0x80800000; |
| 831 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 832 | |
| 833 | if (priv->rf_paths > 1) |
| 834 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); |
| 835 | else |
| 836 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); |
| 837 | |
| 838 | /* |
| 839 | * Disable BT |
| 840 | */ |
| 841 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); |
| 842 | |
| 843 | /* One shot, path A LOK & IQK */ |
| 844 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); |
| 845 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 846 | |
| 847 | mdelay(1); |
| 848 | |
| 849 | /* Restore Ant Path */ |
| 850 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); |
| 851 | #ifdef RTL8723BU_BT |
| 852 | /* GNT_BT = 1 */ |
| 853 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); |
| 854 | #endif |
| 855 | |
| 856 | /* |
| 857 | * Leave IQK mode |
| 858 | */ |
| 859 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 860 | val32 &= 0x000000ff; |
| 861 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 862 | |
| 863 | /* Check failed */ |
| 864 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 865 | reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); |
| 866 | |
| 867 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780); |
| 868 | |
| 869 | val32 = (reg_eac >> 16) & 0x3ff; |
| 870 | if (val32 & 0x200) |
| 871 | val32 = 0x400 - val32; |
| 872 | |
| 873 | if (!(reg_eac & BIT(27)) && |
| 874 | ((reg_ea4 & 0x03ff0000) != 0x01320000) && |
| 875 | ((reg_eac & 0x03ff0000) != 0x00360000) && |
| 876 | ((reg_ea4 & 0x03ff0000) < 0x01100000) && |
| 877 | ((reg_ea4 & 0x03ff0000) > 0x00f00000) && |
| 878 | val32 < 0xf) |
| 879 | result |= 0x02; |
| 880 | else /* If TX not OK, ignore RX */ |
| 881 | goto out; |
| 882 | out: |
| 883 | return result; |
| 884 | } |
| 885 | |
| 886 | static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, |
| 887 | int result[][8], int t) |
| 888 | { |
| 889 | struct device *dev = &priv->udev->dev; |
| 890 | u32 i, val32; |
| 891 | int path_a_ok /*, path_b_ok */; |
| 892 | int retry = 2; |
| 893 | const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { |
| 894 | REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, |
| 895 | REG_RX_WAIT_CCA, REG_TX_CCK_RFON, |
| 896 | REG_TX_CCK_BBON, REG_TX_OFDM_RFON, |
| 897 | REG_TX_OFDM_BBON, REG_TX_TO_RX, |
| 898 | REG_TX_TO_TX, REG_RX_CCK, |
| 899 | REG_RX_OFDM, REG_RX_WAIT_RIFS, |
| 900 | REG_RX_TO_RX, REG_STANDBY, |
| 901 | REG_SLEEP, REG_PMPD_ANAEN |
| 902 | }; |
| 903 | const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { |
| 904 | REG_TXPAUSE, REG_BEACON_CTRL, |
| 905 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG |
| 906 | }; |
| 907 | const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { |
| 908 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, |
| 909 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, |
| 910 | REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, |
| 911 | REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE |
| 912 | }; |
| 913 | u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; |
| 914 | u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; |
| 915 | |
| 916 | /* |
| 917 | * Note: IQ calibration must be performed after loading |
| 918 | * PHY_REG.txt , and radio_a, radio_b.txt |
| 919 | */ |
| 920 | |
| 921 | if (t == 0) { |
| 922 | /* Save ADDA parameters, turn Path A ADDA on */ |
| 923 | rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, |
| 924 | RTL8XXXU_ADDA_REGS); |
| 925 | rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); |
| 926 | rtl8xxxu_save_regs(priv, iqk_bb_regs, |
| 927 | priv->bb_backup, RTL8XXXU_BB_REGS); |
| 928 | } |
| 929 | |
| 930 | rtl8xxxu_path_adda_on(priv, adda_regs, true); |
| 931 | |
| 932 | /* MAC settings */ |
| 933 | rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); |
| 934 | |
| 935 | val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); |
| 936 | val32 |= 0x0f000000; |
| 937 | rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); |
| 938 | |
| 939 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); |
| 940 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); |
| 941 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); |
| 942 | |
| 943 | /* |
| 944 | * RX IQ calibration setting for 8723B D cut large current issue |
| 945 | * when leaving IPS |
| 946 | */ |
| 947 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 948 | val32 &= 0x000000ff; |
| 949 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 950 | |
| 951 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); |
| 952 | val32 |= 0x80000; |
| 953 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); |
| 954 | |
| 955 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); |
| 956 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); |
| 957 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); |
| 958 | |
| 959 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); |
| 960 | val32 |= 0x20; |
| 961 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); |
| 962 | |
| 963 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd); |
| 964 | |
| 965 | for (i = 0; i < retry; i++) { |
| 966 | path_a_ok = rtl8723bu_iqk_path_a(priv); |
| 967 | if (path_a_ok == 0x01) { |
| 968 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 969 | val32 &= 0x000000ff; |
| 970 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 971 | |
| 972 | val32 = rtl8xxxu_read32(priv, |
| 973 | REG_TX_POWER_BEFORE_IQK_A); |
| 974 | result[t][0] = (val32 >> 16) & 0x3ff; |
| 975 | val32 = rtl8xxxu_read32(priv, |
| 976 | REG_TX_POWER_AFTER_IQK_A); |
| 977 | result[t][1] = (val32 >> 16) & 0x3ff; |
| 978 | |
| 979 | break; |
| 980 | } |
| 981 | } |
| 982 | |
| 983 | if (!path_a_ok) |
| 984 | dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); |
| 985 | |
| 986 | for (i = 0; i < retry; i++) { |
| 987 | path_a_ok = rtl8723bu_rx_iqk_path_a(priv); |
| 988 | if (path_a_ok == 0x03) { |
| 989 | val32 = rtl8xxxu_read32(priv, |
| 990 | REG_RX_POWER_BEFORE_IQK_A_2); |
| 991 | result[t][2] = (val32 >> 16) & 0x3ff; |
| 992 | val32 = rtl8xxxu_read32(priv, |
| 993 | REG_RX_POWER_AFTER_IQK_A_2); |
| 994 | result[t][3] = (val32 >> 16) & 0x3ff; |
| 995 | |
| 996 | break; |
| 997 | } |
| 998 | } |
| 999 | |
| 1000 | if (!path_a_ok) |
| 1001 | dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); |
| 1002 | |
| 1003 | if (priv->tx_paths > 1) { |
| 1004 | #if 1 |
| 1005 | dev_warn(dev, "%s: Path B not supported\n", __func__); |
| 1006 | #else |
| 1007 | |
| 1008 | /* |
| 1009 | * Path A into standby |
| 1010 | */ |
| 1011 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 1012 | val32 &= 0x000000ff; |
| 1013 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 1014 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); |
| 1015 | |
| 1016 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 1017 | val32 &= 0x000000ff; |
| 1018 | val32 |= 0x80800000; |
| 1019 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 1020 | |
| 1021 | /* Turn Path B ADDA on */ |
| 1022 | rtl8xxxu_path_adda_on(priv, adda_regs, false); |
| 1023 | |
| 1024 | for (i = 0; i < retry; i++) { |
| 1025 | path_b_ok = rtl8xxxu_iqk_path_b(priv); |
| 1026 | if (path_b_ok == 0x03) { |
| 1027 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
| 1028 | result[t][4] = (val32 >> 16) & 0x3ff; |
| 1029 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
| 1030 | result[t][5] = (val32 >> 16) & 0x3ff; |
| 1031 | break; |
| 1032 | } |
| 1033 | } |
| 1034 | |
| 1035 | if (!path_b_ok) |
| 1036 | dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); |
| 1037 | |
| 1038 | for (i = 0; i < retry; i++) { |
| 1039 | path_b_ok = rtl8723bu_rx_iqk_path_b(priv); |
| 1040 | if (path_a_ok == 0x03) { |
| 1041 | val32 = rtl8xxxu_read32(priv, |
| 1042 | REG_RX_POWER_BEFORE_IQK_B_2); |
| 1043 | result[t][6] = (val32 >> 16) & 0x3ff; |
| 1044 | val32 = rtl8xxxu_read32(priv, |
| 1045 | REG_RX_POWER_AFTER_IQK_B_2); |
| 1046 | result[t][7] = (val32 >> 16) & 0x3ff; |
| 1047 | break; |
| 1048 | } |
| 1049 | } |
| 1050 | |
| 1051 | if (!path_b_ok) |
| 1052 | dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__); |
| 1053 | #endif |
| 1054 | } |
| 1055 | |
| 1056 | /* Back to BB mode, load original value */ |
| 1057 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 1058 | val32 &= 0x000000ff; |
| 1059 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 1060 | |
| 1061 | if (t) { |
| 1062 | /* Reload ADDA power saving parameters */ |
| 1063 | rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, |
| 1064 | RTL8XXXU_ADDA_REGS); |
| 1065 | |
| 1066 | /* Reload MAC parameters */ |
| 1067 | rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); |
| 1068 | |
| 1069 | /* Reload BB parameters */ |
| 1070 | rtl8xxxu_restore_regs(priv, iqk_bb_regs, |
| 1071 | priv->bb_backup, RTL8XXXU_BB_REGS); |
| 1072 | |
| 1073 | /* Restore RX initial gain */ |
| 1074 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); |
| 1075 | val32 &= 0xffffff00; |
| 1076 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); |
| 1077 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); |
| 1078 | |
| 1079 | if (priv->tx_paths > 1) { |
| 1080 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); |
| 1081 | val32 &= 0xffffff00; |
| 1082 | rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, |
| 1083 | val32 | 0x50); |
| 1084 | rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, |
| 1085 | val32 | xb_agc); |
| 1086 | } |
| 1087 | |
| 1088 | /* Load 0xe30 IQC default value */ |
| 1089 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); |
| 1090 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); |
| 1091 | } |
| 1092 | } |
| 1093 | |
| 1094 | static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) |
| 1095 | { |
| 1096 | struct device *dev = &priv->udev->dev; |
| 1097 | int result[4][8]; /* last is final result */ |
| 1098 | int i, candidate; |
| 1099 | bool path_a_ok, path_b_ok; |
| 1100 | u32 reg_e94, reg_e9c, reg_ea4, reg_eac; |
| 1101 | u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; |
| 1102 | u32 val32, bt_control; |
| 1103 | s32 reg_tmp = 0; |
| 1104 | bool simu; |
| 1105 | |
Jes Sorensen | 27c7e89 | 2016-04-28 15:19:14 -0400 | [diff] [blame] | 1106 | rtl8xxxu_gen2_prepare_calibrate(priv, 1); |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1107 | |
| 1108 | memset(result, 0, sizeof(result)); |
| 1109 | candidate = -1; |
| 1110 | |
| 1111 | path_a_ok = false; |
| 1112 | path_b_ok = false; |
| 1113 | |
| 1114 | bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU); |
| 1115 | |
| 1116 | for (i = 0; i < 3; i++) { |
| 1117 | rtl8723bu_phy_iqcalibrate(priv, result, i); |
| 1118 | |
| 1119 | if (i == 1) { |
| 1120 | simu = rtl8xxxu_gen2_simularity_compare(priv, |
| 1121 | result, 0, 1); |
| 1122 | if (simu) { |
| 1123 | candidate = 0; |
| 1124 | break; |
| 1125 | } |
| 1126 | } |
| 1127 | |
| 1128 | if (i == 2) { |
| 1129 | simu = rtl8xxxu_gen2_simularity_compare(priv, |
| 1130 | result, 0, 2); |
| 1131 | if (simu) { |
| 1132 | candidate = 0; |
| 1133 | break; |
| 1134 | } |
| 1135 | |
| 1136 | simu = rtl8xxxu_gen2_simularity_compare(priv, |
| 1137 | result, 1, 2); |
| 1138 | if (simu) { |
| 1139 | candidate = 1; |
| 1140 | } else { |
| 1141 | for (i = 0; i < 8; i++) |
| 1142 | reg_tmp += result[3][i]; |
| 1143 | |
| 1144 | if (reg_tmp) |
| 1145 | candidate = 3; |
| 1146 | else |
| 1147 | candidate = -1; |
| 1148 | } |
| 1149 | } |
| 1150 | } |
| 1151 | |
| 1152 | for (i = 0; i < 4; i++) { |
| 1153 | reg_e94 = result[i][0]; |
| 1154 | reg_e9c = result[i][1]; |
| 1155 | reg_ea4 = result[i][2]; |
| 1156 | reg_eac = result[i][3]; |
| 1157 | reg_eb4 = result[i][4]; |
| 1158 | reg_ebc = result[i][5]; |
| 1159 | reg_ec4 = result[i][6]; |
| 1160 | reg_ecc = result[i][7]; |
| 1161 | } |
| 1162 | |
| 1163 | if (candidate >= 0) { |
| 1164 | reg_e94 = result[candidate][0]; |
| 1165 | priv->rege94 = reg_e94; |
| 1166 | reg_e9c = result[candidate][1]; |
| 1167 | priv->rege9c = reg_e9c; |
| 1168 | reg_ea4 = result[candidate][2]; |
| 1169 | reg_eac = result[candidate][3]; |
| 1170 | reg_eb4 = result[candidate][4]; |
| 1171 | priv->regeb4 = reg_eb4; |
| 1172 | reg_ebc = result[candidate][5]; |
| 1173 | priv->regebc = reg_ebc; |
| 1174 | reg_ec4 = result[candidate][6]; |
| 1175 | reg_ecc = result[candidate][7]; |
| 1176 | dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); |
| 1177 | dev_dbg(dev, |
| 1178 | "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x " |
| 1179 | "ecc=%x\n ", __func__, reg_e94, reg_e9c, |
| 1180 | reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); |
| 1181 | path_a_ok = true; |
| 1182 | path_b_ok = true; |
| 1183 | } else { |
| 1184 | reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; |
| 1185 | reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; |
| 1186 | } |
| 1187 | |
| 1188 | if (reg_e94 && candidate >= 0) |
| 1189 | rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, |
| 1190 | candidate, (reg_ea4 == 0)); |
| 1191 | |
| 1192 | if (priv->tx_paths > 1 && reg_eb4) |
| 1193 | rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, |
| 1194 | candidate, (reg_ec4 == 0)); |
| 1195 | |
| 1196 | rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, |
| 1197 | priv->bb_recovery_backup, RTL8XXXU_BB_REGS); |
| 1198 | |
| 1199 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control); |
| 1200 | |
| 1201 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); |
| 1202 | val32 |= 0x80000; |
| 1203 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); |
| 1204 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000); |
| 1205 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); |
| 1206 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177); |
| 1207 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); |
| 1208 | val32 |= 0x20; |
| 1209 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); |
| 1210 | rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd); |
| 1211 | |
| 1212 | if (priv->rf_paths > 1) |
| 1213 | dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__); |
| 1214 | |
Jes Sorensen | 27c7e89 | 2016-04-28 15:19:14 -0400 | [diff] [blame] | 1215 | rtl8xxxu_gen2_prepare_calibrate(priv, 0); |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1216 | } |
| 1217 | |
| 1218 | static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv) |
| 1219 | { |
| 1220 | u8 val8; |
| 1221 | u16 val16; |
| 1222 | u32 val32; |
| 1223 | int count, ret = 0; |
| 1224 | |
| 1225 | /* Turn off RF */ |
| 1226 | rtl8xxxu_write8(priv, REG_RF_CTRL, 0); |
| 1227 | |
| 1228 | /* Enable rising edge triggering interrupt */ |
| 1229 | val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM); |
| 1230 | val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ; |
| 1231 | rtl8xxxu_write16(priv, REG_GPIO_INTM, val16); |
| 1232 | |
| 1233 | /* Release WLON reset 0x04[16]= 1*/ |
| 1234 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 1235 | val32 |= APS_FSMCO_WLON_RESET; |
| 1236 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 1237 | |
| 1238 | /* 0x0005[1] = 1 turn off MAC by HW state machine*/ |
| 1239 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 1240 | val8 |= BIT(1); |
| 1241 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 1242 | |
| 1243 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 1244 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 1245 | if ((val8 & BIT(1)) == 0) |
| 1246 | break; |
| 1247 | udelay(10); |
| 1248 | } |
| 1249 | |
| 1250 | if (!count) { |
| 1251 | dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", |
| 1252 | __func__); |
| 1253 | ret = -EBUSY; |
| 1254 | goto exit; |
| 1255 | } |
| 1256 | |
| 1257 | /* Enable BT control XTAL setting */ |
| 1258 | val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); |
| 1259 | val8 &= ~AFE_MISC_WL_XTAL_CTRL; |
| 1260 | rtl8xxxu_write8(priv, REG_AFE_MISC, val8); |
| 1261 | |
| 1262 | /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ |
| 1263 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); |
| 1264 | val8 |= SYS_ISO_ANALOG_IPS; |
| 1265 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); |
| 1266 | |
| 1267 | /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ |
| 1268 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); |
| 1269 | val8 &= ~LDOA15_ENABLE; |
| 1270 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); |
| 1271 | |
| 1272 | exit: |
| 1273 | return ret; |
| 1274 | } |
| 1275 | |
| 1276 | static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv) |
| 1277 | { |
| 1278 | u8 val8; |
| 1279 | u32 val32; |
| 1280 | int count, ret = 0; |
| 1281 | |
| 1282 | /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */ |
| 1283 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); |
| 1284 | val8 |= LDOA15_ENABLE; |
| 1285 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); |
| 1286 | |
| 1287 | /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ |
| 1288 | val8 = rtl8xxxu_read8(priv, 0x0067); |
| 1289 | val8 &= ~BIT(4); |
| 1290 | rtl8xxxu_write8(priv, 0x0067, val8); |
| 1291 | |
| 1292 | mdelay(1); |
| 1293 | |
| 1294 | /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ |
| 1295 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); |
| 1296 | val8 &= ~SYS_ISO_ANALOG_IPS; |
| 1297 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); |
| 1298 | |
| 1299 | /* Disable SW LPS 0x04[10]= 0 */ |
| 1300 | val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO); |
| 1301 | val32 &= ~APS_FSMCO_SW_LPS; |
| 1302 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 1303 | |
| 1304 | /* Wait until 0x04[17] = 1 power ready */ |
| 1305 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 1306 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 1307 | if (val32 & BIT(17)) |
| 1308 | break; |
| 1309 | |
| 1310 | udelay(10); |
| 1311 | } |
| 1312 | |
| 1313 | if (!count) { |
| 1314 | ret = -EBUSY; |
| 1315 | goto exit; |
| 1316 | } |
| 1317 | |
| 1318 | /* We should be able to optimize the following three entries into one */ |
| 1319 | |
| 1320 | /* Release WLON reset 0x04[16]= 1*/ |
| 1321 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 1322 | val32 |= APS_FSMCO_WLON_RESET; |
| 1323 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 1324 | |
| 1325 | /* Disable HWPDN 0x04[15]= 0*/ |
| 1326 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 1327 | val32 &= ~APS_FSMCO_HW_POWERDOWN; |
| 1328 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 1329 | |
| 1330 | /* Disable WL suspend*/ |
| 1331 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 1332 | val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); |
| 1333 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 1334 | |
| 1335 | /* Set, then poll until 0 */ |
| 1336 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 1337 | val32 |= APS_FSMCO_MAC_ENABLE; |
| 1338 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 1339 | |
| 1340 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 1341 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 1342 | if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { |
| 1343 | ret = 0; |
| 1344 | break; |
| 1345 | } |
| 1346 | udelay(10); |
| 1347 | } |
| 1348 | |
| 1349 | if (!count) { |
| 1350 | ret = -EBUSY; |
| 1351 | goto exit; |
| 1352 | } |
| 1353 | |
| 1354 | /* Enable WL control XTAL setting */ |
| 1355 | val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); |
| 1356 | val8 |= AFE_MISC_WL_XTAL_CTRL; |
| 1357 | rtl8xxxu_write8(priv, REG_AFE_MISC, val8); |
| 1358 | |
| 1359 | /* Enable falling edge triggering interrupt */ |
| 1360 | val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1); |
| 1361 | val8 |= BIT(1); |
| 1362 | rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8); |
| 1363 | |
| 1364 | /* Enable GPIO9 interrupt mode */ |
| 1365 | val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1); |
| 1366 | val8 |= BIT(1); |
| 1367 | rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8); |
| 1368 | |
| 1369 | /* Enable GPIO9 input mode */ |
| 1370 | val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2); |
| 1371 | val8 &= ~BIT(1); |
| 1372 | rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8); |
| 1373 | |
| 1374 | /* Enable HSISR GPIO[C:0] interrupt */ |
| 1375 | val8 = rtl8xxxu_read8(priv, REG_HSIMR); |
| 1376 | val8 |= BIT(0); |
| 1377 | rtl8xxxu_write8(priv, REG_HSIMR, val8); |
| 1378 | |
| 1379 | /* Enable HSISR GPIO9 interrupt */ |
| 1380 | val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2); |
| 1381 | val8 |= BIT(1); |
| 1382 | rtl8xxxu_write8(priv, REG_HSIMR + 2, val8); |
| 1383 | |
| 1384 | val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL); |
| 1385 | val8 |= MULTI_WIFI_HW_ROF_EN; |
| 1386 | rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8); |
| 1387 | |
| 1388 | /* For GPIO9 internal pull high setting BIT(14) */ |
| 1389 | val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1); |
| 1390 | val8 |= BIT(6); |
| 1391 | rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8); |
| 1392 | |
| 1393 | exit: |
| 1394 | return ret; |
| 1395 | } |
| 1396 | |
| 1397 | static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv) |
| 1398 | { |
| 1399 | u8 val8; |
| 1400 | u16 val16; |
| 1401 | u32 val32; |
| 1402 | int ret; |
| 1403 | |
Jes Sorensen | 993dd9b | 2016-04-28 15:19:12 -0400 | [diff] [blame] | 1404 | rtl8xxxu_disabled_to_emu(priv); |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1405 | |
| 1406 | ret = rtl8723b_emu_to_active(priv); |
| 1407 | if (ret) |
| 1408 | goto exit; |
| 1409 | |
| 1410 | /* |
| 1411 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block |
| 1412 | * Set CR bit10 to enable 32k calibration. |
| 1413 | */ |
| 1414 | val16 = rtl8xxxu_read16(priv, REG_CR); |
| 1415 | val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | |
| 1416 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | |
| 1417 | CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | |
| 1418 | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | |
| 1419 | CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); |
| 1420 | rtl8xxxu_write16(priv, REG_CR, val16); |
| 1421 | |
| 1422 | /* |
| 1423 | * BT coexist power on settings. This is identical for 1 and 2 |
| 1424 | * antenna parts. |
| 1425 | */ |
| 1426 | rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20); |
| 1427 | |
| 1428 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 1429 | val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN; |
| 1430 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 1431 | |
| 1432 | rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18); |
| 1433 | rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); |
| 1434 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); |
| 1435 | /* Antenna inverse */ |
| 1436 | rtl8xxxu_write8(priv, 0xfe08, 0x01); |
| 1437 | |
| 1438 | val16 = rtl8xxxu_read16(priv, REG_PWR_DATA); |
| 1439 | val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; |
| 1440 | rtl8xxxu_write16(priv, REG_PWR_DATA, val16); |
| 1441 | |
| 1442 | val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); |
| 1443 | val32 |= LEDCFG0_DPDT_SELECT; |
| 1444 | rtl8xxxu_write32(priv, REG_LEDCFG0, val32); |
| 1445 | |
| 1446 | val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); |
| 1447 | val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA; |
| 1448 | rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); |
| 1449 | exit: |
| 1450 | return ret; |
| 1451 | } |
| 1452 | |
| 1453 | static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv) |
| 1454 | { |
| 1455 | u8 val8; |
| 1456 | u16 val16; |
| 1457 | |
| 1458 | rtl8xxxu_flush_fifo(priv); |
| 1459 | |
| 1460 | /* |
| 1461 | * Disable TX report timer |
| 1462 | */ |
| 1463 | val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); |
| 1464 | val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; |
| 1465 | rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); |
| 1466 | |
| 1467 | rtl8xxxu_write8(priv, REG_CR, 0x0000); |
| 1468 | |
| 1469 | rtl8xxxu_active_to_lps(priv); |
| 1470 | |
| 1471 | /* Reset Firmware if running in RAM */ |
| 1472 | if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) |
| 1473 | rtl8xxxu_firmware_self_reset(priv); |
| 1474 | |
| 1475 | /* Reset MCU */ |
| 1476 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 1477 | val16 &= ~SYS_FUNC_CPU_ENABLE; |
| 1478 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 1479 | |
| 1480 | /* Reset MCU ready status */ |
| 1481 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); |
| 1482 | |
| 1483 | rtl8723bu_active_to_emu(priv); |
| 1484 | |
| 1485 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 1486 | val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */ |
| 1487 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 1488 | |
| 1489 | /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ |
| 1490 | val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); |
| 1491 | val8 |= BIT(0); |
| 1492 | rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); |
| 1493 | } |
| 1494 | |
| 1495 | static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv) |
| 1496 | { |
| 1497 | struct h2c_cmd h2c; |
| 1498 | u32 val32; |
| 1499 | u8 val8; |
| 1500 | |
Jes Sorensen | ab05e5e | 2016-09-30 19:35:17 -0400 | [diff] [blame] | 1501 | val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); |
| 1502 | val32 |= (BIT(22) | BIT(23)); |
| 1503 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); |
| 1504 | |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1505 | /* |
| 1506 | * No indication anywhere as to what 0x0790 does. The 2 antenna |
| 1507 | * vendor code preserves bits 6-7 here. |
| 1508 | */ |
| 1509 | rtl8xxxu_write8(priv, 0x0790, 0x05); |
| 1510 | /* |
| 1511 | * 0x0778 seems to be related to enabling the number of antennas |
| 1512 | * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it |
| 1513 | * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01 |
| 1514 | */ |
| 1515 | rtl8xxxu_write8(priv, 0x0778, 0x01); |
| 1516 | |
| 1517 | val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); |
| 1518 | val8 |= BIT(5); |
| 1519 | rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); |
| 1520 | |
| 1521 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); |
| 1522 | |
| 1523 | rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */ |
| 1524 | |
| 1525 | /* |
| 1526 | * Set BT grant to low |
| 1527 | */ |
| 1528 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 1529 | h2c.bt_grant.cmd = H2C_8723B_BT_GRANT; |
| 1530 | h2c.bt_grant.data = 0; |
Jes Sorensen | 9c0343d | 2016-04-28 15:19:13 -0400 | [diff] [blame] | 1531 | rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant)); |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1532 | |
| 1533 | /* |
| 1534 | * WLAN action by PTA |
| 1535 | */ |
| 1536 | rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); |
| 1537 | |
| 1538 | /* |
| 1539 | * BT select S0/S1 controlled by WiFi |
| 1540 | */ |
| 1541 | val8 = rtl8xxxu_read8(priv, 0x0067); |
| 1542 | val8 |= BIT(5); |
| 1543 | rtl8xxxu_write8(priv, 0x0067, val8); |
| 1544 | |
| 1545 | val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); |
| 1546 | val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; |
| 1547 | rtl8xxxu_write32(priv, REG_PWR_DATA, val32); |
| 1548 | |
| 1549 | /* |
| 1550 | * Bits 6/7 are marked in/out ... but for what? |
| 1551 | */ |
| 1552 | rtl8xxxu_write8(priv, 0x0974, 0xff); |
| 1553 | |
| 1554 | val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); |
| 1555 | val32 |= (BIT(0) | BIT(1)); |
| 1556 | rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); |
| 1557 | |
| 1558 | rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); |
| 1559 | |
| 1560 | val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); |
| 1561 | val32 &= ~BIT(24); |
| 1562 | val32 |= BIT(23); |
| 1563 | rtl8xxxu_write32(priv, REG_LEDCFG0, val32); |
| 1564 | |
| 1565 | /* |
| 1566 | * Fix external switch Main->S1, Aux->S0 |
| 1567 | */ |
| 1568 | val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); |
| 1569 | val8 &= ~BIT(0); |
| 1570 | rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); |
| 1571 | |
| 1572 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 1573 | h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV; |
| 1574 | h2c.ant_sel_rsv.ant_inverse = 1; |
| 1575 | h2c.ant_sel_rsv.int_switch_type = 0; |
Jes Sorensen | 9c0343d | 2016-04-28 15:19:13 -0400 | [diff] [blame] | 1576 | rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv)); |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1577 | |
| 1578 | /* |
| 1579 | * 0x280, 0x00, 0x200, 0x80 - not clear |
| 1580 | */ |
| 1581 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); |
| 1582 | |
| 1583 | /* |
| 1584 | * Software control, antenna at WiFi side |
| 1585 | */ |
| 1586 | #ifdef NEED_PS_TDMA |
| 1587 | rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00); |
| 1588 | #endif |
| 1589 | |
| 1590 | rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); |
| 1591 | rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); |
| 1592 | rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); |
| 1593 | rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); |
| 1594 | |
| 1595 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 1596 | h2c.bt_info.cmd = H2C_8723B_BT_INFO; |
| 1597 | h2c.bt_info.data = BIT(0); |
Jes Sorensen | 9c0343d | 2016-04-28 15:19:13 -0400 | [diff] [blame] | 1598 | rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info)); |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1599 | |
| 1600 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 1601 | h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT; |
| 1602 | h2c.ignore_wlan.data = 0; |
Jes Sorensen | 9c0343d | 2016-04-28 15:19:13 -0400 | [diff] [blame] | 1603 | rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan)); |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1604 | } |
| 1605 | |
| 1606 | static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv) |
| 1607 | { |
| 1608 | u32 agg_rx; |
| 1609 | u8 agg_ctrl; |
| 1610 | |
| 1611 | /* |
| 1612 | * For now simply disable RX aggregation |
| 1613 | */ |
| 1614 | agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); |
| 1615 | agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; |
| 1616 | |
| 1617 | agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); |
| 1618 | agg_rx &= ~RXDMA_USB_AGG_ENABLE; |
| 1619 | agg_rx &= ~0xff0f; |
| 1620 | |
| 1621 | rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); |
| 1622 | rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); |
| 1623 | } |
| 1624 | |
| 1625 | static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv) |
| 1626 | { |
| 1627 | u32 val32; |
| 1628 | |
| 1629 | /* Time duration for NHM unit: 4us, 0x2710=40ms */ |
| 1630 | rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710); |
| 1631 | rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); |
| 1632 | rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52); |
| 1633 | rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); |
| 1634 | /* TH8 */ |
| 1635 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 1636 | val32 |= 0xff; |
| 1637 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 1638 | /* Enable CCK */ |
| 1639 | val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); |
| 1640 | val32 |= BIT(8) | BIT(9) | BIT(10); |
| 1641 | rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); |
| 1642 | /* Max power amongst all RX antennas */ |
| 1643 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); |
| 1644 | val32 |= BIT(7); |
| 1645 | rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); |
| 1646 | } |
| 1647 | |
| 1648 | struct rtl8xxxu_fileops rtl8723bu_fops = { |
| 1649 | .parse_efuse = rtl8723bu_parse_efuse, |
| 1650 | .load_firmware = rtl8723bu_load_firmware, |
| 1651 | .power_on = rtl8723bu_power_on, |
| 1652 | .power_off = rtl8723bu_power_off, |
| 1653 | .reset_8051 = rtl8723bu_reset_8051, |
| 1654 | .llt_init = rtl8xxxu_auto_llt_table, |
| 1655 | .init_phy_bb = rtl8723bu_init_phy_bb, |
| 1656 | .init_phy_rf = rtl8723bu_init_phy_rf, |
| 1657 | .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, |
| 1658 | .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate, |
| 1659 | .config_channel = rtl8xxxu_gen2_config_channel, |
| 1660 | .parse_rx_desc = rtl8xxxu_parse_rxdesc24, |
| 1661 | .init_aggregation = rtl8723bu_init_aggregation, |
| 1662 | .init_statistics = rtl8723bu_init_statistics, |
| 1663 | .enable_rf = rtl8723b_enable_rf, |
| 1664 | .disable_rf = rtl8xxxu_gen2_disable_rf, |
| 1665 | .usb_quirks = rtl8xxxu_gen2_usb_quirks, |
| 1666 | .set_tx_power = rtl8723b_set_tx_power, |
| 1667 | .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, |
| 1668 | .report_connect = rtl8xxxu_gen2_report_connect, |
Jes Sorensen | b59415c | 2016-08-19 17:46:40 -0400 | [diff] [blame] | 1669 | .fill_txdesc = rtl8xxxu_fill_txdesc_v2, |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1670 | .writeN_block_size = 1024, |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1671 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), |
| 1672 | .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), |
| 1673 | .has_s0s1 = 1, |
Jes Sorensen | e3ebcd7 | 2016-08-19 17:46:34 -0400 | [diff] [blame] | 1674 | .has_tx_report = 1, |
Jes Sorensen | eed145a | 2016-08-19 17:46:36 -0400 | [diff] [blame] | 1675 | .gen2_thermal_meter = 1, |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1676 | .adda_1t_init = 0x01c00014, |
| 1677 | .adda_1t_path_on = 0x01c00014, |
| 1678 | .adda_2t_path_on_a = 0x01c00014, |
| 1679 | .adda_2t_path_on_b = 0x01c00014, |
| 1680 | .trxff_boundary = 0x3f7f, |
| 1681 | .pbp_rx = PBP_PAGE_SIZE_256, |
| 1682 | .pbp_tx = PBP_PAGE_SIZE_256, |
| 1683 | .mactable = rtl8723b_mac_init_table, |
Jes Sorensen | 44abaa0 | 2016-08-19 17:46:27 -0400 | [diff] [blame] | 1684 | .total_page_num = TX_TOTAL_PAGE_NUM_8723B, |
| 1685 | .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B, |
| 1686 | .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B, |
| 1687 | .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B, |
Jes Sorensen | 6c46ca3 | 2016-04-28 15:19:07 -0400 | [diff] [blame] | 1688 | }; |