Steven J. Hill | 2299c49 | 2012-08-31 16:13:07 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) |
| 7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. |
| 8 | */ |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 9 | #include <linux/bitmap.h> |
| 10 | #include <linux/init.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 11 | #include <linux/smp.h> |
David Howells | ca4d3e67 | 2010-10-07 14:08:54 +0100 | [diff] [blame] | 12 | #include <linux/irq.h> |
Steven J. Hill | dfa762e | 2013-04-10 16:28:36 -0500 | [diff] [blame] | 13 | #include <linux/clocksource.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 14 | |
| 15 | #include <asm/io.h> |
| 16 | #include <asm/gic.h> |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 17 | #include <asm/setup.h> |
| 18 | #include <asm/traps.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 19 | #include <linux/hardirq.h> |
| 20 | #include <asm-generic/bitops/find.h> |
| 21 | |
Steven J. Hill | 28ea215 | 2013-04-10 16:27:50 -0500 | [diff] [blame] | 22 | unsigned int gic_frequency; |
Steven J. Hill | ff86714 | 2013-04-10 16:27:04 -0500 | [diff] [blame] | 23 | unsigned int gic_present; |
Steven J. Hill | 0b271f5 | 2012-08-31 16:05:37 -0500 | [diff] [blame] | 24 | unsigned long _gic_base; |
| 25 | unsigned int gic_irq_base; |
| 26 | unsigned int gic_irq_flags[GIC_NUM_INTRS]; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 27 | |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 28 | /* The index into this array is the vector # of the interrupt. */ |
| 29 | struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS]; |
| 30 | |
Steven J. Hill | 0b271f5 | 2012-08-31 16:05:37 -0500 | [diff] [blame] | 31 | static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 32 | static struct gic_pending_regs pending_regs[NR_CPUS]; |
| 33 | static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; |
| 34 | |
Raghu Gandham | 0ab2b7d | 2013-04-10 16:30:12 -0500 | [diff] [blame] | 35 | #if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC) |
Steven J. Hill | dfa762e | 2013-04-10 16:28:36 -0500 | [diff] [blame] | 36 | cycle_t gic_read_count(void) |
| 37 | { |
| 38 | unsigned int hi, hi2, lo; |
| 39 | |
| 40 | do { |
| 41 | GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi); |
| 42 | GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo); |
| 43 | GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2); |
| 44 | } while (hi2 != hi); |
| 45 | |
| 46 | return (((cycle_t) hi) << 32) + lo; |
| 47 | } |
Raghu Gandham | 0ab2b7d | 2013-04-10 16:30:12 -0500 | [diff] [blame] | 48 | |
| 49 | void gic_write_compare(cycle_t cnt) |
| 50 | { |
| 51 | GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), |
| 52 | (int)(cnt >> 32)); |
| 53 | GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), |
| 54 | (int)(cnt & 0xffffffff)); |
| 55 | } |
| 56 | |
Paul Burton | 414408d0 | 2014-03-05 11:35:53 +0000 | [diff] [blame^] | 57 | void gic_write_cpu_compare(cycle_t cnt, int cpu) |
| 58 | { |
| 59 | unsigned long flags; |
| 60 | |
| 61 | local_irq_save(flags); |
| 62 | |
| 63 | GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu); |
| 64 | GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI), |
| 65 | (int)(cnt >> 32)); |
| 66 | GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO), |
| 67 | (int)(cnt & 0xffffffff)); |
| 68 | |
| 69 | local_irq_restore(flags); |
| 70 | } |
| 71 | |
Raghu Gandham | 0ab2b7d | 2013-04-10 16:30:12 -0500 | [diff] [blame] | 72 | cycle_t gic_read_compare(void) |
| 73 | { |
| 74 | unsigned int hi, lo; |
| 75 | |
| 76 | GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), hi); |
| 77 | GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), lo); |
| 78 | |
| 79 | return (((cycle_t) hi) << 32) + lo; |
| 80 | } |
Steven J. Hill | dfa762e | 2013-04-10 16:28:36 -0500 | [diff] [blame] | 81 | #endif |
| 82 | |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 83 | unsigned int gic_get_timer_pending(void) |
| 84 | { |
| 85 | unsigned int vpe_pending; |
| 86 | |
| 87 | GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0); |
| 88 | GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending); |
| 89 | return (vpe_pending & GIC_VPE_PEND_TIMER_MSK); |
| 90 | } |
| 91 | |
| 92 | void gic_bind_eic_interrupt(int irq, int set) |
| 93 | { |
| 94 | /* Convert irq vector # to hw int # */ |
| 95 | irq -= GIC_PIN_TO_VEC_OFFSET; |
| 96 | |
| 97 | /* Set irq to use shadow set */ |
| 98 | GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set); |
| 99 | } |
| 100 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 101 | void gic_send_ipi(unsigned int intr) |
| 102 | { |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 103 | GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 104 | } |
| 105 | |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 106 | static void gic_eic_irq_dispatch(void) |
| 107 | { |
| 108 | unsigned int cause = read_c0_cause(); |
| 109 | int irq; |
| 110 | |
| 111 | irq = (cause & ST0_IM) >> STATUSB_IP2; |
| 112 | if (irq == 0) |
| 113 | irq = -1; |
| 114 | |
| 115 | if (irq >= 0) |
| 116 | do_IRQ(gic_irq_base + irq); |
| 117 | else |
| 118 | spurious_interrupt(); |
| 119 | } |
| 120 | |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 121 | static void __init vpe_local_setup(unsigned int numvpes) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 122 | { |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 123 | unsigned long timer_intr = GIC_INT_TMR; |
| 124 | unsigned long perf_intr = GIC_INT_PERFCTR; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 125 | unsigned int vpe_ctl; |
Steven J. Hill | 2299c49 | 2012-08-31 16:13:07 -0500 | [diff] [blame] | 126 | int i; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 127 | |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 128 | if (cpu_has_veic) { |
| 129 | /* |
| 130 | * GIC timer interrupt -> CPU HW Int X (vector X+2) -> |
| 131 | * map to pin X+2-1 (since GIC adds 1) |
| 132 | */ |
| 133 | timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET); |
| 134 | /* |
| 135 | * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) -> |
| 136 | * map to pin X+2-1 (since GIC adds 1) |
| 137 | */ |
| 138 | perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET); |
| 139 | } |
| 140 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 141 | /* |
| 142 | * Setup the default performance counter timer interrupts |
| 143 | * for all VPEs |
| 144 | */ |
| 145 | for (i = 0; i < numvpes; i++) { |
| 146 | GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
| 147 | |
| 148 | /* Are Interrupts locally routable? */ |
| 149 | GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl); |
| 150 | if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK) |
| 151 | GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 152 | GIC_MAP_TO_PIN_MSK | timer_intr); |
| 153 | if (cpu_has_veic) { |
| 154 | set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET, |
| 155 | gic_eic_irq_dispatch); |
| 156 | gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK; |
| 157 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 158 | |
| 159 | if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK) |
| 160 | GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 161 | GIC_MAP_TO_PIN_MSK | perf_intr); |
| 162 | if (cpu_has_veic) { |
| 163 | set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch); |
| 164 | gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK; |
| 165 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 166 | } |
| 167 | } |
| 168 | |
Raghu Gandham | 0ab2b7d | 2013-04-10 16:30:12 -0500 | [diff] [blame] | 169 | unsigned int gic_compare_int(void) |
| 170 | { |
| 171 | unsigned int pending; |
| 172 | |
| 173 | GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_PEND), pending); |
| 174 | if (pending & GIC_VPE_PEND_CMP_MSK) |
| 175 | return 1; |
| 176 | else |
| 177 | return 0; |
| 178 | } |
| 179 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 180 | unsigned int gic_get_int(void) |
| 181 | { |
| 182 | unsigned int i; |
| 183 | unsigned long *pending, *intrmask, *pcpu_mask; |
| 184 | unsigned long *pending_abs, *intrmask_abs; |
| 185 | |
| 186 | /* Get per-cpu bitmaps */ |
| 187 | pending = pending_regs[smp_processor_id()].pending; |
| 188 | intrmask = intrmask_regs[smp_processor_id()].intrmask; |
| 189 | pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask; |
| 190 | |
| 191 | pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED, |
| 192 | GIC_SH_PEND_31_0_OFS); |
| 193 | intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED, |
| 194 | GIC_SH_MASK_31_0_OFS); |
| 195 | |
| 196 | for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) { |
| 197 | GICREAD(*pending_abs, pending[i]); |
| 198 | GICREAD(*intrmask_abs, intrmask[i]); |
| 199 | pending_abs++; |
| 200 | intrmask_abs++; |
| 201 | } |
| 202 | |
| 203 | bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS); |
| 204 | bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS); |
| 205 | |
Steven J. Hill | 2299c49 | 2012-08-31 16:13:07 -0500 | [diff] [blame] | 206 | return find_first_bit(pending, GIC_NUM_INTRS); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 207 | } |
| 208 | |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 209 | static void gic_mask_irq(struct irq_data *d) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 210 | { |
Steven J. Hill | 2299c49 | 2012-08-31 16:13:07 -0500 | [diff] [blame] | 211 | GIC_CLR_INTR_MASK(d->irq - gic_irq_base); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 212 | } |
| 213 | |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 214 | static void gic_unmask_irq(struct irq_data *d) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 215 | { |
Steven J. Hill | 2299c49 | 2012-08-31 16:13:07 -0500 | [diff] [blame] | 216 | GIC_SET_INTR_MASK(d->irq - gic_irq_base); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | #ifdef CONFIG_SMP |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 220 | static DEFINE_SPINLOCK(gic_lock); |
| 221 | |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 222 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
| 223 | bool force) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 224 | { |
Steven J. Hill | 2299c49 | 2012-08-31 16:13:07 -0500 | [diff] [blame] | 225 | unsigned int irq = (d->irq - gic_irq_base); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 226 | cpumask_t tmp = CPU_MASK_NONE; |
| 227 | unsigned long flags; |
| 228 | int i; |
| 229 | |
Rusty Russell | 0de2652 | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 230 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 231 | if (cpus_empty(tmp)) |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 232 | return -1; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 233 | |
| 234 | /* Assumption : cpumask refers to a single CPU */ |
| 235 | spin_lock_irqsave(&gic_lock, flags); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 236 | |
Tony Wu | c214c03 | 2013-06-21 10:13:08 +0000 | [diff] [blame] | 237 | /* Re-route this IRQ */ |
| 238 | GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp)); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 239 | |
Tony Wu | c214c03 | 2013-06-21 10:13:08 +0000 | [diff] [blame] | 240 | /* Update the pcpu_masks */ |
| 241 | for (i = 0; i < NR_CPUS; i++) |
| 242 | clear_bit(irq, pcpu_masks[i].pcpu_mask); |
| 243 | set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); |
| 244 | |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 245 | cpumask_copy(d->affinity, cpumask); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 246 | spin_unlock_irqrestore(&gic_lock, flags); |
| 247 | |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 248 | return IRQ_SET_MASK_OK_NOCOPY; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 249 | } |
| 250 | #endif |
| 251 | |
| 252 | static struct irq_chip gic_irq_controller = { |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 253 | .name = "MIPS GIC", |
| 254 | .irq_ack = gic_irq_ack, |
| 255 | .irq_mask = gic_mask_irq, |
| 256 | .irq_mask_ack = gic_mask_irq, |
| 257 | .irq_unmask = gic_unmask_irq, |
Steven J. Hill | ec167f2 | 2012-08-31 16:20:08 -0500 | [diff] [blame] | 258 | .irq_eoi = gic_finish_irq, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 259 | #ifdef CONFIG_SMP |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 260 | .irq_set_affinity = gic_set_affinity, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 261 | #endif |
| 262 | }; |
| 263 | |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 264 | static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, |
| 265 | unsigned int pin, unsigned int polarity, unsigned int trigtype, |
| 266 | unsigned int flags) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 267 | { |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 268 | struct gic_shared_intr_map *map_ptr; |
| 269 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 270 | /* Setup Intr to Pin mapping */ |
| 271 | if (pin & GIC_MAP_TO_NMI_MSK) { |
| 272 | GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin); |
| 273 | /* FIXME: hack to route NMI to all cpu's */ |
| 274 | for (cpu = 0; cpu < NR_CPUS; cpu += 32) { |
| 275 | GICWRITE(GIC_REG_ADDR(SHARED, |
| 276 | GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)), |
| 277 | 0xffffffff); |
| 278 | } |
| 279 | } else { |
| 280 | GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), |
| 281 | GIC_MAP_TO_PIN_MSK | pin); |
| 282 | /* Setup Intr to CPU mapping */ |
| 283 | GIC_SH_MAP_TO_VPE_SMASK(intr, cpu); |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 284 | if (cpu_has_veic) { |
| 285 | set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET, |
| 286 | gic_eic_irq_dispatch); |
| 287 | map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET]; |
| 288 | if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR) |
| 289 | BUG(); |
| 290 | map_ptr->intr_list[map_ptr->num_shared_intr++] = intr; |
| 291 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 292 | } |
| 293 | |
| 294 | /* Setup Intr Polarity */ |
| 295 | GIC_SET_POLARITY(intr, polarity); |
| 296 | |
| 297 | /* Setup Intr Trigger Type */ |
| 298 | GIC_SET_TRIGGER(intr, trigtype); |
| 299 | |
| 300 | /* Init Intr Masks */ |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 301 | GIC_CLR_INTR_MASK(intr); |
| 302 | /* Initialise per-cpu Interrupt software masks */ |
| 303 | if (flags & GIC_FLAG_IPI) |
| 304 | set_bit(intr, pcpu_masks[cpu].pcpu_mask); |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 305 | if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0)) |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 306 | GIC_SET_INTR_MASK(intr); |
| 307 | if (trigtype == GIC_TRIG_EDGE) |
Steven J. Hill | 0b271f5 | 2012-08-31 16:05:37 -0500 | [diff] [blame] | 308 | gic_irq_flags[intr] |= GIC_TRIG_EDGE; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 309 | } |
| 310 | |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 311 | static void __init gic_basic_init(int numintrs, int numvpes, |
| 312 | struct gic_intr_map *intrmap, int mapsize) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 313 | { |
| 314 | unsigned int i, cpu; |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 315 | unsigned int pin_offset = 0; |
| 316 | |
| 317 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 318 | |
| 319 | /* Setup defaults */ |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 320 | for (i = 0; i < numintrs; i++) { |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 321 | GIC_SET_POLARITY(i, GIC_POL_POS); |
| 322 | GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL); |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 323 | GIC_CLR_INTR_MASK(i); |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 324 | if (i < GIC_NUM_INTRS) { |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 325 | gic_irq_flags[i] = 0; |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 326 | gic_shared_intr_map[i].num_shared_intr = 0; |
| 327 | gic_shared_intr_map[i].local_intr_mask = 0; |
| 328 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 329 | } |
| 330 | |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 331 | /* |
| 332 | * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract |
| 333 | * one because the GIC will add one (since 0=no intr). |
| 334 | */ |
| 335 | if (cpu_has_veic) |
| 336 | pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET); |
| 337 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 338 | /* Setup specifics */ |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 339 | for (i = 0; i < mapsize; i++) { |
| 340 | cpu = intrmap[i].cpunum; |
Ralf Baechle | 863cb9b | 2010-09-17 17:07:48 +0100 | [diff] [blame] | 341 | if (cpu == GIC_UNUSED) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 342 | continue; |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 343 | if (cpu == 0 && i != 0 && intrmap[i].flags == 0) |
Tim Anderson | a214cef | 2009-06-17 16:22:25 -0700 | [diff] [blame] | 344 | continue; |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 345 | gic_setup_intr(i, |
| 346 | intrmap[i].cpunum, |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 347 | intrmap[i].pin + pin_offset, |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 348 | intrmap[i].polarity, |
| 349 | intrmap[i].trigtype, |
| 350 | intrmap[i].flags); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 351 | } |
| 352 | |
| 353 | vpe_local_setup(numvpes); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 354 | } |
| 355 | |
| 356 | void __init gic_init(unsigned long gic_base_addr, |
| 357 | unsigned long gic_addrspace_size, |
| 358 | struct gic_intr_map *intr_map, unsigned int intr_map_size, |
| 359 | unsigned int irqbase) |
| 360 | { |
| 361 | unsigned int gicconfig; |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 362 | int numvpes, numintrs; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 363 | |
| 364 | _gic_base = (unsigned long) ioremap_nocache(gic_base_addr, |
| 365 | gic_addrspace_size); |
Steven J. Hill | 0b271f5 | 2012-08-31 16:05:37 -0500 | [diff] [blame] | 366 | gic_irq_base = irqbase; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 367 | |
| 368 | GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); |
| 369 | numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> |
| 370 | GIC_SH_CONFIG_NUMINTRS_SHF; |
| 371 | numintrs = ((numintrs + 1) * 8); |
| 372 | |
| 373 | numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> |
| 374 | GIC_SH_CONFIG_NUMVPES_SHF; |
Steven J. Hill | 3234f44 | 2012-08-31 16:23:49 -0500 | [diff] [blame] | 375 | numvpes = numvpes + 1; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 376 | |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 377 | gic_basic_init(numintrs, numvpes, intr_map, intr_map_size); |
Steven J. Hill | 0b271f5 | 2012-08-31 16:05:37 -0500 | [diff] [blame] | 378 | |
| 379 | gic_platform_init(numintrs, &gic_irq_controller); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 380 | } |