blob: 7ef39a6e8c065afc97bba75dd26b2b691be95e4b [file] [log] [blame]
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001/*
Bryan Wu131b17d2007-12-04 23:45:12 -08002 * File: drivers/spi/bfin5xx_spi.c
3 * Maintainer:
4 * Bryan Wu <bryan.wu@analog.com>
5 * Original Author:
6 * Luke Yang (Analog Devices Inc.)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07007 *
Bryan Wu131b17d2007-12-04 23:45:12 -08008 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
Wu, Bryana5f6abd2007-05-06 14:50:34 -070011 *
12 * Modified:
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
Bryan Wu131b17d2007-12-04 23:45:12 -080015 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
Bryan Wua32c6912007-12-04 23:45:15 -080016 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
Wu, Bryana5f6abd2007-05-06 14:50:34 -070018 *
Bryan Wu131b17d2007-12-04 23:45:12 -080019 * Copyright 2004-2007 Analog Devices Inc.
Wu, Bryana5f6abd2007-05-06 14:50:34 -070020 *
21 * This program is free software ; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation ; either version 2, or (at your option)
24 * any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program ; see the file COPYING.
33 * If not, write to the Free Software Foundation,
34 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
35 */
36
37#include <linux/init.h>
38#include <linux/module.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080039#include <linux/delay.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070040#include <linux/device.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080041#include <linux/io.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070042#include <linux/ioport.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080043#include <linux/irq.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070044#include <linux/errno.h>
45#include <linux/interrupt.h>
46#include <linux/platform_device.h>
47#include <linux/dma-mapping.h>
48#include <linux/spi/spi.h>
49#include <linux/workqueue.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070050
Wu, Bryana5f6abd2007-05-06 14:50:34 -070051#include <asm/dma.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080052#include <asm/portmux.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070053#include <asm/bfin5xx_spi.h>
54
Bryan Wua32c6912007-12-04 23:45:15 -080055#define DRV_NAME "bfin-spi"
56#define DRV_AUTHOR "Bryan Wu, Luke Yang"
Will Newton6b1a8022007-12-10 15:49:26 -080057#define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
Bryan Wua32c6912007-12-04 23:45:15 -080058#define DRV_VERSION "1.0"
59
60MODULE_AUTHOR(DRV_AUTHOR);
61MODULE_DESCRIPTION(DRV_DESC);
Wu, Bryana5f6abd2007-05-06 14:50:34 -070062MODULE_LICENSE("GPL");
63
Bryan Wubb90eb02007-12-04 23:45:18 -080064#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
Wu, Bryana5f6abd2007-05-06 14:50:34 -070065
Bryan Wubb90eb02007-12-04 23:45:18 -080066#define START_STATE ((void *)0)
67#define RUNNING_STATE ((void *)1)
68#define DONE_STATE ((void *)2)
69#define ERROR_STATE ((void *)-1)
70#define QUEUE_RUNNING 0
71#define QUEUE_STOPPED 1
Wu, Bryana5f6abd2007-05-06 14:50:34 -070072
73struct driver_data {
74 /* Driver model hookup */
75 struct platform_device *pdev;
76
77 /* SPI framework hookup */
78 struct spi_master *master;
79
Bryan Wubb90eb02007-12-04 23:45:18 -080080 /* Regs base of SPI controller */
Bryan Wuf4521262007-12-04 23:45:22 -080081 void __iomem *regs_base;
Bryan Wubb90eb02007-12-04 23:45:18 -080082
Bryan Wu003d9222007-12-04 23:45:22 -080083 /* Pin request list */
84 u16 *pin_req;
85
Wu, Bryana5f6abd2007-05-06 14:50:34 -070086 /* BFIN hookup */
87 struct bfin5xx_spi_master *master_info;
88
89 /* Driver message queue */
90 struct workqueue_struct *workqueue;
91 struct work_struct pump_messages;
92 spinlock_t lock;
93 struct list_head queue;
94 int busy;
95 int run;
96
97 /* Message Transfer pump */
98 struct tasklet_struct pump_transfers;
99
100 /* Current message transfer state info */
101 struct spi_message *cur_msg;
102 struct spi_transfer *cur_transfer;
103 struct chip_data *cur_chip;
104 size_t len_in_bytes;
105 size_t len;
106 void *tx;
107 void *tx_end;
108 void *rx;
109 void *rx_end;
Bryan Wubb90eb02007-12-04 23:45:18 -0800110
111 /* DMA stuffs */
112 int dma_channel;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700113 int dma_mapped;
Bryan Wubb90eb02007-12-04 23:45:18 -0800114 int dma_requested;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700115 dma_addr_t rx_dma;
116 dma_addr_t tx_dma;
Bryan Wubb90eb02007-12-04 23:45:18 -0800117
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700118 size_t rx_map_len;
119 size_t tx_map_len;
120 u8 n_bytes;
Bryan Wufad91c82007-12-04 23:45:14 -0800121 int cs_change;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700122 void (*write) (struct driver_data *);
123 void (*read) (struct driver_data *);
124 void (*duplex) (struct driver_data *);
125};
126
127struct chip_data {
128 u16 ctl_reg;
129 u16 baud;
130 u16 flag;
131
132 u8 chip_select_num;
133 u8 n_bytes;
Bryan Wu88b40362007-05-21 18:32:16 +0800134 u8 width; /* 0 or 1 */
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700135 u8 enable_dma;
136 u8 bits_per_word; /* 8 or 16 */
137 u8 cs_change_per_word;
Bryan Wu62310e52007-12-04 23:45:20 -0800138 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700139 void (*write) (struct driver_data *);
140 void (*read) (struct driver_data *);
141 void (*duplex) (struct driver_data *);
142};
143
Bryan Wubb90eb02007-12-04 23:45:18 -0800144#define DEFINE_SPI_REG(reg, off) \
145static inline u16 read_##reg(struct driver_data *drv_data) \
146 { return bfin_read16(drv_data->regs_base + off); } \
147static inline void write_##reg(struct driver_data *drv_data, u16 v) \
148 { bfin_write16(drv_data->regs_base + off, v); }
149
150DEFINE_SPI_REG(CTRL, 0x00)
151DEFINE_SPI_REG(FLAG, 0x04)
152DEFINE_SPI_REG(STAT, 0x08)
153DEFINE_SPI_REG(TDBR, 0x0C)
154DEFINE_SPI_REG(RDBR, 0x10)
155DEFINE_SPI_REG(BAUD, 0x14)
156DEFINE_SPI_REG(SHAW, 0x18)
157
Bryan Wu88b40362007-05-21 18:32:16 +0800158static void bfin_spi_enable(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700159{
160 u16 cr;
161
Bryan Wubb90eb02007-12-04 23:45:18 -0800162 cr = read_CTRL(drv_data);
163 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700164}
165
Bryan Wu88b40362007-05-21 18:32:16 +0800166static void bfin_spi_disable(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700167{
168 u16 cr;
169
Bryan Wubb90eb02007-12-04 23:45:18 -0800170 cr = read_CTRL(drv_data);
171 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700172}
173
174/* Caculate the SPI_BAUD register value based on input HZ */
175static u16 hz_to_spi_baud(u32 speed_hz)
176{
177 u_long sclk = get_sclk();
178 u16 spi_baud = (sclk / (2 * speed_hz));
179
180 if ((sclk % (2 * speed_hz)) > 0)
181 spi_baud++;
182
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700183 return spi_baud;
184}
185
186static int flush(struct driver_data *drv_data)
187{
188 unsigned long limit = loops_per_jiffy << 1;
189
190 /* wait for stop and clear stat */
Bryan Wubb90eb02007-12-04 23:45:18 -0800191 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
Bryan Wud8c05002007-12-04 23:45:21 -0800192 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700193
Bryan Wubb90eb02007-12-04 23:45:18 -0800194 write_STAT(drv_data, BIT_STAT_CLR);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700195
196 return limit;
197}
198
Bryan Wufad91c82007-12-04 23:45:14 -0800199/* Chip select operation functions for cs_change flag */
Bryan Wubb90eb02007-12-04 23:45:18 -0800200static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
Bryan Wufad91c82007-12-04 23:45:14 -0800201{
Bryan Wubb90eb02007-12-04 23:45:18 -0800202 u16 flag = read_FLAG(drv_data);
Bryan Wufad91c82007-12-04 23:45:14 -0800203
204 flag |= chip->flag;
205 flag &= ~(chip->flag << 8);
206
Bryan Wubb90eb02007-12-04 23:45:18 -0800207 write_FLAG(drv_data, flag);
Bryan Wufad91c82007-12-04 23:45:14 -0800208}
209
Bryan Wubb90eb02007-12-04 23:45:18 -0800210static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
Bryan Wufad91c82007-12-04 23:45:14 -0800211{
Bryan Wubb90eb02007-12-04 23:45:18 -0800212 u16 flag = read_FLAG(drv_data);
Bryan Wufad91c82007-12-04 23:45:14 -0800213
214 flag |= (chip->flag << 8);
215
Bryan Wubb90eb02007-12-04 23:45:18 -0800216 write_FLAG(drv_data, flag);
Bryan Wu62310e52007-12-04 23:45:20 -0800217
218 /* Move delay here for consistency */
219 if (chip->cs_chg_udelay)
220 udelay(chip->cs_chg_udelay);
Bryan Wufad91c82007-12-04 23:45:14 -0800221}
222
Sonic Zhang7c4ef092007-12-04 23:45:16 -0800223#define MAX_SPI_SSEL 7
Bryan Wu5fec5b52007-12-04 23:45:13 -0800224
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700225/* stop controller and re-config current chip*/
Bryan Wu5fec5b52007-12-04 23:45:13 -0800226static int restore_state(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700227{
228 struct chip_data *chip = drv_data->cur_chip;
Bryan Wu5fec5b52007-12-04 23:45:13 -0800229 int ret = 0;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700230
231 /* Clear status and disable clock */
Bryan Wubb90eb02007-12-04 23:45:18 -0800232 write_STAT(drv_data, BIT_STAT_CLR);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700233 bfin_spi_disable(drv_data);
Bryan Wu88b40362007-05-21 18:32:16 +0800234 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700235
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700236 /* Load the registers */
Bryan Wubb90eb02007-12-04 23:45:18 -0800237 write_CTRL(drv_data, chip->ctl_reg);
Bryan Wu092e1fd2007-12-04 23:45:23 -0800238 write_BAUD(drv_data, chip->baud);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800239
240 bfin_spi_enable(drv_data);
Sonic Zhang07612e52007-12-04 23:45:21 -0800241 cs_active(drv_data, chip);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800242
Bryan Wu5fec5b52007-12-04 23:45:13 -0800243 if (ret)
244 dev_dbg(&drv_data->pdev->dev,
245 ": request chip select number %d failed\n",
246 chip->chip_select_num);
247
248 return ret;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700249}
250
251/* used to kick off transfer in rx mode */
Bryan Wubb90eb02007-12-04 23:45:18 -0800252static unsigned short dummy_read(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700253{
254 unsigned short tmp;
Bryan Wubb90eb02007-12-04 23:45:18 -0800255 tmp = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700256 return tmp;
257}
258
259static void null_writer(struct driver_data *drv_data)
260{
261 u8 n_bytes = drv_data->n_bytes;
262
263 while (drv_data->tx < drv_data->tx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800264 write_TDBR(drv_data, 0);
265 while ((read_STAT(drv_data) & BIT_STAT_TXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800266 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700267 drv_data->tx += n_bytes;
268 }
269}
270
271static void null_reader(struct driver_data *drv_data)
272{
273 u8 n_bytes = drv_data->n_bytes;
Bryan Wubb90eb02007-12-04 23:45:18 -0800274 dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700275
276 while (drv_data->rx < drv_data->rx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800277 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800278 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800279 dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700280 drv_data->rx += n_bytes;
281 }
282}
283
284static void u8_writer(struct driver_data *drv_data)
285{
Bryan Wu131b17d2007-12-04 23:45:12 -0800286 dev_dbg(&drv_data->pdev->dev,
Bryan Wubb90eb02007-12-04 23:45:18 -0800287 "cr8-s is 0x%x\n", read_STAT(drv_data));
Sonic Zhangcc487e72007-12-04 23:45:17 -0800288
Sonic Zhang3f479a62007-12-04 23:45:18 -0800289 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800290 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800291 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800292
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700293 while (drv_data->tx < drv_data->tx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800294 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
295 while (read_STAT(drv_data) & BIT_STAT_TXS)
Bryan Wud8c05002007-12-04 23:45:21 -0800296 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700297 ++drv_data->tx;
298 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700299}
300
301static void u8_cs_chg_writer(struct driver_data *drv_data)
302{
303 struct chip_data *chip = drv_data->cur_chip;
304
Sonic Zhang3f479a62007-12-04 23:45:18 -0800305 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800306 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800307 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800308
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700309 while (drv_data->tx < drv_data->tx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800310 cs_active(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700311
Bryan Wubb90eb02007-12-04 23:45:18 -0800312 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
313 while (read_STAT(drv_data) & BIT_STAT_TXS)
Bryan Wud8c05002007-12-04 23:45:21 -0800314 cpu_relax();
Bryan Wu62310e52007-12-04 23:45:20 -0800315
Bryan Wubb90eb02007-12-04 23:45:18 -0800316 cs_deactive(drv_data, chip);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800317
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700318 ++drv_data->tx;
319 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700320}
321
322static void u8_reader(struct driver_data *drv_data)
323{
Bryan Wu131b17d2007-12-04 23:45:12 -0800324 dev_dbg(&drv_data->pdev->dev,
Bryan Wubb90eb02007-12-04 23:45:18 -0800325 "cr-8 is 0x%x\n", read_STAT(drv_data));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700326
Sonic Zhang3f479a62007-12-04 23:45:18 -0800327 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800328 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800329 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800330
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700331 /* clear TDBR buffer before read(else it will be shifted out) */
Bryan Wubb90eb02007-12-04 23:45:18 -0800332 write_TDBR(drv_data, 0xFFFF);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700333
Bryan Wubb90eb02007-12-04 23:45:18 -0800334 dummy_read(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800335
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700336 while (drv_data->rx < drv_data->rx_end - 1) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800337 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800338 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800339 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700340 ++drv_data->rx;
341 }
342
Bryan Wubb90eb02007-12-04 23:45:18 -0800343 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800344 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800345 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700346 ++drv_data->rx;
347}
348
349static void u8_cs_chg_reader(struct driver_data *drv_data)
350{
351 struct chip_data *chip = drv_data->cur_chip;
352
Sonic Zhang3f479a62007-12-04 23:45:18 -0800353 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800354 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800355 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800356
Sonic Zhangcc487e72007-12-04 23:45:17 -0800357 /* clear TDBR buffer before read(else it will be shifted out) */
Bryan Wubb90eb02007-12-04 23:45:18 -0800358 write_TDBR(drv_data, 0xFFFF);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700359
Bryan Wubb90eb02007-12-04 23:45:18 -0800360 cs_active(drv_data, chip);
361 dummy_read(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800362
363 while (drv_data->rx < drv_data->rx_end - 1) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800364 cs_deactive(drv_data, chip);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800365
Bryan Wubb90eb02007-12-04 23:45:18 -0800366 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800367 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800368 cs_active(drv_data, chip);
369 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700370 ++drv_data->rx;
371 }
Bryan Wubb90eb02007-12-04 23:45:18 -0800372 cs_deactive(drv_data, chip);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800373
Bryan Wubb90eb02007-12-04 23:45:18 -0800374 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800375 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800376 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800377 ++drv_data->rx;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700378}
379
380static void u8_duplex(struct driver_data *drv_data)
381{
Sonic Zhang3f479a62007-12-04 23:45:18 -0800382 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800383 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800384 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800385
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700386 /* in duplex mode, clk is triggered by writing of TDBR */
387 while (drv_data->rx < drv_data->rx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800388 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
389 while (read_STAT(drv_data) & BIT_STAT_TXS)
Bryan Wud8c05002007-12-04 23:45:21 -0800390 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800391 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800392 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800393 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700394 ++drv_data->rx;
395 ++drv_data->tx;
396 }
397}
398
399static void u8_cs_chg_duplex(struct driver_data *drv_data)
400{
401 struct chip_data *chip = drv_data->cur_chip;
402
Sonic Zhang3f479a62007-12-04 23:45:18 -0800403 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800404 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800405 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800406
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700407 while (drv_data->rx < drv_data->rx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800408 cs_active(drv_data, chip);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800409
Bryan Wubb90eb02007-12-04 23:45:18 -0800410 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
411 while (read_STAT(drv_data) & BIT_STAT_TXS)
Bryan Wud8c05002007-12-04 23:45:21 -0800412 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800413 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800414 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800415 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
Bryan Wu62310e52007-12-04 23:45:20 -0800416
Bryan Wubb90eb02007-12-04 23:45:18 -0800417 cs_deactive(drv_data, chip);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800418
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700419 ++drv_data->rx;
420 ++drv_data->tx;
421 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700422}
423
424static void u16_writer(struct driver_data *drv_data)
425{
Bryan Wu131b17d2007-12-04 23:45:12 -0800426 dev_dbg(&drv_data->pdev->dev,
Bryan Wubb90eb02007-12-04 23:45:18 -0800427 "cr16 is 0x%x\n", read_STAT(drv_data));
Bryan Wu88b40362007-05-21 18:32:16 +0800428
Sonic Zhang3f479a62007-12-04 23:45:18 -0800429 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800430 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800431 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800432
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700433 while (drv_data->tx < drv_data->tx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800434 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
435 while ((read_STAT(drv_data) & BIT_STAT_TXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800436 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700437 drv_data->tx += 2;
438 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700439}
440
441static void u16_cs_chg_writer(struct driver_data *drv_data)
442{
443 struct chip_data *chip = drv_data->cur_chip;
444
Sonic Zhang3f479a62007-12-04 23:45:18 -0800445 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800446 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800447 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800448
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700449 while (drv_data->tx < drv_data->tx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800450 cs_active(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700451
Bryan Wubb90eb02007-12-04 23:45:18 -0800452 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
453 while ((read_STAT(drv_data) & BIT_STAT_TXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800454 cpu_relax();
Bryan Wu62310e52007-12-04 23:45:20 -0800455
Bryan Wubb90eb02007-12-04 23:45:18 -0800456 cs_deactive(drv_data, chip);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800457
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700458 drv_data->tx += 2;
459 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700460}
461
462static void u16_reader(struct driver_data *drv_data)
463{
Bryan Wu88b40362007-05-21 18:32:16 +0800464 dev_dbg(&drv_data->pdev->dev,
Bryan Wubb90eb02007-12-04 23:45:18 -0800465 "cr-16 is 0x%x\n", read_STAT(drv_data));
Sonic Zhangcc487e72007-12-04 23:45:17 -0800466
Sonic Zhang3f479a62007-12-04 23:45:18 -0800467 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800468 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800469 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800470
Sonic Zhangcc487e72007-12-04 23:45:17 -0800471 /* clear TDBR buffer before read(else it will be shifted out) */
Bryan Wubb90eb02007-12-04 23:45:18 -0800472 write_TDBR(drv_data, 0xFFFF);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800473
Bryan Wubb90eb02007-12-04 23:45:18 -0800474 dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700475
476 while (drv_data->rx < (drv_data->rx_end - 2)) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800477 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800478 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800479 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700480 drv_data->rx += 2;
481 }
482
Bryan Wubb90eb02007-12-04 23:45:18 -0800483 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800484 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800485 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700486 drv_data->rx += 2;
487}
488
489static void u16_cs_chg_reader(struct driver_data *drv_data)
490{
491 struct chip_data *chip = drv_data->cur_chip;
492
Sonic Zhang3f479a62007-12-04 23:45:18 -0800493 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800494 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800495 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800496
Sonic Zhangcc487e72007-12-04 23:45:17 -0800497 /* clear TDBR buffer before read(else it will be shifted out) */
Bryan Wubb90eb02007-12-04 23:45:18 -0800498 write_TDBR(drv_data, 0xFFFF);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700499
Bryan Wubb90eb02007-12-04 23:45:18 -0800500 cs_active(drv_data, chip);
501 dummy_read(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800502
Bryan Wuc3061ab2007-12-04 23:45:19 -0800503 while (drv_data->rx < drv_data->rx_end - 2) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800504 cs_deactive(drv_data, chip);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800505
Bryan Wubb90eb02007-12-04 23:45:18 -0800506 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800507 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800508 cs_active(drv_data, chip);
509 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700510 drv_data->rx += 2;
511 }
Bryan Wubb90eb02007-12-04 23:45:18 -0800512 cs_deactive(drv_data, chip);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800513
Bryan Wubb90eb02007-12-04 23:45:18 -0800514 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800515 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800516 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800517 drv_data->rx += 2;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700518}
519
520static void u16_duplex(struct driver_data *drv_data)
521{
Sonic Zhang3f479a62007-12-04 23:45:18 -0800522 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800523 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800524 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800525
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700526 /* in duplex mode, clk is triggered by writing of TDBR */
527 while (drv_data->tx < drv_data->tx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800528 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
529 while (read_STAT(drv_data) & BIT_STAT_TXS)
Bryan Wud8c05002007-12-04 23:45:21 -0800530 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800531 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800532 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800533 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700534 drv_data->rx += 2;
535 drv_data->tx += 2;
536 }
537}
538
539static void u16_cs_chg_duplex(struct driver_data *drv_data)
540{
541 struct chip_data *chip = drv_data->cur_chip;
542
Sonic Zhang3f479a62007-12-04 23:45:18 -0800543 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800544 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800545 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800546
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700547 while (drv_data->tx < drv_data->tx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800548 cs_active(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700549
Bryan Wubb90eb02007-12-04 23:45:18 -0800550 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
551 while (read_STAT(drv_data) & BIT_STAT_TXS)
Bryan Wud8c05002007-12-04 23:45:21 -0800552 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800553 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800554 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800555 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
Bryan Wu62310e52007-12-04 23:45:20 -0800556
Bryan Wubb90eb02007-12-04 23:45:18 -0800557 cs_deactive(drv_data, chip);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800558
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700559 drv_data->rx += 2;
560 drv_data->tx += 2;
561 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700562}
563
564/* test if ther is more transfer to be done */
565static void *next_transfer(struct driver_data *drv_data)
566{
567 struct spi_message *msg = drv_data->cur_msg;
568 struct spi_transfer *trans = drv_data->cur_transfer;
569
570 /* Move to next transfer */
571 if (trans->transfer_list.next != &msg->transfers) {
572 drv_data->cur_transfer =
573 list_entry(trans->transfer_list.next,
574 struct spi_transfer, transfer_list);
575 return RUNNING_STATE;
576 } else
577 return DONE_STATE;
578}
579
580/*
581 * caller already set message->status;
582 * dma and pio irqs are blocked give finished message back
583 */
584static void giveback(struct driver_data *drv_data)
585{
Bryan Wufad91c82007-12-04 23:45:14 -0800586 struct chip_data *chip = drv_data->cur_chip;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700587 struct spi_transfer *last_transfer;
588 unsigned long flags;
589 struct spi_message *msg;
590
591 spin_lock_irqsave(&drv_data->lock, flags);
592 msg = drv_data->cur_msg;
593 drv_data->cur_msg = NULL;
594 drv_data->cur_transfer = NULL;
595 drv_data->cur_chip = NULL;
596 queue_work(drv_data->workqueue, &drv_data->pump_messages);
597 spin_unlock_irqrestore(&drv_data->lock, flags);
598
599 last_transfer = list_entry(msg->transfers.prev,
600 struct spi_transfer, transfer_list);
601
602 msg->state = NULL;
603
604 /* disable chip select signal. And not stop spi in autobuffer mode */
605 if (drv_data->tx_dma != 0xFFFF) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800606 cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700607 bfin_spi_disable(drv_data);
608 }
609
Bryan Wufad91c82007-12-04 23:45:14 -0800610 if (!drv_data->cs_change)
Bryan Wubb90eb02007-12-04 23:45:18 -0800611 cs_deactive(drv_data, chip);
Bryan Wufad91c82007-12-04 23:45:14 -0800612
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700613 if (msg->complete)
614 msg->complete(msg->context);
615}
616
Bryan Wu88b40362007-05-21 18:32:16 +0800617static irqreturn_t dma_irq_handler(int irq, void *dev_id)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700618{
619 struct driver_data *drv_data = (struct driver_data *)dev_id;
Bryan Wufad91c82007-12-04 23:45:14 -0800620 struct chip_data *chip = drv_data->cur_chip;
Bryan Wubb90eb02007-12-04 23:45:18 -0800621 struct spi_message *msg = drv_data->cur_msg;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700622
Bryan Wu88b40362007-05-21 18:32:16 +0800623 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
Bryan Wubb90eb02007-12-04 23:45:18 -0800624 clear_dma_irqstat(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700625
Bryan Wud6fe89b2007-06-11 17:34:17 +0800626 /* Wait for DMA to complete */
Bryan Wubb90eb02007-12-04 23:45:18 -0800627 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
Bryan Wud8c05002007-12-04 23:45:21 -0800628 cpu_relax();
Bryan Wud6fe89b2007-06-11 17:34:17 +0800629
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700630 /*
Bryan Wud6fe89b2007-06-11 17:34:17 +0800631 * wait for the last transaction shifted out. HRM states:
632 * at this point there may still be data in the SPI DMA FIFO waiting
633 * to be transmitted ... software needs to poll TXS in the SPI_STAT
634 * register until it goes low for 2 successive reads
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700635 */
636 if (drv_data->tx != NULL) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800637 while ((read_STAT(drv_data) & TXS) ||
638 (read_STAT(drv_data) & TXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800639 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700640 }
641
Bryan Wubb90eb02007-12-04 23:45:18 -0800642 while (!(read_STAT(drv_data) & SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800643 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700644
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700645 msg->actual_length += drv_data->len_in_bytes;
646
Bryan Wufad91c82007-12-04 23:45:14 -0800647 if (drv_data->cs_change)
Bryan Wubb90eb02007-12-04 23:45:18 -0800648 cs_deactive(drv_data, chip);
Bryan Wufad91c82007-12-04 23:45:14 -0800649
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700650 /* Move to next transfer */
651 msg->state = next_transfer(drv_data);
652
653 /* Schedule transfer tasklet */
654 tasklet_schedule(&drv_data->pump_transfers);
655
656 /* free the irq handler before next transfer */
Bryan Wu88b40362007-05-21 18:32:16 +0800657 dev_dbg(&drv_data->pdev->dev,
658 "disable dma channel irq%d\n",
Bryan Wubb90eb02007-12-04 23:45:18 -0800659 drv_data->dma_channel);
660 dma_disable_irq(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700661
662 return IRQ_HANDLED;
663}
664
665static void pump_transfers(unsigned long data)
666{
667 struct driver_data *drv_data = (struct driver_data *)data;
668 struct spi_message *message = NULL;
669 struct spi_transfer *transfer = NULL;
670 struct spi_transfer *previous = NULL;
671 struct chip_data *chip = NULL;
Bryan Wu88b40362007-05-21 18:32:16 +0800672 u8 width;
673 u16 cr, dma_width, dma_config;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700674 u32 tranf_success = 1;
675
676 /* Get current state information */
677 message = drv_data->cur_msg;
678 transfer = drv_data->cur_transfer;
679 chip = drv_data->cur_chip;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800680
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700681 /*
682 * if msg is error or done, report it back using complete() callback
683 */
684
685 /* Handle for abort */
686 if (message->state == ERROR_STATE) {
687 message->status = -EIO;
688 giveback(drv_data);
689 return;
690 }
691
692 /* Handle end of message */
693 if (message->state == DONE_STATE) {
694 message->status = 0;
695 giveback(drv_data);
696 return;
697 }
698
699 /* Delay if requested at end of transfer */
700 if (message->state == RUNNING_STATE) {
701 previous = list_entry(transfer->transfer_list.prev,
702 struct spi_transfer, transfer_list);
703 if (previous->delay_usecs)
704 udelay(previous->delay_usecs);
705 }
706
707 /* Setup the transfer state based on the type of transfer */
708 if (flush(drv_data) == 0) {
709 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
710 message->status = -EIO;
711 giveback(drv_data);
712 return;
713 }
714
715 if (transfer->tx_buf != NULL) {
716 drv_data->tx = (void *)transfer->tx_buf;
717 drv_data->tx_end = drv_data->tx + transfer->len;
Bryan Wu88b40362007-05-21 18:32:16 +0800718 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
719 transfer->tx_buf, drv_data->tx_end);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700720 } else {
721 drv_data->tx = NULL;
722 }
723
724 if (transfer->rx_buf != NULL) {
725 drv_data->rx = transfer->rx_buf;
726 drv_data->rx_end = drv_data->rx + transfer->len;
Bryan Wu88b40362007-05-21 18:32:16 +0800727 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
728 transfer->rx_buf, drv_data->rx_end);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700729 } else {
730 drv_data->rx = NULL;
731 }
732
733 drv_data->rx_dma = transfer->rx_dma;
734 drv_data->tx_dma = transfer->tx_dma;
735 drv_data->len_in_bytes = transfer->len;
Bryan Wufad91c82007-12-04 23:45:14 -0800736 drv_data->cs_change = transfer->cs_change;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700737
Bryan Wu092e1fd2007-12-04 23:45:23 -0800738 /* Bits per word setup */
739 switch (transfer->bits_per_word) {
740 case 8:
741 drv_data->n_bytes = 1;
742 width = CFG_SPI_WORDSIZE8;
743 drv_data->read = chip->cs_change_per_word ?
744 u8_cs_chg_reader : u8_reader;
745 drv_data->write = chip->cs_change_per_word ?
746 u8_cs_chg_writer : u8_writer;
747 drv_data->duplex = chip->cs_change_per_word ?
748 u8_cs_chg_duplex : u8_duplex;
749 break;
750
751 case 16:
752 drv_data->n_bytes = 2;
753 width = CFG_SPI_WORDSIZE16;
754 drv_data->read = chip->cs_change_per_word ?
755 u16_cs_chg_reader : u16_reader;
756 drv_data->write = chip->cs_change_per_word ?
757 u16_cs_chg_writer : u16_writer;
758 drv_data->duplex = chip->cs_change_per_word ?
759 u16_cs_chg_duplex : u16_duplex;
760 break;
761
762 default:
763 /* No change, the same as default setting */
764 drv_data->n_bytes = chip->n_bytes;
765 width = chip->width;
766 drv_data->write = drv_data->tx ? chip->write : null_writer;
767 drv_data->read = drv_data->rx ? chip->read : null_reader;
768 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
769 break;
770 }
771 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
772 cr |= (width << 8);
773 write_CTRL(drv_data, cr);
774
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700775 if (width == CFG_SPI_WORDSIZE16) {
776 drv_data->len = (transfer->len) >> 1;
777 } else {
778 drv_data->len = transfer->len;
779 }
Bryan Wu131b17d2007-12-04 23:45:12 -0800780 dev_dbg(&drv_data->pdev->dev, "transfer: ",
781 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
782 drv_data->write, chip->write, null_writer);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700783
784 /* speed and width has been set on per message */
785 message->state = RUNNING_STATE;
786 dma_config = 0;
787
Bryan Wu092e1fd2007-12-04 23:45:23 -0800788 /* Speed setup (surely valid because already checked) */
789 if (transfer->speed_hz)
790 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
791 else
792 write_BAUD(drv_data, chip->baud);
793
Bryan Wubb90eb02007-12-04 23:45:18 -0800794 write_STAT(drv_data, BIT_STAT_CLR);
795 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
796 cs_active(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700797
Bryan Wu88b40362007-05-21 18:32:16 +0800798 dev_dbg(&drv_data->pdev->dev,
799 "now pumping a transfer: width is %d, len is %d\n",
800 width, transfer->len);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700801
802 /*
803 * Try to map dma buffer and do a dma transfer if
804 * successful use different way to r/w according to
805 * drv_data->cur_chip->enable_dma
806 */
807 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
808
Bryan Wubb90eb02007-12-04 23:45:18 -0800809 disable_dma(drv_data->dma_channel);
810 clear_dma_irqstat(drv_data->dma_channel);
Sonic Zhang07612e52007-12-04 23:45:21 -0800811 bfin_spi_disable(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700812
813 /* config dma channel */
Bryan Wu88b40362007-05-21 18:32:16 +0800814 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700815 if (width == CFG_SPI_WORDSIZE16) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800816 set_dma_x_count(drv_data->dma_channel, drv_data->len);
817 set_dma_x_modify(drv_data->dma_channel, 2);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700818 dma_width = WDSIZE_16;
819 } else {
Bryan Wubb90eb02007-12-04 23:45:18 -0800820 set_dma_x_count(drv_data->dma_channel, drv_data->len);
821 set_dma_x_modify(drv_data->dma_channel, 1);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700822 dma_width = WDSIZE_8;
823 }
824
Sonic Zhang3f479a62007-12-04 23:45:18 -0800825 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800826 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800827 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800828
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700829 /* dirty hack for autobuffer DMA mode */
830 if (drv_data->tx_dma == 0xFFFF) {
Bryan Wu88b40362007-05-21 18:32:16 +0800831 dev_dbg(&drv_data->pdev->dev,
832 "doing autobuffer DMA out.\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700833
834 /* no irq in autobuffer mode */
835 dma_config =
836 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
Bryan Wubb90eb02007-12-04 23:45:18 -0800837 set_dma_config(drv_data->dma_channel, dma_config);
838 set_dma_start_addr(drv_data->dma_channel,
Bryan Wua32c6912007-12-04 23:45:15 -0800839 (unsigned long)drv_data->tx);
Bryan Wubb90eb02007-12-04 23:45:18 -0800840 enable_dma(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700841
Sonic Zhang07612e52007-12-04 23:45:21 -0800842 /* start SPI transfer */
843 write_CTRL(drv_data,
844 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
845
846 /* just return here, there can only be one transfer
847 * in this mode
848 */
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700849 message->status = 0;
850 giveback(drv_data);
851 return;
852 }
853
854 /* In dma mode, rx or tx must be NULL in one transfer */
855 if (drv_data->rx != NULL) {
856 /* set transfer mode, and enable SPI */
Bryan Wu88b40362007-05-21 18:32:16 +0800857 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700858
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700859 /* clear tx reg soformer data is not shifted out */
Bryan Wubb90eb02007-12-04 23:45:18 -0800860 write_TDBR(drv_data, 0xFFFF);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700861
Bryan Wubb90eb02007-12-04 23:45:18 -0800862 set_dma_x_count(drv_data->dma_channel, drv_data->len);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700863
864 /* start dma */
Bryan Wubb90eb02007-12-04 23:45:18 -0800865 dma_enable_irq(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700866 dma_config = (WNR | RESTART | dma_width | DI_EN);
Bryan Wubb90eb02007-12-04 23:45:18 -0800867 set_dma_config(drv_data->dma_channel, dma_config);
868 set_dma_start_addr(drv_data->dma_channel,
Bryan Wua32c6912007-12-04 23:45:15 -0800869 (unsigned long)drv_data->rx);
Bryan Wubb90eb02007-12-04 23:45:18 -0800870 enable_dma(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700871
Sonic Zhang07612e52007-12-04 23:45:21 -0800872 /* start SPI transfer */
873 write_CTRL(drv_data,
874 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
875
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700876 } else if (drv_data->tx != NULL) {
Bryan Wu88b40362007-05-21 18:32:16 +0800877 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700878
879 /* start dma */
Bryan Wubb90eb02007-12-04 23:45:18 -0800880 dma_enable_irq(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700881 dma_config = (RESTART | dma_width | DI_EN);
Bryan Wubb90eb02007-12-04 23:45:18 -0800882 set_dma_config(drv_data->dma_channel, dma_config);
883 set_dma_start_addr(drv_data->dma_channel,
Bryan Wua32c6912007-12-04 23:45:15 -0800884 (unsigned long)drv_data->tx);
Bryan Wubb90eb02007-12-04 23:45:18 -0800885 enable_dma(drv_data->dma_channel);
Sonic Zhang07612e52007-12-04 23:45:21 -0800886
887 /* start SPI transfer */
888 write_CTRL(drv_data,
889 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700890 }
891 } else {
892 /* IO mode write then read */
Bryan Wu88b40362007-05-21 18:32:16 +0800893 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700894
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700895 if (drv_data->tx != NULL && drv_data->rx != NULL) {
896 /* full duplex mode */
897 BUG_ON((drv_data->tx_end - drv_data->tx) !=
898 (drv_data->rx_end - drv_data->rx));
Bryan Wu88b40362007-05-21 18:32:16 +0800899 dev_dbg(&drv_data->pdev->dev,
900 "IO duplex: cr is 0x%x\n", cr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700901
Sonic Zhangcc487e72007-12-04 23:45:17 -0800902 /* set SPI transfer mode */
Bryan Wubb90eb02007-12-04 23:45:18 -0800903 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700904
905 drv_data->duplex(drv_data);
906
907 if (drv_data->tx != drv_data->tx_end)
908 tranf_success = 0;
909 } else if (drv_data->tx != NULL) {
910 /* write only half duplex */
Bryan Wu131b17d2007-12-04 23:45:12 -0800911 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800912 "IO write: cr is 0x%x\n", cr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700913
Sonic Zhangcc487e72007-12-04 23:45:17 -0800914 /* set SPI transfer mode */
Bryan Wubb90eb02007-12-04 23:45:18 -0800915 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700916
917 drv_data->write(drv_data);
918
919 if (drv_data->tx != drv_data->tx_end)
920 tranf_success = 0;
921 } else if (drv_data->rx != NULL) {
922 /* read only half duplex */
Bryan Wu131b17d2007-12-04 23:45:12 -0800923 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800924 "IO read: cr is 0x%x\n", cr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700925
Sonic Zhangcc487e72007-12-04 23:45:17 -0800926 /* set SPI transfer mode */
Bryan Wubb90eb02007-12-04 23:45:18 -0800927 write_CTRL(drv_data, (cr | CFG_SPI_READ));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700928
929 drv_data->read(drv_data);
930 if (drv_data->rx != drv_data->rx_end)
931 tranf_success = 0;
932 }
933
934 if (!tranf_success) {
Bryan Wu131b17d2007-12-04 23:45:12 -0800935 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800936 "IO write error!\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700937 message->state = ERROR_STATE;
938 } else {
939 /* Update total byte transfered */
940 message->actual_length += drv_data->len;
941
942 /* Move to next transfer of this msg */
943 message->state = next_transfer(drv_data);
944 }
945
946 /* Schedule next transfer tasklet */
947 tasklet_schedule(&drv_data->pump_transfers);
948
949 }
950}
951
952/* pop a msg from queue and kick off real transfer */
953static void pump_messages(struct work_struct *work)
954{
Bryan Wu131b17d2007-12-04 23:45:12 -0800955 struct driver_data *drv_data;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700956 unsigned long flags;
957
Bryan Wu131b17d2007-12-04 23:45:12 -0800958 drv_data = container_of(work, struct driver_data, pump_messages);
959
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700960 /* Lock queue and check for queue work */
961 spin_lock_irqsave(&drv_data->lock, flags);
962 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
963 /* pumper kicked off but no work to do */
964 drv_data->busy = 0;
965 spin_unlock_irqrestore(&drv_data->lock, flags);
966 return;
967 }
968
969 /* Make sure we are not already running a message */
970 if (drv_data->cur_msg) {
971 spin_unlock_irqrestore(&drv_data->lock, flags);
972 return;
973 }
974
975 /* Extract head of queue */
976 drv_data->cur_msg = list_entry(drv_data->queue.next,
977 struct spi_message, queue);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800978
979 /* Setup the SSP using the per chip configuration */
980 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
981 if (restore_state(drv_data)) {
982 spin_unlock_irqrestore(&drv_data->lock, flags);
983 return;
984 };
985
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700986 list_del_init(&drv_data->cur_msg->queue);
987
988 /* Initial message state */
989 drv_data->cur_msg->state = START_STATE;
990 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
991 struct spi_transfer, transfer_list);
992
Bryan Wu5fec5b52007-12-04 23:45:13 -0800993 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
994 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
995 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
996 drv_data->cur_chip->ctl_reg);
Bryan Wu131b17d2007-12-04 23:45:12 -0800997
998 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800999 "the first transfer len is %d\n",
1000 drv_data->cur_transfer->len);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001001
1002 /* Mark as busy and launch transfers */
1003 tasklet_schedule(&drv_data->pump_transfers);
1004
1005 drv_data->busy = 1;
1006 spin_unlock_irqrestore(&drv_data->lock, flags);
1007}
1008
1009/*
1010 * got a msg to transfer, queue it in drv_data->queue.
1011 * And kick off message pumper
1012 */
1013static int transfer(struct spi_device *spi, struct spi_message *msg)
1014{
1015 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1016 unsigned long flags;
1017
1018 spin_lock_irqsave(&drv_data->lock, flags);
1019
1020 if (drv_data->run == QUEUE_STOPPED) {
1021 spin_unlock_irqrestore(&drv_data->lock, flags);
1022 return -ESHUTDOWN;
1023 }
1024
1025 msg->actual_length = 0;
1026 msg->status = -EINPROGRESS;
1027 msg->state = START_STATE;
1028
Bryan Wu88b40362007-05-21 18:32:16 +08001029 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001030 list_add_tail(&msg->queue, &drv_data->queue);
1031
1032 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1033 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1034
1035 spin_unlock_irqrestore(&drv_data->lock, flags);
1036
1037 return 0;
1038}
1039
Sonic Zhang12e17c42007-12-04 23:45:16 -08001040#define MAX_SPI_SSEL 7
1041
1042static u16 ssel[3][MAX_SPI_SSEL] = {
1043 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1044 P_SPI0_SSEL4, P_SPI0_SSEL5,
1045 P_SPI0_SSEL6, P_SPI0_SSEL7},
1046
1047 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1048 P_SPI1_SSEL4, P_SPI1_SSEL5,
1049 P_SPI1_SSEL6, P_SPI1_SSEL7},
1050
1051 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1052 P_SPI2_SSEL4, P_SPI2_SSEL5,
1053 P_SPI2_SSEL6, P_SPI2_SSEL7},
1054};
1055
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001056/* first setup for new devices */
1057static int setup(struct spi_device *spi)
1058{
1059 struct bfin5xx_spi_chip *chip_info = NULL;
1060 struct chip_data *chip;
1061 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1062 u8 spi_flg;
1063
1064 /* Abort device setup if requested features are not supported */
1065 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1066 dev_err(&spi->dev, "requested mode not fully supported\n");
1067 return -EINVAL;
1068 }
1069
1070 /* Zero (the default) here means 8 bits */
1071 if (!spi->bits_per_word)
1072 spi->bits_per_word = 8;
1073
1074 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1075 return -EINVAL;
1076
1077 /* Only alloc (or use chip_info) on first setup */
1078 chip = spi_get_ctldata(spi);
1079 if (chip == NULL) {
1080 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1081 if (!chip)
1082 return -ENOMEM;
1083
1084 chip->enable_dma = 0;
1085 chip_info = spi->controller_data;
1086 }
1087
1088 /* chip_info isn't always needed */
1089 if (chip_info) {
Mike Frysinger2ed35512007-12-04 23:45:14 -08001090 /* Make sure people stop trying to set fields via ctl_reg
1091 * when they should actually be using common SPI framework.
1092 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1093 * Not sure if a user actually needs/uses any of these,
1094 * but let's assume (for now) they do.
1095 */
1096 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1097 dev_err(&spi->dev, "do not set bits in ctl_reg "
1098 "that the SPI framework manages\n");
1099 return -EINVAL;
1100 }
1101
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001102 chip->enable_dma = chip_info->enable_dma != 0
1103 && drv_data->master_info->enable_dma;
1104 chip->ctl_reg = chip_info->ctl_reg;
1105 chip->bits_per_word = chip_info->bits_per_word;
1106 chip->cs_change_per_word = chip_info->cs_change_per_word;
1107 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1108 }
1109
1110 /* translate common spi framework into our register */
1111 if (spi->mode & SPI_CPOL)
1112 chip->ctl_reg |= CPOL;
1113 if (spi->mode & SPI_CPHA)
1114 chip->ctl_reg |= CPHA;
1115 if (spi->mode & SPI_LSB_FIRST)
1116 chip->ctl_reg |= LSBF;
1117 /* we dont support running in slave mode (yet?) */
1118 chip->ctl_reg |= MSTR;
1119
1120 /*
1121 * if any one SPI chip is registered and wants DMA, request the
1122 * DMA channel for it
1123 */
Bryan Wubb90eb02007-12-04 23:45:18 -08001124 if (chip->enable_dma && !drv_data->dma_requested) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001125 /* register dma irq handler */
Bryan Wubb90eb02007-12-04 23:45:18 -08001126 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
Bryan Wu88b40362007-05-21 18:32:16 +08001127 dev_dbg(&spi->dev,
1128 "Unable to request BlackFin SPI DMA channel\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001129 return -ENODEV;
1130 }
Bryan Wubb90eb02007-12-04 23:45:18 -08001131 if (set_dma_callback(drv_data->dma_channel,
1132 (void *)dma_irq_handler, drv_data) < 0) {
Bryan Wu88b40362007-05-21 18:32:16 +08001133 dev_dbg(&spi->dev, "Unable to set dma callback\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001134 return -EPERM;
1135 }
Bryan Wubb90eb02007-12-04 23:45:18 -08001136 dma_disable_irq(drv_data->dma_channel);
1137 drv_data->dma_requested = 1;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001138 }
1139
1140 /*
1141 * Notice: for blackfin, the speed_hz is the value of register
1142 * SPI_BAUD, not the real baudrate
1143 */
1144 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1145 spi_flg = ~(1 << (spi->chip_select));
1146 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1147 chip->chip_select_num = spi->chip_select;
1148
1149 switch (chip->bits_per_word) {
1150 case 8:
1151 chip->n_bytes = 1;
1152 chip->width = CFG_SPI_WORDSIZE8;
1153 chip->read = chip->cs_change_per_word ?
1154 u8_cs_chg_reader : u8_reader;
1155 chip->write = chip->cs_change_per_word ?
1156 u8_cs_chg_writer : u8_writer;
1157 chip->duplex = chip->cs_change_per_word ?
1158 u8_cs_chg_duplex : u8_duplex;
1159 break;
1160
1161 case 16:
1162 chip->n_bytes = 2;
1163 chip->width = CFG_SPI_WORDSIZE16;
1164 chip->read = chip->cs_change_per_word ?
1165 u16_cs_chg_reader : u16_reader;
1166 chip->write = chip->cs_change_per_word ?
1167 u16_cs_chg_writer : u16_writer;
1168 chip->duplex = chip->cs_change_per_word ?
1169 u16_cs_chg_duplex : u16_duplex;
1170 break;
1171
1172 default:
1173 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1174 chip->bits_per_word);
1175 kfree(chip);
1176 return -ENODEV;
1177 }
1178
Joe Perches898eb712007-10-18 03:06:30 -07001179 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001180 spi->modalias, chip->width, chip->enable_dma);
Bryan Wu88b40362007-05-21 18:32:16 +08001181 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001182 chip->ctl_reg, chip->flag);
1183
1184 spi_set_ctldata(spi, chip);
1185
Sonic Zhang12e17c42007-12-04 23:45:16 -08001186 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1187 if ((chip->chip_select_num > 0)
1188 && (chip->chip_select_num <= spi->master->num_chipselect))
1189 peripheral_request(ssel[spi->master->bus_num]
1190 [chip->chip_select_num-1], DRV_NAME);
1191
Sonic Zhang07612e52007-12-04 23:45:21 -08001192 cs_deactive(drv_data, chip);
1193
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001194 return 0;
1195}
1196
1197/*
1198 * callback for spi framework.
1199 * clean driver specific data
1200 */
Bryan Wu88b40362007-05-21 18:32:16 +08001201static void cleanup(struct spi_device *spi)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001202{
Mike Frysinger27bb9e72007-06-11 15:31:30 +08001203 struct chip_data *chip = spi_get_ctldata(spi);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001204
Sonic Zhang12e17c42007-12-04 23:45:16 -08001205 if ((chip->chip_select_num > 0)
1206 && (chip->chip_select_num <= spi->master->num_chipselect))
1207 peripheral_free(ssel[spi->master->bus_num]
1208 [chip->chip_select_num-1]);
1209
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001210 kfree(chip);
1211}
1212
1213static inline int init_queue(struct driver_data *drv_data)
1214{
1215 INIT_LIST_HEAD(&drv_data->queue);
1216 spin_lock_init(&drv_data->lock);
1217
1218 drv_data->run = QUEUE_STOPPED;
1219 drv_data->busy = 0;
1220
1221 /* init transfer tasklet */
1222 tasklet_init(&drv_data->pump_transfers,
1223 pump_transfers, (unsigned long)drv_data);
1224
1225 /* init messages workqueue */
1226 INIT_WORK(&drv_data->pump_messages, pump_messages);
1227 drv_data->workqueue =
Tony Jones49dce682007-10-16 01:27:48 -07001228 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001229 if (drv_data->workqueue == NULL)
1230 return -EBUSY;
1231
1232 return 0;
1233}
1234
1235static inline int start_queue(struct driver_data *drv_data)
1236{
1237 unsigned long flags;
1238
1239 spin_lock_irqsave(&drv_data->lock, flags);
1240
1241 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1242 spin_unlock_irqrestore(&drv_data->lock, flags);
1243 return -EBUSY;
1244 }
1245
1246 drv_data->run = QUEUE_RUNNING;
1247 drv_data->cur_msg = NULL;
1248 drv_data->cur_transfer = NULL;
1249 drv_data->cur_chip = NULL;
1250 spin_unlock_irqrestore(&drv_data->lock, flags);
1251
1252 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1253
1254 return 0;
1255}
1256
1257static inline int stop_queue(struct driver_data *drv_data)
1258{
1259 unsigned long flags;
1260 unsigned limit = 500;
1261 int status = 0;
1262
1263 spin_lock_irqsave(&drv_data->lock, flags);
1264
1265 /*
1266 * This is a bit lame, but is optimized for the common execution path.
1267 * A wait_queue on the drv_data->busy could be used, but then the common
1268 * execution path (pump_messages) would be required to call wake_up or
1269 * friends on every SPI message. Do this instead
1270 */
1271 drv_data->run = QUEUE_STOPPED;
1272 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1273 spin_unlock_irqrestore(&drv_data->lock, flags);
1274 msleep(10);
1275 spin_lock_irqsave(&drv_data->lock, flags);
1276 }
1277
1278 if (!list_empty(&drv_data->queue) || drv_data->busy)
1279 status = -EBUSY;
1280
1281 spin_unlock_irqrestore(&drv_data->lock, flags);
1282
1283 return status;
1284}
1285
1286static inline int destroy_queue(struct driver_data *drv_data)
1287{
1288 int status;
1289
1290 status = stop_queue(drv_data);
1291 if (status != 0)
1292 return status;
1293
1294 destroy_workqueue(drv_data->workqueue);
1295
1296 return 0;
1297}
1298
1299static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1300{
1301 struct device *dev = &pdev->dev;
1302 struct bfin5xx_spi_master *platform_info;
1303 struct spi_master *master;
1304 struct driver_data *drv_data = 0;
Bryan Wua32c6912007-12-04 23:45:15 -08001305 struct resource *res;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001306 int status = 0;
1307
1308 platform_info = dev->platform_data;
1309
1310 /* Allocate master with space for drv_data */
1311 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1312 if (!master) {
1313 dev_err(&pdev->dev, "can not alloc spi_master\n");
1314 return -ENOMEM;
1315 }
Bryan Wu131b17d2007-12-04 23:45:12 -08001316
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001317 drv_data = spi_master_get_devdata(master);
1318 drv_data->master = master;
1319 drv_data->master_info = platform_info;
1320 drv_data->pdev = pdev;
Bryan Wu003d9222007-12-04 23:45:22 -08001321 drv_data->pin_req = platform_info->pin_req;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001322
1323 master->bus_num = pdev->id;
1324 master->num_chipselect = platform_info->num_chipselect;
1325 master->cleanup = cleanup;
1326 master->setup = setup;
1327 master->transfer = transfer;
1328
Bryan Wua32c6912007-12-04 23:45:15 -08001329 /* Find and map our resources */
1330 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1331 if (res == NULL) {
1332 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1333 status = -ENOENT;
1334 goto out_error_get_res;
1335 }
1336
Bryan Wuf4521262007-12-04 23:45:22 -08001337 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1338 if (drv_data->regs_base == NULL) {
Bryan Wua32c6912007-12-04 23:45:15 -08001339 dev_err(dev, "Cannot map IO\n");
1340 status = -ENXIO;
1341 goto out_error_ioremap;
1342 }
1343
Bryan Wubb90eb02007-12-04 23:45:18 -08001344 drv_data->dma_channel = platform_get_irq(pdev, 0);
1345 if (drv_data->dma_channel < 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001346 dev_err(dev, "No DMA channel specified\n");
1347 status = -ENOENT;
1348 goto out_error_no_dma_ch;
1349 }
1350
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001351 /* Initial and start queue */
1352 status = init_queue(drv_data);
1353 if (status != 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001354 dev_err(dev, "problem initializing queue\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001355 goto out_error_queue_alloc;
1356 }
Bryan Wua32c6912007-12-04 23:45:15 -08001357
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001358 status = start_queue(drv_data);
1359 if (status != 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001360 dev_err(dev, "problem starting queue\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001361 goto out_error_queue_alloc;
1362 }
1363
1364 /* Register with the SPI framework */
1365 platform_set_drvdata(pdev, drv_data);
1366 status = spi_register_master(master);
1367 if (status != 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001368 dev_err(dev, "problem registering spi master\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001369 goto out_error_queue_alloc;
1370 }
Bryan Wua32c6912007-12-04 23:45:15 -08001371
Bryan Wu003d9222007-12-04 23:45:22 -08001372 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1373 if (status != 0) {
Sonic Zhang7c4ef092007-12-04 23:45:16 -08001374 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1375 goto out_error;
1376 }
1377
Bryan Wuf4521262007-12-04 23:45:22 -08001378 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
Bryan Wubb90eb02007-12-04 23:45:18 -08001379 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1380 drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001381 return status;
1382
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001383out_error_queue_alloc:
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001384 destroy_queue(drv_data);
Bryan Wua32c6912007-12-04 23:45:15 -08001385out_error_no_dma_ch:
Bryan Wubb90eb02007-12-04 23:45:18 -08001386 iounmap((void *) drv_data->regs_base);
Bryan Wua32c6912007-12-04 23:45:15 -08001387out_error_ioremap:
1388out_error_get_res:
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001389out_error:
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001390 spi_master_put(master);
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001391
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001392 return status;
1393}
1394
1395/* stop hardware and remove the driver */
1396static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1397{
1398 struct driver_data *drv_data = platform_get_drvdata(pdev);
1399 int status = 0;
1400
1401 if (!drv_data)
1402 return 0;
1403
1404 /* Remove the queue */
1405 status = destroy_queue(drv_data);
1406 if (status != 0)
1407 return status;
1408
1409 /* Disable the SSP at the peripheral and SOC level */
1410 bfin_spi_disable(drv_data);
1411
1412 /* Release DMA */
1413 if (drv_data->master_info->enable_dma) {
Bryan Wubb90eb02007-12-04 23:45:18 -08001414 if (dma_channel_active(drv_data->dma_channel))
1415 free_dma(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001416 }
1417
1418 /* Disconnect from the SPI framework */
1419 spi_unregister_master(drv_data->master);
1420
Bryan Wu003d9222007-12-04 23:45:22 -08001421 peripheral_free_list(drv_data->pin_req);
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001422
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001423 /* Prevent double remove */
1424 platform_set_drvdata(pdev, NULL);
1425
1426 return 0;
1427}
1428
1429#ifdef CONFIG_PM
1430static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1431{
1432 struct driver_data *drv_data = platform_get_drvdata(pdev);
1433 int status = 0;
1434
1435 status = stop_queue(drv_data);
1436 if (status != 0)
1437 return status;
1438
1439 /* stop hardware */
1440 bfin_spi_disable(drv_data);
1441
1442 return 0;
1443}
1444
1445static int bfin5xx_spi_resume(struct platform_device *pdev)
1446{
1447 struct driver_data *drv_data = platform_get_drvdata(pdev);
1448 int status = 0;
1449
1450 /* Enable the SPI interface */
1451 bfin_spi_enable(drv_data);
1452
1453 /* Start the queue running */
1454 status = start_queue(drv_data);
1455 if (status != 0) {
1456 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1457 return status;
1458 }
1459
1460 return 0;
1461}
1462#else
1463#define bfin5xx_spi_suspend NULL
1464#define bfin5xx_spi_resume NULL
1465#endif /* CONFIG_PM */
1466
David Brownellfc3ba952007-08-30 23:56:24 -07001467MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001468static struct platform_driver bfin5xx_spi_driver = {
David Brownellfc3ba952007-08-30 23:56:24 -07001469 .driver = {
Bryan Wua32c6912007-12-04 23:45:15 -08001470 .name = DRV_NAME,
Bryan Wu88b40362007-05-21 18:32:16 +08001471 .owner = THIS_MODULE,
1472 },
1473 .suspend = bfin5xx_spi_suspend,
1474 .resume = bfin5xx_spi_resume,
1475 .remove = __devexit_p(bfin5xx_spi_remove),
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001476};
1477
1478static int __init bfin5xx_spi_init(void)
1479{
Bryan Wu88b40362007-05-21 18:32:16 +08001480 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001481}
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001482module_init(bfin5xx_spi_init);
1483
1484static void __exit bfin5xx_spi_exit(void)
1485{
1486 platform_driver_unregister(&bfin5xx_spi_driver);
1487}
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001488module_exit(bfin5xx_spi_exit);