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gerrit-public.fairphone.software / kernel / msm-4.9 / 41844e36206be90cd4d962ea49b0abc3612a99d0 / . / arch / mips / include / asm / asmmacro.h
blob: 83054f79f72aa62595923ca017936f6cd60075fd [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ralf Baechle
7 */
8#ifndef _ASM_ASMMACRO_H
9#define _ASM_ASMMACRO_H
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700[diff] [blame]10
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]11#include <asm/hazards.h>
Jim Quinlan71ca7582013-11-27 15:34:50 -0500[diff] [blame]12#include <asm/asm-offsets.h>
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]13#include <asm/msa.h>
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700[diff] [blame]14
Ralf Baechle875d43e2005-09-03 15:56:16 -0700[diff] [blame]15#ifdef CONFIG_32BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]16#include <asm/asmmacro-32.h>
17#endif
Ralf Baechle875d43e2005-09-03 15:56:16 -0700[diff] [blame]18#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]19#include <asm/asmmacro-64.h>
20#endif
21
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]22/*
23 * Helper macros for generating raw instruction encodings.
24 */
25#ifdef CONFIG_CPU_MICROMIPS
26 .macro insn32_if_mm enc
27 .insn
28 .hword ((\enc) >> 16)
29 .hword ((\enc) & 0xffff)
30 .endm
31
32 .macro insn_if_mips enc
33 .endm
34#else
35 .macro insn32_if_mm enc
36 .endm
37
38 .macro insn_if_mips enc
39 .insn
40 .word (\enc)
41 .endm
42#endif
43
Leonid Yegoshin226da552014-11-05 12:56:40 +0000[diff] [blame]44#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
David Daneyb6354db2008-12-10 08:37:25 -0800[diff] [blame]45 .macro local_irq_enable reg=t0
46 ei
47 irq_enable_hazard
48 .endm
49
50 .macro local_irq_disable reg=t0
51 di
52 irq_disable_hazard
53 .endm
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]54#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]55 .macro local_irq_enable reg=t0
56 mfc0 \reg, CP0_STATUS
57 ori \reg, \reg, 1
58 mtc0 \reg, CP0_STATUS
59 irq_enable_hazard
60 .endm
61
62 .macro local_irq_disable reg=t0
Jim Quinlan71ca7582013-11-27 15:34:50 -0500[diff] [blame]63#ifdef CONFIG_PREEMPT
64 lw \reg, TI_PRE_COUNT($28)
65 addi \reg, \reg, 1
66 sw \reg, TI_PRE_COUNT($28)
67#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]68 mfc0 \reg, CP0_STATUS
69 ori \reg, \reg, 1
70 xori \reg, \reg, 1
71 mtc0 \reg, CP0_STATUS
72 irq_disable_hazard
Jim Quinlan71ca7582013-11-27 15:34:50 -0500[diff] [blame]73#ifdef CONFIG_PREEMPT
74 lw \reg, TI_PRE_COUNT($28)
75 addi \reg, \reg, -1
76 sw \reg, TI_PRE_COUNT($28)
77#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]78 .endm
Ralf Baechleb633648c52014-05-23 16:29:44 +0200[diff] [blame]79#endif /* CONFIG_CPU_MIPSR2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]80
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]81 .macro fpu_save_16even thread tmp=t0
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]82 .set push
83 SET_HARDFLOAT
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]84 cfc1 \tmp, fcr31
James Hogan466aec52015-01-30 12:09:38 +0000[diff] [blame]85 sdc1 $f0, THREAD_FPR0(\thread)
86 sdc1 $f2, THREAD_FPR2(\thread)
87 sdc1 $f4, THREAD_FPR4(\thread)
88 sdc1 $f6, THREAD_FPR6(\thread)
89 sdc1 $f8, THREAD_FPR8(\thread)
90 sdc1 $f10, THREAD_FPR10(\thread)
91 sdc1 $f12, THREAD_FPR12(\thread)
92 sdc1 $f14, THREAD_FPR14(\thread)
93 sdc1 $f16, THREAD_FPR16(\thread)
94 sdc1 $f18, THREAD_FPR18(\thread)
95 sdc1 $f20, THREAD_FPR20(\thread)
96 sdc1 $f22, THREAD_FPR22(\thread)
97 sdc1 $f24, THREAD_FPR24(\thread)
98 sdc1 $f26, THREAD_FPR26(\thread)
99 sdc1 $f28, THREAD_FPR28(\thread)
100 sdc1 $f30, THREAD_FPR30(\thread)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]101 sw \tmp, THREAD_FCR31(\thread)
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]102 .set pop
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]103 .endm
104
105 .macro fpu_save_16odd thread
106 .set push
107 .set mips64r2
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]108 SET_HARDFLOAT
James Hogan466aec52015-01-30 12:09:38 +0000[diff] [blame]109 sdc1 $f1, THREAD_FPR1(\thread)
110 sdc1 $f3, THREAD_FPR3(\thread)
111 sdc1 $f5, THREAD_FPR5(\thread)
112 sdc1 $f7, THREAD_FPR7(\thread)
113 sdc1 $f9, THREAD_FPR9(\thread)
114 sdc1 $f11, THREAD_FPR11(\thread)
115 sdc1 $f13, THREAD_FPR13(\thread)
116 sdc1 $f15, THREAD_FPR15(\thread)
117 sdc1 $f17, THREAD_FPR17(\thread)
118 sdc1 $f19, THREAD_FPR19(\thread)
119 sdc1 $f21, THREAD_FPR21(\thread)
120 sdc1 $f23, THREAD_FPR23(\thread)
121 sdc1 $f25, THREAD_FPR25(\thread)
122 sdc1 $f27, THREAD_FPR27(\thread)
123 sdc1 $f29, THREAD_FPR29(\thread)
124 sdc1 $f31, THREAD_FPR31(\thread)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]125 .set pop
126 .endm
127
128 .macro fpu_save_double thread status tmp
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]129#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
130 defined(CONFIG_CPU_MIPS32_R6)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]131 sll \tmp, \status, 5
132 bgez \tmp, 10f
133 fpu_save_16odd \thread
13410:
135#endif
136 fpu_save_16even \thread \tmp
137 .endm
138
139 .macro fpu_restore_16even thread tmp=t0
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]140 .set push
141 SET_HARDFLOAT
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]142 lw \tmp, THREAD_FCR31(\thread)
James Hogan466aec52015-01-30 12:09:38 +0000[diff] [blame]143 ldc1 $f0, THREAD_FPR0(\thread)
144 ldc1 $f2, THREAD_FPR2(\thread)
145 ldc1 $f4, THREAD_FPR4(\thread)
146 ldc1 $f6, THREAD_FPR6(\thread)
147 ldc1 $f8, THREAD_FPR8(\thread)
148 ldc1 $f10, THREAD_FPR10(\thread)
149 ldc1 $f12, THREAD_FPR12(\thread)
150 ldc1 $f14, THREAD_FPR14(\thread)
151 ldc1 $f16, THREAD_FPR16(\thread)
152 ldc1 $f18, THREAD_FPR18(\thread)
153 ldc1 $f20, THREAD_FPR20(\thread)
154 ldc1 $f22, THREAD_FPR22(\thread)
155 ldc1 $f24, THREAD_FPR24(\thread)
156 ldc1 $f26, THREAD_FPR26(\thread)
157 ldc1 $f28, THREAD_FPR28(\thread)
158 ldc1 $f30, THREAD_FPR30(\thread)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]159 ctc1 \tmp, fcr31
Huacai Chen3cbc6fc2016-09-05 08:48:03 +0800[diff] [blame]160 .set pop
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]161 .endm
162
163 .macro fpu_restore_16odd thread
164 .set push
165 .set mips64r2
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]166 SET_HARDFLOAT
James Hogan466aec52015-01-30 12:09:38 +0000[diff] [blame]167 ldc1 $f1, THREAD_FPR1(\thread)
168 ldc1 $f3, THREAD_FPR3(\thread)
169 ldc1 $f5, THREAD_FPR5(\thread)
170 ldc1 $f7, THREAD_FPR7(\thread)
171 ldc1 $f9, THREAD_FPR9(\thread)
172 ldc1 $f11, THREAD_FPR11(\thread)
173 ldc1 $f13, THREAD_FPR13(\thread)
174 ldc1 $f15, THREAD_FPR15(\thread)
175 ldc1 $f17, THREAD_FPR17(\thread)
176 ldc1 $f19, THREAD_FPR19(\thread)
177 ldc1 $f21, THREAD_FPR21(\thread)
178 ldc1 $f23, THREAD_FPR23(\thread)
179 ldc1 $f25, THREAD_FPR25(\thread)
180 ldc1 $f27, THREAD_FPR27(\thread)
181 ldc1 $f29, THREAD_FPR29(\thread)
182 ldc1 $f31, THREAD_FPR31(\thread)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]183 .set pop
184 .endm
185
186 .macro fpu_restore_double thread status tmp
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]187#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
188 defined(CONFIG_CPU_MIPS32_R6)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]189 sll \tmp, \status, 5
190 bgez \tmp, 10f # 16 register mode?
191
192 fpu_restore_16odd \thread
19310:
194#endif
195 fpu_restore_16even \thread \tmp
196 .endm
197
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]198#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
Paul Burton1d688082014-01-15 10:31:49 +0000[diff] [blame]199 .macro _EXT rd, rs, p, s
200 ext \rd, \rs, \p, \s
201 .endm
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]202#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
Paul Burton1d688082014-01-15 10:31:49 +0000[diff] [blame]203 .macro _EXT rd, rs, p, s
204 srl \rd, \rs, \p
205 andi \rd, \rd, (1 << \s) - 1
206 .endm
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]207#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
Paul Burton1d688082014-01-15 10:31:49 +0000[diff] [blame]208
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]209/*
210 * Temporary until all gas have MT ASE support
211 */
212 .macro DMT reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]213 .word 0x41600bc1 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]214 .endm
215
216 .macro EMT reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]217 .word 0x41600be1 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]218 .endm
219
220 .macro DVPE reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]221 .word 0x41600001 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]222 .endm
223
224 .macro EVPE reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]225 .word 0x41600021 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]226 .endm
227
228 .macro MFTR rt=0, rd=0, u=0, sel=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]229 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]230 .endm
231
232 .macro MTTR rt=0, rd=0, u=0, sel=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]233 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]234 .endm
235
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]236#ifdef TOOLCHAIN_SUPPORTS_MSA
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]237/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
238#undef fp
239
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]240 .macro _cfcmsa rd, cs
241 .set push
242 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]243 .set fp=64
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]244 .set msa
245 cfcmsa \rd, $\cs
246 .set pop
247 .endm
248
249 .macro _ctcmsa cd, rs
250 .set push
251 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]252 .set fp=64
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]253 .set msa
254 ctcmsa $\cd, \rs
255 .set pop
256 .endm
257
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]258 .macro ld_b wd, off, base
259 .set push
260 .set mips32r2
James Hogan92e99532016-04-15 10:07:26 +0100[diff] [blame]261 .set fp=64
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]262 .set msa
263 ld.b $w\wd, \off(\base)
264 .set pop
265 .endm
266
267 .macro ld_h wd, off, base
268 .set push
269 .set mips32r2
James Hogan92e99532016-04-15 10:07:26 +0100[diff] [blame]270 .set fp=64
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]271 .set msa
272 ld.h $w\wd, \off(\base)
273 .set pop
274 .endm
275
276 .macro ld_w wd, off, base
277 .set push
278 .set mips32r2
James Hogan92e99532016-04-15 10:07:26 +0100[diff] [blame]279 .set fp=64
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]280 .set msa
281 ld.w $w\wd, \off(\base)
282 .set pop
283 .endm
284
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]285 .macro ld_d wd, off, base
286 .set push
287 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]288 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]289 .set msa
290 ld.d $w\wd, \off(\base)
291 .set pop
292 .endm
293
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]294 .macro st_b wd, off, base
295 .set push
296 .set mips32r2
James Hogan92e99532016-04-15 10:07:26 +0100[diff] [blame]297 .set fp=64
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]298 .set msa
299 st.b $w\wd, \off(\base)
300 .set pop
301 .endm
302
303 .macro st_h wd, off, base
304 .set push
305 .set mips32r2
James Hogan92e99532016-04-15 10:07:26 +0100[diff] [blame]306 .set fp=64
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]307 .set msa
308 st.h $w\wd, \off(\base)
309 .set pop
310 .endm
311
312 .macro st_w wd, off, base
313 .set push
314 .set mips32r2
James Hogan92e99532016-04-15 10:07:26 +0100[diff] [blame]315 .set fp=64
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]316 .set msa
317 st.w $w\wd, \off(\base)
318 .set pop
319 .endm
320
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]321 .macro st_d wd, off, base
322 .set push
323 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]324 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]325 .set msa
326 st.d $w\wd, \off(\base)
327 .set pop
328 .endm
329
Paul Burton8a3c8b42016-04-15 10:07:23 +0100[diff] [blame]330 .macro copy_s_w ws, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]331 .set push
332 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]333 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]334 .set msa
Paul Burton8a3c8b42016-04-15 10:07:23 +0100[diff] [blame]335 copy_s.w $1, $w\ws[\n]
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]336 .set pop
337 .endm
338
Paul Burton8a3c8b42016-04-15 10:07:23 +0100[diff] [blame]339 .macro copy_s_d ws, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]340 .set push
341 .set mips64r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]342 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]343 .set msa
Paul Burton8a3c8b42016-04-15 10:07:23 +0100[diff] [blame]344 copy_s.d $1, $w\ws[\n]
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]345 .set pop
346 .endm
347
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]348 .macro insert_w wd, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]349 .set push
350 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]351 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]352 .set msa
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]353 insert.w $w\wd[\n], $1
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]354 .set pop
355 .endm
356
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]357 .macro insert_d wd, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]358 .set push
359 .set mips64r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]360 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]361 .set msa
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]362 insert.d $w\wd[\n], $1
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]363 .set pop
364 .endm
365#else
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]366
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]367 /*
368 * Temporary until all toolchains in use include MSA support.
369 */
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]370 .macro _cfcmsa rd, cs
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]371 .set push
372 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]373 SET_HARDFLOAT
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]374 insn_if_mips 0x787e0059 | (\cs << 11)
375 insn32_if_mm 0x587e0056 | (\cs << 11)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]376 move \rd, $1
377 .set pop
378 .endm
379
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]380 .macro _ctcmsa cd, rs
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]381 .set push
382 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]383 SET_HARDFLOAT
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]384 move $1, \rs
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]385 insn_if_mips 0x783e0819 | (\cd << 6)
386 insn32_if_mm 0x583e0816 | (\cd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]387 .set pop
388 .endm
389
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]390 .macro ld_b wd, off, base
391 .set push
392 .set noat
393 SET_HARDFLOAT
James Hoganea168852016-04-15 10:07:24 +0100[diff] [blame]394 PTR_ADDU $1, \base, \off
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]395 insn_if_mips 0x78000820 | (\wd << 6)
396 insn32_if_mm 0x58000807 | (\wd << 6)
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]397 .set pop
398 .endm
399
400 .macro ld_h wd, off, base
401 .set push
402 .set noat
403 SET_HARDFLOAT
James Hoganea168852016-04-15 10:07:24 +0100[diff] [blame]404 PTR_ADDU $1, \base, \off
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]405 insn_if_mips 0x78000821 | (\wd << 6)
406 insn32_if_mm 0x58000817 | (\wd << 6)
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]407 .set pop
408 .endm
409
410 .macro ld_w wd, off, base
411 .set push
412 .set noat
413 SET_HARDFLOAT
James Hoganea168852016-04-15 10:07:24 +0100[diff] [blame]414 PTR_ADDU $1, \base, \off
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]415 insn_if_mips 0x78000822 | (\wd << 6)
416 insn32_if_mm 0x58000827 | (\wd << 6)
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]417 .set pop
418 .endm
419
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]420 .macro ld_d wd, off, base
421 .set push
422 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]423 SET_HARDFLOAT
James Hoganea168852016-04-15 10:07:24 +0100[diff] [blame]424 PTR_ADDU $1, \base, \off
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]425 insn_if_mips 0x78000823 | (\wd << 6)
426 insn32_if_mm 0x58000837 | (\wd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]427 .set pop
428 .endm
429
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]430 .macro st_b wd, off, base
431 .set push
432 .set noat
433 SET_HARDFLOAT
James Hoganea168852016-04-15 10:07:24 +0100[diff] [blame]434 PTR_ADDU $1, \base, \off
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]435 insn_if_mips 0x78000824 | (\wd << 6)
436 insn32_if_mm 0x5800080f | (\wd << 6)
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]437 .set pop
438 .endm
439
440 .macro st_h wd, off, base
441 .set push
442 .set noat
443 SET_HARDFLOAT
James Hoganea168852016-04-15 10:07:24 +0100[diff] [blame]444 PTR_ADDU $1, \base, \off
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]445 insn_if_mips 0x78000825 | (\wd << 6)
446 insn32_if_mm 0x5800081f | (\wd << 6)
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]447 .set pop
448 .endm
449
450 .macro st_w wd, off, base
451 .set push
452 .set noat
453 SET_HARDFLOAT
James Hoganea168852016-04-15 10:07:24 +0100[diff] [blame]454 PTR_ADDU $1, \base, \off
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]455 insn_if_mips 0x78000826 | (\wd << 6)
456 insn32_if_mm 0x5800082f | (\wd << 6)
Paul Burton6b35e112015-06-22 12:20:59 +0100[diff] [blame]457 .set pop
458 .endm
459
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]460 .macro st_d wd, off, base
461 .set push
462 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]463 SET_HARDFLOAT
James Hoganea168852016-04-15 10:07:24 +0100[diff] [blame]464 PTR_ADDU $1, \base, \off
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]465 insn_if_mips 0x78000827 | (\wd << 6)
466 insn32_if_mm 0x5800083f | (\wd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]467 .set pop
468 .endm
469
Paul Burton8a3c8b42016-04-15 10:07:23 +0100[diff] [blame]470 .macro copy_s_w ws, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]471 .set push
472 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]473 SET_HARDFLOAT
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]474 insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
475 insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]476 .set pop
477 .endm
478
Paul Burton8a3c8b42016-04-15 10:07:23 +0100[diff] [blame]479 .macro copy_s_d ws, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]480 .set push
481 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]482 SET_HARDFLOAT
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]483 insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
484 insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]485 .set pop
486 .endm
487
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]488 .macro insert_w wd, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]489 .set push
490 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]491 SET_HARDFLOAT
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]492 insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
493 insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]494 .set pop
495 .endm
496
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]497 .macro insert_d wd, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]498 .set push
499 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]500 SET_HARDFLOAT
James Hogan6e1b29c2016-05-20 23:28:39 +0100[diff] [blame]501 insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
502 insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]503 .set pop
504 .endm
505#endif
506
James Hogan143e93d2016-04-15 10:07:25 +0100[diff] [blame]507#ifdef TOOLCHAIN_SUPPORTS_MSA
508#define FPR_BASE_OFFS THREAD_FPR0
509#define FPR_BASE $1
510#else
511#define FPR_BASE_OFFS 0
512#define FPR_BASE \thread
513#endif
514
Paul Burton1db1af82014-01-27 15:23:11 +0000[diff] [blame]515 .macro msa_save_all thread
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]516 .set push
517 .set noat
James Hogan143e93d2016-04-15 10:07:25 +0100[diff] [blame]518#ifdef TOOLCHAIN_SUPPORTS_MSA
519 PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
520#endif
521 st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
522 st_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
523 st_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
524 st_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
525 st_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
526 st_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
527 st_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
528 st_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
529 st_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
530 st_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
531 st_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
532 st_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
533 st_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
534 st_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
535 st_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
536 st_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
537 st_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
538 st_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
539 st_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
540 st_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
541 st_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
542 st_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
543 st_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
544 st_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
545 st_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
546 st_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
547 st_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
548 st_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
549 st_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
550 st_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
551 st_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
552 st_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]553 SET_HARDFLOAT
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]554 _cfcmsa $1, MSA_CSR
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]555 sw $1, THREAD_MSA_CSR(\thread)
556 .set pop
Paul Burton1db1af82014-01-27 15:23:11 +0000[diff] [blame]557 .endm
558
559 .macro msa_restore_all thread
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]560 .set push
561 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]562 SET_HARDFLOAT
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]563 lw $1, THREAD_MSA_CSR(\thread)
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]564 _ctcmsa MSA_CSR, $1
James Hogan143e93d2016-04-15 10:07:25 +0100[diff] [blame]565#ifdef TOOLCHAIN_SUPPORTS_MSA
566 PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
567#endif
568 ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
569 ld_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
570 ld_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
571 ld_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
572 ld_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
573 ld_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
574 ld_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
575 ld_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
576 ld_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
577 ld_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
578 ld_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
579 ld_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
580 ld_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
581 ld_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
582 ld_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
583 ld_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
584 ld_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
585 ld_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
586 ld_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
587 ld_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
588 ld_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
589 ld_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
590 ld_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
591 ld_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
592 ld_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
593 ld_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
594 ld_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
595 ld_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
596 ld_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
597 ld_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
598 ld_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
599 ld_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
600 .set pop
Paul Burton1db1af82014-01-27 15:23:11 +0000[diff] [blame]601 .endm
602
James Hogan143e93d2016-04-15 10:07:25 +0100[diff] [blame]603#undef FPR_BASE_OFFS
604#undef FPR_BASE
605
Paul Burtonc9017752014-07-30 08:53:20 +0100[diff] [blame]606 .macro msa_init_upper wd
607#ifdef CONFIG_64BIT
608 insert_d \wd, 1
609#else
610 insert_w \wd, 2
611 insert_w \wd, 3
612#endif
Paul Burtonc9017752014-07-30 08:53:20 +0100[diff] [blame]613 .endm
614
615 .macro msa_init_all_upper
616 .set push
617 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]618 SET_HARDFLOAT
Paul Burtonc9017752014-07-30 08:53:20 +0100[diff] [blame]619 not $1, zero
620 msa_init_upper 0
Paul Burtona3a498102015-01-30 12:09:32 +0000[diff] [blame]621 msa_init_upper 1
622 msa_init_upper 2
623 msa_init_upper 3
624 msa_init_upper 4
625 msa_init_upper 5
626 msa_init_upper 6
627 msa_init_upper 7
628 msa_init_upper 8
629 msa_init_upper 9
630 msa_init_upper 10
631 msa_init_upper 11
632 msa_init_upper 12
633 msa_init_upper 13
634 msa_init_upper 14
635 msa_init_upper 15
636 msa_init_upper 16
637 msa_init_upper 17
638 msa_init_upper 18
639 msa_init_upper 19
640 msa_init_upper 20
641 msa_init_upper 21
642 msa_init_upper 22
643 msa_init_upper 23
644 msa_init_upper 24
645 msa_init_upper 25
646 msa_init_upper 26
647 msa_init_upper 27
648 msa_init_upper 28
649 msa_init_upper 29
650 msa_init_upper 30
651 msa_init_upper 31
Paul Burtonc9017752014-07-30 08:53:20 +0100[diff] [blame]652 .set pop
653 .endm
654
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]655#endif /* _ASM_ASMMACRO_H */