Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1 | /* |
Aravind Gopalakrishnan | ea2ca36 | 2016-03-07 14:02:21 +0100 | [diff] [blame] | 2 | * (c) 2005-2016 Advanced Micro Devices, Inc. |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 3 | * Your use of this code is subject to the terms and conditions of the |
| 4 | * GNU general public license version 2. See "COPYING" or |
| 5 | * http://www.gnu.org/licenses/gpl.html |
| 6 | * |
| 7 | * Written by Jacob Shin - AMD, Inc. |
Borislav Petkov | e6d41e8 | 2012-10-29 18:40:08 +0100 | [diff] [blame] | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 9 | * |
Borislav Petkov | 3490c0e | 2015-05-07 12:06:43 +0200 | [diff] [blame] | 10 | * All MC4_MISCi registers are shared between cores on a node. |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 11 | */ |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 12 | #include <linux/interrupt.h> |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 13 | #include <linux/notifier.h> |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 14 | #include <linux/kobject.h> |
Hidetoshi Seto | 34fa196 | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 15 | #include <linux/percpu.h> |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 16 | #include <linux/errno.h> |
| 17 | #include <linux/sched.h> |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 18 | #include <linux/sysfs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 19 | #include <linux/slab.h> |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 20 | #include <linux/init.h> |
| 21 | #include <linux/cpu.h> |
| 22 | #include <linux/smp.h> |
Yazen Ghannam | 87a6d40 | 2016-09-12 09:59:35 +0200 | [diff] [blame] | 23 | #include <linux/string.h> |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 24 | |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 25 | #include <asm/amd_nb.h> |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 26 | #include <asm/apic.h> |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 27 | #include <asm/idle.h> |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 28 | #include <asm/mce.h> |
| 29 | #include <asm/msr.h> |
Aravind Gopalakrishnan | 24fd78a | 2015-05-06 06:58:56 -0500 | [diff] [blame] | 30 | #include <asm/trace/irq_vectors.h> |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 31 | |
Aravind Gopalakrishnan | 60f116f | 2016-01-25 20:41:50 +0100 | [diff] [blame] | 32 | #define NR_BLOCKS 5 |
Jacob Shin | 2903ee8 | 2006-06-26 13:58:56 +0200 | [diff] [blame] | 33 | #define THRESHOLD_MAX 0xFFF |
| 34 | #define INT_TYPE_APIC 0x00020000 |
| 35 | #define MASK_VALID_HI 0x80000000 |
Jan Beulich | 24ce0e9 | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 36 | #define MASK_CNTP_HI 0x40000000 |
| 37 | #define MASK_LOCKED_HI 0x20000000 |
Jacob Shin | 2903ee8 | 2006-06-26 13:58:56 +0200 | [diff] [blame] | 38 | #define MASK_LVTOFF_HI 0x00F00000 |
| 39 | #define MASK_COUNT_EN_HI 0x00080000 |
| 40 | #define MASK_INT_TYPE_HI 0x00060000 |
| 41 | #define MASK_OVERFLOW_HI 0x00010000 |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 42 | #define MASK_ERR_COUNT_HI 0x00000FFF |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 43 | #define MASK_BLKPTR_LO 0xFF000000 |
| 44 | #define MCG_XBLK_ADDR 0xC0000400 |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 45 | |
Aravind Gopalakrishnan | 24fd78a | 2015-05-06 06:58:56 -0500 | [diff] [blame] | 46 | /* Deferred error settings */ |
| 47 | #define MSR_CU_DEF_ERR 0xC0000410 |
| 48 | #define MASK_DEF_LVTOFF 0x000000F0 |
| 49 | #define MASK_DEF_INT_TYPE 0x00000006 |
| 50 | #define DEF_LVT_OFF 0x2 |
| 51 | #define DEF_INT_TYPE_APIC 0x2 |
| 52 | |
Aravind Gopalakrishnan | f57a1f3 | 2016-01-25 20:41:51 +0100 | [diff] [blame] | 53 | /* Scalable MCA: */ |
| 54 | |
| 55 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ |
| 56 | #define SMCA_THR_LVT_OFF 0xF000 |
| 57 | |
Borislav Petkov | 336d335 | 2012-05-04 17:05:27 +0200 | [diff] [blame] | 58 | static const char * const th_names[] = { |
| 59 | "load_store", |
| 60 | "insn_fetch", |
| 61 | "combined_unit", |
| 62 | "", |
| 63 | "northbridge", |
| 64 | "execution_unit", |
| 65 | }; |
| 66 | |
Yazen Ghannam | 87a6d40 | 2016-09-12 09:59:35 +0200 | [diff] [blame] | 67 | static const char * const smca_umc_block_names[] = { |
| 68 | "dram_ecc", |
| 69 | "misc_umc" |
| 70 | }; |
| 71 | |
Yazen Ghannam | 5896820 | 2016-09-12 09:59:34 +0200 | [diff] [blame] | 72 | struct smca_bank_name smca_bank_names[] = { |
| 73 | [SMCA_LS] = { "load_store", "Load Store Unit" }, |
| 74 | [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, |
| 75 | [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, |
| 76 | [SMCA_DE] = { "decode_unit", "Decode Unit" }, |
| 77 | [SMCA_EX] = { "execution_unit", "Execution Unit" }, |
| 78 | [SMCA_FP] = { "floating_point", "Floating Point Unit" }, |
| 79 | [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, |
| 80 | [SMCA_CS] = { "coherent_slave", "Coherent Slave" }, |
| 81 | [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, |
| 82 | [SMCA_UMC] = { "umc", "Unified Memory Controller" }, |
| 83 | [SMCA_PB] = { "param_block", "Parameter Block" }, |
| 84 | [SMCA_PSP] = { "psp", "Platform Security Processor" }, |
| 85 | [SMCA_SMU] = { "smu", "System Management Unit" }, |
Aravind Gopalakrishnan | be0aec2 | 2016-03-07 14:02:18 +0100 | [diff] [blame] | 86 | }; |
Yazen Ghannam | 5896820 | 2016-09-12 09:59:34 +0200 | [diff] [blame] | 87 | EXPORT_SYMBOL_GPL(smca_bank_names); |
Aravind Gopalakrishnan | be0aec2 | 2016-03-07 14:02:18 +0100 | [diff] [blame] | 88 | |
Yazen Ghannam | 5896820 | 2016-09-12 09:59:34 +0200 | [diff] [blame] | 89 | static struct smca_hwid_mcatype smca_hwid_mcatypes[] = { |
| 90 | /* { bank_type, hwid_mcatype, xec_bitmap } */ |
Aravind Gopalakrishnan | be0aec2 | 2016-03-07 14:02:18 +0100 | [diff] [blame] | 91 | |
Yazen Ghannam | 5896820 | 2016-09-12 09:59:34 +0200 | [diff] [blame] | 92 | /* ZN Core (HWID=0xB0) MCA types */ |
| 93 | { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF }, |
| 94 | { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF }, |
| 95 | { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF }, |
| 96 | { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF }, |
| 97 | /* HWID 0xB0 MCATYPE 0x4 is Reserved */ |
| 98 | { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0x7FF }, |
| 99 | { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F }, |
| 100 | { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF }, |
| 101 | |
| 102 | /* Data Fabric MCA types */ |
| 103 | { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF }, |
| 104 | { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0xF }, |
| 105 | |
| 106 | /* Unified Memory Controller MCA type */ |
| 107 | { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0x3F }, |
| 108 | |
| 109 | /* Parameter Block MCA type */ |
| 110 | { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 }, |
| 111 | |
| 112 | /* Platform Security Processor MCA type */ |
| 113 | { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 }, |
| 114 | |
| 115 | /* System Management Unit MCA type */ |
| 116 | { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, |
Aravind Gopalakrishnan | be0aec2 | 2016-03-07 14:02:18 +0100 | [diff] [blame] | 117 | }; |
Yazen Ghannam | 5896820 | 2016-09-12 09:59:34 +0200 | [diff] [blame] | 118 | |
| 119 | struct smca_bank_info smca_banks[MAX_NR_BANKS]; |
| 120 | EXPORT_SYMBOL_GPL(smca_banks); |
Aravind Gopalakrishnan | be0aec2 | 2016-03-07 14:02:18 +0100 | [diff] [blame] | 121 | |
Yazen Ghannam | 87a6d40 | 2016-09-12 09:59:35 +0200 | [diff] [blame] | 122 | /* |
| 123 | * In SMCA enabled processors, we can have multiple banks for a given IP type. |
| 124 | * So to define a unique name for each bank, we use a temp c-string to append |
| 125 | * the MCA_IPID[InstanceId] to type's name in get_name(). |
| 126 | * |
| 127 | * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN |
| 128 | * is greater than 8 plus 1 (for underscore) plus length of longest type name. |
| 129 | */ |
| 130 | #define MAX_MCATYPE_NAME_LEN 30 |
| 131 | static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; |
| 132 | |
Boris Ostrovsky | bafcdd3 | 2013-03-14 17:10:41 -0400 | [diff] [blame] | 133 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
Aravind Gopalakrishnan | 955d142 | 2016-07-08 11:09:38 +0200 | [diff] [blame] | 134 | static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */ |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 135 | |
Andi Kleen | b276268 | 2009-02-12 13:49:31 +0100 | [diff] [blame] | 136 | static void amd_threshold_interrupt(void); |
Aravind Gopalakrishnan | 24fd78a | 2015-05-06 06:58:56 -0500 | [diff] [blame] | 137 | static void amd_deferred_error_interrupt(void); |
| 138 | |
| 139 | static void default_deferred_error_interrupt(void) |
| 140 | { |
| 141 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); |
| 142 | } |
| 143 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; |
Andi Kleen | b276268 | 2009-02-12 13:49:31 +0100 | [diff] [blame] | 144 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 145 | /* |
| 146 | * CPU Initialization |
| 147 | */ |
| 148 | |
Yazen Ghannam | 5896820 | 2016-09-12 09:59:34 +0200 | [diff] [blame] | 149 | static void get_smca_bank_info(unsigned int bank) |
| 150 | { |
| 151 | unsigned int i, hwid_mcatype, cpu = smp_processor_id(); |
| 152 | struct smca_hwid_mcatype *type; |
| 153 | u32 high, instanceId; |
| 154 | u16 hwid, mcatype; |
| 155 | |
| 156 | /* Collect bank_info using CPU 0 for now. */ |
| 157 | if (cpu) |
| 158 | return; |
| 159 | |
| 160 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &instanceId, &high)) { |
| 161 | pr_warn("Failed to read MCA_IPID for bank %d\n", bank); |
| 162 | return; |
| 163 | } |
| 164 | |
| 165 | hwid = high & MCI_IPID_HWID; |
| 166 | mcatype = (high & MCI_IPID_MCATYPE) >> 16; |
| 167 | hwid_mcatype = HWID_MCATYPE(hwid, mcatype); |
| 168 | |
| 169 | for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { |
| 170 | type = &smca_hwid_mcatypes[i]; |
| 171 | if (hwid_mcatype == type->hwid_mcatype) { |
| 172 | smca_banks[bank].type = type; |
| 173 | smca_banks[bank].type_instance = instanceId; |
| 174 | break; |
| 175 | } |
| 176 | } |
| 177 | } |
| 178 | |
Mike Travis | 4cd4601 | 2008-12-16 17:34:04 -0800 | [diff] [blame] | 179 | struct thresh_restart { |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 180 | struct threshold_block *b; |
| 181 | int reset; |
Robert Richter | 9c37c9d | 2010-10-25 16:03:35 +0200 | [diff] [blame] | 182 | int set_lvt_off; |
| 183 | int lvt_off; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 184 | u16 old_limit; |
Mike Travis | 4cd4601 | 2008-12-16 17:34:04 -0800 | [diff] [blame] | 185 | }; |
| 186 | |
Boris Ostrovsky | c76e816 | 2013-03-14 17:10:40 -0400 | [diff] [blame] | 187 | static inline bool is_shared_bank(int bank) |
| 188 | { |
Aravind Gopalakrishnan | 284b965 | 2016-01-25 20:41:49 +0100 | [diff] [blame] | 189 | /* |
| 190 | * Scalable MCA provides for only one core to have access to the MSRs of |
| 191 | * a shared bank. |
| 192 | */ |
| 193 | if (mce_flags.smca) |
| 194 | return false; |
| 195 | |
Boris Ostrovsky | c76e816 | 2013-03-14 17:10:40 -0400 | [diff] [blame] | 196 | /* Bank 4 is for northbridge reporting and is thus shared */ |
| 197 | return (bank == 4); |
| 198 | } |
| 199 | |
Jan Beulich | 2cd4c30 | 2015-01-23 08:32:01 +0000 | [diff] [blame] | 200 | static const char *bank4_names(const struct threshold_block *b) |
Borislav Petkov | 336d335 | 2012-05-04 17:05:27 +0200 | [diff] [blame] | 201 | { |
| 202 | switch (b->address) { |
| 203 | /* MSR4_MISC0 */ |
| 204 | case 0x00000413: |
| 205 | return "dram"; |
| 206 | |
| 207 | case 0xc0000408: |
| 208 | return "ht_links"; |
| 209 | |
| 210 | case 0xc0000409: |
| 211 | return "l3_cache"; |
| 212 | |
| 213 | default: |
| 214 | WARN(1, "Funny MSR: 0x%08x\n", b->address); |
| 215 | return ""; |
| 216 | } |
| 217 | }; |
| 218 | |
| 219 | |
Borislav Petkov | f227d43 | 2012-04-16 18:01:53 +0200 | [diff] [blame] | 220 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
| 221 | { |
| 222 | /* |
| 223 | * bank 4 supports APIC LVT interrupts implicitly since forever. |
| 224 | */ |
| 225 | if (bank == 4) |
| 226 | return true; |
| 227 | |
| 228 | /* |
| 229 | * IntP: interrupt present; if this bit is set, the thresholding |
| 230 | * bank can generate APIC LVT interrupts |
| 231 | */ |
| 232 | return msr_high_bits & BIT(28); |
| 233 | } |
| 234 | |
Robert Richter | bbaff08 | 2010-10-25 16:03:37 +0200 | [diff] [blame] | 235 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
| 236 | { |
| 237 | int msr = (hi & MASK_LVTOFF_HI) >> 20; |
| 238 | |
| 239 | if (apic < 0) { |
| 240 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " |
| 241 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, |
| 242 | b->bank, b->block, b->address, hi, lo); |
| 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | if (apic != msr) { |
Aravind Gopalakrishnan | f57a1f3 | 2016-01-25 20:41:51 +0100 | [diff] [blame] | 247 | /* |
| 248 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and |
| 249 | * the BIOS provides the value. The original field where LVT offset |
| 250 | * was set is reserved. Return early here: |
| 251 | */ |
| 252 | if (mce_flags.smca) |
| 253 | return 0; |
| 254 | |
Robert Richter | bbaff08 | 2010-10-25 16:03:37 +0200 | [diff] [blame] | 255 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
| 256 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", |
| 257 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); |
| 258 | return 0; |
| 259 | } |
| 260 | |
| 261 | return 1; |
| 262 | }; |
| 263 | |
Aravind Gopalakrishnan | ea2ca36 | 2016-03-07 14:02:21 +0100 | [diff] [blame] | 264 | /* Reprogram MCx_MISC MSR behind this threshold bank. */ |
Andrew Morton | a6b6a14 | 2009-03-18 10:40:25 +1030 | [diff] [blame] | 265 | static void threshold_restart_bank(void *_tr) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 266 | { |
Mike Travis | 4cd4601 | 2008-12-16 17:34:04 -0800 | [diff] [blame] | 267 | struct thresh_restart *tr = _tr; |
Robert Richter | 7203a04 | 2010-10-25 16:03:36 +0200 | [diff] [blame] | 268 | u32 hi, lo; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 269 | |
Robert Richter | 7203a04 | 2010-10-25 16:03:36 +0200 | [diff] [blame] | 270 | rdmsr(tr->b->address, lo, hi); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 271 | |
Robert Richter | 7203a04 | 2010-10-25 16:03:36 +0200 | [diff] [blame] | 272 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
Mike Travis | 4cd4601 | 2008-12-16 17:34:04 -0800 | [diff] [blame] | 273 | tr->reset = 1; /* limit cannot be lower than err count */ |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 274 | |
Mike Travis | 4cd4601 | 2008-12-16 17:34:04 -0800 | [diff] [blame] | 275 | if (tr->reset) { /* reset err count and overflow bit */ |
Robert Richter | 7203a04 | 2010-10-25 16:03:36 +0200 | [diff] [blame] | 276 | hi = |
| 277 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | |
Mike Travis | 4cd4601 | 2008-12-16 17:34:04 -0800 | [diff] [blame] | 278 | (THRESHOLD_MAX - tr->b->threshold_limit); |
| 279 | } else if (tr->old_limit) { /* change limit w/o reset */ |
Robert Richter | 7203a04 | 2010-10-25 16:03:36 +0200 | [diff] [blame] | 280 | int new_count = (hi & THRESHOLD_MAX) + |
Mike Travis | 4cd4601 | 2008-12-16 17:34:04 -0800 | [diff] [blame] | 281 | (tr->old_limit - tr->b->threshold_limit); |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 282 | |
Robert Richter | 7203a04 | 2010-10-25 16:03:36 +0200 | [diff] [blame] | 283 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 284 | (new_count & THRESHOLD_MAX); |
| 285 | } |
| 286 | |
Borislav Petkov | f227d43 | 2012-04-16 18:01:53 +0200 | [diff] [blame] | 287 | /* clear IntType */ |
| 288 | hi &= ~MASK_INT_TYPE_HI; |
| 289 | |
| 290 | if (!tr->b->interrupt_capable) |
| 291 | goto done; |
| 292 | |
Robert Richter | 9c37c9d | 2010-10-25 16:03:35 +0200 | [diff] [blame] | 293 | if (tr->set_lvt_off) { |
Robert Richter | bbaff08 | 2010-10-25 16:03:37 +0200 | [diff] [blame] | 294 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
| 295 | /* set new lvt offset */ |
| 296 | hi &= ~MASK_LVTOFF_HI; |
| 297 | hi |= tr->lvt_off << 20; |
| 298 | } |
Robert Richter | 9c37c9d | 2010-10-25 16:03:35 +0200 | [diff] [blame] | 299 | } |
| 300 | |
Borislav Petkov | f227d43 | 2012-04-16 18:01:53 +0200 | [diff] [blame] | 301 | if (tr->b->interrupt_enable) |
| 302 | hi |= INT_TYPE_APIC; |
| 303 | |
| 304 | done: |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 305 | |
Robert Richter | 7203a04 | 2010-10-25 16:03:36 +0200 | [diff] [blame] | 306 | hi |= MASK_COUNT_EN_HI; |
| 307 | wrmsr(tr->b->address, lo, hi); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 308 | } |
| 309 | |
Robert Richter | 9c37c9d | 2010-10-25 16:03:35 +0200 | [diff] [blame] | 310 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
| 311 | { |
| 312 | struct thresh_restart tr = { |
| 313 | .b = b, |
| 314 | .set_lvt_off = 1, |
| 315 | .lvt_off = offset, |
| 316 | }; |
| 317 | |
| 318 | b->threshold_limit = THRESHOLD_MAX; |
| 319 | threshold_restart_bank(&tr); |
| 320 | }; |
| 321 | |
Aravind Gopalakrishnan | 868c00b | 2015-05-06 06:58:58 -0500 | [diff] [blame] | 322 | static int setup_APIC_mce_threshold(int reserved, int new) |
Robert Richter | bbaff08 | 2010-10-25 16:03:37 +0200 | [diff] [blame] | 323 | { |
| 324 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, |
| 325 | APIC_EILVT_MSG_FIX, 0)) |
| 326 | return new; |
| 327 | |
| 328 | return reserved; |
| 329 | } |
| 330 | |
Aravind Gopalakrishnan | 24fd78a | 2015-05-06 06:58:56 -0500 | [diff] [blame] | 331 | static int setup_APIC_deferred_error(int reserved, int new) |
| 332 | { |
| 333 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, |
| 334 | APIC_EILVT_MSG_FIX, 0)) |
| 335 | return new; |
| 336 | |
| 337 | return reserved; |
| 338 | } |
| 339 | |
| 340 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) |
| 341 | { |
| 342 | u32 low = 0, high = 0; |
| 343 | int def_offset = -1, def_new; |
| 344 | |
| 345 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) |
| 346 | return; |
| 347 | |
| 348 | def_new = (low & MASK_DEF_LVTOFF) >> 4; |
| 349 | if (!(low & MASK_DEF_LVTOFF)) { |
| 350 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); |
| 351 | def_new = DEF_LVT_OFF; |
| 352 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); |
| 353 | } |
| 354 | |
| 355 | def_offset = setup_APIC_deferred_error(def_offset, def_new); |
| 356 | if ((def_offset == def_new) && |
| 357 | (deferred_error_int_vector != amd_deferred_error_interrupt)) |
| 358 | deferred_error_int_vector = amd_deferred_error_interrupt; |
| 359 | |
| 360 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; |
| 361 | wrmsr(MSR_CU_DEF_ERR, low, high); |
| 362 | } |
| 363 | |
Yazen Ghannam | cfee4f6 | 2016-09-12 09:59:31 +0200 | [diff] [blame] | 364 | static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high, |
Aravind Gopalakrishnan | 8dd1e17 | 2016-03-07 14:02:19 +0100 | [diff] [blame] | 365 | unsigned int bank, unsigned int block) |
| 366 | { |
| 367 | u32 addr = 0, offset = 0; |
| 368 | |
| 369 | if (mce_flags.smca) { |
| 370 | if (!block) { |
| 371 | addr = MSR_AMD64_SMCA_MCx_MISC(bank); |
| 372 | } else { |
| 373 | /* |
| 374 | * For SMCA enabled processors, BLKPTR field of the |
| 375 | * first MISC register (MCx_MISC0) indicates presence of |
| 376 | * additional MISC register set (MISC1-4). |
| 377 | */ |
| 378 | u32 low, high; |
| 379 | |
Yazen Ghannam | cfee4f6 | 2016-09-12 09:59:31 +0200 | [diff] [blame] | 380 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) |
Aravind Gopalakrishnan | 8dd1e17 | 2016-03-07 14:02:19 +0100 | [diff] [blame] | 381 | return addr; |
| 382 | |
| 383 | if (!(low & MCI_CONFIG_MCAX)) |
| 384 | return addr; |
| 385 | |
Yazen Ghannam | cfee4f6 | 2016-09-12 09:59:31 +0200 | [diff] [blame] | 386 | if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && |
Aravind Gopalakrishnan | 8dd1e17 | 2016-03-07 14:02:19 +0100 | [diff] [blame] | 387 | (low & MASK_BLKPTR_LO)) |
| 388 | addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); |
| 389 | } |
| 390 | return addr; |
| 391 | } |
| 392 | |
| 393 | /* Fall back to method we used for older processors: */ |
| 394 | switch (block) { |
| 395 | case 0: |
Yazen Ghannam | d9d73fc | 2016-04-30 14:33:55 +0200 | [diff] [blame] | 396 | addr = msr_ops.misc(bank); |
Aravind Gopalakrishnan | 8dd1e17 | 2016-03-07 14:02:19 +0100 | [diff] [blame] | 397 | break; |
| 398 | case 1: |
| 399 | offset = ((low & MASK_BLKPTR_LO) >> 21); |
| 400 | if (offset) |
| 401 | addr = MCG_XBLK_ADDR + offset; |
| 402 | break; |
| 403 | default: |
| 404 | addr = ++current_addr; |
| 405 | } |
| 406 | return addr; |
| 407 | } |
| 408 | |
Borislav Petkov | 429893b | 2016-01-25 20:41:52 +0100 | [diff] [blame] | 409 | static int |
| 410 | prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, |
| 411 | int offset, u32 misc_high) |
| 412 | { |
| 413 | unsigned int cpu = smp_processor_id(); |
Borislav Petkov | e128b4f | 2016-05-11 14:58:25 +0200 | [diff] [blame] | 414 | u32 smca_low, smca_high, smca_addr; |
Borislav Petkov | 429893b | 2016-01-25 20:41:52 +0100 | [diff] [blame] | 415 | struct threshold_block b; |
| 416 | int new; |
| 417 | |
| 418 | if (!block) |
| 419 | per_cpu(bank_map, cpu) |= (1 << bank); |
| 420 | |
| 421 | memset(&b, 0, sizeof(b)); |
| 422 | b.cpu = cpu; |
| 423 | b.bank = bank; |
| 424 | b.block = block; |
| 425 | b.address = addr; |
| 426 | b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); |
| 427 | |
| 428 | if (!b.interrupt_capable) |
| 429 | goto done; |
| 430 | |
| 431 | b.interrupt_enable = 1; |
| 432 | |
Borislav Petkov | e128b4f | 2016-05-11 14:58:25 +0200 | [diff] [blame] | 433 | if (!mce_flags.smca) { |
Borislav Petkov | 429893b | 2016-01-25 20:41:52 +0100 | [diff] [blame] | 434 | new = (misc_high & MASK_LVTOFF_HI) >> 20; |
Borislav Petkov | e128b4f | 2016-05-11 14:58:25 +0200 | [diff] [blame] | 435 | goto set_offset; |
Borislav Petkov | 429893b | 2016-01-25 20:41:52 +0100 | [diff] [blame] | 436 | } |
| 437 | |
Borislav Petkov | e128b4f | 2016-05-11 14:58:25 +0200 | [diff] [blame] | 438 | smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank); |
| 439 | |
| 440 | if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) { |
| 441 | /* |
| 442 | * OS is required to set the MCAX bit to acknowledge that it is |
| 443 | * now using the new MSR ranges and new registers under each |
| 444 | * bank. It also means that the OS will configure deferred |
| 445 | * errors in the new MCx_CONFIG register. If the bit is not set, |
| 446 | * uncorrectable errors will cause a system panic. |
| 447 | * |
| 448 | * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) |
| 449 | */ |
| 450 | smca_high |= BIT(0); |
| 451 | |
| 452 | /* |
| 453 | * SMCA logs Deferred Error information in MCA_DE{STAT,ADDR} |
| 454 | * registers with the option of additionally logging to |
| 455 | * MCA_{STATUS,ADDR} if MCA_CONFIG[LogDeferredInMcaStat] is set. |
| 456 | * |
| 457 | * This bit is usually set by BIOS to retain the old behavior |
| 458 | * for OSes that don't use the new registers. Linux supports the |
| 459 | * new registers so let's disable that additional logging here. |
| 460 | * |
| 461 | * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in the high |
| 462 | * portion of the MSR). |
| 463 | */ |
| 464 | smca_high &= ~BIT(2); |
| 465 | |
Yazen Ghannam | 66ef269 | 2016-09-12 09:59:36 +0200 | [diff] [blame] | 466 | /* |
| 467 | * SMCA sets the Deferred Error Interrupt type per bank. |
| 468 | * |
| 469 | * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us |
| 470 | * if the DeferredIntType bit field is available. |
| 471 | * |
| 472 | * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the |
| 473 | * high portion of the MSR). OS should set this to 0x1 to enable |
| 474 | * APIC based interrupt. First, check that no interrupt has been |
| 475 | * set. |
| 476 | */ |
| 477 | if ((smca_low & BIT(5)) && !((smca_high >> 5) & 0x3)) |
| 478 | smca_high |= BIT(5); |
| 479 | |
Borislav Petkov | e128b4f | 2016-05-11 14:58:25 +0200 | [diff] [blame] | 480 | wrmsr(smca_addr, smca_low, smca_high); |
| 481 | } |
| 482 | |
| 483 | /* Gather LVT offset for thresholding: */ |
| 484 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) |
| 485 | goto out; |
| 486 | |
| 487 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; |
| 488 | |
| 489 | set_offset: |
Borislav Petkov | 429893b | 2016-01-25 20:41:52 +0100 | [diff] [blame] | 490 | offset = setup_APIC_mce_threshold(offset, new); |
| 491 | |
| 492 | if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt)) |
| 493 | mce_threshold_vector = amd_threshold_interrupt; |
| 494 | |
| 495 | done: |
| 496 | mce_threshold_block_init(&b, offset); |
| 497 | |
| 498 | out: |
| 499 | return offset; |
| 500 | } |
| 501 | |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 502 | /* cpu init entry point, called from mce.c with preempt off */ |
H. Peter Anvin | cc3ca22 | 2009-02-20 23:35:51 -0800 | [diff] [blame] | 503 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 504 | { |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 505 | u32 low = 0, high = 0, address = 0; |
Yazen Ghannam | cfee4f6 | 2016-09-12 09:59:31 +0200 | [diff] [blame] | 506 | unsigned int bank, block, cpu = smp_processor_id(); |
Borislav Petkov | 429893b | 2016-01-25 20:41:52 +0100 | [diff] [blame] | 507 | int offset = -1; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 508 | |
Boris Ostrovsky | bafcdd3 | 2013-03-14 17:10:41 -0400 | [diff] [blame] | 509 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
Yazen Ghannam | 5896820 | 2016-09-12 09:59:34 +0200 | [diff] [blame] | 510 | if (mce_flags.smca) |
| 511 | get_smca_bank_info(bank); |
| 512 | |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 513 | for (block = 0; block < NR_BLOCKS; ++block) { |
Yazen Ghannam | cfee4f6 | 2016-09-12 09:59:31 +0200 | [diff] [blame] | 514 | address = get_block_address(cpu, address, low, high, bank, block); |
Aravind Gopalakrishnan | 8dd1e17 | 2016-03-07 14:02:19 +0100 | [diff] [blame] | 515 | if (!address) |
| 516 | break; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 517 | |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 518 | if (rdmsr_safe(address, &low, &high)) |
Jan Beulich | 24ce0e9 | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 519 | break; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 520 | |
Borislav Petkov | 6dcbfe4 | 2010-10-08 12:08:34 +0200 | [diff] [blame] | 521 | if (!(high & MASK_VALID_HI)) |
| 522 | continue; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 523 | |
Jan Beulich | 24ce0e9 | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 524 | if (!(high & MASK_CNTP_HI) || |
| 525 | (high & MASK_LOCKED_HI)) |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 526 | continue; |
| 527 | |
Borislav Petkov | 429893b | 2016-01-25 20:41:52 +0100 | [diff] [blame] | 528 | offset = prepare_threshold_block(bank, block, address, offset, high); |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 529 | } |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 530 | } |
Aravind Gopalakrishnan | 24fd78a | 2015-05-06 06:58:56 -0500 | [diff] [blame] | 531 | |
| 532 | if (mce_flags.succor) |
| 533 | deferred_error_interrupt_enable(c); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 534 | } |
| 535 | |
Yazen Ghannam | 3410200 | 2016-05-11 14:58:23 +0200 | [diff] [blame] | 536 | static void |
| 537 | __log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc) |
Aravind Gopalakrishnan | afdf344 | 2015-05-06 06:58:53 -0500 | [diff] [blame] | 538 | { |
Yazen Ghannam | 3410200 | 2016-05-11 14:58:23 +0200 | [diff] [blame] | 539 | u32 msr_status = msr_ops.status(bank); |
| 540 | u32 msr_addr = msr_ops.addr(bank); |
Aravind Gopalakrishnan | afdf344 | 2015-05-06 06:58:53 -0500 | [diff] [blame] | 541 | struct mce m; |
| 542 | u64 status; |
| 543 | |
Yazen Ghannam | 3410200 | 2016-05-11 14:58:23 +0200 | [diff] [blame] | 544 | WARN_ON_ONCE(deferred_err && threshold_err); |
| 545 | |
| 546 | if (deferred_err && mce_flags.smca) { |
| 547 | msr_status = MSR_AMD64_SMCA_MCx_DESTAT(bank); |
| 548 | msr_addr = MSR_AMD64_SMCA_MCx_DEADDR(bank); |
| 549 | } |
| 550 | |
| 551 | rdmsrl(msr_status, status); |
| 552 | |
Aravind Gopalakrishnan | afdf344 | 2015-05-06 06:58:53 -0500 | [diff] [blame] | 553 | if (!(status & MCI_STATUS_VAL)) |
| 554 | return; |
| 555 | |
| 556 | mce_setup(&m); |
| 557 | |
| 558 | m.status = status; |
| 559 | m.bank = bank; |
Aravind Gopalakrishnan | 6e6e746 | 2015-05-06 06:58:54 -0500 | [diff] [blame] | 560 | |
Aravind Gopalakrishnan | afdf344 | 2015-05-06 06:58:53 -0500 | [diff] [blame] | 561 | if (threshold_err) |
| 562 | m.misc = misc; |
| 563 | |
Yazen Ghannam | 4f29b73 | 2016-09-12 09:59:39 +0200 | [diff] [blame] | 564 | if (m.status & MCI_STATUS_ADDRV) { |
Yazen Ghannam | 3410200 | 2016-05-11 14:58:23 +0200 | [diff] [blame] | 565 | rdmsrl(msr_addr, m.addr); |
Aravind Gopalakrishnan | afdf344 | 2015-05-06 06:58:53 -0500 | [diff] [blame] | 566 | |
Yazen Ghannam | 4f29b73 | 2016-09-12 09:59:39 +0200 | [diff] [blame] | 567 | /* |
| 568 | * Extract [55:<lsb>] where lsb is the least significant |
| 569 | * *valid* bit of the address bits. |
| 570 | */ |
| 571 | if (mce_flags.smca) { |
| 572 | u8 lsb = (m.addr >> 56) & 0x3f; |
| 573 | |
| 574 | m.addr &= GENMASK_ULL(55, lsb); |
| 575 | } |
| 576 | } |
| 577 | |
Yazen Ghannam | 5828c46 | 2016-09-12 09:59:37 +0200 | [diff] [blame] | 578 | if (mce_flags.smca) { |
| 579 | rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); |
| 580 | |
| 581 | if (m.status & MCI_STATUS_SYNDV) |
| 582 | rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); |
| 583 | } |
Yazen Ghannam | db819d6 | 2016-09-12 09:59:28 +0200 | [diff] [blame] | 584 | |
Aravind Gopalakrishnan | 6e6e746 | 2015-05-06 06:58:54 -0500 | [diff] [blame] | 585 | mce_log(&m); |
Yazen Ghannam | 3410200 | 2016-05-11 14:58:23 +0200 | [diff] [blame] | 586 | |
| 587 | wrmsrl(msr_status, 0); |
Aravind Gopalakrishnan | afdf344 | 2015-05-06 06:58:53 -0500 | [diff] [blame] | 588 | } |
| 589 | |
Aravind Gopalakrishnan | 24fd78a | 2015-05-06 06:58:56 -0500 | [diff] [blame] | 590 | static inline void __smp_deferred_error_interrupt(void) |
| 591 | { |
| 592 | inc_irq_stat(irq_deferred_error_count); |
| 593 | deferred_error_int_vector(); |
| 594 | } |
| 595 | |
| 596 | asmlinkage __visible void smp_deferred_error_interrupt(void) |
| 597 | { |
| 598 | entering_irq(); |
| 599 | __smp_deferred_error_interrupt(); |
| 600 | exiting_ack_irq(); |
| 601 | } |
| 602 | |
| 603 | asmlinkage __visible void smp_trace_deferred_error_interrupt(void) |
| 604 | { |
| 605 | entering_irq(); |
| 606 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); |
| 607 | __smp_deferred_error_interrupt(); |
| 608 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); |
| 609 | exiting_ack_irq(); |
| 610 | } |
| 611 | |
| 612 | /* APIC interrupt handler for deferred errors */ |
| 613 | static void amd_deferred_error_interrupt(void) |
| 614 | { |
Aravind Gopalakrishnan | 24fd78a | 2015-05-06 06:58:56 -0500 | [diff] [blame] | 615 | unsigned int bank; |
Yazen Ghannam | 3410200 | 2016-05-11 14:58:23 +0200 | [diff] [blame] | 616 | u32 msr_status; |
| 617 | u64 status; |
Aravind Gopalakrishnan | 24fd78a | 2015-05-06 06:58:56 -0500 | [diff] [blame] | 618 | |
| 619 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
Yazen Ghannam | 3410200 | 2016-05-11 14:58:23 +0200 | [diff] [blame] | 620 | msr_status = (mce_flags.smca) ? MSR_AMD64_SMCA_MCx_DESTAT(bank) |
| 621 | : msr_ops.status(bank); |
| 622 | |
| 623 | rdmsrl(msr_status, status); |
Aravind Gopalakrishnan | 24fd78a | 2015-05-06 06:58:56 -0500 | [diff] [blame] | 624 | |
| 625 | if (!(status & MCI_STATUS_VAL) || |
| 626 | !(status & MCI_STATUS_DEFERRED)) |
| 627 | continue; |
| 628 | |
Yazen Ghannam | 3410200 | 2016-05-11 14:58:23 +0200 | [diff] [blame] | 629 | __log_error(bank, true, false, 0); |
Aravind Gopalakrishnan | 24fd78a | 2015-05-06 06:58:56 -0500 | [diff] [blame] | 630 | break; |
| 631 | } |
| 632 | } |
| 633 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 634 | /* |
| 635 | * APIC Interrupt Handler |
| 636 | */ |
| 637 | |
| 638 | /* |
| 639 | * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. |
| 640 | * the interrupt goes off when error_count reaches threshold_limit. |
| 641 | * the handler will simply log mcelog w/ software defined bank number. |
| 642 | */ |
Aravind Gopalakrishnan | afdf344 | 2015-05-06 06:58:53 -0500 | [diff] [blame] | 643 | |
Andi Kleen | b276268 | 2009-02-12 13:49:31 +0100 | [diff] [blame] | 644 | static void amd_threshold_interrupt(void) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 645 | { |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 646 | u32 low = 0, high = 0, address = 0; |
Yazen Ghannam | cfee4f6 | 2016-09-12 09:59:31 +0200 | [diff] [blame] | 647 | unsigned int bank, block, cpu = smp_processor_id(); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 648 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 649 | /* assume first bank caused it */ |
Boris Ostrovsky | bafcdd3 | 2013-03-14 17:10:41 -0400 | [diff] [blame] | 650 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
Chen Yucong | 44612a3 | 2014-10-02 14:48:19 +0200 | [diff] [blame] | 651 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
Jan Beulich | 24ce0e9 | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 652 | continue; |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 653 | for (block = 0; block < NR_BLOCKS; ++block) { |
Yazen Ghannam | cfee4f6 | 2016-09-12 09:59:31 +0200 | [diff] [blame] | 654 | address = get_block_address(cpu, address, low, high, bank, block); |
Aravind Gopalakrishnan | 8dd1e17 | 2016-03-07 14:02:19 +0100 | [diff] [blame] | 655 | if (!address) |
| 656 | break; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 657 | |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 658 | if (rdmsr_safe(address, &low, &high)) |
Jan Beulich | 24ce0e9 | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 659 | break; |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 660 | |
| 661 | if (!(high & MASK_VALID_HI)) { |
| 662 | if (block) |
| 663 | continue; |
| 664 | else |
| 665 | break; |
| 666 | } |
| 667 | |
Jan Beulich | 24ce0e9 | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 668 | if (!(high & MASK_CNTP_HI) || |
| 669 | (high & MASK_LOCKED_HI)) |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 670 | continue; |
| 671 | |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 672 | /* |
| 673 | * Log the machine check that caused the threshold |
| 674 | * event. |
| 675 | */ |
Chen Yucong | 44612a3 | 2014-10-02 14:48:19 +0200 | [diff] [blame] | 676 | if (high & MASK_OVERFLOW_HI) |
| 677 | goto log; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 678 | } |
| 679 | } |
Chen Yucong | 44612a3 | 2014-10-02 14:48:19 +0200 | [diff] [blame] | 680 | return; |
| 681 | |
| 682 | log: |
Yazen Ghannam | 3410200 | 2016-05-11 14:58:23 +0200 | [diff] [blame] | 683 | __log_error(bank, false, true, ((u64)high << 32) | low); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 684 | } |
| 685 | |
| 686 | /* |
| 687 | * Sysfs Interface |
| 688 | */ |
| 689 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 690 | struct threshold_attr { |
Jacob Shin | 2903ee8 | 2006-06-26 13:58:56 +0200 | [diff] [blame] | 691 | struct attribute attr; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 692 | ssize_t (*show) (struct threshold_block *, char *); |
| 693 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 694 | }; |
| 695 | |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 696 | #define SHOW_FIELDS(name) \ |
| 697 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ |
| 698 | { \ |
Borislav Petkov | 18c20f3 | 2012-04-27 12:31:34 +0200 | [diff] [blame] | 699 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
Jacob Shin | 2903ee8 | 2006-06-26 13:58:56 +0200 | [diff] [blame] | 700 | } |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 701 | SHOW_FIELDS(interrupt_enable) |
| 702 | SHOW_FIELDS(threshold_limit) |
| 703 | |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 704 | static ssize_t |
Hidetoshi Seto | 9319cec | 2009-04-14 17:26:30 +0900 | [diff] [blame] | 705 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 706 | { |
Mike Travis | 4cd4601 | 2008-12-16 17:34:04 -0800 | [diff] [blame] | 707 | struct thresh_restart tr; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 708 | unsigned long new; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 709 | |
Borislav Petkov | f227d43 | 2012-04-16 18:01:53 +0200 | [diff] [blame] | 710 | if (!b->interrupt_capable) |
| 711 | return -EINVAL; |
| 712 | |
Daniel Walter | 164109e | 2014-08-08 14:24:03 -0700 | [diff] [blame] | 713 | if (kstrtoul(buf, 0, &new) < 0) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 714 | return -EINVAL; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 715 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 716 | b->interrupt_enable = !!new; |
| 717 | |
Robert Richter | 9c37c9d | 2010-10-25 16:03:35 +0200 | [diff] [blame] | 718 | memset(&tr, 0, sizeof(tr)); |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 719 | tr.b = b; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 720 | |
Andrew Morton | a6b6a14 | 2009-03-18 10:40:25 +1030 | [diff] [blame] | 721 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 722 | |
Hidetoshi Seto | 9319cec | 2009-04-14 17:26:30 +0900 | [diff] [blame] | 723 | return size; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 724 | } |
| 725 | |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 726 | static ssize_t |
Hidetoshi Seto | 9319cec | 2009-04-14 17:26:30 +0900 | [diff] [blame] | 727 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 728 | { |
Mike Travis | 4cd4601 | 2008-12-16 17:34:04 -0800 | [diff] [blame] | 729 | struct thresh_restart tr; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 730 | unsigned long new; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 731 | |
Daniel Walter | 164109e | 2014-08-08 14:24:03 -0700 | [diff] [blame] | 732 | if (kstrtoul(buf, 0, &new) < 0) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 733 | return -EINVAL; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 734 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 735 | if (new > THRESHOLD_MAX) |
| 736 | new = THRESHOLD_MAX; |
| 737 | if (new < 1) |
| 738 | new = 1; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 739 | |
Robert Richter | 9c37c9d | 2010-10-25 16:03:35 +0200 | [diff] [blame] | 740 | memset(&tr, 0, sizeof(tr)); |
Mike Travis | 4cd4601 | 2008-12-16 17:34:04 -0800 | [diff] [blame] | 741 | tr.old_limit = b->threshold_limit; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 742 | b->threshold_limit = new; |
Mike Travis | 4cd4601 | 2008-12-16 17:34:04 -0800 | [diff] [blame] | 743 | tr.b = b; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 744 | |
Andrew Morton | a6b6a14 | 2009-03-18 10:40:25 +1030 | [diff] [blame] | 745 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 746 | |
Hidetoshi Seto | 9319cec | 2009-04-14 17:26:30 +0900 | [diff] [blame] | 747 | return size; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 748 | } |
| 749 | |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 750 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 751 | { |
Borislav Petkov | 2c9c42f | 2012-04-27 12:53:59 +0200 | [diff] [blame] | 752 | u32 lo, hi; |
Andrew Morton | a6b6a14 | 2009-03-18 10:40:25 +1030 | [diff] [blame] | 753 | |
Borislav Petkov | 2c9c42f | 2012-04-27 12:53:59 +0200 | [diff] [blame] | 754 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); |
| 755 | |
| 756 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
| 757 | (THRESHOLD_MAX - b->threshold_limit))); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 758 | } |
| 759 | |
Borislav Petkov | 6e92736 | 2012-04-27 15:37:25 +0200 | [diff] [blame] | 760 | static struct threshold_attr error_count = { |
| 761 | .attr = {.name = __stringify(error_count), .mode = 0444 }, |
| 762 | .show = show_error_count, |
| 763 | }; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 764 | |
Hidetoshi Seto | 34fa196 | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 765 | #define RW_ATTR(val) \ |
| 766 | static struct threshold_attr val = { \ |
| 767 | .attr = {.name = __stringify(val), .mode = 0644 }, \ |
| 768 | .show = show_## val, \ |
| 769 | .store = store_## val, \ |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 770 | }; |
| 771 | |
Jacob Shin | 2903ee8 | 2006-06-26 13:58:56 +0200 | [diff] [blame] | 772 | RW_ATTR(interrupt_enable); |
| 773 | RW_ATTR(threshold_limit); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 774 | |
| 775 | static struct attribute *default_attrs[] = { |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 776 | &threshold_limit.attr, |
| 777 | &error_count.attr, |
Borislav Petkov | d26ecc4 | 2012-04-16 18:20:36 +0200 | [diff] [blame] | 778 | NULL, /* possibly interrupt_enable if supported, see below */ |
| 779 | NULL, |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 780 | }; |
| 781 | |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 782 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
| 783 | #define to_attr(a) container_of(a, struct threshold_attr, attr) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 784 | |
| 785 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) |
| 786 | { |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 787 | struct threshold_block *b = to_block(kobj); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 788 | struct threshold_attr *a = to_attr(attr); |
| 789 | ssize_t ret; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 790 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 791 | ret = a->show ? a->show(b, buf) : -EIO; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 792 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 793 | return ret; |
| 794 | } |
| 795 | |
| 796 | static ssize_t store(struct kobject *kobj, struct attribute *attr, |
| 797 | const char *buf, size_t count) |
| 798 | { |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 799 | struct threshold_block *b = to_block(kobj); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 800 | struct threshold_attr *a = to_attr(attr); |
| 801 | ssize_t ret; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 802 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 803 | ret = a->store ? a->store(b, buf, count) : -EIO; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 804 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 805 | return ret; |
| 806 | } |
| 807 | |
Emese Revfy | 52cf25d | 2010-01-19 02:58:23 +0100 | [diff] [blame] | 808 | static const struct sysfs_ops threshold_ops = { |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 809 | .show = show, |
| 810 | .store = store, |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 811 | }; |
| 812 | |
| 813 | static struct kobj_type threshold_ktype = { |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 814 | .sysfs_ops = &threshold_ops, |
| 815 | .default_attrs = default_attrs, |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 816 | }; |
| 817 | |
Yazen Ghannam | 87a6d40 | 2016-09-12 09:59:35 +0200 | [diff] [blame] | 818 | static const char *get_name(unsigned int bank, struct threshold_block *b) |
| 819 | { |
| 820 | unsigned int bank_type; |
| 821 | |
| 822 | if (!mce_flags.smca) { |
| 823 | if (b && bank == 4) |
| 824 | return bank4_names(b); |
| 825 | |
| 826 | return th_names[bank]; |
| 827 | } |
| 828 | |
| 829 | if (!smca_banks[bank].type) |
| 830 | return NULL; |
| 831 | |
| 832 | bank_type = smca_banks[bank].type->bank_type; |
| 833 | |
| 834 | if (b && bank_type == SMCA_UMC) { |
| 835 | if (b->block < ARRAY_SIZE(smca_umc_block_names)) |
| 836 | return smca_umc_block_names[b->block]; |
| 837 | return NULL; |
| 838 | } |
| 839 | |
| 840 | snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, |
| 841 | "%s_%x", smca_bank_names[bank_type].name, |
| 842 | smca_banks[bank].type_instance); |
| 843 | return buf_mcatype; |
| 844 | } |
| 845 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 846 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
| 847 | unsigned int block, u32 address) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 848 | { |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 849 | struct threshold_block *b = NULL; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 850 | u32 low, high; |
| 851 | int err; |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 852 | |
Boris Ostrovsky | bafcdd3 | 2013-03-14 17:10:41 -0400 | [diff] [blame] | 853 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 854 | return 0; |
| 855 | |
Andrew Morton | a6b6a14 | 2009-03-18 10:40:25 +1030 | [diff] [blame] | 856 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
Jan Beulich | 24ce0e9 | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 857 | return 0; |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 858 | |
| 859 | if (!(high & MASK_VALID_HI)) { |
| 860 | if (block) |
| 861 | goto recurse; |
| 862 | else |
| 863 | return 0; |
| 864 | } |
| 865 | |
Jan Beulich | 24ce0e9 | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 866 | if (!(high & MASK_CNTP_HI) || |
| 867 | (high & MASK_LOCKED_HI)) |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 868 | goto recurse; |
| 869 | |
| 870 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); |
| 871 | if (!b) |
| 872 | return -ENOMEM; |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 873 | |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 874 | b->block = block; |
| 875 | b->bank = bank; |
| 876 | b->cpu = cpu; |
| 877 | b->address = address; |
| 878 | b->interrupt_enable = 0; |
Borislav Petkov | f227d43 | 2012-04-16 18:01:53 +0200 | [diff] [blame] | 879 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 880 | b->threshold_limit = THRESHOLD_MAX; |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 881 | |
Aravind Gopalakrishnan | d79f931 | 2015-02-02 11:02:41 -0600 | [diff] [blame] | 882 | if (b->interrupt_capable) { |
Borislav Petkov | d26ecc4 | 2012-04-16 18:20:36 +0200 | [diff] [blame] | 883 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
Aravind Gopalakrishnan | d79f931 | 2015-02-02 11:02:41 -0600 | [diff] [blame] | 884 | b->interrupt_enable = 1; |
| 885 | } else { |
Borislav Petkov | d26ecc4 | 2012-04-16 18:20:36 +0200 | [diff] [blame] | 886 | threshold_ktype.default_attrs[2] = NULL; |
Aravind Gopalakrishnan | d79f931 | 2015-02-02 11:02:41 -0600 | [diff] [blame] | 887 | } |
Borislav Petkov | d26ecc4 | 2012-04-16 18:20:36 +0200 | [diff] [blame] | 888 | |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 889 | INIT_LIST_HEAD(&b->miscj); |
| 890 | |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 891 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 892 | list_add(&b->miscj, |
| 893 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 894 | } else { |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 895 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 896 | } |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 897 | |
Greg Kroah-Hartman | 542eb75 | 2007-12-19 09:23:20 -0800 | [diff] [blame] | 898 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
| 899 | per_cpu(threshold_banks, cpu)[bank]->kobj, |
Yazen Ghannam | 87a6d40 | 2016-09-12 09:59:35 +0200 | [diff] [blame] | 900 | get_name(bank, b)); |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 901 | if (err) |
| 902 | goto out_free; |
| 903 | recurse: |
Yazen Ghannam | cfee4f6 | 2016-09-12 09:59:31 +0200 | [diff] [blame] | 904 | address = get_block_address(cpu, address, low, high, bank, ++block); |
Aravind Gopalakrishnan | 8dd1e17 | 2016-03-07 14:02:19 +0100 | [diff] [blame] | 905 | if (!address) |
| 906 | return 0; |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 907 | |
Aravind Gopalakrishnan | 8dd1e17 | 2016-03-07 14:02:19 +0100 | [diff] [blame] | 908 | err = allocate_threshold_blocks(cpu, bank, block, address); |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 909 | if (err) |
| 910 | goto out_free; |
| 911 | |
Greg KH | 213eca7f | 2008-01-30 13:29:58 +0100 | [diff] [blame] | 912 | if (b) |
| 913 | kobject_uevent(&b->kobj, KOBJ_ADD); |
Greg Kroah-Hartman | 542eb75 | 2007-12-19 09:23:20 -0800 | [diff] [blame] | 914 | |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 915 | return err; |
| 916 | |
| 917 | out_free: |
| 918 | if (b) { |
Greg Kroah-Hartman | 38a382a | 2007-12-20 08:13:05 -0800 | [diff] [blame] | 919 | kobject_put(&b->kobj); |
Julia Lawall | d9a5ac9 | 2011-05-13 15:52:09 +0200 | [diff] [blame] | 920 | list_del(&b->miscj); |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 921 | kfree(b); |
| 922 | } |
| 923 | return err; |
| 924 | } |
| 925 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 926 | static int __threshold_add_blocks(struct threshold_bank *b) |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 927 | { |
| 928 | struct list_head *head = &b->blocks->miscj; |
| 929 | struct threshold_block *pos = NULL; |
| 930 | struct threshold_block *tmp = NULL; |
| 931 | int err = 0; |
| 932 | |
| 933 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); |
| 934 | if (err) |
| 935 | return err; |
| 936 | |
| 937 | list_for_each_entry_safe(pos, tmp, head, miscj) { |
| 938 | |
| 939 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); |
| 940 | if (err) { |
| 941 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) |
| 942 | kobject_del(&pos->kobj); |
| 943 | |
| 944 | return err; |
| 945 | } |
| 946 | } |
| 947 | return err; |
| 948 | } |
| 949 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 950 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 951 | { |
Greg Kroah-Hartman | d6126ef | 2012-01-26 15:49:14 -0800 | [diff] [blame] | 952 | struct device *dev = per_cpu(mce_device, cpu); |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 953 | struct amd_northbridge *nb = NULL; |
Borislav Petkov | 92e26e2 | 2012-05-02 16:20:49 +0200 | [diff] [blame] | 954 | struct threshold_bank *b = NULL; |
Yazen Ghannam | 87a6d40 | 2016-09-12 09:59:35 +0200 | [diff] [blame] | 955 | const char *name = get_name(bank, NULL); |
Borislav Petkov | 92e26e2 | 2012-05-02 16:20:49 +0200 | [diff] [blame] | 956 | int err = 0; |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 957 | |
Boris Ostrovsky | c76e816 | 2013-03-14 17:10:40 -0400 | [diff] [blame] | 958 | if (is_shared_bank(bank)) { |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 959 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 960 | |
| 961 | /* threshold descriptor already initialized on this node? */ |
Daniel J Blueman | 21c5e50 | 2012-10-01 14:42:05 +0800 | [diff] [blame] | 962 | if (nb && nb->bank4) { |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 963 | /* yes, use it */ |
| 964 | b = nb->bank4; |
| 965 | err = kobject_add(b->kobj, &dev->kobj, name); |
| 966 | if (err) |
| 967 | goto out; |
| 968 | |
| 969 | per_cpu(threshold_banks, cpu)[bank] = b; |
| 970 | atomic_inc(&b->cpus); |
| 971 | |
| 972 | err = __threshold_add_blocks(b); |
| 973 | |
| 974 | goto out; |
| 975 | } |
| 976 | } |
| 977 | |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 978 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 979 | if (!b) { |
| 980 | err = -ENOMEM; |
| 981 | goto out; |
| 982 | } |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 983 | |
Greg Kroah-Hartman | e032d807 | 2012-01-16 14:40:28 -0800 | [diff] [blame] | 984 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
Borislav Petkov | 92e26e2 | 2012-05-02 16:20:49 +0200 | [diff] [blame] | 985 | if (!b->kobj) { |
| 986 | err = -EINVAL; |
Greg Kroah-Hartman | a521cf2 | 2007-12-19 09:23:20 -0800 | [diff] [blame] | 987 | goto out_free; |
Borislav Petkov | 92e26e2 | 2012-05-02 16:20:49 +0200 | [diff] [blame] | 988 | } |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 989 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 990 | per_cpu(threshold_banks, cpu)[bank] = b; |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 991 | |
Boris Ostrovsky | c76e816 | 2013-03-14 17:10:40 -0400 | [diff] [blame] | 992 | if (is_shared_bank(bank)) { |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 993 | atomic_set(&b->cpus, 1); |
| 994 | |
| 995 | /* nb is already initialized, see above */ |
Daniel J Blueman | 21c5e50 | 2012-10-01 14:42:05 +0800 | [diff] [blame] | 996 | if (nb) { |
| 997 | WARN_ON(nb->bank4); |
| 998 | nb->bank4 = b; |
| 999 | } |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 1000 | } |
| 1001 | |
Yazen Ghannam | 74ab0e7 | 2016-09-12 09:59:27 +0200 | [diff] [blame] | 1002 | err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank)); |
Borislav Petkov | 92e26e2 | 2012-05-02 16:20:49 +0200 | [diff] [blame] | 1003 | if (!err) |
| 1004 | goto out; |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 1005 | |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 1006 | out_free: |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 1007 | kfree(b); |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 1008 | |
| 1009 | out: |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1010 | return err; |
| 1011 | } |
| 1012 | |
| 1013 | /* create dir/files for all valid threshold banks */ |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 1014 | static int threshold_create_device(unsigned int cpu) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1015 | { |
Jacob Shin | 2903ee8 | 2006-06-26 13:58:56 +0200 | [diff] [blame] | 1016 | unsigned int bank; |
Boris Ostrovsky | bafcdd3 | 2013-03-14 17:10:41 -0400 | [diff] [blame] | 1017 | struct threshold_bank **bp; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1018 | int err = 0; |
| 1019 | |
Boris Ostrovsky | bafcdd3 | 2013-03-14 17:10:41 -0400 | [diff] [blame] | 1020 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
| 1021 | GFP_KERNEL); |
| 1022 | if (!bp) |
| 1023 | return -ENOMEM; |
| 1024 | |
| 1025 | per_cpu(threshold_banks, cpu) = bp; |
| 1026 | |
| 1027 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
Yinghai Lu | 5a96f4a | 2008-01-30 13:33:40 +0100 | [diff] [blame] | 1028 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1029 | continue; |
| 1030 | err = threshold_create_bank(cpu, bank); |
| 1031 | if (err) |
Robert Richter | 0a17941 | 2010-10-25 16:03:38 +0200 | [diff] [blame] | 1032 | return err; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1033 | } |
Robert Richter | 0a17941 | 2010-10-25 16:03:38 +0200 | [diff] [blame] | 1034 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1035 | return err; |
| 1036 | } |
| 1037 | |
Chandra Seetharaman | be6b5a3 | 2006-07-30 03:03:37 -0700 | [diff] [blame] | 1038 | static void deallocate_threshold_block(unsigned int cpu, |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 1039 | unsigned int bank) |
| 1040 | { |
| 1041 | struct threshold_block *pos = NULL; |
| 1042 | struct threshold_block *tmp = NULL; |
| 1043 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; |
| 1044 | |
| 1045 | if (!head) |
| 1046 | return; |
| 1047 | |
| 1048 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { |
Greg Kroah-Hartman | 38a382a | 2007-12-20 08:13:05 -0800 | [diff] [blame] | 1049 | kobject_put(&pos->kobj); |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 1050 | list_del(&pos->miscj); |
| 1051 | kfree(pos); |
| 1052 | } |
| 1053 | |
| 1054 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); |
| 1055 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; |
| 1056 | } |
| 1057 | |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 1058 | static void __threshold_remove_blocks(struct threshold_bank *b) |
| 1059 | { |
| 1060 | struct threshold_block *pos = NULL; |
| 1061 | struct threshold_block *tmp = NULL; |
| 1062 | |
| 1063 | kobject_del(b->kobj); |
| 1064 | |
| 1065 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) |
| 1066 | kobject_del(&pos->kobj); |
| 1067 | } |
| 1068 | |
Chandra Seetharaman | be6b5a3 | 2006-07-30 03:03:37 -0700 | [diff] [blame] | 1069 | static void threshold_remove_bank(unsigned int cpu, int bank) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1070 | { |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 1071 | struct amd_northbridge *nb; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1072 | struct threshold_bank *b; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1073 | |
| 1074 | b = per_cpu(threshold_banks, cpu)[bank]; |
| 1075 | if (!b) |
| 1076 | return; |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 1077 | |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 1078 | if (!b->blocks) |
| 1079 | goto free_out; |
| 1080 | |
Boris Ostrovsky | c76e816 | 2013-03-14 17:10:40 -0400 | [diff] [blame] | 1081 | if (is_shared_bank(bank)) { |
Borislav Petkov | 019f34f | 2012-05-02 17:16:59 +0200 | [diff] [blame] | 1082 | if (!atomic_dec_and_test(&b->cpus)) { |
| 1083 | __threshold_remove_blocks(b); |
| 1084 | per_cpu(threshold_banks, cpu)[bank] = NULL; |
| 1085 | return; |
| 1086 | } else { |
| 1087 | /* |
| 1088 | * the last CPU on this node using the shared bank is |
| 1089 | * going away, remove that bank now. |
| 1090 | */ |
| 1091 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
| 1092 | nb->bank4 = NULL; |
| 1093 | } |
| 1094 | } |
| 1095 | |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 1096 | deallocate_threshold_block(cpu, bank); |
| 1097 | |
| 1098 | free_out: |
Rafael J. Wysocki | 8735728 | 2008-08-22 22:23:09 +0200 | [diff] [blame] | 1099 | kobject_del(b->kobj); |
Greg Kroah-Hartman | 38a382a | 2007-12-20 08:13:05 -0800 | [diff] [blame] | 1100 | kobject_put(b->kobj); |
Jacob Shin | 9526866 | 2006-06-26 13:58:53 +0200 | [diff] [blame] | 1101 | kfree(b); |
| 1102 | per_cpu(threshold_banks, cpu)[bank] = NULL; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1103 | } |
| 1104 | |
Chandra Seetharaman | be6b5a3 | 2006-07-30 03:03:37 -0700 | [diff] [blame] | 1105 | static void threshold_remove_device(unsigned int cpu) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1106 | { |
Jacob Shin | 2903ee8 | 2006-06-26 13:58:56 +0200 | [diff] [blame] | 1107 | unsigned int bank; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1108 | |
Boris Ostrovsky | bafcdd3 | 2013-03-14 17:10:41 -0400 | [diff] [blame] | 1109 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
Yinghai Lu | 5a96f4a | 2008-01-30 13:33:40 +0100 | [diff] [blame] | 1110 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1111 | continue; |
| 1112 | threshold_remove_bank(cpu, bank); |
| 1113 | } |
Boris Ostrovsky | bafcdd3 | 2013-03-14 17:10:41 -0400 | [diff] [blame] | 1114 | kfree(per_cpu(threshold_banks, cpu)); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1115 | } |
| 1116 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1117 | /* get notified when a cpu comes on/off */ |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 1118 | static void |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 1119 | amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu) |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1120 | { |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1121 | switch (action) { |
| 1122 | case CPU_ONLINE: |
Rafael J. Wysocki | 8bb7844 | 2007-05-09 02:35:10 -0700 | [diff] [blame] | 1123 | case CPU_ONLINE_FROZEN: |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1124 | threshold_create_device(cpu); |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1125 | break; |
| 1126 | case CPU_DEAD: |
Rafael J. Wysocki | 8bb7844 | 2007-05-09 02:35:10 -0700 | [diff] [blame] | 1127 | case CPU_DEAD_FROZEN: |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1128 | threshold_remove_device(cpu); |
| 1129 | break; |
| 1130 | default: |
| 1131 | break; |
| 1132 | } |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1133 | } |
| 1134 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1135 | static __init int threshold_init_device(void) |
| 1136 | { |
Jacob Shin | 2903ee8 | 2006-06-26 13:58:56 +0200 | [diff] [blame] | 1137 | unsigned lcpu = 0; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1138 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1139 | /* to hit CPUs online before the notifier is up */ |
| 1140 | for_each_online_cpu(lcpu) { |
Jacob Shin | fff2e89 | 2006-06-26 13:58:50 +0200 | [diff] [blame] | 1141 | int err = threshold_create_device(lcpu); |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 1142 | |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1143 | if (err) |
Jacob Shin | fff2e89 | 2006-06-26 13:58:50 +0200 | [diff] [blame] | 1144 | return err; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1145 | } |
Rafael J. Wysocki | 8735728 | 2008-08-22 22:23:09 +0200 | [diff] [blame] | 1146 | threshold_cpu_callback = amd_64_threshold_cpu_callback; |
Ingo Molnar | 1cb2a8e | 2009-04-08 12:31:18 +0200 | [diff] [blame] | 1147 | |
Jacob Shin | fff2e89 | 2006-06-26 13:58:50 +0200 | [diff] [blame] | 1148 | return 0; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1149 | } |
Liu, Jinsong | a8fccdb | 2012-06-07 19:58:50 +0800 | [diff] [blame] | 1150 | /* |
| 1151 | * there are 3 funcs which need to be _initcalled in a logic sequence: |
| 1152 | * 1. xen_late_init_mcelog |
| 1153 | * 2. mcheck_init_device |
| 1154 | * 3. threshold_init_device |
| 1155 | * |
| 1156 | * xen_late_init_mcelog must register xen_mce_chrdev_device before |
| 1157 | * native mce_chrdev_device registration if running under xen platform; |
| 1158 | * |
| 1159 | * mcheck_init_device should be inited before threshold_init_device to |
| 1160 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. |
| 1161 | * |
| 1162 | * so we use following _initcalls |
| 1163 | * 1. device_initcall(xen_late_init_mcelog); |
| 1164 | * 2. device_initcall_sync(mcheck_init_device); |
| 1165 | * 3. late_initcall(threshold_init_device); |
| 1166 | * |
| 1167 | * when running under xen, the initcall order is 1,2,3; |
| 1168 | * on baremetal, we skip 1 and we do only 2 and 3. |
| 1169 | */ |
| 1170 | late_initcall(threshold_init_device); |