Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 1 | /* |
Vivien Didelot | 0d3cd4b | 2016-06-21 12:28:19 -0400 | [diff] [blame] | 2 | * Marvell 88e6xxx common definitions |
| 3 | * |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 4 | * Copyright (c) 2008 Marvell Semiconductor |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | #ifndef __MV88E6XXX_H |
| 13 | #define __MV88E6XXX_H |
| 14 | |
Vivien Didelot | 194fea7 | 2015-08-10 09:09:47 -0400 | [diff] [blame] | 15 | #include <linux/if_vlan.h> |
Andrew Lunn | 52638f7 | 2016-05-10 23:27:22 +0200 | [diff] [blame] | 16 | #include <linux/gpio/consumer.h> |
Vivien Didelot | 194fea7 | 2015-08-10 09:09:47 -0400 | [diff] [blame] | 17 | |
Andrew Lunn | 80c4627 | 2015-06-20 18:42:30 +0200 | [diff] [blame] | 18 | #ifndef UINT64_MAX |
| 19 | #define UINT64_MAX (u64)(~((u64)0)) |
| 20 | #endif |
| 21 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 22 | #define SMI_CMD 0x00 |
| 23 | #define SMI_CMD_BUSY BIT(15) |
| 24 | #define SMI_CMD_CLAUSE_22 BIT(12) |
| 25 | #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) |
| 26 | #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) |
| 27 | #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) |
| 28 | #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) |
| 29 | #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) |
| 30 | #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) |
| 31 | #define SMI_DATA 0x01 |
Guenter Roeck | b2eb066 | 2015-04-02 04:06:30 +0200 | [diff] [blame] | 32 | |
Vivien Didelot | 09cb7df | 2016-08-15 17:19:01 -0400 | [diff] [blame] | 33 | /* PHY Registers */ |
| 34 | #define PHY_PAGE 0x16 |
| 35 | #define PHY_PAGE_COPPER 0x00 |
| 36 | |
| 37 | #define ADDR_SERDES 0x0f |
| 38 | #define SERDES_PAGE_FIBER 0x01 |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 39 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 40 | #define PORT_STATUS 0x00 |
| 41 | #define PORT_STATUS_PAUSE_EN BIT(15) |
| 42 | #define PORT_STATUS_MY_PAUSE BIT(14) |
| 43 | #define PORT_STATUS_HD_FLOW BIT(13) |
| 44 | #define PORT_STATUS_PHY_DETECT BIT(12) |
| 45 | #define PORT_STATUS_LINK BIT(11) |
| 46 | #define PORT_STATUS_DUPLEX BIT(10) |
| 47 | #define PORT_STATUS_SPEED_MASK 0x0300 |
| 48 | #define PORT_STATUS_SPEED_10 0x0000 |
| 49 | #define PORT_STATUS_SPEED_100 0x0100 |
| 50 | #define PORT_STATUS_SPEED_1000 0x0200 |
| 51 | #define PORT_STATUS_EEE BIT(6) /* 6352 */ |
| 52 | #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */ |
| 53 | #define PORT_STATUS_MGMII BIT(6) /* 6185 */ |
| 54 | #define PORT_STATUS_TX_PAUSED BIT(5) |
| 55 | #define PORT_STATUS_FLOW_CTRL BIT(4) |
Patrick Uiterwijk | 13a7ebb | 2016-03-30 01:39:41 +0000 | [diff] [blame] | 56 | #define PORT_STATUS_CMODE_MASK 0x0f |
| 57 | #define PORT_STATUS_CMODE_100BASE_X 0x8 |
| 58 | #define PORT_STATUS_CMODE_1000BASE_X 0x9 |
| 59 | #define PORT_STATUS_CMODE_SGMII 0xa |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 60 | #define PORT_PCS_CTRL 0x01 |
Andrew Lunn | e7e72ac | 2015-08-31 15:56:51 +0200 | [diff] [blame] | 61 | #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15) |
| 62 | #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 63 | #define PORT_PCS_CTRL_FC BIT(7) |
| 64 | #define PORT_PCS_CTRL_FORCE_FC BIT(6) |
| 65 | #define PORT_PCS_CTRL_LINK_UP BIT(5) |
| 66 | #define PORT_PCS_CTRL_FORCE_LINK BIT(4) |
| 67 | #define PORT_PCS_CTRL_DUPLEX_FULL BIT(3) |
| 68 | #define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2) |
| 69 | #define PORT_PCS_CTRL_10 0x00 |
| 70 | #define PORT_PCS_CTRL_100 0x01 |
| 71 | #define PORT_PCS_CTRL_1000 0x02 |
| 72 | #define PORT_PCS_CTRL_UNFORCED 0x03 |
| 73 | #define PORT_PAUSE_CTRL 0x02 |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 74 | #define PORT_SWITCH_ID 0x03 |
Vivien Didelot | f6271e6 | 2016-04-17 13:23:59 -0400 | [diff] [blame] | 75 | #define PORT_SWITCH_ID_PROD_NUM_6085 0x04a |
| 76 | #define PORT_SWITCH_ID_PROD_NUM_6095 0x095 |
| 77 | #define PORT_SWITCH_ID_PROD_NUM_6131 0x106 |
| 78 | #define PORT_SWITCH_ID_PROD_NUM_6320 0x115 |
| 79 | #define PORT_SWITCH_ID_PROD_NUM_6123 0x121 |
| 80 | #define PORT_SWITCH_ID_PROD_NUM_6161 0x161 |
| 81 | #define PORT_SWITCH_ID_PROD_NUM_6165 0x165 |
| 82 | #define PORT_SWITCH_ID_PROD_NUM_6171 0x171 |
| 83 | #define PORT_SWITCH_ID_PROD_NUM_6172 0x172 |
| 84 | #define PORT_SWITCH_ID_PROD_NUM_6175 0x175 |
| 85 | #define PORT_SWITCH_ID_PROD_NUM_6176 0x176 |
| 86 | #define PORT_SWITCH_ID_PROD_NUM_6185 0x1a7 |
| 87 | #define PORT_SWITCH_ID_PROD_NUM_6240 0x240 |
| 88 | #define PORT_SWITCH_ID_PROD_NUM_6321 0x310 |
| 89 | #define PORT_SWITCH_ID_PROD_NUM_6352 0x352 |
| 90 | #define PORT_SWITCH_ID_PROD_NUM_6350 0x371 |
| 91 | #define PORT_SWITCH_ID_PROD_NUM_6351 0x375 |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 92 | #define PORT_CONTROL 0x04 |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 93 | #define PORT_CONTROL_USE_CORE_TAG BIT(15) |
| 94 | #define PORT_CONTROL_DROP_ON_LOCK BIT(14) |
| 95 | #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12) |
| 96 | #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12) |
| 97 | #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12) |
| 98 | #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12) |
| 99 | #define PORT_CONTROL_HEADER BIT(11) |
| 100 | #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10) |
| 101 | #define PORT_CONTROL_DOUBLE_TAG BIT(9) |
| 102 | #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8) |
| 103 | #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8) |
| 104 | #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8) |
| 105 | #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8) |
| 106 | #define PORT_CONTROL_DSA_TAG BIT(8) |
| 107 | #define PORT_CONTROL_VLAN_TUNNEL BIT(7) |
| 108 | #define PORT_CONTROL_TAG_IF_BOTH BIT(6) |
| 109 | #define PORT_CONTROL_USE_IP BIT(5) |
| 110 | #define PORT_CONTROL_USE_TAG BIT(4) |
| 111 | #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3) |
| 112 | #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 113 | #define PORT_CONTROL_STATE_MASK 0x03 |
| 114 | #define PORT_CONTROL_STATE_DISABLED 0x00 |
| 115 | #define PORT_CONTROL_STATE_BLOCKING 0x01 |
| 116 | #define PORT_CONTROL_STATE_LEARNING 0x02 |
| 117 | #define PORT_CONTROL_STATE_FORWARDING 0x03 |
| 118 | #define PORT_CONTROL_1 0x05 |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 119 | #define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 120 | #define PORT_BASE_VLAN 0x06 |
Vivien Didelot | 2db9ce1 | 2016-02-26 13:16:04 -0500 | [diff] [blame] | 121 | #define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 122 | #define PORT_DEFAULT_VLAN 0x07 |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 123 | #define PORT_DEFAULT_VLAN_MASK 0xfff |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 124 | #define PORT_CONTROL_2 0x08 |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 125 | #define PORT_CONTROL_2_IGNORE_FCS BIT(15) |
| 126 | #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14) |
| 127 | #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13) |
| 128 | #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12) |
| 129 | #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12) |
| 130 | #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12) |
| 131 | #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12) |
Vivien Didelot | 8efdda4 | 2015-08-13 12:52:23 -0400 | [diff] [blame] | 132 | #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10) |
| 133 | #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10) |
| 134 | #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10) |
| 135 | #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10) |
| 136 | #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 137 | #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9) |
| 138 | #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8) |
| 139 | #define PORT_CONTROL_2_MAP_DA BIT(7) |
| 140 | #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6) |
| 141 | #define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6) |
| 142 | #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5) |
| 143 | #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 144 | #define PORT_RATE_CONTROL 0x09 |
| 145 | #define PORT_RATE_CONTROL_2 0x0a |
| 146 | #define PORT_ASSOC_VECTOR 0x0b |
Andrew Lunn | 4c7ea3c | 2015-11-03 10:52:36 -0500 | [diff] [blame] | 147 | #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15) |
| 148 | #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14) |
| 149 | #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13) |
| 150 | #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12) |
| 151 | #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11) |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 152 | #define PORT_ATU_CONTROL 0x0c |
| 153 | #define PORT_PRI_OVERRIDE 0x0d |
| 154 | #define PORT_ETH_TYPE 0x0f |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 155 | #define PORT_IN_DISCARD_LO 0x10 |
| 156 | #define PORT_IN_DISCARD_HI 0x11 |
| 157 | #define PORT_IN_FILTERED 0x12 |
| 158 | #define PORT_OUT_FILTERED 0x13 |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 159 | #define PORT_TAG_REGMAP_0123 0x18 |
| 160 | #define PORT_TAG_REGMAP_4567 0x19 |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 161 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 162 | #define GLOBAL_STATUS 0x00 |
| 163 | #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */ |
| 164 | /* Two bits for 6165, 6185 etc */ |
| 165 | #define GLOBAL_STATUS_PPU_MASK (0x3 << 14) |
| 166 | #define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14) |
| 167 | #define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14) |
| 168 | #define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14) |
| 169 | #define GLOBAL_STATUS_PPU_POLLING (0x3 << 14) |
| 170 | #define GLOBAL_MAC_01 0x01 |
| 171 | #define GLOBAL_MAC_23 0x02 |
| 172 | #define GLOBAL_MAC_45 0x03 |
Vivien Didelot | 6dc10bb | 2016-09-29 12:21:55 -0400 | [diff] [blame] | 173 | #define GLOBAL_ATU_FID 0x01 |
| 174 | #define GLOBAL_VTU_FID 0x02 |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 175 | #define GLOBAL_VTU_FID_MASK 0xfff |
| 176 | #define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */ |
| 177 | #define GLOBAL_VTU_SID_MASK 0x3f |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 178 | #define GLOBAL_CONTROL 0x04 |
| 179 | #define GLOBAL_CONTROL_SW_RESET BIT(15) |
| 180 | #define GLOBAL_CONTROL_PPU_ENABLE BIT(14) |
| 181 | #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */ |
| 182 | #define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */ |
| 183 | #define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */ |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 184 | #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */ |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 185 | #define GLOBAL_CONTROL_DEVICE_EN BIT(7) |
| 186 | #define GLOBAL_CONTROL_STATS_DONE_EN BIT(6) |
| 187 | #define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5) |
| 188 | #define GLOBAL_CONTROL_VTU_DONE_EN BIT(4) |
| 189 | #define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3) |
| 190 | #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) |
| 191 | #define GLOBAL_CONTROL_TCAM_EN BIT(1) |
| 192 | #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) |
| 193 | #define GLOBAL_VTU_OP 0x05 |
Vivien Didelot | 6b17e86 | 2015-08-13 12:52:18 -0400 | [diff] [blame] | 194 | #define GLOBAL_VTU_OP_BUSY BIT(15) |
| 195 | #define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY) |
Vivien Didelot | 7dad08d | 2015-08-13 12:52:21 -0400 | [diff] [blame] | 196 | #define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY) |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 197 | #define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY) |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 198 | #define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY) |
| 199 | #define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 200 | #define GLOBAL_VTU_VID 0x06 |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 201 | #define GLOBAL_VTU_VID_MASK 0xfff |
| 202 | #define GLOBAL_VTU_VID_VALID BIT(12) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 203 | #define GLOBAL_VTU_DATA_0_3 0x07 |
| 204 | #define GLOBAL_VTU_DATA_4_7 0x08 |
| 205 | #define GLOBAL_VTU_DATA_8_11 0x09 |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 206 | #define GLOBAL_VTU_STU_DATA_MASK 0x03 |
| 207 | #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00 |
| 208 | #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01 |
| 209 | #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02 |
| 210 | #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03 |
Vivien Didelot | 0d3b33e | 2015-08-13 12:52:22 -0400 | [diff] [blame] | 211 | #define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00 |
| 212 | #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01 |
| 213 | #define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02 |
| 214 | #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03 |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 215 | #define GLOBAL_ATU_CONTROL 0x0a |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 216 | #define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 217 | #define GLOBAL_ATU_OP 0x0b |
| 218 | #define GLOBAL_ATU_OP_BUSY BIT(15) |
| 219 | #define GLOBAL_ATU_OP_NOP (0 << 12) |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 220 | #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY) |
| 221 | #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 222 | #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY) |
| 223 | #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY) |
Vivien Didelot | 7fb5e75 | 2015-09-04 14:34:12 -0400 | [diff] [blame] | 224 | #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY) |
| 225 | #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 226 | #define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY) |
| 227 | #define GLOBAL_ATU_DATA 0x0c |
Andrew Lunn | 8a0a265 | 2015-06-20 18:42:29 +0200 | [diff] [blame] | 228 | #define GLOBAL_ATU_DATA_TRUNK BIT(15) |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 229 | #define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0 |
| 230 | #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4 |
Andrew Lunn | 8a0a265 | 2015-06-20 18:42:29 +0200 | [diff] [blame] | 231 | #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 |
| 232 | #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4 |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 233 | #define GLOBAL_ATU_DATA_STATE_MASK 0x0f |
| 234 | #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00 |
| 235 | #define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d |
| 236 | #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e |
| 237 | #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f |
| 238 | #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05 |
| 239 | #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07 |
| 240 | #define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e |
| 241 | #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f |
| 242 | #define GLOBAL_ATU_MAC_01 0x0d |
| 243 | #define GLOBAL_ATU_MAC_23 0x0e |
| 244 | #define GLOBAL_ATU_MAC_45 0x0f |
| 245 | #define GLOBAL_IP_PRI_0 0x10 |
| 246 | #define GLOBAL_IP_PRI_1 0x11 |
| 247 | #define GLOBAL_IP_PRI_2 0x12 |
| 248 | #define GLOBAL_IP_PRI_3 0x13 |
| 249 | #define GLOBAL_IP_PRI_4 0x14 |
| 250 | #define GLOBAL_IP_PRI_5 0x15 |
| 251 | #define GLOBAL_IP_PRI_6 0x16 |
| 252 | #define GLOBAL_IP_PRI_7 0x17 |
| 253 | #define GLOBAL_IEEE_PRI 0x18 |
| 254 | #define GLOBAL_CORE_TAG_TYPE 0x19 |
| 255 | #define GLOBAL_MONITOR_CONTROL 0x1a |
Andrew Lunn | 15966a2 | 2015-05-06 01:09:49 +0200 | [diff] [blame] | 256 | #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12 |
| 257 | #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8 |
| 258 | #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4 |
| 259 | #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0 |
| 260 | #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 261 | #define GLOBAL_CONTROL_2 0x1c |
Andrew Lunn | 15966a2 | 2015-05-06 01:09:49 +0200 | [diff] [blame] | 262 | #define GLOBAL_CONTROL_2_NO_CASCADE 0xe000 |
| 263 | #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000 |
| 264 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 265 | #define GLOBAL_STATS_OP 0x1d |
| 266 | #define GLOBAL_STATS_OP_BUSY BIT(15) |
| 267 | #define GLOBAL_STATS_OP_NOP (0 << 12) |
| 268 | #define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY) |
| 269 | #define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY) |
| 270 | #define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY) |
| 271 | #define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY) |
| 272 | #define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY) |
| 273 | #define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY) |
| 274 | #define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY) |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 275 | #define GLOBAL_STATS_OP_BANK_1 BIT(9) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 276 | #define GLOBAL_STATS_COUNTER_32 0x1e |
| 277 | #define GLOBAL_STATS_COUNTER_01 0x1f |
| 278 | |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 279 | #define GLOBAL2_INT_SOURCE 0x00 |
| 280 | #define GLOBAL2_INT_MASK 0x01 |
| 281 | #define GLOBAL2_MGMT_EN_2X 0x02 |
| 282 | #define GLOBAL2_MGMT_EN_0X 0x03 |
| 283 | #define GLOBAL2_FLOW_CONTROL 0x04 |
| 284 | #define GLOBAL2_SWITCH_MGMT 0x05 |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 285 | #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15) |
| 286 | #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14) |
| 287 | #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13) |
| 288 | #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7) |
| 289 | #define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 290 | #define GLOBAL2_DEVICE_MAPPING 0x06 |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 291 | #define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15) |
| 292 | #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8 |
Andrew Lunn | d35bd87 | 2015-06-20 18:42:32 +0200 | [diff] [blame] | 293 | #define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 294 | #define GLOBAL2_TRUNK_MASK 0x07 |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 295 | #define GLOBAL2_TRUNK_MASK_UPDATE BIT(15) |
| 296 | #define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12 |
Vivien Didelot | 5154041 | 2016-07-18 20:45:32 -0400 | [diff] [blame] | 297 | #define GLOBAL2_TRUNK_MASK_HASK BIT(11) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 298 | #define GLOBAL2_TRUNK_MAPPING 0x08 |
Andrew Lunn | 54d792f | 2015-05-06 01:09:47 +0200 | [diff] [blame] | 299 | #define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15) |
| 300 | #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11 |
Vivien Didelot | 8ec61c7 | 2016-07-18 20:45:37 -0400 | [diff] [blame] | 301 | #define GLOBAL2_IRL_CMD 0x09 |
| 302 | #define GLOBAL2_IRL_CMD_BUSY BIT(15) |
| 303 | #define GLOBAL2_IRL_CMD_OP_INIT_ALL ((0x001 << 12) | GLOBAL2_IRL_CMD_BUSY) |
| 304 | #define GLOBAL2_IRL_CMD_OP_INIT_SEL ((0x010 << 12) | GLOBAL2_IRL_CMD_BUSY) |
| 305 | #define GLOBAL2_IRL_CMD_OP_WRITE_SEL ((0x011 << 12) | GLOBAL2_IRL_CMD_BUSY) |
| 306 | #define GLOBAL2_IRL_CMD_OP_READ_SEL ((0x100 << 12) | GLOBAL2_IRL_CMD_BUSY) |
| 307 | #define GLOBAL2_IRL_DATA 0x0a |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 308 | #define GLOBAL2_PVT_ADDR 0x0b |
Vivien Didelot | 63ed880 | 2016-07-18 20:45:35 -0400 | [diff] [blame] | 309 | #define GLOBAL2_PVT_ADDR_BUSY BIT(15) |
| 310 | #define GLOBAL2_PVT_ADDR_OP_INIT_ONES ((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY) |
| 311 | #define GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN ((0x03 << 12) | GLOBAL2_PVT_ADDR_BUSY) |
| 312 | #define GLOBAL2_PVT_ADDR_OP_READ ((0x04 << 12) | GLOBAL2_PVT_ADDR_BUSY) |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 313 | #define GLOBAL2_PVT_DATA 0x0c |
| 314 | #define GLOBAL2_SWITCH_MAC 0x0d |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 315 | #define GLOBAL2_ATU_STATS 0x0e |
| 316 | #define GLOBAL2_PRIO_OVERRIDE 0x0f |
Andrew Lunn | 15966a2 | 2015-05-06 01:09:49 +0200 | [diff] [blame] | 317 | #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7) |
| 318 | #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4 |
| 319 | #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3) |
| 320 | #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0 |
Vivien Didelot | 855b193 | 2016-07-20 18:18:35 -0400 | [diff] [blame] | 321 | #define GLOBAL2_EEPROM_CMD 0x14 |
| 322 | #define GLOBAL2_EEPROM_CMD_BUSY BIT(15) |
| 323 | #define GLOBAL2_EEPROM_CMD_OP_WRITE ((0x3 << 12) | GLOBAL2_EEPROM_CMD_BUSY) |
| 324 | #define GLOBAL2_EEPROM_CMD_OP_READ ((0x4 << 12) | GLOBAL2_EEPROM_CMD_BUSY) |
| 325 | #define GLOBAL2_EEPROM_CMD_OP_LOAD ((0x6 << 12) | GLOBAL2_EEPROM_CMD_BUSY) |
| 326 | #define GLOBAL2_EEPROM_CMD_RUNNING BIT(11) |
| 327 | #define GLOBAL2_EEPROM_CMD_WRITE_EN BIT(10) |
| 328 | #define GLOBAL2_EEPROM_CMD_ADDR_MASK 0xff |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 329 | #define GLOBAL2_EEPROM_DATA 0x15 |
| 330 | #define GLOBAL2_PTP_AVB_OP 0x16 |
| 331 | #define GLOBAL2_PTP_AVB_DATA 0x17 |
Vivien Didelot | 57c67cf | 2016-08-15 17:18:59 -0400 | [diff] [blame] | 332 | #define GLOBAL2_SMI_PHY_CMD 0x18 |
| 333 | #define GLOBAL2_SMI_PHY_CMD_BUSY BIT(15) |
| 334 | #define GLOBAL2_SMI_PHY_CMD_MODE_22 BIT(12) |
| 335 | #define GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA ((0x1 << 10) | \ |
| 336 | GLOBAL2_SMI_PHY_CMD_MODE_22 | \ |
| 337 | GLOBAL2_SMI_PHY_CMD_BUSY) |
| 338 | #define GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA ((0x2 << 10) | \ |
| 339 | GLOBAL2_SMI_PHY_CMD_MODE_22 | \ |
| 340 | GLOBAL2_SMI_PHY_CMD_BUSY) |
| 341 | #define GLOBAL2_SMI_PHY_DATA 0x19 |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 342 | #define GLOBAL2_SCRATCH_MISC 0x1a |
Andrew Lunn | 56d95e2 | 2015-06-20 18:42:33 +0200 | [diff] [blame] | 343 | #define GLOBAL2_SCRATCH_BUSY BIT(15) |
| 344 | #define GLOBAL2_SCRATCH_REGISTER_SHIFT 8 |
| 345 | #define GLOBAL2_SCRATCH_VALUE_MASK 0xff |
Andrew Lunn | cca8b13 | 2015-04-02 04:06:39 +0200 | [diff] [blame] | 346 | #define GLOBAL2_WDOG_CONTROL 0x1b |
| 347 | #define GLOBAL2_QOS_WEIGHT 0x1c |
| 348 | #define GLOBAL2_MISC 0x1d |
Guenter Roeck | defb05b | 2015-03-26 18:36:38 -0700 | [diff] [blame] | 349 | |
Vivien Didelot | 3285f9e | 2016-02-26 13:16:03 -0500 | [diff] [blame] | 350 | #define MV88E6XXX_N_FID 4096 |
| 351 | |
Vivien Didelot | f81ec90 | 2016-05-09 13:22:58 -0400 | [diff] [blame] | 352 | /* List of supported models */ |
| 353 | enum mv88e6xxx_model { |
| 354 | MV88E6085, |
| 355 | MV88E6095, |
| 356 | MV88E6123, |
| 357 | MV88E6131, |
| 358 | MV88E6161, |
| 359 | MV88E6165, |
| 360 | MV88E6171, |
| 361 | MV88E6172, |
| 362 | MV88E6175, |
| 363 | MV88E6176, |
| 364 | MV88E6185, |
| 365 | MV88E6240, |
| 366 | MV88E6320, |
| 367 | MV88E6321, |
| 368 | MV88E6350, |
| 369 | MV88E6351, |
| 370 | MV88E6352, |
| 371 | }; |
| 372 | |
Vivien Didelot | 2235647 | 2016-04-17 13:24:00 -0400 | [diff] [blame] | 373 | enum mv88e6xxx_family { |
| 374 | MV88E6XXX_FAMILY_NONE, |
| 375 | MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ |
| 376 | MV88E6XXX_FAMILY_6095, /* 6092 6095 */ |
| 377 | MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ |
| 378 | MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ |
| 379 | MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ |
| 380 | MV88E6XXX_FAMILY_6320, /* 6320 6321 */ |
| 381 | MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ |
| 382 | MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ |
| 383 | }; |
| 384 | |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 385 | enum mv88e6xxx_cap { |
Andrew Lunn | 2bbb33b | 2016-08-22 16:01:02 +0200 | [diff] [blame] | 386 | /* Two different tag protocols can be used by the driver. All |
| 387 | * switches support DSA, but only later generations support |
| 388 | * EDSA. |
| 389 | */ |
| 390 | MV88E6XXX_CAP_EDSA, |
| 391 | |
Vivien Didelot | aadbdb8 | 2016-05-09 13:22:44 -0400 | [diff] [blame] | 392 | /* Energy Efficient Ethernet. |
| 393 | */ |
| 394 | MV88E6XXX_CAP_EEE, |
| 395 | |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 396 | /* Multi-chip Addressing Mode. |
| 397 | * Some chips respond to only 2 registers of its own SMI device address |
| 398 | * when it is non-zero, and use indirect access to internal registers. |
| 399 | */ |
| 400 | MV88E6XXX_CAP_SMI_CMD, /* (0x00) SMI Command */ |
| 401 | MV88E6XXX_CAP_SMI_DATA, /* (0x01) SMI Data */ |
| 402 | |
Vivien Didelot | 09cb7df | 2016-08-15 17:19:01 -0400 | [diff] [blame] | 403 | /* PHY Registers. |
| 404 | */ |
| 405 | MV88E6XXX_CAP_PHY_PAGE, /* (0x16) Page Register */ |
| 406 | |
| 407 | /* Fiber/SERDES Registers (SMI address F). |
| 408 | */ |
| 409 | MV88E6XXX_CAP_SERDES, |
| 410 | |
Vivien Didelot | 6dc10bb | 2016-09-29 12:21:55 -0400 | [diff] [blame] | 411 | /* Switch Global (1) Registers. |
| 412 | */ |
| 413 | MV88E6XXX_CAP_G1_ATU_FID, /* (0x01) ATU FID Register */ |
| 414 | MV88E6XXX_CAP_G1_VTU_FID, /* (0x02) VTU FID Register */ |
| 415 | |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 416 | /* Switch Global 2 Registers. |
| 417 | * The device contains a second set of global 16-bit registers. |
| 418 | */ |
| 419 | MV88E6XXX_CAP_GLOBAL2, |
Vivien Didelot | 47395ed | 2016-07-18 20:45:33 -0400 | [diff] [blame] | 420 | MV88E6XXX_CAP_G2_MGMT_EN_2X, /* (0x02) MGMT Enable Register 2x */ |
| 421 | MV88E6XXX_CAP_G2_MGMT_EN_0X, /* (0x03) MGMT Enable Register 0x */ |
Vivien Didelot | 8ec61c7 | 2016-07-18 20:45:37 -0400 | [diff] [blame] | 422 | MV88E6XXX_CAP_G2_IRL_CMD, /* (0x09) Ingress Rate Command */ |
| 423 | MV88E6XXX_CAP_G2_IRL_DATA, /* (0x0a) Ingress Rate Data */ |
Vivien Didelot | 63ed880 | 2016-07-18 20:45:35 -0400 | [diff] [blame] | 424 | MV88E6XXX_CAP_G2_PVT_ADDR, /* (0x0b) Cross Chip Port VLAN Addr */ |
| 425 | MV88E6XXX_CAP_G2_PVT_DATA, /* (0x0c) Cross Chip Port VLAN Data */ |
Vivien Didelot | 9bda889 | 2016-07-18 20:45:36 -0400 | [diff] [blame] | 426 | MV88E6XXX_CAP_G2_POT, /* (0x0f) Priority Override Table */ |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 427 | |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 428 | /* PHY Polling Unit. |
| 429 | * See GLOBAL_CONTROL_PPU_ENABLE and GLOBAL_STATUS_PPU_POLLING. |
| 430 | */ |
| 431 | MV88E6XXX_CAP_PPU, |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 432 | MV88E6XXX_CAP_PPU_ACTIVE, |
Vivien Didelot | 6d5834a | 2016-05-09 13:22:40 -0400 | [diff] [blame] | 433 | |
Vivien Didelot | cb9b902 | 2016-05-10 15:44:29 -0400 | [diff] [blame] | 434 | /* Per VLAN Spanning Tree Unit (STU). |
| 435 | * The Port State database, if present, is accessed through VTU |
| 436 | * operations and dedicated SID registers. See GLOBAL_VTU_SID. |
| 437 | */ |
| 438 | MV88E6XXX_CAP_STU, |
| 439 | |
Vivien Didelot | 6594f61 | 2016-05-09 13:22:42 -0400 | [diff] [blame] | 440 | /* Internal temperature sensor. |
| 441 | * Available from any enabled port's PHY register 26, page 6. |
| 442 | */ |
| 443 | MV88E6XXX_CAP_TEMP, |
| 444 | MV88E6XXX_CAP_TEMP_LIMIT, |
Vivien Didelot | 936f234 | 2016-05-09 13:22:46 -0400 | [diff] [blame] | 445 | |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 446 | /* VLAN Table Unit. |
| 447 | * The VTU is used to program 802.1Q VLANs. See GLOBAL_VTU_OP. |
| 448 | */ |
| 449 | MV88E6XXX_CAP_VTU, |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 450 | }; |
Vivien Didelot | b5058d7 | 2016-05-09 13:22:38 -0400 | [diff] [blame] | 451 | |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 452 | /* Bitmask of capabilities */ |
Andrew Lunn | d6b1023 | 2016-09-21 01:40:32 +0200 | [diff] [blame] | 453 | #define MV88E6XXX_FLAG_EDSA BIT_ULL(MV88E6XXX_CAP_EDSA) |
| 454 | #define MV88E6XXX_FLAG_EEE BIT_ULL(MV88E6XXX_CAP_EEE) |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 455 | |
Andrew Lunn | d6b1023 | 2016-09-21 01:40:32 +0200 | [diff] [blame] | 456 | #define MV88E6XXX_FLAG_SMI_CMD BIT_ULL(MV88E6XXX_CAP_SMI_CMD) |
| 457 | #define MV88E6XXX_FLAG_SMI_DATA BIT_ULL(MV88E6XXX_CAP_SMI_DATA) |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 458 | |
Andrew Lunn | d6b1023 | 2016-09-21 01:40:32 +0200 | [diff] [blame] | 459 | #define MV88E6XXX_FLAG_PHY_PAGE BIT_ULL(MV88E6XXX_CAP_PHY_PAGE) |
Vivien Didelot | 09cb7df | 2016-08-15 17:19:01 -0400 | [diff] [blame] | 460 | |
Andrew Lunn | d6b1023 | 2016-09-21 01:40:32 +0200 | [diff] [blame] | 461 | #define MV88E6XXX_FLAG_SERDES BIT_ULL(MV88E6XXX_CAP_SERDES) |
Vivien Didelot | 09cb7df | 2016-08-15 17:19:01 -0400 | [diff] [blame] | 462 | |
Vivien Didelot | 6dc10bb | 2016-09-29 12:21:55 -0400 | [diff] [blame] | 463 | #define MV88E6XXX_FLAG_G1_ATU_FID BIT_ULL(MV88E6XXX_CAP_G1_ATU_FID) |
| 464 | #define MV88E6XXX_FLAG_G1_VTU_FID BIT_ULL(MV88E6XXX_CAP_G1_VTU_FID) |
| 465 | |
Andrew Lunn | d6b1023 | 2016-09-21 01:40:32 +0200 | [diff] [blame] | 466 | #define MV88E6XXX_FLAG_GLOBAL2 BIT_ULL(MV88E6XXX_CAP_GLOBAL2) |
| 467 | #define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_2X) |
| 468 | #define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_0X) |
| 469 | #define MV88E6XXX_FLAG_G2_IRL_CMD BIT_ULL(MV88E6XXX_CAP_G2_IRL_CMD) |
| 470 | #define MV88E6XXX_FLAG_G2_IRL_DATA BIT_ULL(MV88E6XXX_CAP_G2_IRL_DATA) |
| 471 | #define MV88E6XXX_FLAG_G2_PVT_ADDR BIT_ULL(MV88E6XXX_CAP_G2_PVT_ADDR) |
| 472 | #define MV88E6XXX_FLAG_G2_PVT_DATA BIT_ULL(MV88E6XXX_CAP_G2_PVT_DATA) |
Andrew Lunn | d6b1023 | 2016-09-21 01:40:32 +0200 | [diff] [blame] | 473 | #define MV88E6XXX_FLAG_G2_POT BIT_ULL(MV88E6XXX_CAP_G2_POT) |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 474 | |
Andrew Lunn | d6b1023 | 2016-09-21 01:40:32 +0200 | [diff] [blame] | 475 | #define MV88E6XXX_FLAG_PPU BIT_ULL(MV88E6XXX_CAP_PPU) |
| 476 | #define MV88E6XXX_FLAG_PPU_ACTIVE BIT_ULL(MV88E6XXX_CAP_PPU_ACTIVE) |
| 477 | #define MV88E6XXX_FLAG_STU BIT_ULL(MV88E6XXX_CAP_STU) |
| 478 | #define MV88E6XXX_FLAG_TEMP BIT_ULL(MV88E6XXX_CAP_TEMP) |
| 479 | #define MV88E6XXX_FLAG_TEMP_LIMIT BIT_ULL(MV88E6XXX_CAP_TEMP_LIMIT) |
| 480 | #define MV88E6XXX_FLAG_VTU BIT_ULL(MV88E6XXX_CAP_VTU) |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 481 | |
Vivien Didelot | 8ec61c7 | 2016-07-18 20:45:37 -0400 | [diff] [blame] | 482 | /* Ingress Rate Limit unit */ |
| 483 | #define MV88E6XXX_FLAGS_IRL \ |
| 484 | (MV88E6XXX_FLAG_G2_IRL_CMD | \ |
| 485 | MV88E6XXX_FLAG_G2_IRL_DATA) |
| 486 | |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 487 | /* Multi-chip Addressing Mode */ |
| 488 | #define MV88E6XXX_FLAGS_MULTI_CHIP \ |
| 489 | (MV88E6XXX_FLAG_SMI_CMD | \ |
| 490 | MV88E6XXX_FLAG_SMI_DATA) |
| 491 | |
Vivien Didelot | 63ed880 | 2016-07-18 20:45:35 -0400 | [diff] [blame] | 492 | /* Cross-chip Port VLAN Table */ |
| 493 | #define MV88E6XXX_FLAGS_PVT \ |
| 494 | (MV88E6XXX_FLAG_G2_PVT_ADDR | \ |
| 495 | MV88E6XXX_FLAG_G2_PVT_DATA) |
| 496 | |
Vivien Didelot | 09cb7df | 2016-08-15 17:19:01 -0400 | [diff] [blame] | 497 | /* Fiber/SERDES Registers at SMI address F, page 1 */ |
| 498 | #define MV88E6XXX_FLAGS_SERDES \ |
| 499 | (MV88E6XXX_FLAG_PHY_PAGE | \ |
| 500 | MV88E6XXX_FLAG_SERDES) |
| 501 | |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 502 | #define MV88E6XXX_FLAGS_FAMILY_6095 \ |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 503 | (MV88E6XXX_FLAG_GLOBAL2 | \ |
Vivien Didelot | 47395ed | 2016-07-18 20:45:33 -0400 | [diff] [blame] | 504 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
Vivien Didelot | 2672f82 | 2016-05-09 13:22:48 -0400 | [diff] [blame] | 505 | MV88E6XXX_FLAG_PPU | \ |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 506 | MV88E6XXX_FLAG_VTU | \ |
| 507 | MV88E6XXX_FLAGS_MULTI_CHIP) |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 508 | |
| 509 | #define MV88E6XXX_FLAGS_FAMILY_6097 \ |
Vivien Didelot | 6dc10bb | 2016-09-29 12:21:55 -0400 | [diff] [blame] | 510 | (MV88E6XXX_FLAG_G1_ATU_FID | \ |
| 511 | MV88E6XXX_FLAG_G1_VTU_FID | \ |
| 512 | MV88E6XXX_FLAG_GLOBAL2 | \ |
Vivien Didelot | 47395ed | 2016-07-18 20:45:33 -0400 | [diff] [blame] | 513 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
| 514 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
Vivien Didelot | 9bda889 | 2016-07-18 20:45:36 -0400 | [diff] [blame] | 515 | MV88E6XXX_FLAG_G2_POT | \ |
Vivien Didelot | 2672f82 | 2016-05-09 13:22:48 -0400 | [diff] [blame] | 516 | MV88E6XXX_FLAG_PPU | \ |
Vivien Didelot | cb9b902 | 2016-05-10 15:44:29 -0400 | [diff] [blame] | 517 | MV88E6XXX_FLAG_STU | \ |
Vivien Didelot | 63ed880 | 2016-07-18 20:45:35 -0400 | [diff] [blame] | 518 | MV88E6XXX_FLAG_VTU | \ |
Vivien Didelot | 8ec61c7 | 2016-07-18 20:45:37 -0400 | [diff] [blame] | 519 | MV88E6XXX_FLAGS_IRL | \ |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 520 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
Vivien Didelot | 63ed880 | 2016-07-18 20:45:35 -0400 | [diff] [blame] | 521 | MV88E6XXX_FLAGS_PVT) |
Vivien Didelot | b5058d7 | 2016-05-09 13:22:38 -0400 | [diff] [blame] | 522 | |
Vivien Didelot | 6594f61 | 2016-05-09 13:22:42 -0400 | [diff] [blame] | 523 | #define MV88E6XXX_FLAGS_FAMILY_6165 \ |
Vivien Didelot | 6dc10bb | 2016-09-29 12:21:55 -0400 | [diff] [blame] | 524 | (MV88E6XXX_FLAG_G1_ATU_FID | \ |
| 525 | MV88E6XXX_FLAG_G1_VTU_FID | \ |
| 526 | MV88E6XXX_FLAG_GLOBAL2 | \ |
Vivien Didelot | 47395ed | 2016-07-18 20:45:33 -0400 | [diff] [blame] | 527 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
| 528 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
Vivien Didelot | 9bda889 | 2016-07-18 20:45:36 -0400 | [diff] [blame] | 529 | MV88E6XXX_FLAG_G2_POT | \ |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 530 | MV88E6XXX_FLAG_STU | \ |
Vivien Didelot | cb9b902 | 2016-05-10 15:44:29 -0400 | [diff] [blame] | 531 | MV88E6XXX_FLAG_TEMP | \ |
Vivien Didelot | 63ed880 | 2016-07-18 20:45:35 -0400 | [diff] [blame] | 532 | MV88E6XXX_FLAG_VTU | \ |
Vivien Didelot | 8ec61c7 | 2016-07-18 20:45:37 -0400 | [diff] [blame] | 533 | MV88E6XXX_FLAGS_IRL | \ |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 534 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
Vivien Didelot | 63ed880 | 2016-07-18 20:45:35 -0400 | [diff] [blame] | 535 | MV88E6XXX_FLAGS_PVT) |
Vivien Didelot | b5058d7 | 2016-05-09 13:22:38 -0400 | [diff] [blame] | 536 | |
Vivien Didelot | 8c9983a | 2016-05-09 13:22:39 -0400 | [diff] [blame] | 537 | #define MV88E6XXX_FLAGS_FAMILY_6185 \ |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 538 | (MV88E6XXX_FLAG_GLOBAL2 | \ |
Vivien Didelot | 47395ed | 2016-07-18 20:45:33 -0400 | [diff] [blame] | 539 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 540 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
Vivien Didelot | 2672f82 | 2016-05-09 13:22:48 -0400 | [diff] [blame] | 541 | MV88E6XXX_FLAG_PPU | \ |
Vivien Didelot | 54d77b5 | 2016-05-09 13:22:47 -0400 | [diff] [blame] | 542 | MV88E6XXX_FLAG_VTU) |
Vivien Didelot | b5058d7 | 2016-05-09 13:22:38 -0400 | [diff] [blame] | 543 | |
Vivien Didelot | 6d5834a | 2016-05-09 13:22:40 -0400 | [diff] [blame] | 544 | #define MV88E6XXX_FLAGS_FAMILY_6320 \ |
Andrew Lunn | 2bbb33b | 2016-08-22 16:01:02 +0200 | [diff] [blame] | 545 | (MV88E6XXX_FLAG_EDSA | \ |
| 546 | MV88E6XXX_FLAG_EEE | \ |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 547 | MV88E6XXX_FLAG_GLOBAL2 | \ |
Vivien Didelot | 47395ed | 2016-07-18 20:45:33 -0400 | [diff] [blame] | 548 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
| 549 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
Vivien Didelot | 9bda889 | 2016-07-18 20:45:36 -0400 | [diff] [blame] | 550 | MV88E6XXX_FLAG_G2_POT | \ |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 551 | MV88E6XXX_FLAG_PPU_ACTIVE | \ |
Vivien Didelot | 6594f61 | 2016-05-09 13:22:42 -0400 | [diff] [blame] | 552 | MV88E6XXX_FLAG_TEMP | \ |
Vivien Didelot | 936f234 | 2016-05-09 13:22:46 -0400 | [diff] [blame] | 553 | MV88E6XXX_FLAG_TEMP_LIMIT | \ |
Vivien Didelot | 63ed880 | 2016-07-18 20:45:35 -0400 | [diff] [blame] | 554 | MV88E6XXX_FLAG_VTU | \ |
Vivien Didelot | 8ec61c7 | 2016-07-18 20:45:37 -0400 | [diff] [blame] | 555 | MV88E6XXX_FLAGS_IRL | \ |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 556 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 557 | MV88E6XXX_FLAGS_PVT) |
Vivien Didelot | b5058d7 | 2016-05-09 13:22:38 -0400 | [diff] [blame] | 558 | |
Vivien Didelot | 6d5834a | 2016-05-09 13:22:40 -0400 | [diff] [blame] | 559 | #define MV88E6XXX_FLAGS_FAMILY_6351 \ |
Andrew Lunn | 2bbb33b | 2016-08-22 16:01:02 +0200 | [diff] [blame] | 560 | (MV88E6XXX_FLAG_EDSA | \ |
Vivien Didelot | 6dc10bb | 2016-09-29 12:21:55 -0400 | [diff] [blame] | 561 | MV88E6XXX_FLAG_G1_ATU_FID | \ |
| 562 | MV88E6XXX_FLAG_G1_VTU_FID | \ |
Andrew Lunn | 2bbb33b | 2016-08-22 16:01:02 +0200 | [diff] [blame] | 563 | MV88E6XXX_FLAG_GLOBAL2 | \ |
Vivien Didelot | 47395ed | 2016-07-18 20:45:33 -0400 | [diff] [blame] | 564 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
| 565 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
Vivien Didelot | 9bda889 | 2016-07-18 20:45:36 -0400 | [diff] [blame] | 566 | MV88E6XXX_FLAG_G2_POT | \ |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 567 | MV88E6XXX_FLAG_PPU_ACTIVE | \ |
Vivien Didelot | cb9b902 | 2016-05-10 15:44:29 -0400 | [diff] [blame] | 568 | MV88E6XXX_FLAG_STU | \ |
Vivien Didelot | 936f234 | 2016-05-09 13:22:46 -0400 | [diff] [blame] | 569 | MV88E6XXX_FLAG_TEMP | \ |
Vivien Didelot | 63ed880 | 2016-07-18 20:45:35 -0400 | [diff] [blame] | 570 | MV88E6XXX_FLAG_VTU | \ |
Vivien Didelot | 8ec61c7 | 2016-07-18 20:45:37 -0400 | [diff] [blame] | 571 | MV88E6XXX_FLAGS_IRL | \ |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 572 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 573 | MV88E6XXX_FLAGS_PVT) |
Vivien Didelot | b5058d7 | 2016-05-09 13:22:38 -0400 | [diff] [blame] | 574 | |
Vivien Didelot | 6d5834a | 2016-05-09 13:22:40 -0400 | [diff] [blame] | 575 | #define MV88E6XXX_FLAGS_FAMILY_6352 \ |
Andrew Lunn | 2bbb33b | 2016-08-22 16:01:02 +0200 | [diff] [blame] | 576 | (MV88E6XXX_FLAG_EDSA | \ |
| 577 | MV88E6XXX_FLAG_EEE | \ |
Vivien Didelot | 6dc10bb | 2016-09-29 12:21:55 -0400 | [diff] [blame] | 578 | MV88E6XXX_FLAG_G1_ATU_FID | \ |
| 579 | MV88E6XXX_FLAG_G1_VTU_FID | \ |
Vivien Didelot | 9729934 | 2016-07-18 20:45:30 -0400 | [diff] [blame] | 580 | MV88E6XXX_FLAG_GLOBAL2 | \ |
Vivien Didelot | 47395ed | 2016-07-18 20:45:33 -0400 | [diff] [blame] | 581 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
| 582 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
Vivien Didelot | 9bda889 | 2016-07-18 20:45:36 -0400 | [diff] [blame] | 583 | MV88E6XXX_FLAG_G2_POT | \ |
Vivien Didelot | 552238b | 2016-05-09 13:22:49 -0400 | [diff] [blame] | 584 | MV88E6XXX_FLAG_PPU_ACTIVE | \ |
Vivien Didelot | cb9b902 | 2016-05-10 15:44:29 -0400 | [diff] [blame] | 585 | MV88E6XXX_FLAG_STU | \ |
Vivien Didelot | 6594f61 | 2016-05-09 13:22:42 -0400 | [diff] [blame] | 586 | MV88E6XXX_FLAG_TEMP | \ |
Vivien Didelot | 936f234 | 2016-05-09 13:22:46 -0400 | [diff] [blame] | 587 | MV88E6XXX_FLAG_TEMP_LIMIT | \ |
Vivien Didelot | 63ed880 | 2016-07-18 20:45:35 -0400 | [diff] [blame] | 588 | MV88E6XXX_FLAG_VTU | \ |
Vivien Didelot | 8ec61c7 | 2016-07-18 20:45:37 -0400 | [diff] [blame] | 589 | MV88E6XXX_FLAGS_IRL | \ |
Vivien Didelot | a0ffff2 | 2016-08-15 17:18:58 -0400 | [diff] [blame] | 590 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
Vivien Didelot | 57c67cf | 2016-08-15 17:18:59 -0400 | [diff] [blame] | 591 | MV88E6XXX_FLAGS_PVT | \ |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 592 | MV88E6XXX_FLAGS_SERDES) |
| 593 | |
| 594 | struct mv88e6xxx_ops; |
Vivien Didelot | b5058d7 | 2016-05-09 13:22:38 -0400 | [diff] [blame] | 595 | |
Vivien Didelot | f6271e6 | 2016-04-17 13:23:59 -0400 | [diff] [blame] | 596 | struct mv88e6xxx_info { |
Vivien Didelot | 2235647 | 2016-04-17 13:24:00 -0400 | [diff] [blame] | 597 | enum mv88e6xxx_family family; |
Vivien Didelot | f6271e6 | 2016-04-17 13:23:59 -0400 | [diff] [blame] | 598 | u16 prod_num; |
| 599 | const char *name; |
Vivien Didelot | cd5a2c8 | 2016-04-17 13:24:02 -0400 | [diff] [blame] | 600 | unsigned int num_databases; |
Vivien Didelot | 009a2b9 | 2016-04-17 13:24:01 -0400 | [diff] [blame] | 601 | unsigned int num_ports; |
Vivien Didelot | 9dddd47 | 2016-06-20 13:14:10 -0400 | [diff] [blame] | 602 | unsigned int port_base_addr; |
Vivien Didelot | a935c05 | 2016-09-29 12:21:53 -0400 | [diff] [blame] | 603 | unsigned int global1_addr; |
Vivien Didelot | acddbd2 | 2016-07-18 20:45:39 -0400 | [diff] [blame] | 604 | unsigned int age_time_coeff; |
Andrew Lunn | d6b1023 | 2016-09-21 01:40:32 +0200 | [diff] [blame] | 605 | unsigned long long flags; |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 606 | const struct mv88e6xxx_ops *ops; |
Vivien Didelot | b9b3771 | 2015-10-30 19:39:48 -0400 | [diff] [blame] | 607 | }; |
| 608 | |
Vivien Didelot | fd231c8 | 2015-08-10 09:09:50 -0400 | [diff] [blame] | 609 | struct mv88e6xxx_atu_entry { |
| 610 | u16 fid; |
| 611 | u8 state; |
| 612 | bool trunk; |
| 613 | u16 portv_trunkid; |
| 614 | u8 mac[ETH_ALEN]; |
| 615 | }; |
| 616 | |
Vivien Didelot | b4e47c0 | 2016-09-29 12:21:58 -0400 | [diff] [blame] | 617 | struct mv88e6xxx_vtu_entry { |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 618 | u16 vid; |
| 619 | u16 fid; |
Vivien Didelot | b8fee95 | 2015-08-13 12:52:19 -0400 | [diff] [blame] | 620 | u8 sid; |
| 621 | bool valid; |
| 622 | u8 data[DSA_MAX_PORTS]; |
| 623 | }; |
| 624 | |
Vivien Didelot | c08026a | 2016-09-29 12:21:59 -0400 | [diff] [blame] | 625 | struct mv88e6xxx_bus_ops; |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 626 | |
Vivien Didelot | d715fa6 | 2016-02-12 12:09:38 -0500 | [diff] [blame] | 627 | struct mv88e6xxx_priv_port { |
Vivien Didelot | a669275 | 2016-02-12 12:09:39 -0500 | [diff] [blame] | 628 | struct net_device *bridge_dev; |
Vivien Didelot | d715fa6 | 2016-02-12 12:09:38 -0500 | [diff] [blame] | 629 | }; |
| 630 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 631 | struct mv88e6xxx_chip { |
Vivien Didelot | f6271e6 | 2016-04-17 13:23:59 -0400 | [diff] [blame] | 632 | const struct mv88e6xxx_info *info; |
| 633 | |
Andrew Lunn | 7543a6d | 2016-04-13 02:40:40 +0200 | [diff] [blame] | 634 | /* The dsa_switch this private structure is related to */ |
| 635 | struct dsa_switch *ds; |
| 636 | |
Andrew Lunn | 158bc06 | 2016-04-28 21:24:06 -0400 | [diff] [blame] | 637 | /* The device this structure is associated to */ |
| 638 | struct device *dev; |
| 639 | |
Vivien Didelot | 9f8b3ee | 2016-06-20 13:14:05 -0400 | [diff] [blame] | 640 | /* This mutex protects the access to the switch registers */ |
| 641 | struct mutex reg_lock; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 642 | |
Andrew Lunn | a77d43f | 2016-04-13 02:40:42 +0200 | [diff] [blame] | 643 | /* The MII bus and the address on the bus that is used to |
| 644 | * communication with the switch |
| 645 | */ |
Vivien Didelot | c08026a | 2016-09-29 12:21:59 -0400 | [diff] [blame] | 646 | const struct mv88e6xxx_bus_ops *smi_ops; |
Andrew Lunn | a77d43f | 2016-04-13 02:40:42 +0200 | [diff] [blame] | 647 | struct mii_bus *bus; |
| 648 | int sw_addr; |
| 649 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 650 | /* Handles automatic disabling and re-enabling of the PHY |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 651 | * polling unit. |
| 652 | */ |
Vivien Didelot | c08026a | 2016-09-29 12:21:59 -0400 | [diff] [blame] | 653 | const struct mv88e6xxx_bus_ops *phy_ops; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 654 | struct mutex ppu_mutex; |
| 655 | int ppu_disabled; |
| 656 | struct work_struct ppu_work; |
| 657 | struct timer_list ppu_timer; |
Lennert Buytenhek | 2e5f032 | 2008-10-07 13:45:18 +0000 | [diff] [blame] | 658 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 659 | /* This mutex serialises access to the statistics unit. |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 660 | * Hold this mutex over snapshot + dump sequences. |
| 661 | */ |
| 662 | struct mutex stats_mutex; |
Peter Korsgaard | ec80bfc | 2011-04-05 03:03:56 +0000 | [diff] [blame] | 663 | |
Vivien Didelot | d715fa6 | 2016-02-12 12:09:38 -0500 | [diff] [blame] | 664 | struct mv88e6xxx_priv_port ports[DSA_MAX_PORTS]; |
| 665 | |
Andrew Lunn | 52638f7 | 2016-05-10 23:27:22 +0200 | [diff] [blame] | 666 | /* A switch may have a GPIO line tied to its reset pin. Parse |
| 667 | * this from the device tree, and use it before performing |
| 668 | * switch soft reset. |
| 669 | */ |
| 670 | struct gpio_desc *reset; |
Andrew Lunn | f8cd875 | 2016-05-10 23:27:25 +0200 | [diff] [blame] | 671 | |
| 672 | /* set to size of eeprom if supported by the switch */ |
| 673 | int eeprom_len; |
Andrew Lunn | b516d45 | 2016-06-04 21:17:06 +0200 | [diff] [blame] | 674 | |
| 675 | /* Device node for the MDIO bus */ |
| 676 | struct device_node *mdio_np; |
| 677 | |
| 678 | /* And the MDIO bus itself */ |
| 679 | struct mii_bus *mdio_bus; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 680 | }; |
| 681 | |
Vivien Didelot | c08026a | 2016-09-29 12:21:59 -0400 | [diff] [blame] | 682 | struct mv88e6xxx_bus_ops { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 683 | int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); |
| 684 | int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); |
Vivien Didelot | 914b32f | 2016-06-20 13:14:11 -0400 | [diff] [blame] | 685 | }; |
| 686 | |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 687 | struct mv88e6xxx_ops { |
Vivien Didelot | ee4dc2e7 | 2016-09-29 12:22:02 -0400 | [diff] [blame] | 688 | int (*get_eeprom)(struct mv88e6xxx_chip *chip, |
| 689 | struct ethtool_eeprom *eeprom, u8 *data); |
| 690 | int (*set_eeprom)(struct mv88e6xxx_chip *chip, |
| 691 | struct ethtool_eeprom *eeprom, u8 *data); |
| 692 | |
Vivien Didelot | b073d4e | 2016-09-29 12:22:01 -0400 | [diff] [blame] | 693 | int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); |
| 694 | |
Vivien Didelot | b3469dd | 2016-09-29 12:22:00 -0400 | [diff] [blame] | 695 | int (*phy_read)(struct mv88e6xxx_chip *chip, int addr, int reg, |
| 696 | u16 *val); |
| 697 | int (*phy_write)(struct mv88e6xxx_chip *chip, int addr, int reg, |
| 698 | u16 val); |
| 699 | }; |
| 700 | |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 701 | enum stat_type { |
| 702 | BANK0, |
| 703 | BANK1, |
| 704 | PORT, |
| 705 | }; |
| 706 | |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 707 | struct mv88e6xxx_hw_stat { |
| 708 | char string[ETH_GSTRING_LEN]; |
| 709 | int sizeof_stat; |
| 710 | int reg; |
Andrew Lunn | f5e2ed0 | 2015-12-23 13:23:17 +0100 | [diff] [blame] | 711 | enum stat_type type; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 712 | }; |
| 713 | |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 714 | static inline bool mv88e6xxx_has(struct mv88e6xxx_chip *chip, |
Vivien Didelot | b5058d7 | 2016-05-09 13:22:38 -0400 | [diff] [blame] | 715 | unsigned long flags) |
| 716 | { |
Vivien Didelot | fad09c7 | 2016-06-21 12:28:20 -0400 | [diff] [blame] | 717 | return (chip->info->flags & flags) == flags; |
Vivien Didelot | b5058d7 | 2016-05-09 13:22:38 -0400 | [diff] [blame] | 718 | } |
| 719 | |
Vivien Didelot | de33376 | 2016-09-29 12:21:56 -0400 | [diff] [blame] | 720 | static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) |
| 721 | { |
| 722 | return chip->info->num_databases; |
| 723 | } |
| 724 | |
Vivien Didelot | 370b4ff | 2016-09-29 12:21:57 -0400 | [diff] [blame] | 725 | static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) |
| 726 | { |
| 727 | return chip->info->num_ports; |
| 728 | } |
| 729 | |
Vivien Didelot | ec56127 | 2016-09-02 14:45:33 -0400 | [diff] [blame] | 730 | int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); |
| 731 | int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); |
| 732 | int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, |
| 733 | u16 update); |
| 734 | int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask); |
| 735 | |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 736 | #endif |