huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014-2015 Hisilicon Limited. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | */ |
| 9 | |
| 10 | #ifndef __HNS_DSAF_MAIN_H |
| 11 | #define __HNS_DSAF_MAIN_H |
| 12 | #include "hnae.h" |
| 13 | |
| 14 | #include "hns_dsaf_reg.h" |
| 15 | #include "hns_dsaf_mac.h" |
| 16 | |
| 17 | struct hns_mac_cb; |
| 18 | |
| 19 | #define DSAF_DRV_NAME "hns_dsaf" |
| 20 | #define DSAF_MOD_VERSION "v1.0" |
yankejian | 48189d6 | 2016-01-20 16:00:19 +0800 | [diff] [blame] | 21 | #define DSAF_DEVICE_NAME "dsaf" |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 22 | |
Salil | 13ac695 | 2015-12-03 12:17:53 +0000 | [diff] [blame] | 23 | #define HNS_DSAF_DEBUG_NW_REG_OFFSET 0x100000 |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 24 | |
Salil | 13ac695 | 2015-12-03 12:17:53 +0000 | [diff] [blame] | 25 | #define DSAF_BASE_INNER_PORT_NUM 127/* mac tbl qid*/ |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 26 | |
Salil | 13ac695 | 2015-12-03 12:17:53 +0000 | [diff] [blame] | 27 | #define DSAF_MAX_CHIP_NUM 2 /*max 2 chips */ |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 28 | |
Salil | 13ac695 | 2015-12-03 12:17:53 +0000 | [diff] [blame] | 29 | #define DSAF_DEFAUTL_QUEUE_NUM_PER_PPE 22 |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 30 | |
Salil | 13ac695 | 2015-12-03 12:17:53 +0000 | [diff] [blame] | 31 | #define HNS_DSAF_MAX_DESC_CNT 1024 |
| 32 | #define HNS_DSAF_MIN_DESC_CNT 16 |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 33 | |
Salil | 13ac695 | 2015-12-03 12:17:53 +0000 | [diff] [blame] | 34 | #define DSAF_INVALID_ENTRY_IDX 0xffff |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 35 | |
Salil | 13ac695 | 2015-12-03 12:17:53 +0000 | [diff] [blame] | 36 | #define DSAF_CFG_READ_CNT 30 |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 37 | |
| 38 | #define MAC_NUM_OCTETS_PER_ADDR 6 |
| 39 | |
| 40 | #define DSAF_DUMP_REGS_NUM 504 |
| 41 | #define DSAF_STATIC_NUM 28 |
Daode Huang | 379d395 | 2016-06-21 11:56:30 +0800 | [diff] [blame] | 42 | #define DSAF_V2_STATIC_NUM 44 |
| 43 | #define DSAF_PRIO_NR 8 |
| 44 | #define DSAF_REG_PER_ZONE 3 |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 45 | |
oulijun | e018068 | 2016-08-18 20:32:52 +0800 | [diff] [blame] | 46 | #define DSAF_ROCE_CREDIT_CHN 8 |
| 47 | #define DSAF_ROCE_CHAN_MODE 3 |
| 48 | |
| 49 | enum dsaf_roce_port_mode { |
| 50 | DSAF_ROCE_6PORT_MODE, |
| 51 | DSAF_ROCE_4PORT_MODE, |
| 52 | DSAF_ROCE_2PORT_MODE, |
| 53 | DSAF_ROCE_CHAN_MODE_NUM, |
| 54 | }; |
| 55 | |
| 56 | enum dsaf_roce_port_num { |
| 57 | DSAF_ROCE_PORT_0, |
| 58 | DSAF_ROCE_PORT_1, |
| 59 | DSAF_ROCE_PORT_2, |
| 60 | DSAF_ROCE_PORT_3, |
| 61 | DSAF_ROCE_PORT_4, |
| 62 | DSAF_ROCE_PORT_5, |
| 63 | }; |
| 64 | |
| 65 | enum dsaf_roce_qos_sl { |
| 66 | DSAF_ROCE_SL_0, |
| 67 | DSAF_ROCE_SL_1, |
| 68 | DSAF_ROCE_SL_2, |
| 69 | DSAF_ROCE_SL_3, |
| 70 | }; |
| 71 | |
huangdaode | e4600d6 | 2015-09-27 15:22:44 +0800 | [diff] [blame] | 72 | #define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) |
Yisen.Zhuang\(Zhuangyuzeng\) | 89a4409 | 2016-04-23 17:05:05 +0800 | [diff] [blame] | 73 | #define HNS_DSAF_IS_DEBUG(dev) (dev->dsaf_mode == DSAF_MODE_DISABLE_SP) |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 74 | |
| 75 | enum hal_dsaf_mode { |
| 76 | HRD_DSAF_NO_DSAF_MODE = 0x0, |
| 77 | HRD_DSAF_MODE = 0x1, |
| 78 | }; |
| 79 | |
| 80 | enum hal_dsaf_tc_mode { |
| 81 | HRD_DSAF_4TC_MODE = 0X0, |
| 82 | HRD_DSAF_8TC_MODE = 0X1, |
| 83 | }; |
| 84 | |
| 85 | struct dsaf_vm_def_vlan { |
| 86 | u32 vm_def_vlan_id; |
| 87 | u32 vm_def_vlan_cfi; |
| 88 | u32 vm_def_vlan_pri; |
| 89 | }; |
| 90 | |
| 91 | struct dsaf_tbl_tcam_data { |
| 92 | u32 tbl_tcam_data_high; |
| 93 | u32 tbl_tcam_data_low; |
| 94 | }; |
| 95 | |
| 96 | #define DSAF_PORT_MSK_NUM \ |
| 97 | ((DSAF_TOTAL_QUEUE_NUM + DSAF_SERVICE_NW_NUM - 1) / 32 + 1) |
| 98 | struct dsaf_tbl_tcam_mcast_cfg { |
| 99 | u8 tbl_mcast_old_en; |
| 100 | u8 tbl_mcast_item_vld; |
| 101 | u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM]; |
| 102 | }; |
| 103 | |
| 104 | struct dsaf_tbl_tcam_ucast_cfg { |
| 105 | u32 tbl_ucast_old_en; |
| 106 | u32 tbl_ucast_item_vld; |
| 107 | u32 tbl_ucast_mac_discard; |
| 108 | u32 tbl_ucast_dvc; |
| 109 | u32 tbl_ucast_out_port; |
| 110 | }; |
| 111 | |
| 112 | struct dsaf_tbl_line_cfg { |
| 113 | u32 tbl_line_mac_discard; |
| 114 | u32 tbl_line_dvc; |
| 115 | u32 tbl_line_out_port; |
| 116 | }; |
| 117 | |
| 118 | enum dsaf_port_rate_mode { |
| 119 | DSAF_PORT_RATE_1000 = 0, |
| 120 | DSAF_PORT_RATE_2500, |
| 121 | DSAF_PORT_RATE_10000 |
| 122 | }; |
| 123 | |
| 124 | enum dsaf_stp_port_type { |
| 125 | DSAF_STP_PORT_TYPE_DISCARD = 0, |
| 126 | DSAF_STP_PORT_TYPE_BLOCK = 1, |
| 127 | DSAF_STP_PORT_TYPE_LISTEN = 2, |
| 128 | DSAF_STP_PORT_TYPE_LEARN = 3, |
| 129 | DSAF_STP_PORT_TYPE_FORWARD = 4 |
| 130 | }; |
| 131 | |
| 132 | enum dsaf_sw_port_type { |
| 133 | DSAF_SW_PORT_TYPE_NON_VLAN = 0, |
| 134 | DSAF_SW_PORT_TYPE_ACCESS = 1, |
| 135 | DSAF_SW_PORT_TYPE_TRUNK = 2, |
| 136 | }; |
| 137 | |
| 138 | #define DSAF_SUB_BASE_SIZE (0x10000) |
| 139 | |
| 140 | /* dsaf mode define */ |
| 141 | enum dsaf_mode { |
| 142 | DSAF_MODE_INVALID = 0, /**< Invalid dsaf mode */ |
| 143 | DSAF_MODE_ENABLE_FIX, /**< en DSAF-mode, fixed to queue*/ |
| 144 | DSAF_MODE_ENABLE_0VM, /**< en DSAF-mode, support 0 VM */ |
| 145 | DSAF_MODE_ENABLE_8VM, /**< en DSAF-mode, support 8 VM */ |
| 146 | DSAF_MODE_ENABLE_16VM, /**< en DSAF-mode, support 16 VM */ |
| 147 | DSAF_MODE_ENABLE_32VM, /**< en DSAF-mode, support 32 VM */ |
| 148 | DSAF_MODE_ENABLE_128VM, /**< en DSAF-mode, support 128 VM */ |
| 149 | DSAF_MODE_ENABLE, /**< before is enable DSAF mode*/ |
Yisen.Zhuang\(Zhuangyuzeng\) | 89a4409 | 2016-04-23 17:05:05 +0800 | [diff] [blame] | 150 | DSAF_MODE_DISABLE_SP, /* <non-dsaf, single port mode */ |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 151 | DSAF_MODE_DISABLE_FIX, /**< non-dasf, fixed to queue*/ |
| 152 | DSAF_MODE_DISABLE_2PORT_8VM, /**< non-dasf, 2port 8VM */ |
| 153 | DSAF_MODE_DISABLE_2PORT_16VM, /**< non-dasf, 2port 16VM */ |
| 154 | DSAF_MODE_DISABLE_2PORT_64VM, /**< non-dasf, 2port 64VM */ |
| 155 | DSAF_MODE_DISABLE_6PORT_0VM, /**< non-dasf, 6port 0VM */ |
| 156 | DSAF_MODE_DISABLE_6PORT_2VM, /**< non-dasf, 6port 2VM */ |
| 157 | DSAF_MODE_DISABLE_6PORT_4VM, /**< non-dasf, 6port 4VM */ |
| 158 | DSAF_MODE_DISABLE_6PORT_16VM, /**< non-dasf, 6port 16VM */ |
| 159 | DSAF_MODE_MAX /**< the last one, use as the num */ |
| 160 | }; |
| 161 | |
| 162 | #define DSAF_DEST_PORT_NUM 256 /* DSAF max port num */ |
| 163 | #define DSAF_WORD_BIT_CNT 32 /* the num bit of word */ |
| 164 | |
| 165 | /*mac entry, mc or uc entry*/ |
| 166 | struct dsaf_drv_mac_single_dest_entry { |
| 167 | /* mac addr, match the entry*/ |
| 168 | u8 addr[MAC_NUM_OCTETS_PER_ADDR]; |
| 169 | u16 in_vlan_id; /* value of VlanId */ |
| 170 | |
| 171 | /* the vld input port num, dsaf-mode fix 0, */ |
| 172 | /* non-dasf is the entry whitch port vld*/ |
| 173 | u8 in_port_num; |
| 174 | |
| 175 | u8 port_num; /*output port num*/ |
| 176 | u8 rsv[6]; |
| 177 | }; |
| 178 | |
| 179 | /*only mc entry*/ |
| 180 | struct dsaf_drv_mac_multi_dest_entry { |
| 181 | /* mac addr, match the entry*/ |
| 182 | u8 addr[MAC_NUM_OCTETS_PER_ADDR]; |
| 183 | u16 in_vlan_id; |
| 184 | /* this mac addr output port,*/ |
| 185 | /* bit0-bit5 means Port0-Port5(1bit is vld)**/ |
| 186 | u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT]; |
| 187 | |
| 188 | /* the vld input port num, dsaf-mode fix 0,*/ |
| 189 | /* non-dasf is the entry whitch port vld*/ |
| 190 | u8 in_port_num; |
| 191 | u8 rsv[7]; |
| 192 | }; |
| 193 | |
| 194 | struct dsaf_hw_stats { |
| 195 | u64 pad_drop; |
| 196 | u64 man_pkts; |
| 197 | u64 rx_pkts; |
| 198 | u64 rx_pkt_id; |
| 199 | u64 rx_pause_frame; |
| 200 | u64 release_buf_num; |
| 201 | u64 sbm_drop; |
| 202 | u64 crc_false; |
| 203 | u64 bp_drop; |
| 204 | u64 rslt_drop; |
| 205 | u64 local_addr_false; |
| 206 | u64 vlan_drop; |
| 207 | u64 stp_drop; |
Daode Huang | 379d395 | 2016-06-21 11:56:30 +0800 | [diff] [blame] | 208 | u64 rx_pfc[DSAF_PRIO_NR]; |
| 209 | u64 tx_pfc[DSAF_PRIO_NR]; |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 210 | u64 tx_pkts; |
| 211 | }; |
| 212 | |
| 213 | struct hnae_vf_cb { |
| 214 | u8 port_index; |
| 215 | struct hns_mac_cb *mac_cb; |
| 216 | struct dsaf_device *dsaf_dev; |
| 217 | struct hnae_handle ae_handle; /* must be the last number */ |
| 218 | }; |
| 219 | |
| 220 | struct dsaf_int_xge_src { |
| 221 | u32 xid_xge_ecc_err_int_src; |
| 222 | u32 xid_xge_fsm_timout_int_src; |
| 223 | u32 sbm_xge_lnk_fsm_timout_int_src; |
| 224 | u32 sbm_xge_lnk_ecc_2bit_int_src; |
| 225 | u32 sbm_xge_mib_req_failed_int_src; |
| 226 | u32 sbm_xge_mib_req_fsm_timout_int_src; |
| 227 | u32 sbm_xge_mib_rels_fsm_timout_int_src; |
| 228 | u32 sbm_xge_sram_ecc_2bit_int_src; |
| 229 | u32 sbm_xge_mib_buf_sum_err_int_src; |
| 230 | u32 sbm_xge_mib_req_extra_int_src; |
| 231 | u32 sbm_xge_mib_rels_extra_int_src; |
| 232 | u32 voq_xge_start_to_over_0_int_src; |
| 233 | u32 voq_xge_start_to_over_1_int_src; |
| 234 | u32 voq_xge_ecc_err_int_src; |
| 235 | }; |
| 236 | |
| 237 | struct dsaf_int_ppe_src { |
| 238 | u32 xid_ppe_fsm_timout_int_src; |
| 239 | u32 sbm_ppe_lnk_fsm_timout_int_src; |
| 240 | u32 sbm_ppe_lnk_ecc_2bit_int_src; |
| 241 | u32 sbm_ppe_mib_req_failed_int_src; |
| 242 | u32 sbm_ppe_mib_req_fsm_timout_int_src; |
| 243 | u32 sbm_ppe_mib_rels_fsm_timout_int_src; |
| 244 | u32 sbm_ppe_sram_ecc_2bit_int_src; |
| 245 | u32 sbm_ppe_mib_buf_sum_err_int_src; |
| 246 | u32 sbm_ppe_mib_req_extra_int_src; |
| 247 | u32 sbm_ppe_mib_rels_extra_int_src; |
| 248 | u32 voq_ppe_start_to_over_0_int_src; |
| 249 | u32 voq_ppe_ecc_err_int_src; |
| 250 | u32 xod_ppe_fifo_rd_empty_int_src; |
| 251 | u32 xod_ppe_fifo_wr_full_int_src; |
| 252 | }; |
| 253 | |
| 254 | struct dsaf_int_rocee_src { |
| 255 | u32 xid_rocee_fsm_timout_int_src; |
| 256 | u32 sbm_rocee_lnk_fsm_timout_int_src; |
| 257 | u32 sbm_rocee_lnk_ecc_2bit_int_src; |
| 258 | u32 sbm_rocee_mib_req_failed_int_src; |
| 259 | u32 sbm_rocee_mib_req_fsm_timout_int_src; |
| 260 | u32 sbm_rocee_mib_rels_fsm_timout_int_src; |
| 261 | u32 sbm_rocee_sram_ecc_2bit_int_src; |
| 262 | u32 sbm_rocee_mib_buf_sum_err_int_src; |
| 263 | u32 sbm_rocee_mib_req_extra_int_src; |
| 264 | u32 sbm_rocee_mib_rels_extra_int_src; |
| 265 | u32 voq_rocee_start_to_over_0_int_src; |
| 266 | u32 voq_rocee_ecc_err_int_src; |
| 267 | }; |
| 268 | |
| 269 | struct dsaf_int_tbl_src { |
| 270 | u32 tbl_da0_mis_src; |
| 271 | u32 tbl_da1_mis_src; |
| 272 | u32 tbl_da2_mis_src; |
| 273 | u32 tbl_da3_mis_src; |
| 274 | u32 tbl_da4_mis_src; |
| 275 | u32 tbl_da5_mis_src; |
| 276 | u32 tbl_da6_mis_src; |
| 277 | u32 tbl_da7_mis_src; |
| 278 | u32 tbl_sa_mis_src; |
| 279 | u32 tbl_old_sech_end_src; |
| 280 | u32 lram_ecc_err1_src; |
| 281 | u32 lram_ecc_err2_src; |
| 282 | u32 tram_ecc_err1_src; |
| 283 | u32 tram_ecc_err2_src; |
| 284 | u32 tbl_ucast_bcast_xge0_src; |
| 285 | u32 tbl_ucast_bcast_xge1_src; |
| 286 | u32 tbl_ucast_bcast_xge2_src; |
| 287 | u32 tbl_ucast_bcast_xge3_src; |
| 288 | u32 tbl_ucast_bcast_xge4_src; |
| 289 | u32 tbl_ucast_bcast_xge5_src; |
| 290 | u32 tbl_ucast_bcast_ppe_src; |
| 291 | u32 tbl_ucast_bcast_rocee_src; |
| 292 | }; |
| 293 | |
| 294 | struct dsaf_int_stat { |
| 295 | struct dsaf_int_xge_src dsaf_int_xge_stat[DSAF_COMM_CHN]; |
| 296 | struct dsaf_int_ppe_src dsaf_int_ppe_stat[DSAF_COMM_CHN]; |
| 297 | struct dsaf_int_rocee_src dsaf_int_rocee_stat[DSAF_COMM_CHN]; |
| 298 | struct dsaf_int_tbl_src dsaf_int_tbl_stat[1]; |
| 299 | |
| 300 | }; |
| 301 | |
Kejian Yan | a24274a | 2016-06-03 10:55:17 +0800 | [diff] [blame] | 302 | struct dsaf_misc_op { |
| 303 | void (*cpld_set_led)(struct hns_mac_cb *mac_cb, int link_status, |
| 304 | u16 speed, int data); |
| 305 | void (*cpld_reset_led)(struct hns_mac_cb *mac_cb); |
| 306 | int (*cpld_set_led_id)(struct hns_mac_cb *mac_cb, |
| 307 | enum hnae_led_state status); |
| 308 | /* reset seris function, it will be reset if the dereseet is 0 */ |
| 309 | void (*dsaf_reset)(struct dsaf_device *dsaf_dev, bool dereset); |
| 310 | void (*xge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset); |
| 311 | void (*xge_core_srst)(struct dsaf_device *dsaf_dev, u32 port, |
| 312 | bool dereset); |
| 313 | void (*ge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset); |
| 314 | void (*ppe_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset); |
| 315 | void (*ppe_comm_srst)(struct dsaf_device *dsaf_dev, bool dereset); |
| 316 | |
| 317 | phy_interface_t (*get_phy_if)(struct hns_mac_cb *mac_cb); |
| 318 | int (*get_sfp_prsnt)(struct hns_mac_cb *mac_cb, int *sfp_prsnt); |
| 319 | |
| 320 | int (*cfg_serdes_loopback)(struct hns_mac_cb *mac_cb, bool en); |
| 321 | }; |
| 322 | |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 323 | /* Dsaf device struct define ,and mac -> dsaf */ |
| 324 | struct dsaf_device { |
| 325 | struct device *dev; |
| 326 | struct hnae_ae_dev ae_dev; |
| 327 | |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 328 | u8 __iomem *sc_base; |
| 329 | u8 __iomem *sds_base; |
| 330 | u8 __iomem *ppe_base; |
| 331 | u8 __iomem *io_base; |
Yisen.Zhuang\(Zhuangyuzeng\) | 831d828 | 2016-04-23 17:05:11 +0800 | [diff] [blame] | 332 | struct regmap *sub_ctrl; |
| 333 | phys_addr_t ppe_paddr; |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 334 | |
| 335 | u32 desc_num; /* desc num per queue*/ |
| 336 | u32 buf_size; /* ring buffer size */ |
Yisen.Zhuang\(Zhuangyuzeng\) | 422c310 | 2016-04-23 17:05:08 +0800 | [diff] [blame] | 337 | u32 reset_offset; /* reset field offset in sub sysctrl */ |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 338 | int buf_size_type; /* ring buffer size-type */ |
| 339 | enum dsaf_mode dsaf_mode; /* dsaf mode */ |
| 340 | enum hal_dsaf_mode dsaf_en; |
| 341 | enum hal_dsaf_tc_mode dsaf_tc_mode; |
| 342 | u32 dsaf_ver; |
| 343 | |
| 344 | struct ppe_common_cb *ppe_common[DSAF_COMM_DEV_NUM]; |
| 345 | struct rcb_common_cb *rcb_common[DSAF_COMM_DEV_NUM]; |
Yisen.Zhuang\(Zhuangyuzeng\) | 831d828 | 2016-04-23 17:05:11 +0800 | [diff] [blame] | 346 | struct hns_mac_cb *mac_cb[DSAF_MAX_PORT_NUM]; |
Kejian Yan | a24274a | 2016-06-03 10:55:17 +0800 | [diff] [blame] | 347 | struct dsaf_misc_op *misc_op; |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 348 | |
| 349 | struct dsaf_hw_stats hw_stats[DSAF_NODE_NUM]; |
| 350 | struct dsaf_int_stat int_stat; |
Daode Huang | b762381 | 2016-06-21 11:56:31 +0800 | [diff] [blame] | 351 | /* make sure tcam table config spinlock */ |
| 352 | spinlock_t tcam_lock; |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 353 | }; |
| 354 | |
| 355 | static inline void *hns_dsaf_dev_priv(const struct dsaf_device *dsaf_dev) |
| 356 | { |
huangdaode | e4600d6 | 2015-09-27 15:22:44 +0800 | [diff] [blame] | 357 | return (void *)((u8 *)dsaf_dev + sizeof(*dsaf_dev)); |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | struct dsaf_drv_tbl_tcam_key { |
| 361 | union { |
| 362 | struct { |
| 363 | u8 mac_3; |
| 364 | u8 mac_2; |
| 365 | u8 mac_1; |
| 366 | u8 mac_0; |
| 367 | } bits; |
| 368 | |
| 369 | u32 val; |
| 370 | } high; |
| 371 | union { |
| 372 | struct { |
| 373 | u32 port:4; /* port id, */ |
| 374 | /* dsaf-mode fixed 0, non-dsaf-mode port id*/ |
| 375 | u32 vlan:12; /* vlan id */ |
| 376 | u32 mac_5:8; |
| 377 | u32 mac_4:8; |
| 378 | } bits; |
| 379 | |
| 380 | u32 val; |
| 381 | } low; |
| 382 | }; |
| 383 | |
| 384 | struct dsaf_drv_soft_mac_tbl { |
| 385 | struct dsaf_drv_tbl_tcam_key tcam_key; |
| 386 | u16 index; /*the entry's index in tcam tab*/ |
| 387 | }; |
| 388 | |
| 389 | struct dsaf_drv_priv { |
| 390 | /* soft tab Mac key, for hardware tab*/ |
| 391 | struct dsaf_drv_soft_mac_tbl *soft_mac_tbl; |
| 392 | }; |
| 393 | |
| 394 | static inline void hns_dsaf_tbl_tcam_addr_cfg(struct dsaf_device *dsaf_dev, |
| 395 | u32 tab_tcam_addr) |
| 396 | { |
| 397 | dsaf_set_dev_field(dsaf_dev, DSAF_TBL_TCAM_ADDR_0_REG, |
| 398 | DSAF_TBL_TCAM_ADDR_M, DSAF_TBL_TCAM_ADDR_S, |
| 399 | tab_tcam_addr); |
| 400 | } |
| 401 | |
| 402 | static inline void hns_dsaf_tbl_tcam_load_pul(struct dsaf_device *dsaf_dev) |
| 403 | { |
| 404 | u32 o_tbl_pul; |
| 405 | |
| 406 | o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); |
| 407 | dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 1); |
| 408 | dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); |
| 409 | dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 0); |
| 410 | dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); |
| 411 | } |
| 412 | |
| 413 | static inline void hns_dsaf_tbl_line_addr_cfg(struct dsaf_device *dsaf_dev, |
| 414 | u32 tab_line_addr) |
| 415 | { |
| 416 | dsaf_set_dev_field(dsaf_dev, DSAF_TBL_LINE_ADDR_0_REG, |
| 417 | DSAF_TBL_LINE_ADDR_M, DSAF_TBL_LINE_ADDR_S, |
| 418 | tab_line_addr); |
| 419 | } |
| 420 | |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 421 | static inline struct hnae_vf_cb *hns_ae_get_vf_cb( |
| 422 | struct hnae_handle *handle) |
| 423 | { |
| 424 | return container_of(handle, struct hnae_vf_cb, ae_handle); |
| 425 | } |
| 426 | |
| 427 | int hns_dsaf_set_mac_uc_entry(struct dsaf_device *dsaf_dev, |
| 428 | struct dsaf_drv_mac_single_dest_entry *mac_entry); |
| 429 | int hns_dsaf_set_mac_mc_entry(struct dsaf_device *dsaf_dev, |
| 430 | struct dsaf_drv_mac_multi_dest_entry *mac_entry); |
| 431 | int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev, |
| 432 | struct dsaf_drv_mac_single_dest_entry *mac_entry); |
| 433 | int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id, |
| 434 | u8 in_port_num, u8 *addr); |
| 435 | int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev, |
| 436 | struct dsaf_drv_mac_single_dest_entry *mac_entry); |
| 437 | int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev, |
| 438 | struct dsaf_drv_mac_single_dest_entry *mac_entry); |
| 439 | int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev, |
| 440 | struct dsaf_drv_mac_multi_dest_entry *mac_entry); |
| 441 | int hns_dsaf_get_mac_entry_by_index( |
| 442 | struct dsaf_device *dsaf_dev, |
| 443 | u16 entry_index, |
| 444 | struct dsaf_drv_mac_multi_dest_entry *mac_entry); |
| 445 | |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 446 | void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb); |
| 447 | |
oulijun | e018068 | 2016-08-18 20:32:52 +0800 | [diff] [blame] | 448 | void hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool enable); |
| 449 | |
| 450 | void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool enable); |
| 451 | |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 452 | int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev); |
| 453 | void hns_dsaf_ae_uninit(struct dsaf_device *dsaf_dev); |
| 454 | |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 455 | void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 inode_num); |
| 456 | |
Daode Huang | 379d395 | 2016-06-21 11:56:30 +0800 | [diff] [blame] | 457 | int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset); |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 458 | void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port); |
Daode Huang | 379d395 | 2016-06-21 11:56:30 +0800 | [diff] [blame] | 459 | void hns_dsaf_get_strings(int stringset, u8 *data, int port, |
| 460 | struct dsaf_device *dsaf_dev); |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 461 | |
| 462 | void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data); |
| 463 | int hns_dsaf_get_regs_count(void); |
yankejian | 4568637 | 2015-10-13 09:53:45 +0800 | [diff] [blame] | 464 | void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en); |
Lisheng | 5ada37b | 2016-03-31 21:00:09 +0800 | [diff] [blame] | 465 | |
| 466 | void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, |
| 467 | u32 *en); |
| 468 | int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, |
| 469 | u32 en); |
yankejian | 68c222a | 2016-03-05 14:10:42 +0800 | [diff] [blame] | 470 | void hns_dsaf_set_inner_lb(struct dsaf_device *dsaf_dev, u32 mac_id, u32 en); |
huangdaode | 511e6bc | 2015-09-17 14:51:49 +0800 | [diff] [blame] | 471 | |
| 472 | #endif /* __HNS_DSAF_MAIN_H__ */ |