Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Driver for Microsemi VSC85xx PHYs |
| 3 | * |
| 4 | * Author: Nagaraju Lakkaraju |
| 5 | * License: Dual MIT/GPL |
| 6 | * Copyright (c) 2016 Microsemi Corporation |
| 7 | */ |
| 8 | |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/module.h> |
| 11 | #include <linux/mdio.h> |
| 12 | #include <linux/mii.h> |
| 13 | #include <linux/phy.h> |
Raju Lakkaraju | a4cc96d | 2016-10-03 12:53:13 +0530 | [diff] [blame] | 14 | #include <linux/of.h> |
| 15 | #include <dt-bindings/net/mscc-phy-vsc8531.h> |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 16 | |
| 17 | enum rgmii_rx_clock_delay { |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 18 | RGMII_RX_CLK_DELAY_0_2_NS = 0, |
| 19 | RGMII_RX_CLK_DELAY_0_8_NS = 1, |
| 20 | RGMII_RX_CLK_DELAY_1_1_NS = 2, |
| 21 | RGMII_RX_CLK_DELAY_1_7_NS = 3, |
| 22 | RGMII_RX_CLK_DELAY_2_0_NS = 4, |
| 23 | RGMII_RX_CLK_DELAY_2_3_NS = 5, |
| 24 | RGMII_RX_CLK_DELAY_2_6_NS = 6, |
| 25 | RGMII_RX_CLK_DELAY_3_4_NS = 7 |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 26 | }; |
| 27 | |
Raju Lakkaraju | 1a21101 | 2016-09-19 15:33:54 +0530 | [diff] [blame] | 28 | /* Microsemi VSC85xx PHY registers */ |
| 29 | /* IEEE 802. Std Registers */ |
| 30 | #define MSCC_PHY_EXT_PHY_CNTL_1 23 |
| 31 | #define MAC_IF_SELECTION_MASK 0x1800 |
| 32 | #define MAC_IF_SELECTION_GMII 0 |
| 33 | #define MAC_IF_SELECTION_RMII 1 |
| 34 | #define MAC_IF_SELECTION_RGMII 2 |
| 35 | #define MAC_IF_SELECTION_POS 11 |
| 36 | #define FAR_END_LOOPBACK_MODE_MASK 0x0008 |
| 37 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 38 | #define MII_VSC85XX_INT_MASK 25 |
| 39 | #define MII_VSC85XX_INT_MASK_MASK 0xa000 |
| 40 | #define MII_VSC85XX_INT_STATUS 26 |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 41 | |
Raju Lakkaraju | a4cc96d | 2016-10-03 12:53:13 +0530 | [diff] [blame] | 42 | #define MSCC_PHY_WOL_MAC_CONTROL 27 |
| 43 | #define EDGE_RATE_CNTL_POS 5 |
| 44 | #define EDGE_RATE_CNTL_MASK 0x00E0 |
| 45 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 46 | #define MSCC_EXT_PAGE_ACCESS 31 |
| 47 | #define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */ |
| 48 | #define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */ |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 49 | |
| 50 | /* Extended Page 2 Registers */ |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 51 | #define MSCC_PHY_RGMII_CNTL 20 |
| 52 | #define RGMII_RX_CLK_DELAY_MASK 0x0070 |
| 53 | #define RGMII_RX_CLK_DELAY_POS 4 |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 54 | |
| 55 | /* Microsemi PHY ID's */ |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 56 | #define PHY_ID_VSC8531 0x00070570 |
| 57 | #define PHY_ID_VSC8541 0x00070770 |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 58 | |
Raju Lakkaraju | a4cc96d | 2016-10-03 12:53:13 +0530 | [diff] [blame] | 59 | struct edge_rate_table { |
| 60 | u16 vddmac; |
| 61 | int slowdown[MSCC_SLOWDOWN_MAX]; |
| 62 | }; |
| 63 | |
| 64 | struct edge_rate_table edge_table[MSCC_VDDMAC_MAX] = { |
| 65 | {3300, { 0, -2, -4, -7, -10, -17, -29, -53} }, |
| 66 | {2500, { 0, -3, -6, -10, -14, -23, -37, -63} }, |
| 67 | {1800, { 0, -5, -9, -16, -23, -35, -52, -76} }, |
| 68 | {1500, { 0, -6, -14, -21, -29, -42, -58, -77} }, |
| 69 | }; |
| 70 | |
| 71 | struct vsc8531_private { |
| 72 | u8 edge_slowdown; |
| 73 | u16 vddmac; |
| 74 | }; |
| 75 | |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 76 | static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page) |
| 77 | { |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 78 | int rc; |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 79 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 80 | rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); |
| 81 | return rc; |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 82 | } |
| 83 | |
Raju Lakkaraju | a4cc96d | 2016-10-03 12:53:13 +0530 | [diff] [blame] | 84 | static u8 edge_rate_magic_get(u16 vddmac, |
| 85 | int slowdown) |
| 86 | { |
| 87 | int rc = (MSCC_SLOWDOWN_MAX - 1); |
| 88 | u8 vdd; |
| 89 | u8 sd; |
| 90 | |
| 91 | for (vdd = 0; vdd < MSCC_VDDMAC_MAX; vdd++) { |
| 92 | if (edge_table[vdd].vddmac == vddmac) { |
| 93 | for (sd = 0; sd < MSCC_SLOWDOWN_MAX; sd++) { |
| 94 | if (edge_table[vdd].slowdown[sd] <= slowdown) { |
| 95 | rc = (MSCC_SLOWDOWN_MAX - sd - 1); |
| 96 | break; |
| 97 | } |
| 98 | } |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | return rc; |
| 103 | } |
| 104 | |
| 105 | static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, |
| 106 | u8 edge_rate) |
| 107 | { |
| 108 | int rc; |
| 109 | u16 reg_val; |
| 110 | |
| 111 | mutex_lock(&phydev->lock); |
| 112 | rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2); |
| 113 | if (rc != 0) |
| 114 | goto out_unlock; |
| 115 | reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); |
| 116 | reg_val &= ~(EDGE_RATE_CNTL_MASK); |
| 117 | reg_val |= (edge_rate << EDGE_RATE_CNTL_POS); |
| 118 | rc = phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); |
| 119 | if (rc != 0) |
| 120 | goto out_unlock; |
| 121 | rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD); |
| 122 | |
| 123 | out_unlock: |
| 124 | mutex_unlock(&phydev->lock); |
| 125 | |
| 126 | return rc; |
| 127 | } |
| 128 | |
Raju Lakkaraju | 1a21101 | 2016-09-19 15:33:54 +0530 | [diff] [blame] | 129 | static int vsc85xx_mac_if_set(struct phy_device *phydev, |
| 130 | phy_interface_t interface) |
| 131 | { |
| 132 | int rc; |
| 133 | u16 reg_val; |
| 134 | |
| 135 | mutex_lock(&phydev->lock); |
| 136 | reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); |
| 137 | reg_val &= ~(MAC_IF_SELECTION_MASK); |
| 138 | switch (interface) { |
| 139 | case PHY_INTERFACE_MODE_RGMII: |
| 140 | reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS); |
| 141 | break; |
| 142 | case PHY_INTERFACE_MODE_RMII: |
| 143 | reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS); |
| 144 | break; |
| 145 | case PHY_INTERFACE_MODE_MII: |
| 146 | case PHY_INTERFACE_MODE_GMII: |
| 147 | reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS); |
| 148 | break; |
| 149 | default: |
| 150 | rc = -EINVAL; |
| 151 | goto out_unlock; |
| 152 | } |
| 153 | rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); |
| 154 | if (rc != 0) |
| 155 | goto out_unlock; |
| 156 | |
| 157 | rc = genphy_soft_reset(phydev); |
| 158 | |
| 159 | out_unlock: |
| 160 | mutex_unlock(&phydev->lock); |
| 161 | |
| 162 | return rc; |
| 163 | } |
| 164 | |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 165 | static int vsc85xx_default_config(struct phy_device *phydev) |
| 166 | { |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 167 | int rc; |
| 168 | u16 reg_val; |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 169 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 170 | mutex_lock(&phydev->lock); |
| 171 | rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2); |
| 172 | if (rc != 0) |
| 173 | goto out_unlock; |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 174 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 175 | reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL); |
| 176 | reg_val &= ~(RGMII_RX_CLK_DELAY_MASK); |
| 177 | reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS); |
| 178 | phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val); |
| 179 | rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD); |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 180 | |
| 181 | out_unlock: |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 182 | mutex_unlock(&phydev->lock); |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 183 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 184 | return rc; |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 185 | } |
| 186 | |
Raju Lakkaraju | a4cc96d | 2016-10-03 12:53:13 +0530 | [diff] [blame] | 187 | #ifdef CONFIG_OF_MDIO |
| 188 | static int vsc8531_of_init(struct phy_device *phydev) |
| 189 | { |
| 190 | int rc; |
| 191 | struct vsc8531_private *vsc8531 = phydev->priv; |
| 192 | struct device *dev = &phydev->mdio.dev; |
| 193 | struct device_node *of_node = dev->of_node; |
| 194 | |
| 195 | if (!of_node) |
| 196 | return -ENODEV; |
| 197 | |
| 198 | rc = of_property_read_u16(of_node, "vsc8531,vddmac", |
| 199 | &vsc8531->vddmac); |
| 200 | if (rc == -EINVAL) |
| 201 | vsc8531->vddmac = MSCC_VDDMAC_3300; |
| 202 | rc = of_property_read_u8(of_node, "vsc8531,edge-slowdown", |
| 203 | &vsc8531->edge_slowdown); |
| 204 | if (rc == -EINVAL) |
| 205 | vsc8531->edge_slowdown = 0; |
| 206 | |
| 207 | rc = 0; |
| 208 | return rc; |
| 209 | } |
| 210 | #else |
| 211 | static int vsc8531_of_init(struct phy_device *phydev) |
| 212 | { |
| 213 | return 0; |
| 214 | } |
| 215 | #endif /* CONFIG_OF_MDIO */ |
| 216 | |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 217 | static int vsc85xx_config_init(struct phy_device *phydev) |
| 218 | { |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 219 | int rc; |
Raju Lakkaraju | a4cc96d | 2016-10-03 12:53:13 +0530 | [diff] [blame] | 220 | struct vsc8531_private *vsc8531 = phydev->priv; |
| 221 | u8 edge_rate; |
| 222 | |
| 223 | rc = vsc8531_of_init(phydev); |
| 224 | if (rc) |
| 225 | return rc; |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 226 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 227 | rc = vsc85xx_default_config(phydev); |
| 228 | if (rc) |
| 229 | return rc; |
Raju Lakkaraju | 1a21101 | 2016-09-19 15:33:54 +0530 | [diff] [blame] | 230 | |
| 231 | rc = vsc85xx_mac_if_set(phydev, phydev->interface); |
| 232 | if (rc) |
| 233 | return rc; |
| 234 | |
Raju Lakkaraju | a4cc96d | 2016-10-03 12:53:13 +0530 | [diff] [blame] | 235 | edge_rate = edge_rate_magic_get(vsc8531->vddmac, |
| 236 | -(int)vsc8531->edge_slowdown); |
| 237 | rc = vsc85xx_edge_rate_cntl_set(phydev, edge_rate); |
| 238 | if (rc) |
| 239 | return rc; |
| 240 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 241 | rc = genphy_config_init(phydev); |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 242 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 243 | return rc; |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 244 | } |
| 245 | |
| 246 | static int vsc85xx_ack_interrupt(struct phy_device *phydev) |
| 247 | { |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 248 | int rc = 0; |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 249 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 250 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
| 251 | rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 252 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 253 | return (rc < 0) ? rc : 0; |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | static int vsc85xx_config_intr(struct phy_device *phydev) |
| 257 | { |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 258 | int rc; |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 259 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 260 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
| 261 | rc = phy_write(phydev, MII_VSC85XX_INT_MASK, |
| 262 | MII_VSC85XX_INT_MASK_MASK); |
| 263 | } else { |
| 264 | rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); |
| 265 | if (rc < 0) |
| 266 | return rc; |
| 267 | rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); |
| 268 | } |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 269 | |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 270 | return rc; |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 271 | } |
| 272 | |
Raju Lakkaraju | a4cc96d | 2016-10-03 12:53:13 +0530 | [diff] [blame] | 273 | static int vsc85xx_probe(struct phy_device *phydev) |
| 274 | { |
| 275 | struct vsc8531_private *vsc8531; |
| 276 | |
| 277 | vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); |
| 278 | if (!vsc8531) |
| 279 | return -ENOMEM; |
| 280 | |
| 281 | phydev->priv = vsc8531; |
| 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 286 | /* Microsemi VSC85xx PHYs */ |
| 287 | static struct phy_driver vsc85xx_driver[] = { |
| 288 | { |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 289 | .phy_id = PHY_ID_VSC8531, |
| 290 | .name = "Microsemi VSC8531", |
| 291 | .phy_id_mask = 0xfffffff0, |
| 292 | .features = PHY_GBIT_FEATURES, |
| 293 | .flags = PHY_HAS_INTERRUPT, |
| 294 | .soft_reset = &genphy_soft_reset, |
| 295 | .config_init = &vsc85xx_config_init, |
| 296 | .config_aneg = &genphy_config_aneg, |
| 297 | .aneg_done = &genphy_aneg_done, |
| 298 | .read_status = &genphy_read_status, |
| 299 | .ack_interrupt = &vsc85xx_ack_interrupt, |
| 300 | .config_intr = &vsc85xx_config_intr, |
| 301 | .suspend = &genphy_suspend, |
| 302 | .resume = &genphy_resume, |
Raju Lakkaraju | a4cc96d | 2016-10-03 12:53:13 +0530 | [diff] [blame] | 303 | .probe = &vsc85xx_probe, |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 304 | }, |
| 305 | { |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 306 | .phy_id = PHY_ID_VSC8541, |
| 307 | .name = "Microsemi VSC8541 SyncE", |
| 308 | .phy_id_mask = 0xfffffff0, |
| 309 | .features = PHY_GBIT_FEATURES, |
| 310 | .flags = PHY_HAS_INTERRUPT, |
| 311 | .soft_reset = &genphy_soft_reset, |
| 312 | .config_init = &vsc85xx_config_init, |
| 313 | .config_aneg = &genphy_config_aneg, |
| 314 | .aneg_done = &genphy_aneg_done, |
| 315 | .read_status = &genphy_read_status, |
| 316 | .ack_interrupt = &vsc85xx_ack_interrupt, |
| 317 | .config_intr = &vsc85xx_config_intr, |
| 318 | .suspend = &genphy_suspend, |
| 319 | .resume = &genphy_resume, |
Raju Lakkaraju | a4cc96d | 2016-10-03 12:53:13 +0530 | [diff] [blame] | 320 | .probe = &vsc85xx_probe, |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 321 | } |
| 322 | |
| 323 | }; |
| 324 | |
| 325 | module_phy_driver(vsc85xx_driver); |
| 326 | |
| 327 | static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = { |
Raju Lakkaraju | 4ffd03f | 2016-09-08 14:09:31 +0530 | [diff] [blame] | 328 | { PHY_ID_VSC8531, 0xfffffff0, }, |
| 329 | { PHY_ID_VSC8541, 0xfffffff0, }, |
| 330 | { } |
Raju Lakkaraju | d50736a | 2016-08-05 17:54:21 +0530 | [diff] [blame] | 331 | }; |
| 332 | |
| 333 | MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl); |
| 334 | |
| 335 | MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver"); |
| 336 | MODULE_AUTHOR("Nagaraju Lakkaraju"); |
| 337 | MODULE_LICENSE("Dual MIT/GPL"); |