| Andrew Jeffery | 4d3d0e4 | 2016-08-30 17:24:24 +0930 | [diff] [blame] | 1 | config PINCTRL_ASPEED |
| 2 | bool |
| 3 | depends on (ARCH_ASPEED || COMPILE_TEST) && OF |
| 4 | depends on MFD_SYSCON |
| 5 | select PINMUX |
| 6 | select PINCONF |
| 7 | select GENERIC_PINCONF |
| 8 | select REGMAP_MMIO |
| Andrew Jeffery | 524594d | 2016-08-30 17:24:25 +0930 | [diff] [blame] | 9 | |
| 10 | config PINCTRL_ASPEED_G4 |
| 11 | bool "Aspeed G4 SoC pin control" |
| 12 | depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF |
| 13 | select PINCTRL_ASPEED |
| 14 | help |
| 15 | Say Y here to enable pin controller support for Aspeed's 4th |
| 16 | generation SoCs. GPIO is provided by a separate GPIO driver. |
| Andrew Jeffery | 56e57cb | 2016-08-30 17:24:26 +0930 | [diff] [blame] | 17 | |
| 18 | config PINCTRL_ASPEED_G5 |
| 19 | bool "Aspeed G5 SoC pin control" |
| 20 | depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF |
| 21 | select PINCTRL_ASPEED |
| 22 | help |
| 23 | Say Y here to enable pin controller support for Aspeed's 5th |
| 24 | generation SoCs. GPIO is provided by a separate GPIO driver. |