Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * dim2_hal.c - DIM2 HAL implementation |
| 3 | * (MediaLB, Device Interface Macro IP, OS62420) |
| 4 | * |
Andrey Shvetsov | 9b762fd | 2016-09-15 16:19:05 +0200 | [diff] [blame] | 5 | * Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | * This file is licensed under GPLv2. |
| 13 | */ |
| 14 | |
| 15 | /* Author: Andrey Shvetsov <andrey.shvetsov@k2l.de> */ |
| 16 | |
| 17 | #include "dim2_hal.h" |
| 18 | #include "dim2_errors.h" |
| 19 | #include "dim2_reg.h" |
| 20 | #include <linux/stddef.h> |
| 21 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 22 | /* |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 23 | * Size factor for isochronous DBR buffer. |
| 24 | * Minimal value is 3. |
| 25 | */ |
| 26 | #define ISOC_DBR_FACTOR 3u |
| 27 | |
| 28 | /* |
| 29 | * Number of 32-bit units for DBR map. |
| 30 | * |
| 31 | * 1: block size is 512, max allocation is 16K |
| 32 | * 2: block size is 256, max allocation is 8K |
| 33 | * 4: block size is 128, max allocation is 4K |
| 34 | * 8: block size is 64, max allocation is 2K |
| 35 | * |
| 36 | * Min allocated space is block size. |
| 37 | * Max possible allocated space is 32 blocks. |
| 38 | */ |
| 39 | #define DBR_MAP_SIZE 2 |
| 40 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 41 | /* -------------------------------------------------------------------------- */ |
| 42 | /* not configurable area */ |
| 43 | |
| 44 | #define CDT 0x00 |
| 45 | #define ADT 0x40 |
| 46 | #define MLB_CAT 0x80 |
| 47 | #define AHB_CAT 0x88 |
| 48 | |
Christian Gromm | 16dc374 | 2015-10-21 17:50:40 +0200 | [diff] [blame] | 49 | #define DBR_SIZE (16 * 1024) /* specified by IP */ |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 50 | #define DBR_BLOCK_SIZE (DBR_SIZE / 32 / DBR_MAP_SIZE) |
| 51 | |
Andrey Shvetsov | a85ee2a | 2016-09-15 16:19:07 +0200 | [diff] [blame] | 52 | #define ROUND_UP_TO(x, d) (((x) + (d) - 1) / (d) * (d)) |
| 53 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 54 | /* -------------------------------------------------------------------------- */ |
| 55 | /* generic helper functions and macros */ |
| 56 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 57 | static inline u32 bit_mask(u8 position) |
| 58 | { |
| 59 | return (u32)1 << position; |
| 60 | } |
| 61 | |
| 62 | static inline bool dim_on_error(u8 error_id, const char *error_message) |
| 63 | { |
Chaehyun Lim | de66873 | 2015-11-02 22:59:02 +0900 | [diff] [blame] | 64 | dimcb_on_error(error_id, error_message); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 65 | return false; |
| 66 | } |
| 67 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 68 | /* -------------------------------------------------------------------------- */ |
| 69 | /* types and local variables */ |
| 70 | |
Andrey Shvetsov | 8f53346 | 2016-09-15 16:19:13 +0200 | [diff] [blame] | 71 | struct async_tx_dbr { |
| 72 | u8 ch_addr; |
| 73 | u16 rpc; |
| 74 | u16 wpc; |
| 75 | u16 rest_size; |
| 76 | u16 sz_queue[CDT0_RPC_MASK + 1]; |
| 77 | }; |
| 78 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 79 | struct lld_global_vars_t { |
| 80 | bool dim_is_initialized; |
| 81 | bool mcm_is_initialized; |
Hugo Camboulive | 092c78f | 2016-01-02 22:33:26 +0000 | [diff] [blame] | 82 | struct dim2_regs __iomem *dim2; /* DIM2 core base address */ |
Andrey Shvetsov | 8f53346 | 2016-09-15 16:19:13 +0200 | [diff] [blame] | 83 | struct async_tx_dbr atx_dbr; |
Christian Gromm | 63c8766 | 2016-06-13 16:24:24 +0200 | [diff] [blame] | 84 | u32 fcnt; |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 85 | u32 dbr_map[DBR_MAP_SIZE]; |
| 86 | }; |
| 87 | |
| 88 | static struct lld_global_vars_t g = { false }; |
| 89 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 90 | /* -------------------------------------------------------------------------- */ |
| 91 | |
| 92 | static int dbr_get_mask_size(u16 size) |
| 93 | { |
| 94 | int i; |
| 95 | |
| 96 | for (i = 0; i < 6; i++) |
| 97 | if (size <= (DBR_BLOCK_SIZE << i)) |
| 98 | return 1 << i; |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | /** |
| 103 | * Allocates DBR memory. |
| 104 | * @param size Allocating memory size. |
| 105 | * @return Offset in DBR memory by success or DBR_SIZE if out of memory. |
| 106 | */ |
| 107 | static int alloc_dbr(u16 size) |
| 108 | { |
| 109 | int mask_size; |
| 110 | int i, block_idx = 0; |
| 111 | |
| 112 | if (size <= 0) |
| 113 | return DBR_SIZE; /* out of memory */ |
| 114 | |
| 115 | mask_size = dbr_get_mask_size(size); |
| 116 | if (mask_size == 0) |
| 117 | return DBR_SIZE; /* out of memory */ |
| 118 | |
| 119 | for (i = 0; i < DBR_MAP_SIZE; i++) { |
| 120 | u32 const blocks = (size + DBR_BLOCK_SIZE - 1) / DBR_BLOCK_SIZE; |
| 121 | u32 mask = ~((~(u32)0) << blocks); |
| 122 | |
| 123 | do { |
| 124 | if ((g.dbr_map[i] & mask) == 0) { |
| 125 | g.dbr_map[i] |= mask; |
| 126 | return block_idx * DBR_BLOCK_SIZE; |
| 127 | } |
| 128 | block_idx += mask_size; |
Christian Gromm | 9158d33 | 2015-10-15 13:28:51 +0200 | [diff] [blame] | 129 | /* do shift left with 2 steps in case mask_size == 32 */ |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 130 | mask <<= mask_size - 1; |
| 131 | } while ((mask <<= 1) != 0); |
| 132 | } |
| 133 | |
| 134 | return DBR_SIZE; /* out of memory */ |
| 135 | } |
| 136 | |
| 137 | static void free_dbr(int offs, int size) |
| 138 | { |
| 139 | int block_idx = offs / DBR_BLOCK_SIZE; |
| 140 | u32 const blocks = (size + DBR_BLOCK_SIZE - 1) / DBR_BLOCK_SIZE; |
| 141 | u32 mask = ~((~(u32)0) << blocks); |
| 142 | |
| 143 | mask <<= block_idx % 32; |
| 144 | g.dbr_map[block_idx / 32] &= ~mask; |
| 145 | } |
| 146 | |
| 147 | /* -------------------------------------------------------------------------- */ |
| 148 | |
Christian Gromm | 95a31ef | 2016-08-18 16:58:47 +0200 | [diff] [blame] | 149 | static void dim2_transfer_madr(u32 val) |
| 150 | { |
| 151 | dimcb_io_write(&g.dim2->MADR, val); |
| 152 | |
| 153 | /* wait for transfer completion */ |
| 154 | while ((dimcb_io_read(&g.dim2->MCTL) & 1) != 1) |
| 155 | continue; |
| 156 | |
| 157 | dimcb_io_write(&g.dim2->MCTL, 0); /* clear transfer complete */ |
| 158 | } |
| 159 | |
Christian Gromm | 9fe7aea | 2016-08-18 16:58:46 +0200 | [diff] [blame] | 160 | static void dim2_clear_dbr(u16 addr, u16 size) |
| 161 | { |
| 162 | enum { MADR_TB_BIT = 30, MADR_WNR_BIT = 31 }; |
| 163 | |
| 164 | u16 const end_addr = addr + size; |
| 165 | u32 const cmd = bit_mask(MADR_WNR_BIT) | bit_mask(MADR_TB_BIT); |
| 166 | |
| 167 | dimcb_io_write(&g.dim2->MCTL, 0); /* clear transfer complete */ |
| 168 | dimcb_io_write(&g.dim2->MDAT0, 0); |
| 169 | |
Christian Gromm | 95a31ef | 2016-08-18 16:58:47 +0200 | [diff] [blame] | 170 | for (; addr < end_addr; addr++) |
| 171 | dim2_transfer_madr(cmd | addr); |
Christian Gromm | 9fe7aea | 2016-08-18 16:58:46 +0200 | [diff] [blame] | 172 | } |
| 173 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 174 | static u32 dim2_read_ctr(u32 ctr_addr, u16 mdat_idx) |
| 175 | { |
Christian Gromm | 95a31ef | 2016-08-18 16:58:47 +0200 | [diff] [blame] | 176 | dim2_transfer_madr(ctr_addr); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 177 | |
Chaehyun Lim | 5888978 | 2015-11-02 22:59:04 +0900 | [diff] [blame] | 178 | return dimcb_io_read((&g.dim2->MDAT0) + mdat_idx); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32 *value) |
| 182 | { |
| 183 | enum { MADR_WNR_BIT = 31 }; |
| 184 | |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 185 | dimcb_io_write(&g.dim2->MCTL, 0); /* clear transfer complete */ |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 186 | |
| 187 | if (mask[0] != 0) |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 188 | dimcb_io_write(&g.dim2->MDAT0, value[0]); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 189 | if (mask[1] != 0) |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 190 | dimcb_io_write(&g.dim2->MDAT1, value[1]); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 191 | if (mask[2] != 0) |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 192 | dimcb_io_write(&g.dim2->MDAT2, value[2]); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 193 | if (mask[3] != 0) |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 194 | dimcb_io_write(&g.dim2->MDAT3, value[3]); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 195 | |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 196 | dimcb_io_write(&g.dim2->MDWE0, mask[0]); |
| 197 | dimcb_io_write(&g.dim2->MDWE1, mask[1]); |
| 198 | dimcb_io_write(&g.dim2->MDWE2, mask[2]); |
| 199 | dimcb_io_write(&g.dim2->MDWE3, mask[3]); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 200 | |
Christian Gromm | 95a31ef | 2016-08-18 16:58:47 +0200 | [diff] [blame] | 201 | dim2_transfer_madr(bit_mask(MADR_WNR_BIT) | ctr_addr); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 202 | } |
| 203 | |
| 204 | static inline void dim2_write_ctr(u32 ctr_addr, const u32 *value) |
| 205 | { |
| 206 | u32 const mask[4] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }; |
| 207 | |
| 208 | dim2_write_ctr_mask(ctr_addr, mask, value); |
| 209 | } |
| 210 | |
| 211 | static inline void dim2_clear_ctr(u32 ctr_addr) |
| 212 | { |
| 213 | u32 const value[4] = { 0, 0, 0, 0 }; |
| 214 | |
| 215 | dim2_write_ctr(ctr_addr, value); |
| 216 | } |
| 217 | |
| 218 | static void dim2_configure_cat(u8 cat_base, u8 ch_addr, u8 ch_type, |
| 219 | bool read_not_write, bool sync_mfe) |
| 220 | { |
| 221 | u16 const cat = |
| 222 | (read_not_write << CAT_RNW_BIT) | |
| 223 | (ch_type << CAT_CT_SHIFT) | |
| 224 | (ch_addr << CAT_CL_SHIFT) | |
| 225 | (sync_mfe << CAT_MFE_BIT) | |
| 226 | (false << CAT_MT_BIT) | |
| 227 | (true << CAT_CE_BIT); |
| 228 | u8 const ctr_addr = cat_base + ch_addr / 8; |
| 229 | u8 const idx = (ch_addr % 8) / 2; |
| 230 | u8 const shift = (ch_addr % 2) * 16; |
| 231 | u32 mask[4] = { 0, 0, 0, 0 }; |
| 232 | u32 value[4] = { 0, 0, 0, 0 }; |
| 233 | |
| 234 | mask[idx] = (u32)0xFFFF << shift; |
| 235 | value[idx] = cat << shift; |
| 236 | dim2_write_ctr_mask(ctr_addr, mask, value); |
| 237 | } |
| 238 | |
| 239 | static void dim2_clear_cat(u8 cat_base, u8 ch_addr) |
| 240 | { |
| 241 | u8 const ctr_addr = cat_base + ch_addr / 8; |
| 242 | u8 const idx = (ch_addr % 8) / 2; |
| 243 | u8 const shift = (ch_addr % 2) * 16; |
| 244 | u32 mask[4] = { 0, 0, 0, 0 }; |
| 245 | u32 value[4] = { 0, 0, 0, 0 }; |
| 246 | |
| 247 | mask[idx] = (u32)0xFFFF << shift; |
| 248 | dim2_write_ctr_mask(ctr_addr, mask, value); |
| 249 | } |
| 250 | |
| 251 | static void dim2_configure_cdt(u8 ch_addr, u16 dbr_address, u16 hw_buffer_size, |
| 252 | u16 packet_length) |
| 253 | { |
| 254 | u32 cdt[4] = { 0, 0, 0, 0 }; |
| 255 | |
| 256 | if (packet_length) |
| 257 | cdt[1] = ((packet_length - 1) << CDT1_BS_ISOC_SHIFT); |
| 258 | |
| 259 | cdt[3] = |
| 260 | ((hw_buffer_size - 1) << CDT3_BD_SHIFT) | |
| 261 | (dbr_address << CDT3_BA_SHIFT); |
| 262 | dim2_write_ctr(CDT + ch_addr, cdt); |
| 263 | } |
| 264 | |
Andrey Shvetsov | 8f53346 | 2016-09-15 16:19:13 +0200 | [diff] [blame] | 265 | static u16 dim2_rpc(u8 ch_addr) |
| 266 | { |
| 267 | u32 cdt0 = dim2_read_ctr(CDT + ch_addr, 0); |
| 268 | |
| 269 | return (cdt0 >> CDT0_RPC_SHIFT) & CDT0_RPC_MASK; |
| 270 | } |
| 271 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 272 | static void dim2_clear_cdt(u8 ch_addr) |
| 273 | { |
| 274 | u32 cdt[4] = { 0, 0, 0, 0 }; |
| 275 | |
| 276 | dim2_write_ctr(CDT + ch_addr, cdt); |
| 277 | } |
| 278 | |
| 279 | static void dim2_configure_adt(u8 ch_addr) |
| 280 | { |
| 281 | u32 adt[4] = { 0, 0, 0, 0 }; |
| 282 | |
| 283 | adt[0] = |
| 284 | (true << ADT0_CE_BIT) | |
| 285 | (true << ADT0_LE_BIT) | |
| 286 | (0 << ADT0_PG_BIT); |
| 287 | |
| 288 | dim2_write_ctr(ADT + ch_addr, adt); |
| 289 | } |
| 290 | |
| 291 | static void dim2_clear_adt(u8 ch_addr) |
| 292 | { |
| 293 | u32 adt[4] = { 0, 0, 0, 0 }; |
| 294 | |
| 295 | dim2_write_ctr(ADT + ch_addr, adt); |
| 296 | } |
| 297 | |
| 298 | static void dim2_start_ctrl_async(u8 ch_addr, u8 idx, u32 buf_addr, |
| 299 | u16 buffer_size) |
| 300 | { |
| 301 | u8 const shift = idx * 16; |
| 302 | |
| 303 | u32 mask[4] = { 0, 0, 0, 0 }; |
| 304 | u32 adt[4] = { 0, 0, 0, 0 }; |
| 305 | |
| 306 | mask[1] = |
| 307 | bit_mask(ADT1_PS_BIT + shift) | |
| 308 | bit_mask(ADT1_RDY_BIT + shift) | |
| 309 | (ADT1_CTRL_ASYNC_BD_MASK << (ADT1_BD_SHIFT + shift)); |
| 310 | adt[1] = |
| 311 | (true << (ADT1_PS_BIT + shift)) | |
| 312 | (true << (ADT1_RDY_BIT + shift)) | |
| 313 | ((buffer_size - 1) << (ADT1_BD_SHIFT + shift)); |
| 314 | |
| 315 | mask[idx + 2] = 0xFFFFFFFF; |
| 316 | adt[idx + 2] = buf_addr; |
| 317 | |
| 318 | dim2_write_ctr_mask(ADT + ch_addr, mask, adt); |
| 319 | } |
| 320 | |
| 321 | static void dim2_start_isoc_sync(u8 ch_addr, u8 idx, u32 buf_addr, |
| 322 | u16 buffer_size) |
| 323 | { |
| 324 | u8 const shift = idx * 16; |
| 325 | |
| 326 | u32 mask[4] = { 0, 0, 0, 0 }; |
| 327 | u32 adt[4] = { 0, 0, 0, 0 }; |
| 328 | |
| 329 | mask[1] = |
| 330 | bit_mask(ADT1_RDY_BIT + shift) | |
| 331 | (ADT1_ISOC_SYNC_BD_MASK << (ADT1_BD_SHIFT + shift)); |
| 332 | adt[1] = |
| 333 | (true << (ADT1_RDY_BIT + shift)) | |
| 334 | ((buffer_size - 1) << (ADT1_BD_SHIFT + shift)); |
| 335 | |
| 336 | mask[idx + 2] = 0xFFFFFFFF; |
| 337 | adt[idx + 2] = buf_addr; |
| 338 | |
| 339 | dim2_write_ctr_mask(ADT + ch_addr, mask, adt); |
| 340 | } |
| 341 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 342 | static void dim2_clear_ctram(void) |
| 343 | { |
| 344 | u32 ctr_addr; |
| 345 | |
| 346 | for (ctr_addr = 0; ctr_addr < 0x90; ctr_addr++) |
| 347 | dim2_clear_ctr(ctr_addr); |
| 348 | } |
| 349 | |
| 350 | static void dim2_configure_channel( |
| 351 | u8 ch_addr, u8 type, u8 is_tx, u16 dbr_address, u16 hw_buffer_size, |
| 352 | u16 packet_length, bool sync_mfe) |
| 353 | { |
| 354 | dim2_configure_cdt(ch_addr, dbr_address, hw_buffer_size, packet_length); |
| 355 | dim2_configure_cat(MLB_CAT, ch_addr, type, is_tx ? 1 : 0, sync_mfe); |
| 356 | |
| 357 | dim2_configure_adt(ch_addr); |
| 358 | dim2_configure_cat(AHB_CAT, ch_addr, type, is_tx ? 0 : 1, sync_mfe); |
| 359 | |
| 360 | /* unmask interrupt for used channel, enable mlb_sys_int[0] interrupt */ |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 361 | dimcb_io_write(&g.dim2->ACMR0, |
Chaehyun Lim | 5888978 | 2015-11-02 22:59:04 +0900 | [diff] [blame] | 362 | dimcb_io_read(&g.dim2->ACMR0) | bit_mask(ch_addr)); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 363 | } |
| 364 | |
| 365 | static void dim2_clear_channel(u8 ch_addr) |
| 366 | { |
| 367 | /* mask interrupt for used channel, disable mlb_sys_int[0] interrupt */ |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 368 | dimcb_io_write(&g.dim2->ACMR0, |
Chaehyun Lim | 5888978 | 2015-11-02 22:59:04 +0900 | [diff] [blame] | 369 | dimcb_io_read(&g.dim2->ACMR0) & ~bit_mask(ch_addr)); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 370 | |
| 371 | dim2_clear_cat(AHB_CAT, ch_addr); |
| 372 | dim2_clear_adt(ch_addr); |
| 373 | |
| 374 | dim2_clear_cat(MLB_CAT, ch_addr); |
| 375 | dim2_clear_cdt(ch_addr); |
Christian Gromm | 1c88f8ff | 2016-06-13 16:24:25 +0200 | [diff] [blame] | 376 | |
| 377 | /* clear channel status bit */ |
| 378 | dimcb_io_write(&g.dim2->ACSR0, bit_mask(ch_addr)); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 379 | } |
| 380 | |
| 381 | /* -------------------------------------------------------------------------- */ |
Andrey Shvetsov | 8f53346 | 2016-09-15 16:19:13 +0200 | [diff] [blame] | 382 | /* trace async tx dbr fill state */ |
| 383 | |
| 384 | static inline u16 norm_pc(u16 pc) |
| 385 | { |
| 386 | return pc & CDT0_RPC_MASK; |
| 387 | } |
| 388 | |
| 389 | static void dbrcnt_init(u8 ch_addr, u16 dbr_size) |
| 390 | { |
| 391 | g.atx_dbr.rest_size = dbr_size; |
| 392 | g.atx_dbr.rpc = dim2_rpc(ch_addr); |
| 393 | g.atx_dbr.wpc = g.atx_dbr.rpc; |
| 394 | } |
| 395 | |
| 396 | static void dbrcnt_enq(int buf_sz) |
| 397 | { |
| 398 | g.atx_dbr.rest_size -= buf_sz; |
| 399 | g.atx_dbr.sz_queue[norm_pc(g.atx_dbr.wpc)] = buf_sz; |
| 400 | g.atx_dbr.wpc++; |
| 401 | } |
| 402 | |
| 403 | u16 dim_dbr_space(struct dim_channel *ch) |
| 404 | { |
| 405 | u16 cur_rpc; |
| 406 | struct async_tx_dbr *dbr = &g.atx_dbr; |
| 407 | |
| 408 | if (ch->addr != dbr->ch_addr) |
| 409 | return 0xFFFF; |
| 410 | |
| 411 | cur_rpc = dim2_rpc(ch->addr); |
| 412 | |
| 413 | while (norm_pc(dbr->rpc) != cur_rpc) { |
| 414 | dbr->rest_size += dbr->sz_queue[norm_pc(dbr->rpc)]; |
| 415 | dbr->rpc++; |
| 416 | } |
| 417 | |
| 418 | if ((u16)(dbr->wpc - dbr->rpc) >= CDT0_RPC_MASK) |
| 419 | return 0; |
| 420 | |
| 421 | return dbr->rest_size; |
| 422 | } |
| 423 | |
| 424 | /* -------------------------------------------------------------------------- */ |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 425 | /* channel state helpers */ |
| 426 | |
| 427 | static void state_init(struct int_ch_state *state) |
| 428 | { |
| 429 | state->request_counter = 0; |
| 430 | state->service_counter = 0; |
| 431 | |
| 432 | state->idx1 = 0; |
| 433 | state->idx2 = 0; |
| 434 | state->level = 0; |
| 435 | } |
| 436 | |
| 437 | /* -------------------------------------------------------------------------- */ |
| 438 | /* macro helper functions */ |
| 439 | |
| 440 | static inline bool check_channel_address(u32 ch_address) |
| 441 | { |
| 442 | return ch_address > 0 && (ch_address % 2) == 0 && |
| 443 | (ch_address / 2) <= (u32)CAT_CL_MASK; |
| 444 | } |
| 445 | |
| 446 | static inline bool check_packet_length(u32 packet_length) |
| 447 | { |
| 448 | u16 const max_size = ((u16)CDT3_BD_ISOC_MASK + 1u) / ISOC_DBR_FACTOR; |
| 449 | |
| 450 | if (packet_length <= 0) |
| 451 | return false; /* too small */ |
| 452 | |
| 453 | if (packet_length > max_size) |
| 454 | return false; /* too big */ |
| 455 | |
| 456 | if (packet_length - 1u > (u32)CDT1_BS_ISOC_MASK) |
| 457 | return false; /* too big */ |
| 458 | |
| 459 | return true; |
| 460 | } |
| 461 | |
| 462 | static inline bool check_bytes_per_frame(u32 bytes_per_frame) |
| 463 | { |
Christian Gromm | 63c8766 | 2016-06-13 16:24:24 +0200 | [diff] [blame] | 464 | u16 const bd_factor = g.fcnt + 2; |
| 465 | u16 const max_size = ((u16)CDT3_BD_MASK + 1u) >> bd_factor; |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 466 | |
| 467 | if (bytes_per_frame <= 0) |
| 468 | return false; /* too small */ |
| 469 | |
| 470 | if (bytes_per_frame > max_size) |
| 471 | return false; /* too big */ |
| 472 | |
| 473 | return true; |
| 474 | } |
| 475 | |
| 476 | static inline u16 norm_ctrl_async_buffer_size(u16 buf_size) |
| 477 | { |
| 478 | u16 const max_size = (u16)ADT1_CTRL_ASYNC_BD_MASK + 1u; |
| 479 | |
| 480 | if (buf_size > max_size) |
| 481 | return max_size; |
| 482 | |
| 483 | return buf_size; |
| 484 | } |
| 485 | |
| 486 | static inline u16 norm_isoc_buffer_size(u16 buf_size, u16 packet_length) |
| 487 | { |
| 488 | u16 n; |
| 489 | u16 const max_size = (u16)ADT1_ISOC_SYNC_BD_MASK + 1u; |
| 490 | |
| 491 | if (buf_size > max_size) |
| 492 | buf_size = max_size; |
| 493 | |
| 494 | n = buf_size / packet_length; |
| 495 | |
| 496 | if (n < 2u) |
| 497 | return 0; /* too small buffer for given packet_length */ |
| 498 | |
| 499 | return packet_length * n; |
| 500 | } |
| 501 | |
| 502 | static inline u16 norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame) |
| 503 | { |
| 504 | u16 n; |
| 505 | u16 const max_size = (u16)ADT1_ISOC_SYNC_BD_MASK + 1u; |
Christian Gromm | 63c8766 | 2016-06-13 16:24:24 +0200 | [diff] [blame] | 506 | u32 const unit = bytes_per_frame << g.fcnt; |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 507 | |
| 508 | if (buf_size > max_size) |
| 509 | buf_size = max_size; |
| 510 | |
| 511 | n = buf_size / unit; |
| 512 | |
| 513 | if (n < 1u) |
| 514 | return 0; /* too small buffer for given bytes_per_frame */ |
| 515 | |
| 516 | return unit * n; |
| 517 | } |
| 518 | |
| 519 | static void dim2_cleanup(void) |
| 520 | { |
| 521 | /* disable MediaLB */ |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 522 | dimcb_io_write(&g.dim2->MLBC0, false << MLBC0_MLBEN_BIT); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 523 | |
| 524 | dim2_clear_ctram(); |
| 525 | |
| 526 | /* disable mlb_int interrupt */ |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 527 | dimcb_io_write(&g.dim2->MIEN, 0); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 528 | |
| 529 | /* clear status for all dma channels */ |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 530 | dimcb_io_write(&g.dim2->ACSR0, 0xFFFFFFFF); |
| 531 | dimcb_io_write(&g.dim2->ACSR1, 0xFFFFFFFF); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 532 | |
| 533 | /* mask interrupts for all channels */ |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 534 | dimcb_io_write(&g.dim2->ACMR0, 0); |
| 535 | dimcb_io_write(&g.dim2->ACMR1, 0); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 536 | } |
| 537 | |
| 538 | static void dim2_initialize(bool enable_6pin, u8 mlb_clock) |
| 539 | { |
| 540 | dim2_cleanup(); |
| 541 | |
| 542 | /* configure and enable MediaLB */ |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 543 | dimcb_io_write(&g.dim2->MLBC0, |
| 544 | enable_6pin << MLBC0_MLBPEN_BIT | |
| 545 | mlb_clock << MLBC0_MLBCLK_SHIFT | |
Christian Gromm | 63c8766 | 2016-06-13 16:24:24 +0200 | [diff] [blame] | 546 | g.fcnt << MLBC0_FCNT_SHIFT | |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 547 | true << MLBC0_MLBEN_BIT); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 548 | |
| 549 | /* activate all HBI channels */ |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 550 | dimcb_io_write(&g.dim2->HCMR0, 0xFFFFFFFF); |
| 551 | dimcb_io_write(&g.dim2->HCMR1, 0xFFFFFFFF); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 552 | |
| 553 | /* enable HBI */ |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 554 | dimcb_io_write(&g.dim2->HCTL, bit_mask(HCTL_EN_BIT)); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 555 | |
| 556 | /* configure DMA */ |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 557 | dimcb_io_write(&g.dim2->ACTL, |
| 558 | ACTL_DMA_MODE_VAL_DMA_MODE_1 << ACTL_DMA_MODE_BIT | |
| 559 | true << ACTL_SCE_BIT); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 560 | } |
| 561 | |
| 562 | static bool dim2_is_mlb_locked(void) |
| 563 | { |
| 564 | u32 const mask0 = bit_mask(MLBC0_MLBLK_BIT); |
| 565 | u32 const mask1 = bit_mask(MLBC1_CLKMERR_BIT) | |
| 566 | bit_mask(MLBC1_LOCKERR_BIT); |
Chaehyun Lim | 5888978 | 2015-11-02 22:59:04 +0900 | [diff] [blame] | 567 | u32 const c1 = dimcb_io_read(&g.dim2->MLBC1); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 568 | u32 const nda_mask = (u32)MLBC1_NDA_MASK << MLBC1_NDA_SHIFT; |
| 569 | |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 570 | dimcb_io_write(&g.dim2->MLBC1, c1 & nda_mask); |
Chaehyun Lim | 5888978 | 2015-11-02 22:59:04 +0900 | [diff] [blame] | 571 | return (dimcb_io_read(&g.dim2->MLBC1) & mask1) == 0 && |
| 572 | (dimcb_io_read(&g.dim2->MLBC0) & mask0) != 0; |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 573 | } |
| 574 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 575 | /* -------------------------------------------------------------------------- */ |
| 576 | /* channel help routines */ |
| 577 | |
| 578 | static inline bool service_channel(u8 ch_addr, u8 idx) |
| 579 | { |
| 580 | u8 const shift = idx * 16; |
| 581 | u32 const adt1 = dim2_read_ctr(ADT + ch_addr, 1); |
Andrey Shvetsov | 9b762fd | 2016-09-15 16:19:05 +0200 | [diff] [blame] | 582 | u32 mask[4] = { 0, 0, 0, 0 }; |
| 583 | u32 adt_w[4] = { 0, 0, 0, 0 }; |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 584 | |
| 585 | if (((adt1 >> (ADT1_DNE_BIT + shift)) & 1) == 0) |
| 586 | return false; |
| 587 | |
Andrey Shvetsov | 9b762fd | 2016-09-15 16:19:05 +0200 | [diff] [blame] | 588 | mask[1] = |
| 589 | bit_mask(ADT1_DNE_BIT + shift) | |
| 590 | bit_mask(ADT1_ERR_BIT + shift) | |
| 591 | bit_mask(ADT1_RDY_BIT + shift); |
| 592 | dim2_write_ctr_mask(ADT + ch_addr, mask, adt_w); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 593 | |
| 594 | /* clear channel status bit */ |
Chaehyun Lim | 1efc456 | 2015-11-02 22:59:03 +0900 | [diff] [blame] | 595 | dimcb_io_write(&g.dim2->ACSR0, bit_mask(ch_addr)); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 596 | |
| 597 | return true; |
| 598 | } |
| 599 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 600 | /* -------------------------------------------------------------------------- */ |
| 601 | /* channel init routines */ |
| 602 | |
| 603 | static void isoc_init(struct dim_channel *ch, u8 ch_addr, u16 packet_length) |
| 604 | { |
| 605 | state_init(&ch->state); |
| 606 | |
| 607 | ch->addr = ch_addr; |
| 608 | |
| 609 | ch->packet_length = packet_length; |
| 610 | ch->bytes_per_frame = 0; |
| 611 | ch->done_sw_buffers_number = 0; |
| 612 | } |
| 613 | |
| 614 | static void sync_init(struct dim_channel *ch, u8 ch_addr, u16 bytes_per_frame) |
| 615 | { |
| 616 | state_init(&ch->state); |
| 617 | |
| 618 | ch->addr = ch_addr; |
| 619 | |
| 620 | ch->packet_length = 0; |
| 621 | ch->bytes_per_frame = bytes_per_frame; |
| 622 | ch->done_sw_buffers_number = 0; |
| 623 | } |
| 624 | |
| 625 | static void channel_init(struct dim_channel *ch, u8 ch_addr) |
| 626 | { |
| 627 | state_init(&ch->state); |
| 628 | |
| 629 | ch->addr = ch_addr; |
| 630 | |
| 631 | ch->packet_length = 0; |
| 632 | ch->bytes_per_frame = 0; |
| 633 | ch->done_sw_buffers_number = 0; |
| 634 | } |
| 635 | |
| 636 | /* returns true if channel interrupt state is cleared */ |
| 637 | static bool channel_service_interrupt(struct dim_channel *ch) |
| 638 | { |
| 639 | struct int_ch_state *const state = &ch->state; |
| 640 | |
| 641 | if (!service_channel(ch->addr, state->idx2)) |
| 642 | return false; |
| 643 | |
| 644 | state->idx2 ^= 1; |
| 645 | state->request_counter++; |
| 646 | return true; |
| 647 | } |
| 648 | |
| 649 | static bool channel_start(struct dim_channel *ch, u32 buf_addr, u16 buf_size) |
| 650 | { |
| 651 | struct int_ch_state *const state = &ch->state; |
| 652 | |
| 653 | if (buf_size <= 0) |
| 654 | return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, "Bad buffer size"); |
| 655 | |
| 656 | if (ch->packet_length == 0 && ch->bytes_per_frame == 0 && |
| 657 | buf_size != norm_ctrl_async_buffer_size(buf_size)) |
| 658 | return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, |
| 659 | "Bad control/async buffer size"); |
| 660 | |
| 661 | if (ch->packet_length && |
| 662 | buf_size != norm_isoc_buffer_size(buf_size, ch->packet_length)) |
| 663 | return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, |
| 664 | "Bad isochronous buffer size"); |
| 665 | |
| 666 | if (ch->bytes_per_frame && |
| 667 | buf_size != norm_sync_buffer_size(buf_size, ch->bytes_per_frame)) |
| 668 | return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, |
| 669 | "Bad synchronous buffer size"); |
| 670 | |
| 671 | if (state->level >= 2u) |
| 672 | return dim_on_error(DIM_ERR_OVERFLOW, "Channel overflow"); |
| 673 | |
| 674 | ++state->level; |
| 675 | |
Andrey Shvetsov | 8f53346 | 2016-09-15 16:19:13 +0200 | [diff] [blame] | 676 | if (ch->addr == g.atx_dbr.ch_addr) |
| 677 | dbrcnt_enq(buf_size); |
| 678 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 679 | if (ch->packet_length || ch->bytes_per_frame) |
| 680 | dim2_start_isoc_sync(ch->addr, state->idx1, buf_addr, buf_size); |
| 681 | else |
Christian Gromm | 9158d33 | 2015-10-15 13:28:51 +0200 | [diff] [blame] | 682 | dim2_start_ctrl_async(ch->addr, state->idx1, buf_addr, |
| 683 | buf_size); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 684 | state->idx1 ^= 1; |
| 685 | |
| 686 | return true; |
| 687 | } |
| 688 | |
| 689 | static u8 channel_service(struct dim_channel *ch) |
| 690 | { |
| 691 | struct int_ch_state *const state = &ch->state; |
| 692 | |
| 693 | if (state->service_counter != state->request_counter) { |
| 694 | state->service_counter++; |
| 695 | if (state->level == 0) |
| 696 | return DIM_ERR_UNDERFLOW; |
| 697 | |
| 698 | --state->level; |
| 699 | ch->done_sw_buffers_number++; |
| 700 | } |
| 701 | |
| 702 | return DIM_NO_ERROR; |
| 703 | } |
| 704 | |
| 705 | static bool channel_detach_buffers(struct dim_channel *ch, u16 buffers_number) |
| 706 | { |
| 707 | if (buffers_number > ch->done_sw_buffers_number) |
| 708 | return dim_on_error(DIM_ERR_UNDERFLOW, "Channel underflow"); |
| 709 | |
| 710 | ch->done_sw_buffers_number -= buffers_number; |
| 711 | return true; |
| 712 | } |
| 713 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 714 | /* -------------------------------------------------------------------------- */ |
| 715 | /* API */ |
| 716 | |
Christian Gromm | 63c8766 | 2016-06-13 16:24:24 +0200 | [diff] [blame] | 717 | u8 dim_startup(struct dim2_regs __iomem *dim_base_address, u32 mlb_clock, |
| 718 | u32 fcnt) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 719 | { |
| 720 | g.dim_is_initialized = false; |
| 721 | |
| 722 | if (!dim_base_address) |
| 723 | return DIM_INIT_ERR_DIM_ADDR; |
| 724 | |
| 725 | /* MediaLB clock: 0 - 256 fs, 1 - 512 fs, 2 - 1024 fs, 3 - 2048 fs */ |
| 726 | /* MediaLB clock: 4 - 3072 fs, 5 - 4096 fs, 6 - 6144 fs, 7 - 8192 fs */ |
| 727 | if (mlb_clock >= 8) |
| 728 | return DIM_INIT_ERR_MLB_CLOCK; |
| 729 | |
Christian Gromm | 63c8766 | 2016-06-13 16:24:24 +0200 | [diff] [blame] | 730 | if (fcnt > MLBC0_FCNT_MAX_VAL) |
| 731 | return DIM_INIT_ERR_MLB_CLOCK; |
| 732 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 733 | g.dim2 = dim_base_address; |
Christian Gromm | 63c8766 | 2016-06-13 16:24:24 +0200 | [diff] [blame] | 734 | g.fcnt = fcnt; |
Christian Gromm | c6c3f34 | 2015-10-21 17:50:42 +0200 | [diff] [blame] | 735 | g.dbr_map[0] = 0; |
| 736 | g.dbr_map[1] = 0; |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 737 | |
| 738 | dim2_initialize(mlb_clock >= 3, mlb_clock); |
| 739 | |
| 740 | g.dim_is_initialized = true; |
| 741 | |
| 742 | return DIM_NO_ERROR; |
| 743 | } |
| 744 | |
Chaehyun Lim | 50a45b1 | 2015-10-29 16:44:12 +0900 | [diff] [blame] | 745 | void dim_shutdown(void) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 746 | { |
| 747 | g.dim_is_initialized = false; |
| 748 | dim2_cleanup(); |
| 749 | } |
| 750 | |
Chaehyun Lim | b724207 | 2015-11-02 22:59:01 +0900 | [diff] [blame] | 751 | bool dim_get_lock_state(void) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 752 | { |
| 753 | return dim2_is_mlb_locked(); |
| 754 | } |
| 755 | |
| 756 | static u8 init_ctrl_async(struct dim_channel *ch, u8 type, u8 is_tx, |
| 757 | u16 ch_address, u16 hw_buffer_size) |
| 758 | { |
| 759 | if (!g.dim_is_initialized || !ch) |
| 760 | return DIM_ERR_DRIVER_NOT_INITIALIZED; |
| 761 | |
| 762 | if (!check_channel_address(ch_address)) |
| 763 | return DIM_INIT_ERR_CHANNEL_ADDRESS; |
| 764 | |
Andrey Shvetsov | a85ee2a | 2016-09-15 16:19:07 +0200 | [diff] [blame] | 765 | ch->dbr_size = ROUND_UP_TO(hw_buffer_size, DBR_BLOCK_SIZE); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 766 | ch->dbr_addr = alloc_dbr(ch->dbr_size); |
| 767 | if (ch->dbr_addr >= DBR_SIZE) |
| 768 | return DIM_INIT_ERR_OUT_OF_MEMORY; |
| 769 | |
| 770 | channel_init(ch, ch_address / 2); |
| 771 | |
| 772 | dim2_configure_channel(ch->addr, type, is_tx, |
| 773 | ch->dbr_addr, ch->dbr_size, 0, false); |
| 774 | |
| 775 | return DIM_NO_ERROR; |
| 776 | } |
| 777 | |
Andrey Shvetsov | 8f53346 | 2016-09-15 16:19:13 +0200 | [diff] [blame] | 778 | void dim_service_mlb_int_irq(void) |
| 779 | { |
| 780 | dimcb_io_write(&g.dim2->MS0, 0); |
| 781 | dimcb_io_write(&g.dim2->MS1, 0); |
| 782 | } |
| 783 | |
Chaehyun Lim | c64c6073 | 2015-11-02 22:59:05 +0900 | [diff] [blame] | 784 | u16 dim_norm_ctrl_async_buffer_size(u16 buf_size) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 785 | { |
| 786 | return norm_ctrl_async_buffer_size(buf_size); |
| 787 | } |
| 788 | |
| 789 | /** |
| 790 | * Retrieves maximal possible correct buffer size for isochronous data type |
| 791 | * conform to given packet length and not bigger than given buffer size. |
| 792 | * |
| 793 | * Returns non-zero correct buffer size or zero by error. |
| 794 | */ |
Chaehyun Lim | e302ca4 | 2015-11-02 22:59:06 +0900 | [diff] [blame] | 795 | u16 dim_norm_isoc_buffer_size(u16 buf_size, u16 packet_length) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 796 | { |
| 797 | if (!check_packet_length(packet_length)) |
| 798 | return 0; |
| 799 | |
| 800 | return norm_isoc_buffer_size(buf_size, packet_length); |
| 801 | } |
| 802 | |
| 803 | /** |
| 804 | * Retrieves maximal possible correct buffer size for synchronous data type |
| 805 | * conform to given bytes per frame and not bigger than given buffer size. |
| 806 | * |
| 807 | * Returns non-zero correct buffer size or zero by error. |
| 808 | */ |
Chaehyun Lim | aff1924 | 2015-11-02 22:59:07 +0900 | [diff] [blame] | 809 | u16 dim_norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 810 | { |
| 811 | if (!check_bytes_per_frame(bytes_per_frame)) |
| 812 | return 0; |
| 813 | |
| 814 | return norm_sync_buffer_size(buf_size, bytes_per_frame); |
| 815 | } |
| 816 | |
Chaehyun Lim | a3f3e92 | 2015-11-02 22:59:08 +0900 | [diff] [blame] | 817 | u8 dim_init_control(struct dim_channel *ch, u8 is_tx, u16 ch_address, |
| 818 | u16 max_buffer_size) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 819 | { |
| 820 | return init_ctrl_async(ch, CAT_CT_VAL_CONTROL, is_tx, ch_address, |
Christian Gromm | c31d9d1 | 2015-09-28 17:18:40 +0200 | [diff] [blame] | 821 | max_buffer_size); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 822 | } |
| 823 | |
Chaehyun Lim | 2630315 | 2015-11-02 22:59:09 +0900 | [diff] [blame] | 824 | u8 dim_init_async(struct dim_channel *ch, u8 is_tx, u16 ch_address, |
| 825 | u16 max_buffer_size) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 826 | { |
Andrey Shvetsov | 8f53346 | 2016-09-15 16:19:13 +0200 | [diff] [blame] | 827 | u8 ret = init_ctrl_async(ch, CAT_CT_VAL_ASYNC, is_tx, ch_address, |
| 828 | max_buffer_size); |
| 829 | |
| 830 | if (is_tx && !g.atx_dbr.ch_addr) { |
| 831 | g.atx_dbr.ch_addr = ch->addr; |
| 832 | dbrcnt_init(ch->addr, ch->dbr_size); |
| 833 | dimcb_io_write(&g.dim2->MIEN, bit_mask(20)); |
| 834 | } |
| 835 | |
| 836 | return ret; |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 837 | } |
| 838 | |
Chaehyun Lim | f138317 | 2015-11-02 22:59:10 +0900 | [diff] [blame] | 839 | u8 dim_init_isoc(struct dim_channel *ch, u8 is_tx, u16 ch_address, |
| 840 | u16 packet_length) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 841 | { |
| 842 | if (!g.dim_is_initialized || !ch) |
| 843 | return DIM_ERR_DRIVER_NOT_INITIALIZED; |
| 844 | |
| 845 | if (!check_channel_address(ch_address)) |
| 846 | return DIM_INIT_ERR_CHANNEL_ADDRESS; |
| 847 | |
| 848 | if (!check_packet_length(packet_length)) |
| 849 | return DIM_ERR_BAD_CONFIG; |
| 850 | |
| 851 | ch->dbr_size = packet_length * ISOC_DBR_FACTOR; |
| 852 | ch->dbr_addr = alloc_dbr(ch->dbr_size); |
| 853 | if (ch->dbr_addr >= DBR_SIZE) |
| 854 | return DIM_INIT_ERR_OUT_OF_MEMORY; |
| 855 | |
| 856 | isoc_init(ch, ch_address / 2, packet_length); |
| 857 | |
| 858 | dim2_configure_channel(ch->addr, CAT_CT_VAL_ISOC, is_tx, ch->dbr_addr, |
| 859 | ch->dbr_size, packet_length, false); |
| 860 | |
| 861 | return DIM_NO_ERROR; |
| 862 | } |
| 863 | |
Chaehyun Lim | 10e5efb | 2015-11-02 22:59:11 +0900 | [diff] [blame] | 864 | u8 dim_init_sync(struct dim_channel *ch, u8 is_tx, u16 ch_address, |
| 865 | u16 bytes_per_frame) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 866 | { |
Christian Gromm | 63c8766 | 2016-06-13 16:24:24 +0200 | [diff] [blame] | 867 | u16 bd_factor = g.fcnt + 2; |
| 868 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 869 | if (!g.dim_is_initialized || !ch) |
| 870 | return DIM_ERR_DRIVER_NOT_INITIALIZED; |
| 871 | |
| 872 | if (!check_channel_address(ch_address)) |
| 873 | return DIM_INIT_ERR_CHANNEL_ADDRESS; |
| 874 | |
| 875 | if (!check_bytes_per_frame(bytes_per_frame)) |
| 876 | return DIM_ERR_BAD_CONFIG; |
| 877 | |
Christian Gromm | 63c8766 | 2016-06-13 16:24:24 +0200 | [diff] [blame] | 878 | ch->dbr_size = bytes_per_frame << bd_factor; |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 879 | ch->dbr_addr = alloc_dbr(ch->dbr_size); |
| 880 | if (ch->dbr_addr >= DBR_SIZE) |
| 881 | return DIM_INIT_ERR_OUT_OF_MEMORY; |
| 882 | |
| 883 | sync_init(ch, ch_address / 2, bytes_per_frame); |
| 884 | |
Christian Gromm | 9fe7aea | 2016-08-18 16:58:46 +0200 | [diff] [blame] | 885 | dim2_clear_dbr(ch->dbr_addr, ch->dbr_size); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 886 | dim2_configure_channel(ch->addr, CAT_CT_VAL_SYNC, is_tx, |
| 887 | ch->dbr_addr, ch->dbr_size, 0, true); |
| 888 | |
| 889 | return DIM_NO_ERROR; |
| 890 | } |
| 891 | |
Chaehyun Lim | a5e4d89 | 2015-11-02 22:59:12 +0900 | [diff] [blame] | 892 | u8 dim_destroy_channel(struct dim_channel *ch) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 893 | { |
| 894 | if (!g.dim_is_initialized || !ch) |
| 895 | return DIM_ERR_DRIVER_NOT_INITIALIZED; |
| 896 | |
Andrey Shvetsov | 8f53346 | 2016-09-15 16:19:13 +0200 | [diff] [blame] | 897 | if (ch->addr == g.atx_dbr.ch_addr) { |
| 898 | dimcb_io_write(&g.dim2->MIEN, 0); |
| 899 | g.atx_dbr.ch_addr = 0; |
| 900 | } |
| 901 | |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 902 | dim2_clear_channel(ch->addr); |
| 903 | if (ch->dbr_addr < DBR_SIZE) |
| 904 | free_dbr(ch->dbr_addr, ch->dbr_size); |
| 905 | ch->dbr_addr = DBR_SIZE; |
| 906 | |
| 907 | return DIM_NO_ERROR; |
| 908 | } |
| 909 | |
Andrey Shvetsov | 055f1d1 | 2016-09-15 16:19:09 +0200 | [diff] [blame] | 910 | void dim_service_ahb_int_irq(struct dim_channel *const *channels) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 911 | { |
| 912 | bool state_changed; |
| 913 | |
| 914 | if (!g.dim_is_initialized) { |
| 915 | dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, |
| 916 | "DIM is not initialized"); |
| 917 | return; |
| 918 | } |
| 919 | |
| 920 | if (!channels) { |
| 921 | dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, "Bad channels"); |
| 922 | return; |
| 923 | } |
| 924 | |
| 925 | /* |
Christian Gromm | 9158d33 | 2015-10-15 13:28:51 +0200 | [diff] [blame] | 926 | * Use while-loop and a flag to make sure the age is changed back at |
| 927 | * least once, otherwise the interrupt may never come if CPU generates |
| 928 | * interrupt on changing age. |
| 929 | * This cycle runs not more than number of channels, because |
| 930 | * channel_service_interrupt() routine doesn't start the channel again. |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 931 | */ |
| 932 | do { |
| 933 | struct dim_channel *const *ch = channels; |
| 934 | |
| 935 | state_changed = false; |
| 936 | |
| 937 | while (*ch) { |
| 938 | state_changed |= channel_service_interrupt(*ch); |
| 939 | ++ch; |
| 940 | } |
| 941 | } while (state_changed); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 942 | } |
| 943 | |
Chaehyun Lim | 0d08d54 | 2015-11-02 22:59:14 +0900 | [diff] [blame] | 944 | u8 dim_service_channel(struct dim_channel *ch) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 945 | { |
| 946 | if (!g.dim_is_initialized || !ch) |
| 947 | return DIM_ERR_DRIVER_NOT_INITIALIZED; |
| 948 | |
| 949 | return channel_service(ch); |
| 950 | } |
| 951 | |
Chaehyun Lim | 60d5f66 | 2015-11-02 22:59:16 +0900 | [diff] [blame] | 952 | struct dim_ch_state_t *dim_get_channel_state(struct dim_channel *ch, |
| 953 | struct dim_ch_state_t *state_ptr) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 954 | { |
| 955 | if (!ch || !state_ptr) |
Tomas Melin | 910bf1e | 2015-08-09 17:08:41 +0300 | [diff] [blame] | 956 | return NULL; |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 957 | |
| 958 | state_ptr->ready = ch->state.level < 2; |
| 959 | state_ptr->done_buffers = ch->done_sw_buffers_number; |
| 960 | |
| 961 | return state_ptr; |
| 962 | } |
| 963 | |
Chaehyun Lim | c904ffd | 2015-11-02 22:59:17 +0900 | [diff] [blame] | 964 | bool dim_enqueue_buffer(struct dim_channel *ch, u32 buffer_addr, |
| 965 | u16 buffer_size) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 966 | { |
| 967 | if (!ch) |
Christian Gromm | 9158d33 | 2015-10-15 13:28:51 +0200 | [diff] [blame] | 968 | return dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, |
| 969 | "Bad channel"); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 970 | |
| 971 | return channel_start(ch, buffer_addr, buffer_size); |
| 972 | } |
| 973 | |
Chaehyun Lim | 38c3854 | 2015-10-29 16:44:13 +0900 | [diff] [blame] | 974 | bool dim_detach_buffers(struct dim_channel *ch, u16 buffers_number) |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 975 | { |
| 976 | if (!ch) |
Christian Gromm | 9158d33 | 2015-10-15 13:28:51 +0200 | [diff] [blame] | 977 | return dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, |
| 978 | "Bad channel"); |
Christian Gromm | ba3d7dd | 2015-07-24 16:11:53 +0200 | [diff] [blame] | 979 | |
| 980 | return channel_detach_buffers(ch, buffers_number); |
| 981 | } |