Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 1 | #ifndef DDK750_DISPLAY_H__ |
| 2 | #define DDK750_DISPLAY_H__ |
| 3 | |
| 4 | /* panel path select |
Elizabeth Ferdman | 35e4d8c | 2016-09-28 14:33:51 -0700 | [diff] [blame] | 5 | * 80000[29:28] |
| 6 | */ |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 7 | |
| 8 | #define PNL_2_OFFSET 0 |
| 9 | #define PNL_2_MASK (3 << PNL_2_OFFSET) |
| 10 | #define PNL_2_USAGE (PNL_2_MASK << 16) |
Rehas Sachdeva | f1f5b43 | 2016-09-19 19:26:32 +0530 | [diff] [blame] | 11 | #define PNL_2_PRI ((0 << PNL_2_OFFSET) | PNL_2_USAGE) |
| 12 | #define PNL_2_SEC ((2 << PNL_2_OFFSET) | PNL_2_USAGE) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 13 | |
| 14 | |
| 15 | /* primary timing & plane enable bit |
Elizabeth Ferdman | 35e4d8c | 2016-09-28 14:33:51 -0700 | [diff] [blame] | 16 | * 1: 80000[8] & 80000[2] on |
| 17 | * 0: both off |
| 18 | */ |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 19 | #define PRI_TP_OFFSET 4 |
Amitoj Kaur Chawla | a5eabae | 2015-10-17 21:20:00 +0530 | [diff] [blame] | 20 | #define PRI_TP_MASK BIT(PRI_TP_OFFSET) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 21 | #define PRI_TP_USAGE (PRI_TP_MASK << 16) |
Rehas Sachdeva | f1f5b43 | 2016-09-19 19:26:32 +0530 | [diff] [blame] | 22 | #define PRI_TP_ON ((0x1 << PRI_TP_OFFSET) | PRI_TP_USAGE) |
| 23 | #define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET) | PRI_TP_USAGE) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 24 | |
| 25 | |
| 26 | /* panel sequency status |
Elizabeth Ferdman | 35e4d8c | 2016-09-28 14:33:51 -0700 | [diff] [blame] | 27 | * 80000[27:24] |
| 28 | */ |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 29 | #define PNL_SEQ_OFFSET 6 |
Amitoj Kaur Chawla | a5eabae | 2015-10-17 21:20:00 +0530 | [diff] [blame] | 30 | #define PNL_SEQ_MASK BIT(PNL_SEQ_OFFSET) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 31 | #define PNL_SEQ_USAGE (PNL_SEQ_MASK << 16) |
Rehas Sachdeva | f1f5b43 | 2016-09-19 19:26:32 +0530 | [diff] [blame] | 32 | #define PNL_SEQ_ON (BIT(PNL_SEQ_OFFSET) | PNL_SEQ_USAGE) |
| 33 | #define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET) | PNL_SEQ_USAGE) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 34 | |
| 35 | /* dual digital output |
Elizabeth Ferdman | 35e4d8c | 2016-09-28 14:33:51 -0700 | [diff] [blame] | 36 | * 80000[19] |
| 37 | */ |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 38 | #define DUAL_TFT_OFFSET 8 |
Amitoj Kaur Chawla | a5eabae | 2015-10-17 21:20:00 +0530 | [diff] [blame] | 39 | #define DUAL_TFT_MASK BIT(DUAL_TFT_OFFSET) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 40 | #define DUAL_TFT_USAGE (DUAL_TFT_MASK << 16) |
Rehas Sachdeva | f1f5b43 | 2016-09-19 19:26:32 +0530 | [diff] [blame] | 41 | #define DUAL_TFT_ON (BIT(DUAL_TFT_OFFSET) | DUAL_TFT_USAGE) |
| 42 | #define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET) | DUAL_TFT_USAGE) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 43 | |
| 44 | /* secondary timing & plane enable bit |
Elizabeth Ferdman | 35e4d8c | 2016-09-28 14:33:51 -0700 | [diff] [blame] | 45 | * 1:80200[8] & 80200[2] on |
| 46 | * 0: both off |
| 47 | */ |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 48 | #define SEC_TP_OFFSET 5 |
Amitoj Kaur Chawla | a5eabae | 2015-10-17 21:20:00 +0530 | [diff] [blame] | 49 | #define SEC_TP_MASK BIT(SEC_TP_OFFSET) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 50 | #define SEC_TP_USAGE (SEC_TP_MASK << 16) |
Rehas Sachdeva | f1f5b43 | 2016-09-19 19:26:32 +0530 | [diff] [blame] | 51 | #define SEC_TP_ON ((0x1 << SEC_TP_OFFSET) | SEC_TP_USAGE) |
| 52 | #define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET) | SEC_TP_USAGE) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 53 | |
| 54 | /* crt path select |
Elizabeth Ferdman | 35e4d8c | 2016-09-28 14:33:51 -0700 | [diff] [blame] | 55 | * 80200[19:18] |
| 56 | */ |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 57 | #define CRT_2_OFFSET 2 |
| 58 | #define CRT_2_MASK (3 << CRT_2_OFFSET) |
| 59 | #define CRT_2_USAGE (CRT_2_MASK << 16) |
Rehas Sachdeva | f1f5b43 | 2016-09-19 19:26:32 +0530 | [diff] [blame] | 60 | #define CRT_2_PRI ((0x0 << CRT_2_OFFSET) | CRT_2_USAGE) |
| 61 | #define CRT_2_SEC ((0x2 << CRT_2_OFFSET) | CRT_2_USAGE) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 62 | |
| 63 | |
| 64 | /* DAC affect both DVI and DSUB |
Elizabeth Ferdman | 35e4d8c | 2016-09-28 14:33:51 -0700 | [diff] [blame] | 65 | * 4[20] |
| 66 | */ |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 67 | #define DAC_OFFSET 7 |
Amitoj Kaur Chawla | a5eabae | 2015-10-17 21:20:00 +0530 | [diff] [blame] | 68 | #define DAC_MASK BIT(DAC_OFFSET) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 69 | #define DAC_USAGE (DAC_MASK << 16) |
Rehas Sachdeva | f1f5b43 | 2016-09-19 19:26:32 +0530 | [diff] [blame] | 70 | #define DAC_ON ((0x0 << DAC_OFFSET) | DAC_USAGE) |
| 71 | #define DAC_OFF ((0x1 << DAC_OFFSET) | DAC_USAGE) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 72 | |
| 73 | /* DPMS only affect D-SUB head |
Elizabeth Ferdman | 35e4d8c | 2016-09-28 14:33:51 -0700 | [diff] [blame] | 74 | * 0[31:30] |
| 75 | */ |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 76 | #define DPMS_OFFSET 9 |
| 77 | #define DPMS_MASK (3 << DPMS_OFFSET) |
| 78 | #define DPMS_USAGE (DPMS_MASK << 16) |
Rehas Sachdeva | f1f5b43 | 2016-09-19 19:26:32 +0530 | [diff] [blame] | 79 | #define DPMS_OFF ((3 << DPMS_OFFSET) | DPMS_USAGE) |
| 80 | #define DPMS_ON ((0 << DPMS_OFFSET) | DPMS_USAGE) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 81 | |
| 82 | |
| 83 | |
Elizabeth Ferdman | 35e4d8c | 2016-09-28 14:33:51 -0700 | [diff] [blame] | 84 | /* LCD1 means panel path TFT1 & panel path DVI (so enable DAC) |
| 85 | * CRT means crt path DSUB |
| 86 | */ |
Juston Li | b63f3dc | 2015-07-14 21:14:37 -0700 | [diff] [blame] | 87 | typedef enum _disp_output_t { |
Rehas Sachdeva | f1f5b43 | 2016-09-19 19:26:32 +0530 | [diff] [blame] | 88 | do_LCD1_PRI = PNL_2_PRI | PRI_TP_ON | PNL_SEQ_ON | DAC_ON, |
| 89 | do_LCD1_SEC = PNL_2_SEC | SEC_TP_ON | PNL_SEQ_ON | DAC_ON, |
| 90 | do_LCD2_PRI = CRT_2_PRI | PRI_TP_ON | DUAL_TFT_ON, |
| 91 | do_LCD2_SEC = CRT_2_SEC | SEC_TP_ON | DUAL_TFT_ON, |
Elizabeth Ferdman | 35e4d8c | 2016-09-28 14:33:51 -0700 | [diff] [blame] | 92 | /* do_DSUB_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON|DAC_ON, |
| 93 | * do_DSUB_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON|DAC_ON, |
| 94 | */ |
Rehas Sachdeva | f1f5b43 | 2016-09-19 19:26:32 +0530 | [diff] [blame] | 95 | do_CRT_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON | DAC_ON, |
| 96 | do_CRT_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON | DAC_ON, |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 97 | } |
| 98 | disp_output_t; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 99 | |
| 100 | void ddk750_setLogicalDispOut(disp_output_t); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 101 | |
| 102 | #endif |