Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 1 | /* |
| 2 | * bxt-sst.c - DSP library functions for BXT platform |
| 3 | * |
| 4 | * Copyright (C) 2015-16 Intel Corp |
| 5 | * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> |
| 6 | * Jeeja KP <jeeja.kp@intel.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but |
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/delay.h> |
| 20 | #include <linux/firmware.h> |
| 21 | #include <linux/device.h> |
| 22 | |
| 23 | #include "../common/sst-dsp.h" |
| 24 | #include "../common/sst-dsp-priv.h" |
| 25 | #include "skl-sst-ipc.h" |
Ramesh Babu | 1ef015e | 2016-07-26 18:06:48 +0530 | [diff] [blame] | 26 | #include "skl-tplg-interface.h" |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 27 | |
| 28 | #define BXT_BASEFW_TIMEOUT 3000 |
| 29 | #define BXT_INIT_TIMEOUT 500 |
| 30 | #define BXT_IPC_PURGE_FW 0x01004000 |
| 31 | |
| 32 | #define BXT_ROM_INIT 0x5 |
| 33 | #define BXT_ADSP_SRAM0_BASE 0x80000 |
| 34 | |
| 35 | /* Firmware status window */ |
| 36 | #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE |
| 37 | #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4) |
| 38 | |
| 39 | #define BXT_ADSP_SRAM1_BASE 0xA0000 |
| 40 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 41 | #define BXT_INSTANCE_ID 0 |
| 42 | #define BXT_BASE_FW_MODULE_ID 0 |
| 43 | |
Ramesh Babu | 1ef015e | 2016-07-26 18:06:48 +0530 | [diff] [blame] | 44 | #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000 |
| 45 | |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 46 | static unsigned int bxt_get_errorcode(struct sst_dsp *ctx) |
| 47 | { |
| 48 | return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE); |
| 49 | } |
| 50 | |
Ramesh Babu | 1ef015e | 2016-07-26 18:06:48 +0530 | [diff] [blame] | 51 | static int |
| 52 | bxt_load_library(struct sst_dsp *ctx, struct skl_dfw_manifest *minfo) |
| 53 | { |
| 54 | struct snd_dma_buffer dmab; |
| 55 | struct skl_sst *skl = ctx->thread_context; |
| 56 | const struct firmware *fw = NULL; |
| 57 | struct firmware stripped_fw; |
| 58 | int ret = 0, i, dma_id, stream_tag; |
| 59 | |
| 60 | /* library indices start from 1 to N. 0 represents base FW */ |
| 61 | for (i = 1; i < minfo->lib_count; i++) { |
| 62 | ret = request_firmware(&fw, minfo->lib[i].name, ctx->dev); |
| 63 | if (ret < 0) { |
| 64 | dev_err(ctx->dev, "Request lib %s failed:%d\n", |
| 65 | minfo->lib[i].name, ret); |
| 66 | return ret; |
| 67 | } |
| 68 | |
| 69 | if (skl->is_first_boot) { |
| 70 | ret = snd_skl_parse_uuids(ctx, fw, |
| 71 | BXT_ADSP_FW_BIN_HDR_OFFSET, i); |
| 72 | if (ret < 0) |
| 73 | goto load_library_failed; |
| 74 | } |
| 75 | |
| 76 | stripped_fw.data = fw->data; |
| 77 | stripped_fw.size = fw->size; |
| 78 | skl_dsp_strip_extended_manifest(&stripped_fw); |
| 79 | |
| 80 | stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, |
| 81 | stripped_fw.size, &dmab); |
| 82 | if (stream_tag <= 0) { |
| 83 | dev_err(ctx->dev, "Lib prepare DMA err: %x\n", |
| 84 | stream_tag); |
| 85 | ret = stream_tag; |
| 86 | goto load_library_failed; |
| 87 | } |
| 88 | |
| 89 | dma_id = stream_tag - 1; |
| 90 | memcpy(dmab.area, stripped_fw.data, stripped_fw.size); |
| 91 | |
| 92 | ctx->dsp_ops.trigger(ctx->dev, true, stream_tag); |
| 93 | ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i); |
| 94 | if (ret < 0) |
| 95 | dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n", |
| 96 | minfo->lib[i].name, ret); |
| 97 | |
| 98 | ctx->dsp_ops.trigger(ctx->dev, false, stream_tag); |
| 99 | ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag); |
| 100 | release_firmware(fw); |
| 101 | fw = NULL; |
| 102 | } |
| 103 | |
| 104 | return ret; |
| 105 | |
| 106 | load_library_failed: |
| 107 | release_firmware(fw); |
| 108 | return ret; |
| 109 | } |
| 110 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 111 | /* |
| 112 | * First boot sequence has some extra steps. Core 0 waits for power |
| 113 | * status on core 1, so power up core 1 also momentarily, keep it in |
| 114 | * reset/stall and then turn it off |
| 115 | */ |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 116 | static int sst_bxt_prepare_fw(struct sst_dsp *ctx, |
| 117 | const void *fwdata, u32 fwsize) |
| 118 | { |
| 119 | int stream_tag, ret, i; |
| 120 | u32 reg; |
| 121 | |
| 122 | stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab); |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 123 | if (stream_tag <= 0) { |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 124 | dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n", |
| 125 | stream_tag); |
| 126 | return stream_tag; |
| 127 | } |
| 128 | |
| 129 | ctx->dsp_ops.stream_tag = stream_tag; |
| 130 | memcpy(ctx->dmab.area, fwdata, fwsize); |
| 131 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 132 | /* Step 1: Power up core 0 and core1 */ |
| 133 | ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK | |
| 134 | SKL_DSP_CORE_MASK(1)); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 135 | if (ret < 0) { |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 136 | dev_err(ctx->dev, "dsp core0/1 power up failed\n"); |
Senthilnathan Veppur | 2023576 | 2016-06-13 17:59:02 +0530 | [diff] [blame] | 137 | goto base_fw_load_failed; |
| 138 | } |
| 139 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 140 | /* Step 2: Purge FW request */ |
Senthilnathan Veppur | 2023576 | 2016-06-13 17:59:02 +0530 | [diff] [blame] | 141 | sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY | |
| 142 | (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9))); |
| 143 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 144 | /* Step 3: Unset core0 reset state & unstall/run core0 */ |
Jayachandran B | 052f103 | 2016-06-21 10:17:41 +0530 | [diff] [blame] | 145 | ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK); |
Senthilnathan Veppur | 2023576 | 2016-06-13 17:59:02 +0530 | [diff] [blame] | 146 | if (ret < 0) { |
| 147 | dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 148 | ret = -EIO; |
| 149 | goto base_fw_load_failed; |
| 150 | } |
| 151 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 152 | /* Step 4: Wait for DONE Bit */ |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 153 | for (i = BXT_INIT_TIMEOUT; i > 0; --i) { |
| 154 | reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE); |
| 155 | |
| 156 | if (reg & SKL_ADSP_REG_HIPCIE_DONE) { |
| 157 | sst_dsp_shim_update_bits_forced(ctx, |
| 158 | SKL_ADSP_REG_HIPCIE, |
| 159 | SKL_ADSP_REG_HIPCIE_DONE, |
| 160 | SKL_ADSP_REG_HIPCIE_DONE); |
| 161 | break; |
| 162 | } |
| 163 | mdelay(1); |
| 164 | } |
| 165 | if (!i) { |
| 166 | dev_info(ctx->dev, "Waiting for HIPCIE done, reg: 0x%x\n", reg); |
| 167 | sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCIE, |
| 168 | SKL_ADSP_REG_HIPCIE_DONE, |
| 169 | SKL_ADSP_REG_HIPCIE_DONE); |
| 170 | } |
| 171 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 172 | /* Step 5: power down core1 */ |
| 173 | ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); |
| 174 | if (ret < 0) { |
| 175 | dev_err(ctx->dev, "dsp core1 power down failed\n"); |
| 176 | goto base_fw_load_failed; |
| 177 | } |
| 178 | |
| 179 | /* Step 6: Enable Interrupt */ |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 180 | skl_ipc_int_enable(ctx); |
| 181 | skl_ipc_op_int_enable(ctx); |
| 182 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 183 | /* Step 7: Wait for ROM init */ |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 184 | for (i = BXT_INIT_TIMEOUT; i > 0; --i) { |
| 185 | if (SKL_FW_INIT == |
| 186 | (sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) & |
| 187 | SKL_FW_STS_MASK)) { |
| 188 | |
| 189 | dev_info(ctx->dev, "ROM loaded, continue FW loading\n"); |
| 190 | break; |
| 191 | } |
| 192 | mdelay(1); |
| 193 | } |
| 194 | if (!i) { |
| 195 | dev_err(ctx->dev, "Timeout for ROM init, HIPCIE: 0x%x\n", reg); |
| 196 | ret = -EIO; |
| 197 | goto base_fw_load_failed; |
| 198 | } |
| 199 | |
| 200 | return ret; |
| 201 | |
| 202 | base_fw_load_failed: |
| 203 | ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag); |
Jayachandran B | 052f103 | 2016-06-21 10:17:41 +0530 | [diff] [blame] | 204 | skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); |
Senthilnathan Veppur | c787226 | 2016-07-14 09:05:25 +0530 | [diff] [blame] | 205 | skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 206 | return ret; |
| 207 | } |
| 208 | |
| 209 | static int sst_transfer_fw_host_dma(struct sst_dsp *ctx) |
| 210 | { |
| 211 | int ret; |
| 212 | |
| 213 | ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag); |
| 214 | ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, |
| 215 | BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot"); |
| 216 | |
| 217 | ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag); |
| 218 | ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag); |
| 219 | |
| 220 | return ret; |
| 221 | } |
| 222 | |
| 223 | static int bxt_load_base_firmware(struct sst_dsp *ctx) |
| 224 | { |
Vinod Koul | bf242d1 | 2016-05-30 17:42:58 +0530 | [diff] [blame] | 225 | struct firmware stripped_fw; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 226 | struct skl_sst *skl = ctx->thread_context; |
| 227 | int ret; |
| 228 | |
Vinod Koul | fdfa82e | 2016-05-30 17:42:56 +0530 | [diff] [blame] | 229 | ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 230 | if (ret < 0) { |
| 231 | dev_err(ctx->dev, "Request firmware failed %d\n", ret); |
| 232 | goto sst_load_base_firmware_failed; |
| 233 | } |
| 234 | |
Vinod Koul | bf242d1 | 2016-05-30 17:42:58 +0530 | [diff] [blame] | 235 | /* check for extended manifest */ |
| 236 | if (ctx->fw == NULL) |
| 237 | goto sst_load_base_firmware_failed; |
| 238 | |
Vinod Koul | 0bdd6d8 | 2016-07-26 18:06:46 +0530 | [diff] [blame] | 239 | /* prase uuids on first boot */ |
| 240 | if (skl->is_first_boot) { |
| 241 | ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0); |
| 242 | if (ret < 0) |
| 243 | goto sst_load_base_firmware_failed; |
| 244 | } |
Vinod Koul | bf242d1 | 2016-05-30 17:42:58 +0530 | [diff] [blame] | 245 | |
| 246 | stripped_fw.data = ctx->fw->data; |
| 247 | stripped_fw.size = ctx->fw->size; |
| 248 | skl_dsp_strip_extended_manifest(&stripped_fw); |
| 249 | |
| 250 | ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 251 | /* Retry Enabling core and ROM load. Retry seemed to help */ |
| 252 | if (ret < 0) { |
Vinod Koul | bf242d1 | 2016-05-30 17:42:58 +0530 | [diff] [blame] | 253 | ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 254 | if (ret < 0) { |
Senthilnathan Veppur | 2023576 | 2016-06-13 17:59:02 +0530 | [diff] [blame] | 255 | dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", |
| 256 | sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), |
| 257 | sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); |
| 258 | |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 259 | dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret); |
| 260 | goto sst_load_base_firmware_failed; |
| 261 | } |
| 262 | } |
| 263 | |
| 264 | ret = sst_transfer_fw_host_dma(ctx); |
| 265 | if (ret < 0) { |
| 266 | dev_err(ctx->dev, "Transfer firmware failed %d\n", ret); |
| 267 | dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n", |
| 268 | sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), |
| 269 | sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); |
| 270 | |
Jayachandran B | 052f103 | 2016-06-21 10:17:41 +0530 | [diff] [blame] | 271 | skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 272 | } else { |
| 273 | dev_dbg(ctx->dev, "Firmware download successful\n"); |
| 274 | ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, |
| 275 | msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); |
| 276 | if (ret == 0) { |
| 277 | dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n"); |
Jayachandran B | 052f103 | 2016-06-21 10:17:41 +0530 | [diff] [blame] | 278 | skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 279 | ret = -EIO; |
| 280 | } else { |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 281 | ret = 0; |
Jayachandran B | 1665c17 | 2016-06-13 17:59:01 +0530 | [diff] [blame] | 282 | skl->fw_loaded = true; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 283 | } |
| 284 | } |
| 285 | |
| 286 | sst_load_base_firmware_failed: |
Vinod Koul | fdfa82e | 2016-05-30 17:42:56 +0530 | [diff] [blame] | 287 | release_firmware(ctx->fw); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 288 | return ret; |
| 289 | } |
| 290 | |
Jayachandran B | 052f103 | 2016-06-21 10:17:41 +0530 | [diff] [blame] | 291 | static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id) |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 292 | { |
| 293 | struct skl_sst *skl = ctx->thread_context; |
| 294 | int ret; |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 295 | struct skl_ipc_dxstate_info dx; |
| 296 | unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); |
Ramesh Babu | 1ef015e | 2016-07-26 18:06:48 +0530 | [diff] [blame] | 297 | struct skl_dfw_manifest *minfo = &skl->manifest; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 298 | |
Jayachandran B | 1665c17 | 2016-06-13 17:59:01 +0530 | [diff] [blame] | 299 | if (skl->fw_loaded == false) { |
Senthilnathan Veppur | c787226 | 2016-07-14 09:05:25 +0530 | [diff] [blame] | 300 | skl->boot_complete = false; |
Jayachandran B | 1665c17 | 2016-06-13 17:59:01 +0530 | [diff] [blame] | 301 | ret = bxt_load_base_firmware(ctx); |
Ramesh Babu | 1ef015e | 2016-07-26 18:06:48 +0530 | [diff] [blame] | 302 | if (ret < 0) { |
Jayachandran B | 1665c17 | 2016-06-13 17:59:01 +0530 | [diff] [blame] | 303 | dev_err(ctx->dev, "reload fw failed: %d\n", ret); |
Ramesh Babu | 1ef015e | 2016-07-26 18:06:48 +0530 | [diff] [blame] | 304 | return ret; |
| 305 | } |
| 306 | |
| 307 | if (minfo->lib_count > 1) { |
| 308 | ret = bxt_load_library(ctx, minfo); |
| 309 | if (ret < 0) { |
| 310 | dev_err(ctx->dev, "reload libs failed: %d\n", ret); |
| 311 | return ret; |
| 312 | } |
| 313 | } |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 314 | return ret; |
| 315 | } |
| 316 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 317 | /* If core 0 is being turned on, turn on core 1 as well */ |
| 318 | if (core_id == SKL_DSP_CORE0_ID) |
| 319 | ret = skl_dsp_core_power_up(ctx, core_mask | |
| 320 | SKL_DSP_CORE_MASK(1)); |
| 321 | else |
| 322 | ret = skl_dsp_core_power_up(ctx, core_mask); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 323 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 324 | if (ret < 0) |
| 325 | goto err; |
| 326 | |
| 327 | if (core_id == SKL_DSP_CORE0_ID) { |
| 328 | |
| 329 | /* |
| 330 | * Enable interrupt after SPA is set and before |
| 331 | * DSP is unstalled |
| 332 | */ |
| 333 | skl_ipc_int_enable(ctx); |
| 334 | skl_ipc_op_int_enable(ctx); |
| 335 | skl->boot_complete = false; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 336 | } |
| 337 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 338 | ret = skl_dsp_start_core(ctx, core_mask); |
| 339 | if (ret < 0) |
| 340 | goto err; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 341 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 342 | if (core_id == SKL_DSP_CORE0_ID) { |
| 343 | ret = wait_event_timeout(skl->boot_wait, |
| 344 | skl->boot_complete, |
| 345 | msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); |
| 346 | |
| 347 | /* If core 1 was turned on for booting core 0, turn it off */ |
| 348 | skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); |
| 349 | if (ret == 0) { |
| 350 | dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__); |
| 351 | dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", |
| 352 | sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), |
| 353 | sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); |
| 354 | dev_err(ctx->dev, "Failed to set core0 to D0 state\n"); |
| 355 | ret = -EIO; |
| 356 | goto err; |
| 357 | } |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 358 | } |
| 359 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 360 | /* Tell FW if additional core in now On */ |
| 361 | |
| 362 | if (core_id != SKL_DSP_CORE0_ID) { |
| 363 | dx.core_mask = core_mask; |
| 364 | dx.dx_mask = core_mask; |
| 365 | |
| 366 | ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, |
| 367 | BXT_BASE_FW_MODULE_ID, &dx); |
| 368 | if (ret < 0) { |
| 369 | dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n", |
| 370 | core_id, ret); |
| 371 | goto err; |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | skl->cores.state[core_id] = SKL_DSP_RUNNING; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 376 | return 0; |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 377 | err: |
| 378 | if (core_id == SKL_DSP_CORE0_ID) |
| 379 | core_mask |= SKL_DSP_CORE_MASK(1); |
| 380 | skl_dsp_disable_core(ctx, core_mask); |
| 381 | |
| 382 | return ret; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 383 | } |
| 384 | |
Jayachandran B | 052f103 | 2016-06-21 10:17:41 +0530 | [diff] [blame] | 385 | static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id) |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 386 | { |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 387 | int ret; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 388 | struct skl_ipc_dxstate_info dx; |
| 389 | struct skl_sst *skl = ctx->thread_context; |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 390 | unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 391 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 392 | dx.core_mask = core_mask; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 393 | dx.dx_mask = SKL_IPC_D3_MASK; |
| 394 | |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 395 | dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n", |
| 396 | dx.core_mask, dx.dx_mask); |
| 397 | |
| 398 | ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, |
| 399 | BXT_BASE_FW_MODULE_ID, &dx); |
| 400 | if (ret < 0) |
| 401 | dev_err(ctx->dev, |
| 402 | "Failed to set DSP to D3:core id = %d;Continue reset\n", |
| 403 | core_id); |
| 404 | |
| 405 | ret = skl_dsp_disable_core(ctx, core_mask); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 406 | if (ret < 0) { |
Colin Ian King | ecd286a | 2016-09-16 18:51:21 +0100 | [diff] [blame] | 407 | dev_err(ctx->dev, "Failed to disable core %d\n", ret); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 408 | return ret; |
| 409 | } |
Jayachandran B | e68aca0 | 2016-06-21 10:17:43 +0530 | [diff] [blame] | 410 | skl->cores.state[core_id] = SKL_DSP_RESET; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 411 | return 0; |
| 412 | } |
| 413 | |
| 414 | static struct skl_dsp_fw_ops bxt_fw_ops = { |
| 415 | .set_state_D0 = bxt_set_dsp_D0, |
| 416 | .set_state_D3 = bxt_set_dsp_D3, |
| 417 | .load_fw = bxt_load_base_firmware, |
| 418 | .get_fw_errcode = bxt_get_errorcode, |
Ramesh Babu | 1ef015e | 2016-07-26 18:06:48 +0530 | [diff] [blame] | 419 | .load_library = bxt_load_library, |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 420 | }; |
| 421 | |
| 422 | static struct sst_ops skl_ops = { |
| 423 | .irq_handler = skl_dsp_sst_interrupt, |
| 424 | .write = sst_shim32_write, |
| 425 | .read = sst_shim32_read, |
| 426 | .ram_read = sst_memcpy_fromio_32, |
| 427 | .ram_write = sst_memcpy_toio_32, |
| 428 | .free = skl_dsp_free, |
| 429 | }; |
| 430 | |
| 431 | static struct sst_dsp_device skl_dev = { |
| 432 | .thread = skl_dsp_irq_thread_handler, |
| 433 | .ops = &skl_ops, |
| 434 | }; |
| 435 | |
| 436 | int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, |
| 437 | const char *fw_name, struct skl_dsp_loader_ops dsp_ops, |
| 438 | struct skl_sst **dsp) |
| 439 | { |
| 440 | struct skl_sst *skl; |
| 441 | struct sst_dsp *sst; |
| 442 | int ret; |
| 443 | |
| 444 | skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL); |
| 445 | if (skl == NULL) |
| 446 | return -ENOMEM; |
| 447 | |
| 448 | skl->dev = dev; |
| 449 | skl_dev.thread_context = skl; |
Vinod Koul | 3467a64 | 2016-05-30 17:43:01 +0530 | [diff] [blame] | 450 | INIT_LIST_HEAD(&skl->uuid_list); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 451 | |
| 452 | skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq); |
| 453 | if (!skl->dsp) { |
| 454 | dev_err(skl->dev, "skl_dsp_ctx_init failed\n"); |
| 455 | return -ENODEV; |
| 456 | } |
| 457 | |
| 458 | sst = skl->dsp; |
| 459 | sst->fw_name = fw_name; |
| 460 | sst->dsp_ops = dsp_ops; |
| 461 | sst->fw_ops = bxt_fw_ops; |
| 462 | sst->addr.lpe = mmio_base; |
| 463 | sst->addr.shim = mmio_base; |
| 464 | |
| 465 | sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), |
| 466 | SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); |
| 467 | |
Vinod Koul | b914bb55 | 2016-06-14 21:33:44 +0530 | [diff] [blame] | 468 | INIT_LIST_HEAD(&sst->module_list); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 469 | ret = skl_ipc_init(dev, skl); |
| 470 | if (ret) |
| 471 | return ret; |
| 472 | |
Jayachandran B | 052f103 | 2016-06-21 10:17:41 +0530 | [diff] [blame] | 473 | skl->cores.count = 2; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 474 | skl->boot_complete = false; |
| 475 | init_waitqueue_head(&skl->boot_wait); |
Vinod Koul | 78cdbbd | 2016-07-26 18:06:42 +0530 | [diff] [blame] | 476 | skl->is_first_boot = true; |
| 477 | |
| 478 | if (dsp) |
| 479 | *dsp = skl; |
| 480 | |
| 481 | return 0; |
| 482 | } |
| 483 | EXPORT_SYMBOL_GPL(bxt_sst_dsp_init); |
| 484 | |
| 485 | int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx) |
| 486 | { |
| 487 | int ret; |
| 488 | struct sst_dsp *sst = ctx->dsp; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 489 | |
| 490 | ret = sst->fw_ops.load_fw(sst); |
| 491 | if (ret < 0) { |
Colin Ian King | ecd286a | 2016-09-16 18:51:21 +0100 | [diff] [blame] | 492 | dev_err(dev, "Load base fw failed: %x\n", ret); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 493 | return ret; |
| 494 | } |
| 495 | |
Jayachandran B | 052f103 | 2016-06-21 10:17:41 +0530 | [diff] [blame] | 496 | skl_dsp_init_core_state(sst); |
| 497 | |
Ramesh Babu | 1ef015e | 2016-07-26 18:06:48 +0530 | [diff] [blame] | 498 | if (ctx->manifest.lib_count > 1) { |
| 499 | ret = sst->fw_ops.load_library(sst, &ctx->manifest); |
| 500 | if (ret < 0) { |
Colin Ian King | ecd286a | 2016-09-16 18:51:21 +0100 | [diff] [blame] | 501 | dev_err(dev, "Load Library failed : %x\n", ret); |
Ramesh Babu | 1ef015e | 2016-07-26 18:06:48 +0530 | [diff] [blame] | 502 | return ret; |
| 503 | } |
| 504 | } |
Vinod Koul | 78cdbbd | 2016-07-26 18:06:42 +0530 | [diff] [blame] | 505 | ctx->is_first_boot = false; |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 506 | |
| 507 | return 0; |
| 508 | } |
Vinod Koul | 78cdbbd | 2016-07-26 18:06:42 +0530 | [diff] [blame] | 509 | EXPORT_SYMBOL_GPL(bxt_sst_init_fw); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 510 | |
| 511 | void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) |
| 512 | { |
Vinod Koul | 3467a64 | 2016-05-30 17:43:01 +0530 | [diff] [blame] | 513 | skl_freeup_uuid_list(ctx); |
Jeeja KP | 92eb4f6 | 2016-03-11 10:12:56 +0530 | [diff] [blame] | 514 | skl_ipc_free(&ctx->ipc); |
| 515 | ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp); |
| 516 | |
| 517 | if (ctx->dsp->addr.lpe) |
| 518 | iounmap(ctx->dsp->addr.lpe); |
| 519 | |
| 520 | ctx->dsp->ops->free(ctx->dsp); |
| 521 | } |
| 522 | EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup); |
| 523 | |
| 524 | MODULE_LICENSE("GPL v2"); |
| 525 | MODULE_DESCRIPTION("Intel Broxton IPC driver"); |