Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #ifndef PP_SMC_H |
| 24 | #define PP_SMC_H |
| 25 | |
| 26 | #pragma pack(push, 1) |
| 27 | |
| 28 | #define PPSMC_SWSTATE_FLAG_DC 0x01 |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 29 | #define PPSMC_SWSTATE_FLAG_UVD 0x02 |
| 30 | #define PPSMC_SWSTATE_FLAG_VCE 0x04 |
| 31 | #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08 |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 32 | |
| 33 | #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 |
| 34 | #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 |
| 35 | #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff |
| 36 | |
| 37 | #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 |
| 38 | #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 |
| 39 | #define PPSMC_SYSTEMFLAG_GDDR5 0x04 |
| 40 | #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 |
| 41 | #define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 42 | #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 |
| 43 | #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO 0x40 |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 44 | |
| 45 | #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 |
| 46 | #define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 |
| 47 | #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 |
| 48 | #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 49 | #define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x02 |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 50 | |
| 51 | #define PPSMC_DISPLAY_WATERMARK_LOW 0 |
| 52 | #define PPSMC_DISPLAY_WATERMARK_HIGH 1 |
| 53 | |
| 54 | #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 |
Alex Deucher | 69e0b57 | 2013-04-12 16:42:42 -0400 | [diff] [blame] | 55 | #define PPSMC_STATEFLAG_POWERBOOST 0x02 |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 56 | #define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 |
| 57 | #define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 58 | |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 59 | #define FDO_MODE_HARDWARE 0 |
| 60 | #define FDO_MODE_PIECE_WISE_LINEAR 1 |
| 61 | |
Alex Deucher | e03cea3 | 2014-09-15 00:15:22 -0400 | [diff] [blame] | 62 | enum FAN_CONTROL { |
| 63 | FAN_CONTROL_FUZZY, |
| 64 | FAN_CONTROL_TABLE |
| 65 | }; |
| 66 | |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 67 | #define PPSMC_Result_OK ((uint8_t)0x01) |
| 68 | #define PPSMC_Result_Failed ((uint8_t)0xFF) |
| 69 | |
| 70 | typedef uint8_t PPSMC_Result; |
| 71 | |
| 72 | #define PPSMC_MSG_Halt ((uint8_t)0x10) |
| 73 | #define PPSMC_MSG_Resume ((uint8_t)0x11) |
| 74 | #define PPSMC_MSG_ZeroLevelsDisabled ((uint8_t)0x13) |
| 75 | #define PPSMC_MSG_OneLevelsDisabled ((uint8_t)0x14) |
| 76 | #define PPSMC_MSG_TwoLevelsDisabled ((uint8_t)0x15) |
| 77 | #define PPSMC_MSG_EnableThermalInterrupt ((uint8_t)0x16) |
Alex Deucher | 69e0b57 | 2013-04-12 16:42:42 -0400 | [diff] [blame] | 78 | #define PPSMC_MSG_RunningOnAC ((uint8_t)0x17) |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 79 | #define PPSMC_MSG_SwitchToSwState ((uint8_t)0x20) |
| 80 | #define PPSMC_MSG_SwitchToInitialState ((uint8_t)0x40) |
| 81 | #define PPSMC_MSG_NoForcedLevel ((uint8_t)0x41) |
Alex Deucher | 8b5e6b7 | 2013-07-02 18:40:35 -0400 | [diff] [blame] | 82 | #define PPSMC_MSG_ForceHigh ((uint8_t)0x42) |
| 83 | #define PPSMC_MSG_ForceMediumOrHigh ((uint8_t)0x43) |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 84 | #define PPSMC_MSG_SwitchToMinimumPower ((uint8_t)0x51) |
| 85 | #define PPSMC_MSG_ResumeFromMinimumPower ((uint8_t)0x52) |
Alex Deucher | 69e0b57 | 2013-04-12 16:42:42 -0400 | [diff] [blame] | 86 | #define PPSMC_MSG_EnableCac ((uint8_t)0x53) |
| 87 | #define PPSMC_MSG_DisableCac ((uint8_t)0x54) |
| 88 | #define PPSMC_TDPClampingActive ((uint8_t)0x59) |
| 89 | #define PPSMC_TDPClampingInactive ((uint8_t)0x5A) |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 90 | #define PPSMC_StartFanControl ((uint8_t)0x5B) |
| 91 | #define PPSMC_StopFanControl ((uint8_t)0x5C) |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 92 | #define PPSMC_MSG_NoDisplay ((uint8_t)0x5D) |
| 93 | #define PPSMC_MSG_HasDisplay ((uint8_t)0x5E) |
Alex Deucher | 69e0b57 | 2013-04-12 16:42:42 -0400 | [diff] [blame] | 94 | #define PPSMC_MSG_UVDPowerOFF ((uint8_t)0x60) |
| 95 | #define PPSMC_MSG_UVDPowerON ((uint8_t)0x61) |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 96 | #define PPSMC_MSG_EnableULV ((uint8_t)0x62) |
| 97 | #define PPSMC_MSG_DisableULV ((uint8_t)0x63) |
| 98 | #define PPSMC_MSG_EnterULV ((uint8_t)0x64) |
| 99 | #define PPSMC_MSG_ExitULV ((uint8_t)0x65) |
Alex Deucher | 69e0b57 | 2013-04-12 16:42:42 -0400 | [diff] [blame] | 100 | #define PPSMC_CACLongTermAvgEnable ((uint8_t)0x6E) |
| 101 | #define PPSMC_CACLongTermAvgDisable ((uint8_t)0x6F) |
| 102 | #define PPSMC_MSG_CollectCAC_PowerCorreln ((uint8_t)0x7A) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 103 | #define PPSMC_FlushDataCache ((uint8_t)0x80) |
Alex Deucher | 69e0b57 | 2013-04-12 16:42:42 -0400 | [diff] [blame] | 104 | #define PPSMC_MSG_SetEnabledLevels ((uint8_t)0x82) |
| 105 | #define PPSMC_MSG_SetForcedLevels ((uint8_t)0x83) |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 106 | #define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 107 | #define PPSMC_MSG_EnableDTE ((uint8_t)0x87) |
| 108 | #define PPSMC_MSG_DisableDTE ((uint8_t)0x88) |
| 109 | #define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96) |
| 110 | #define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97) |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 111 | |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 112 | /* CI/KV/KB */ |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 113 | #define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) |
| 114 | #define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) |
| 115 | #define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) |
| 116 | #define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) |
| 117 | #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) |
| 118 | #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) |
Alex Deucher | 1955f10 | 2014-09-14 23:45:30 -0400 | [diff] [blame] | 119 | #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 120 | #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) |
| 121 | #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 122 | #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 123 | #define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) |
| 124 | #define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) |
| 125 | #define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) |
| 126 | #define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) |
| 127 | #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) |
| 128 | #define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) |
| 129 | #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) |
| 130 | #define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 131 | #define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) |
| 132 | #define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) |
Alex Deucher | 89536fd | 2013-07-15 18:14:24 -0400 | [diff] [blame] | 133 | #define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 134 | #define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 135 | #define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) |
| 136 | #define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 137 | #define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) |
| 138 | #define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 139 | #define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) |
| 140 | #define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) |
| 141 | #define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) |
| 142 | #define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) |
| 143 | #define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) |
| 144 | #define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) |
| 145 | #define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) |
| 146 | #define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 147 | #define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 148 | #define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 149 | #define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) |
| 150 | #define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) |
| 151 | #define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) |
| 152 | #define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) |
| 153 | #define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) |
| 154 | #define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) |
| 155 | #define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 156 | #define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) |
| 157 | #define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 158 | #define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) |
| 159 | #define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) |
| 160 | #define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) |
| 161 | #define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) |
| 162 | #define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) |
Alex Deucher | e03cea3 | 2014-09-15 00:15:22 -0400 | [diff] [blame] | 163 | #define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 164 | |
Alex Deucher | 0e4ed1c | 2014-09-15 02:15:04 -0400 | [diff] [blame] | 165 | #define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) |
| 166 | #define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) |
| 167 | |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 168 | #define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) |
| 169 | #define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 170 | |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 171 | /* TN */ |
| 172 | #define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) |
| 173 | #define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) |
| 174 | #define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) |
Alex Deucher | 1955f10 | 2014-09-14 23:45:30 -0400 | [diff] [blame] | 175 | #define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a) |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 176 | #define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109) |
| 177 | #define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e) |
| 178 | #define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f) |
Alex Deucher | 1955f10 | 2014-09-14 23:45:30 -0400 | [diff] [blame] | 179 | #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 180 | #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) |
| 181 | #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) |
Alex Deucher | ef4e036 | 2013-09-09 18:56:50 -0400 | [diff] [blame] | 182 | #define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120) |
| 183 | #define PPSMC_MSG_DisableBAPM ((uint32_t) 0x121) |
Alex Deucher | 0c4aaea | 2012-11-07 20:05:07 -0500 | [diff] [blame] | 184 | #define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124) |
Alex Deucher | d70229f | 2013-04-12 16:40:41 -0400 | [diff] [blame] | 185 | |
| 186 | |
| 187 | typedef uint16_t PPSMC_Msg; |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 188 | |
| 189 | #pragma pack(pop) |
| 190 | |
| 191 | #endif |