Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
| 29 | #include <drm/radeon_drm.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 30 | #include "radeon.h" |
| 31 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 32 | void radeon_gem_object_free(struct drm_gem_object *gobj) |
| 33 | { |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 34 | struct radeon_bo *robj = gem_to_radeon_bo(gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 35 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 36 | if (robj) { |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 37 | if (robj->gem_base.import_attach) |
| 38 | drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); |
Christian König | 12f1384 | 2015-07-14 15:58:30 +0200 | [diff] [blame] | 39 | radeon_mn_unregister(robj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 40 | radeon_bo_unref(&robj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | } |
| 42 | } |
| 43 | |
Alex Deucher | 391bfec | 2014-07-17 12:26:29 -0400 | [diff] [blame] | 44 | int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 45 | int alignment, int initial_domain, |
Christian König | ed5cb43 | 2014-07-21 13:27:27 +0200 | [diff] [blame] | 46 | u32 flags, bool kernel, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 47 | struct drm_gem_object **obj) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 48 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 49 | struct radeon_bo *robj; |
Christian König | 6c0d112 | 2012-10-23 15:53:18 +0200 | [diff] [blame] | 50 | unsigned long max_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 51 | int r; |
| 52 | |
| 53 | *obj = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 54 | /* At least align on page size */ |
| 55 | if (alignment < PAGE_SIZE) { |
| 56 | alignment = PAGE_SIZE; |
| 57 | } |
Christian König | 6c0d112 | 2012-10-23 15:53:18 +0200 | [diff] [blame] | 58 | |
Alex Deucher | 391bfec | 2014-07-17 12:26:29 -0400 | [diff] [blame] | 59 | /* Maximum bo size is the unpinned gtt size since we use the gtt to |
| 60 | * handle vram to system pool migrations. |
| 61 | */ |
| 62 | max_size = rdev->mc.gtt_size - rdev->gart_pin_size; |
Christian König | 6c0d112 | 2012-10-23 15:53:18 +0200 | [diff] [blame] | 63 | if (size > max_size) { |
Alex Deucher | 391bfec | 2014-07-17 12:26:29 -0400 | [diff] [blame] | 64 | DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", |
Michel Dänzer | 380670a | 2014-07-16 18:40:32 +0900 | [diff] [blame] | 65 | size >> 20, max_size >> 20); |
Christian König | 6c0d112 | 2012-10-23 15:53:18 +0200 | [diff] [blame] | 66 | return -ENOMEM; |
| 67 | } |
| 68 | |
Christian König | 0fe7158 | 2012-10-23 15:53:19 +0200 | [diff] [blame] | 69 | retry: |
Michel Dänzer | 02376d8 | 2014-07-17 19:01:08 +0900 | [diff] [blame] | 70 | r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain, |
Maarten Lankhorst | 831b696 | 2014-09-18 14:11:56 +0200 | [diff] [blame] | 71 | flags, NULL, NULL, &robj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 72 | if (r) { |
Christian König | 0fe7158 | 2012-10-23 15:53:19 +0200 | [diff] [blame] | 73 | if (r != -ERESTARTSYS) { |
| 74 | if (initial_domain == RADEON_GEM_DOMAIN_VRAM) { |
| 75 | initial_domain |= RADEON_GEM_DOMAIN_GTT; |
| 76 | goto retry; |
| 77 | } |
Alex Deucher | 391bfec | 2014-07-17 12:26:29 -0400 | [diff] [blame] | 78 | DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", |
Dave Airlie | ecabd32 | 2009-12-15 10:39:48 +1000 | [diff] [blame] | 79 | size, initial_domain, alignment, r); |
Christian König | 0fe7158 | 2012-10-23 15:53:19 +0200 | [diff] [blame] | 80 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 81 | return r; |
| 82 | } |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 83 | *obj = &robj->gem_base; |
Jerome Glisse | 409851f | 2013-04-25 22:29:27 -0400 | [diff] [blame] | 84 | robj->pid = task_pid_nr(current); |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 85 | |
| 86 | mutex_lock(&rdev->gem.mutex); |
| 87 | list_add_tail(&robj->list, &rdev->gem.objects); |
| 88 | mutex_unlock(&rdev->gem.mutex); |
| 89 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 90 | return 0; |
| 91 | } |
| 92 | |
Rashika Kheria | 248a6c4 | 2014-01-06 20:58:45 +0530 | [diff] [blame] | 93 | static int radeon_gem_set_domain(struct drm_gem_object *gobj, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 94 | uint32_t rdomain, uint32_t wdomain) |
| 95 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 96 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 97 | uint32_t domain; |
Maarten Lankhorst | 39e7f6f | 2014-05-14 15:40:49 +0200 | [diff] [blame] | 98 | long r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 99 | |
| 100 | /* FIXME: reeimplement */ |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 101 | robj = gem_to_radeon_bo(gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 102 | /* work out where to validate the buffer to */ |
| 103 | domain = wdomain; |
| 104 | if (!domain) { |
| 105 | domain = rdomain; |
| 106 | } |
| 107 | if (!domain) { |
| 108 | /* Do nothings */ |
Masanari Iida | b6cafa2 | 2012-02-27 23:28:38 +0900 | [diff] [blame] | 109 | printk(KERN_WARNING "Set domain without domain !\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 110 | return 0; |
| 111 | } |
| 112 | if (domain == RADEON_GEM_DOMAIN_CPU) { |
| 113 | /* Asking for cpu access wait for object idle */ |
Maarten Lankhorst | 39e7f6f | 2014-05-14 15:40:49 +0200 | [diff] [blame] | 114 | r = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ); |
| 115 | if (!r) |
| 116 | r = -EBUSY; |
| 117 | |
| 118 | if (r < 0 && r != -EINTR) { |
| 119 | printk(KERN_ERR "Failed to wait for object: %li\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 120 | return r; |
| 121 | } |
| 122 | } |
| 123 | return 0; |
| 124 | } |
| 125 | |
| 126 | int radeon_gem_init(struct radeon_device *rdev) |
| 127 | { |
| 128 | INIT_LIST_HEAD(&rdev->gem.objects); |
| 129 | return 0; |
| 130 | } |
| 131 | |
| 132 | void radeon_gem_fini(struct radeon_device *rdev) |
| 133 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 134 | radeon_bo_force_delete(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 135 | } |
| 136 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 137 | /* |
| 138 | * Call from drm_gem_handle_create which appear in both new and open ioctl |
| 139 | * case. |
| 140 | */ |
| 141 | int radeon_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) |
| 142 | { |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 143 | struct radeon_bo *rbo = gem_to_radeon_bo(obj); |
| 144 | struct radeon_device *rdev = rbo->rdev; |
| 145 | struct radeon_fpriv *fpriv = file_priv->driver_priv; |
| 146 | struct radeon_vm *vm = &fpriv->vm; |
| 147 | struct radeon_bo_va *bo_va; |
| 148 | int r; |
| 149 | |
Alex Deucher | 544143f | 2015-01-28 14:36:26 -0500 | [diff] [blame] | 150 | if ((rdev->family < CHIP_CAYMAN) || |
| 151 | (!rdev->accel_working)) { |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 152 | return 0; |
| 153 | } |
| 154 | |
| 155 | r = radeon_bo_reserve(rbo, false); |
| 156 | if (r) { |
| 157 | return r; |
| 158 | } |
| 159 | |
| 160 | bo_va = radeon_vm_bo_find(vm, rbo); |
| 161 | if (!bo_va) { |
| 162 | bo_va = radeon_vm_bo_add(rdev, vm, rbo); |
| 163 | } else { |
| 164 | ++bo_va->ref_count; |
| 165 | } |
| 166 | radeon_bo_unreserve(rbo); |
| 167 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 168 | return 0; |
| 169 | } |
| 170 | |
| 171 | void radeon_gem_object_close(struct drm_gem_object *obj, |
| 172 | struct drm_file *file_priv) |
| 173 | { |
| 174 | struct radeon_bo *rbo = gem_to_radeon_bo(obj); |
| 175 | struct radeon_device *rdev = rbo->rdev; |
| 176 | struct radeon_fpriv *fpriv = file_priv->driver_priv; |
| 177 | struct radeon_vm *vm = &fpriv->vm; |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 178 | struct radeon_bo_va *bo_va; |
Christian König | d59f702 | 2012-09-11 16:10:02 +0200 | [diff] [blame] | 179 | int r; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 180 | |
Alex Deucher | 544143f | 2015-01-28 14:36:26 -0500 | [diff] [blame] | 181 | if ((rdev->family < CHIP_CAYMAN) || |
| 182 | (!rdev->accel_working)) { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 183 | return; |
| 184 | } |
| 185 | |
Christian König | d59f702 | 2012-09-11 16:10:02 +0200 | [diff] [blame] | 186 | r = radeon_bo_reserve(rbo, true); |
| 187 | if (r) { |
| 188 | dev_err(rdev->dev, "leaking bo va because " |
| 189 | "we fail to reserve bo (%d)\n", r); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 190 | return; |
| 191 | } |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 192 | bo_va = radeon_vm_bo_find(vm, rbo); |
| 193 | if (bo_va) { |
| 194 | if (--bo_va->ref_count == 0) { |
| 195 | radeon_vm_bo_rmv(rdev, bo_va); |
| 196 | } |
| 197 | } |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 198 | radeon_bo_unreserve(rbo); |
| 199 | } |
| 200 | |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 201 | static int radeon_gem_handle_lockup(struct radeon_device *rdev, int r) |
| 202 | { |
| 203 | if (r == -EDEADLK) { |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 204 | r = radeon_gpu_reset(rdev); |
| 205 | if (!r) |
| 206 | r = -EAGAIN; |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 207 | } |
| 208 | return r; |
| 209 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 210 | |
| 211 | /* |
| 212 | * GEM ioctls. |
| 213 | */ |
| 214 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, |
| 215 | struct drm_file *filp) |
| 216 | { |
| 217 | struct radeon_device *rdev = dev->dev_private; |
| 218 | struct drm_radeon_gem_info *args = data; |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 219 | struct ttm_mem_type_manager *man; |
| 220 | |
| 221 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 222 | |
Michel Dänzer | ebd4c11 | 2017-01-30 12:06:35 +0900 | [diff] [blame] | 223 | args->vram_size = (u64)man->size << PAGE_SHIFT; |
| 224 | args->vram_visible = rdev->mc.visible_vram_size; |
Alex Deucher | ccbe006 | 2014-07-17 12:16:20 -0400 | [diff] [blame] | 225 | args->vram_visible -= rdev->vram_pin_size; |
| 226 | args->gart_size = rdev->mc.gtt_size; |
| 227 | args->gart_size -= rdev->gart_pin_size; |
| 228 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 229 | return 0; |
| 230 | } |
| 231 | |
| 232 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 233 | struct drm_file *filp) |
| 234 | { |
| 235 | /* TODO: implement */ |
| 236 | DRM_ERROR("unimplemented %s\n", __func__); |
| 237 | return -ENOSYS; |
| 238 | } |
| 239 | |
| 240 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 241 | struct drm_file *filp) |
| 242 | { |
| 243 | /* TODO: implement */ |
| 244 | DRM_ERROR("unimplemented %s\n", __func__); |
| 245 | return -ENOSYS; |
| 246 | } |
| 247 | |
| 248 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, |
| 249 | struct drm_file *filp) |
| 250 | { |
| 251 | struct radeon_device *rdev = dev->dev_private; |
| 252 | struct drm_radeon_gem_create *args = data; |
| 253 | struct drm_gem_object *gobj; |
| 254 | uint32_t handle; |
| 255 | int r; |
| 256 | |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 257 | down_read(&rdev->exclusive_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 258 | /* create a gem object to contain this object in */ |
| 259 | args->size = roundup(args->size, PAGE_SIZE); |
| 260 | r = radeon_gem_object_create(rdev, args->size, args->alignment, |
Michel Dänzer | 02376d8 | 2014-07-17 19:01:08 +0900 | [diff] [blame] | 261 | args->initial_domain, args->flags, |
Christian König | ed5cb43 | 2014-07-21 13:27:27 +0200 | [diff] [blame] | 262 | false, &gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 263 | if (r) { |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 264 | up_read(&rdev->exclusive_lock); |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 265 | r = radeon_gem_handle_lockup(rdev, r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 266 | return r; |
| 267 | } |
| 268 | r = drm_gem_handle_create(filp, gobj, &handle); |
Dave Airlie | 29d08b3 | 2010-09-27 16:17:17 +1000 | [diff] [blame] | 269 | /* drop reference from allocate - handle holds it now */ |
| 270 | drm_gem_object_unreference_unlocked(gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 271 | if (r) { |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 272 | up_read(&rdev->exclusive_lock); |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 273 | r = radeon_gem_handle_lockup(rdev, r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 274 | return r; |
| 275 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 276 | args->handle = handle; |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 277 | up_read(&rdev->exclusive_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 278 | return 0; |
| 279 | } |
| 280 | |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 281 | int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, |
| 282 | struct drm_file *filp) |
| 283 | { |
| 284 | struct radeon_device *rdev = dev->dev_private; |
| 285 | struct drm_radeon_gem_userptr *args = data; |
| 286 | struct drm_gem_object *gobj; |
| 287 | struct radeon_bo *bo; |
| 288 | uint32_t handle; |
| 289 | int r; |
| 290 | |
| 291 | if (offset_in_page(args->addr | args->size)) |
| 292 | return -EINVAL; |
| 293 | |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 294 | /* reject unknown flag values */ |
Christian König | ddd00e3 | 2014-08-07 09:36:01 +0200 | [diff] [blame] | 295 | if (args->flags & ~(RADEON_GEM_USERPTR_READONLY | |
Christian König | 341cb9e | 2014-08-07 09:36:03 +0200 | [diff] [blame] | 296 | RADEON_GEM_USERPTR_ANONONLY | RADEON_GEM_USERPTR_VALIDATE | |
| 297 | RADEON_GEM_USERPTR_REGISTER)) |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 298 | return -EINVAL; |
| 299 | |
Christian König | bd645e4 | 2014-08-07 09:36:04 +0200 | [diff] [blame] | 300 | if (args->flags & RADEON_GEM_USERPTR_READONLY) { |
| 301 | /* readonly pages not tested on older hardware */ |
| 302 | if (rdev->family < CHIP_R600) |
| 303 | return -EINVAL; |
| 304 | |
| 305 | } else if (!(args->flags & RADEON_GEM_USERPTR_ANONONLY) || |
| 306 | !(args->flags & RADEON_GEM_USERPTR_REGISTER)) { |
| 307 | |
| 308 | /* if we want to write to it we must require anonymous |
| 309 | memory and install a MMU notifier */ |
| 310 | return -EACCES; |
| 311 | } |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 312 | |
| 313 | down_read(&rdev->exclusive_lock); |
| 314 | |
| 315 | /* create a gem object to contain this object in */ |
| 316 | r = radeon_gem_object_create(rdev, args->size, 0, |
| 317 | RADEON_GEM_DOMAIN_CPU, 0, |
| 318 | false, &gobj); |
| 319 | if (r) |
| 320 | goto handle_lockup; |
| 321 | |
| 322 | bo = gem_to_radeon_bo(gobj); |
| 323 | r = radeon_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); |
| 324 | if (r) |
| 325 | goto release_object; |
| 326 | |
Christian König | 341cb9e | 2014-08-07 09:36:03 +0200 | [diff] [blame] | 327 | if (args->flags & RADEON_GEM_USERPTR_REGISTER) { |
| 328 | r = radeon_mn_register(bo, args->addr); |
| 329 | if (r) |
| 330 | goto release_object; |
| 331 | } |
| 332 | |
Christian König | 2a84a44 | 2014-08-07 09:36:02 +0200 | [diff] [blame] | 333 | if (args->flags & RADEON_GEM_USERPTR_VALIDATE) { |
| 334 | down_read(¤t->mm->mmap_sem); |
| 335 | r = radeon_bo_reserve(bo, true); |
| 336 | if (r) { |
| 337 | up_read(¤t->mm->mmap_sem); |
| 338 | goto release_object; |
| 339 | } |
| 340 | |
| 341 | radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_GTT); |
| 342 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
| 343 | radeon_bo_unreserve(bo); |
| 344 | up_read(¤t->mm->mmap_sem); |
| 345 | if (r) |
| 346 | goto release_object; |
| 347 | } |
| 348 | |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 349 | r = drm_gem_handle_create(filp, gobj, &handle); |
| 350 | /* drop reference from allocate - handle holds it now */ |
| 351 | drm_gem_object_unreference_unlocked(gobj); |
| 352 | if (r) |
| 353 | goto handle_lockup; |
| 354 | |
| 355 | args->handle = handle; |
| 356 | up_read(&rdev->exclusive_lock); |
| 357 | return 0; |
| 358 | |
| 359 | release_object: |
| 360 | drm_gem_object_unreference_unlocked(gobj); |
| 361 | |
| 362 | handle_lockup: |
| 363 | up_read(&rdev->exclusive_lock); |
| 364 | r = radeon_gem_handle_lockup(rdev, r); |
| 365 | |
| 366 | return r; |
| 367 | } |
| 368 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 369 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 370 | struct drm_file *filp) |
| 371 | { |
| 372 | /* transition the BO to a domain - |
| 373 | * just validate the BO into a certain domain */ |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 374 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 375 | struct drm_radeon_gem_set_domain *args = data; |
| 376 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 377 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 378 | int r; |
| 379 | |
| 380 | /* for now if someone requests domain CPU - |
| 381 | * just make sure the buffer is finished with */ |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 382 | down_read(&rdev->exclusive_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 383 | |
| 384 | /* just do a BO wait for now */ |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 385 | gobj = drm_gem_object_lookup(filp, args->handle); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 386 | if (gobj == NULL) { |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 387 | up_read(&rdev->exclusive_lock); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 388 | return -ENOENT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 389 | } |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 390 | robj = gem_to_radeon_bo(gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 391 | |
| 392 | r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain); |
| 393 | |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 394 | drm_gem_object_unreference_unlocked(gobj); |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 395 | up_read(&rdev->exclusive_lock); |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 396 | r = radeon_gem_handle_lockup(robj->rdev, r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 397 | return r; |
| 398 | } |
| 399 | |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 400 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
| 401 | struct drm_device *dev, |
| 402 | uint32_t handle, uint64_t *offset_p) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 403 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 404 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 405 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 406 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 407 | gobj = drm_gem_object_lookup(filp, handle); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 408 | if (gobj == NULL) { |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 409 | return -ENOENT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 410 | } |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 411 | robj = gem_to_radeon_bo(gobj); |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 412 | if (radeon_ttm_tt_has_userptr(robj->tbo.ttm)) { |
| 413 | drm_gem_object_unreference_unlocked(gobj); |
| 414 | return -EPERM; |
| 415 | } |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 416 | *offset_p = radeon_bo_mmap_offset(robj); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 417 | drm_gem_object_unreference_unlocked(gobj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 418 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 419 | } |
| 420 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 421 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 422 | struct drm_file *filp) |
| 423 | { |
| 424 | struct drm_radeon_gem_mmap *args = data; |
| 425 | |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 426 | return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 427 | } |
| 428 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 429 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 430 | struct drm_file *filp) |
| 431 | { |
Dave Airlie | cefb87e | 2009-08-16 21:05:45 +1000 | [diff] [blame] | 432 | struct drm_radeon_gem_busy *args = data; |
| 433 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 434 | struct radeon_bo *robj; |
Dave Airlie | cefb87e | 2009-08-16 21:05:45 +1000 | [diff] [blame] | 435 | int r; |
Dave Airlie | 4361e52 | 2009-12-10 15:59:32 +1000 | [diff] [blame] | 436 | uint32_t cur_placement = 0; |
Dave Airlie | cefb87e | 2009-08-16 21:05:45 +1000 | [diff] [blame] | 437 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 438 | gobj = drm_gem_object_lookup(filp, args->handle); |
Dave Airlie | cefb87e | 2009-08-16 21:05:45 +1000 | [diff] [blame] | 439 | if (gobj == NULL) { |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 440 | return -ENOENT; |
Dave Airlie | cefb87e | 2009-08-16 21:05:45 +1000 | [diff] [blame] | 441 | } |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 442 | robj = gem_to_radeon_bo(gobj); |
Grigori Goronzy | 828202a | 2015-07-03 01:54:10 +0200 | [diff] [blame] | 443 | |
| 444 | r = reservation_object_test_signaled_rcu(robj->tbo.resv, true); |
| 445 | if (r == 0) |
| 446 | r = -EBUSY; |
| 447 | else |
| 448 | r = 0; |
| 449 | |
| 450 | cur_placement = ACCESS_ONCE(robj->tbo.mem.mem_type); |
Marek Olšák | 0bc490a | 2014-03-02 00:56:19 +0100 | [diff] [blame] | 451 | args->domain = radeon_mem_type_to_domain(cur_placement); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 452 | drm_gem_object_unreference_unlocked(gobj); |
Dave Airlie | e3b2415 | 2009-08-21 09:47:45 +1000 | [diff] [blame] | 453 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 454 | } |
| 455 | |
| 456 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
| 457 | struct drm_file *filp) |
| 458 | { |
Jerome Glisse | 1ef5325 | 2012-07-02 12:40:54 -0400 | [diff] [blame] | 459 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 460 | struct drm_radeon_gem_wait_idle *args = data; |
| 461 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 462 | struct radeon_bo *robj; |
Maarten Lankhorst | 39e7f6f | 2014-05-14 15:40:49 +0200 | [diff] [blame] | 463 | int r = 0; |
Michel Dänzer | 404a6a5 | 2014-08-01 17:22:09 +0900 | [diff] [blame] | 464 | uint32_t cur_placement = 0; |
Maarten Lankhorst | 39e7f6f | 2014-05-14 15:40:49 +0200 | [diff] [blame] | 465 | long ret; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 466 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 467 | gobj = drm_gem_object_lookup(filp, args->handle); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 468 | if (gobj == NULL) { |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 469 | return -ENOENT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 470 | } |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 471 | robj = gem_to_radeon_bo(gobj); |
Maarten Lankhorst | 39e7f6f | 2014-05-14 15:40:49 +0200 | [diff] [blame] | 472 | |
| 473 | ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ); |
| 474 | if (ret == 0) |
| 475 | r = -EBUSY; |
| 476 | else if (ret < 0) |
| 477 | r = ret; |
| 478 | |
Michel Dänzer | 124764f | 2014-07-31 18:43:48 +0900 | [diff] [blame] | 479 | /* Flush HDP cache via MMIO if necessary */ |
Grigori Goronzy | 54e0398 | 2015-07-03 01:54:11 +0200 | [diff] [blame] | 480 | cur_placement = ACCESS_ONCE(robj->tbo.mem.mem_type); |
Michel Dänzer | 404a6a5 | 2014-08-01 17:22:09 +0900 | [diff] [blame] | 481 | if (rdev->asic->mmio_hdp_flush && |
| 482 | radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM) |
Michel Dänzer | 124764f | 2014-07-31 18:43:48 +0900 | [diff] [blame] | 483 | robj->rdev->asic->mmio_hdp_flush(rdev); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 484 | drm_gem_object_unreference_unlocked(gobj); |
Jerome Glisse | 1ef5325 | 2012-07-02 12:40:54 -0400 | [diff] [blame] | 485 | r = radeon_gem_handle_lockup(rdev, r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 486 | return r; |
| 487 | } |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 488 | |
| 489 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
| 490 | struct drm_file *filp) |
| 491 | { |
| 492 | struct drm_radeon_gem_set_tiling *args = data; |
| 493 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 494 | struct radeon_bo *robj; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 495 | int r = 0; |
| 496 | |
| 497 | DRM_DEBUG("%d \n", args->handle); |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 498 | gobj = drm_gem_object_lookup(filp, args->handle); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 499 | if (gobj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 500 | return -ENOENT; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 501 | robj = gem_to_radeon_bo(gobj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 502 | r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 503 | drm_gem_object_unreference_unlocked(gobj); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 504 | return r; |
| 505 | } |
| 506 | |
| 507 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, |
| 508 | struct drm_file *filp) |
| 509 | { |
| 510 | struct drm_radeon_gem_get_tiling *args = data; |
| 511 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 512 | struct radeon_bo *rbo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 513 | int r = 0; |
| 514 | |
| 515 | DRM_DEBUG("\n"); |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 516 | gobj = drm_gem_object_lookup(filp, args->handle); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 517 | if (gobj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 518 | return -ENOENT; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 519 | rbo = gem_to_radeon_bo(gobj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 520 | r = radeon_bo_reserve(rbo, false); |
| 521 | if (unlikely(r != 0)) |
Dave Airlie | 51f07b7 | 2009-12-16 13:10:43 +1000 | [diff] [blame] | 522 | goto out; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 523 | radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); |
| 524 | radeon_bo_unreserve(rbo); |
Dave Airlie | 51f07b7 | 2009-12-16 13:10:43 +1000 | [diff] [blame] | 525 | out: |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 526 | drm_gem_object_unreference_unlocked(gobj); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 527 | return r; |
| 528 | } |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 529 | |
Christian König | 2f2624c | 2014-09-12 12:25:45 +0200 | [diff] [blame] | 530 | /** |
| 531 | * radeon_gem_va_update_vm -update the bo_va in its VM |
| 532 | * |
| 533 | * @rdev: radeon_device pointer |
| 534 | * @bo_va: bo_va to update |
| 535 | * |
| 536 | * Update the bo_va directly after setting it's address. Errors are not |
| 537 | * vital here, so they are not reported back to userspace. |
| 538 | */ |
| 539 | static void radeon_gem_va_update_vm(struct radeon_device *rdev, |
| 540 | struct radeon_bo_va *bo_va) |
| 541 | { |
| 542 | struct ttm_validate_buffer tv, *entry; |
Christian König | 1d0c094 | 2014-11-27 14:48:42 +0100 | [diff] [blame] | 543 | struct radeon_bo_list *vm_bos; |
Christian König | 2f2624c | 2014-09-12 12:25:45 +0200 | [diff] [blame] | 544 | struct ww_acquire_ctx ticket; |
| 545 | struct list_head list; |
| 546 | unsigned domain; |
| 547 | int r; |
| 548 | |
| 549 | INIT_LIST_HEAD(&list); |
| 550 | |
| 551 | tv.bo = &bo_va->bo->tbo; |
| 552 | tv.shared = true; |
| 553 | list_add(&tv.head, &list); |
| 554 | |
| 555 | vm_bos = radeon_vm_get_bos(rdev, bo_va->vm, &list); |
| 556 | if (!vm_bos) |
| 557 | return; |
| 558 | |
Christian König | aa35071 | 2014-12-03 15:46:48 +0100 | [diff] [blame] | 559 | r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL); |
Christian König | 2f2624c | 2014-09-12 12:25:45 +0200 | [diff] [blame] | 560 | if (r) |
| 561 | goto error_free; |
| 562 | |
| 563 | list_for_each_entry(entry, &list, head) { |
| 564 | domain = radeon_mem_type_to_domain(entry->bo->mem.mem_type); |
| 565 | /* if anything is swapped out don't swap it in here, |
| 566 | just abort and wait for the next CS */ |
| 567 | if (domain == RADEON_GEM_DOMAIN_CPU) |
| 568 | goto error_unreserve; |
| 569 | } |
| 570 | |
| 571 | mutex_lock(&bo_va->vm->mutex); |
| 572 | r = radeon_vm_clear_freed(rdev, bo_va->vm); |
| 573 | if (r) |
| 574 | goto error_unlock; |
| 575 | |
| 576 | if (bo_va->it.start) |
| 577 | r = radeon_vm_bo_update(rdev, bo_va, &bo_va->bo->tbo.mem); |
| 578 | |
| 579 | error_unlock: |
| 580 | mutex_unlock(&bo_va->vm->mutex); |
| 581 | |
| 582 | error_unreserve: |
| 583 | ttm_eu_backoff_reservation(&ticket, &list); |
| 584 | |
| 585 | error_free: |
| 586 | drm_free_large(vm_bos); |
| 587 | |
Christian König | ad1a622 | 2015-01-09 11:07:49 +0100 | [diff] [blame] | 588 | if (r && r != -ERESTARTSYS) |
Christian König | 2f2624c | 2014-09-12 12:25:45 +0200 | [diff] [blame] | 589 | DRM_ERROR("Couldn't update BO_VA (%d)\n", r); |
| 590 | } |
| 591 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 592 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
| 593 | struct drm_file *filp) |
| 594 | { |
| 595 | struct drm_radeon_gem_va *args = data; |
| 596 | struct drm_gem_object *gobj; |
| 597 | struct radeon_device *rdev = dev->dev_private; |
| 598 | struct radeon_fpriv *fpriv = filp->driver_priv; |
| 599 | struct radeon_bo *rbo; |
| 600 | struct radeon_bo_va *bo_va; |
| 601 | u32 invalid_flags; |
| 602 | int r = 0; |
| 603 | |
Alex Deucher | 67e915e | 2012-01-06 09:38:15 -0500 | [diff] [blame] | 604 | if (!rdev->vm_manager.enabled) { |
| 605 | args->operation = RADEON_VA_RESULT_ERROR; |
| 606 | return -ENOTTY; |
| 607 | } |
| 608 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 609 | /* !! DONT REMOVE !! |
| 610 | * We don't support vm_id yet, to be sure we don't have have broken |
| 611 | * userspace, reject anyone trying to use non 0 value thus moving |
| 612 | * forward we can use those fields without breaking existant userspace |
| 613 | */ |
| 614 | if (args->vm_id) { |
| 615 | args->operation = RADEON_VA_RESULT_ERROR; |
| 616 | return -EINVAL; |
| 617 | } |
| 618 | |
| 619 | if (args->offset < RADEON_VA_RESERVED_SIZE) { |
| 620 | dev_err(&dev->pdev->dev, |
| 621 | "offset 0x%lX is in reserved area 0x%X\n", |
| 622 | (unsigned long)args->offset, |
| 623 | RADEON_VA_RESERVED_SIZE); |
| 624 | args->operation = RADEON_VA_RESULT_ERROR; |
| 625 | return -EINVAL; |
| 626 | } |
| 627 | |
| 628 | /* don't remove, we need to enforce userspace to set the snooped flag |
| 629 | * otherwise we will endup with broken userspace and we won't be able |
| 630 | * to enable this feature without adding new interface |
| 631 | */ |
| 632 | invalid_flags = RADEON_VM_PAGE_VALID | RADEON_VM_PAGE_SYSTEM; |
| 633 | if ((args->flags & invalid_flags)) { |
| 634 | dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", |
| 635 | args->flags, invalid_flags); |
| 636 | args->operation = RADEON_VA_RESULT_ERROR; |
| 637 | return -EINVAL; |
| 638 | } |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 639 | |
| 640 | switch (args->operation) { |
| 641 | case RADEON_VA_MAP: |
| 642 | case RADEON_VA_UNMAP: |
| 643 | break; |
| 644 | default: |
| 645 | dev_err(&dev->pdev->dev, "unsupported operation %d\n", |
| 646 | args->operation); |
| 647 | args->operation = RADEON_VA_RESULT_ERROR; |
| 648 | return -EINVAL; |
| 649 | } |
| 650 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 651 | gobj = drm_gem_object_lookup(filp, args->handle); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 652 | if (gobj == NULL) { |
| 653 | args->operation = RADEON_VA_RESULT_ERROR; |
| 654 | return -ENOENT; |
| 655 | } |
| 656 | rbo = gem_to_radeon_bo(gobj); |
| 657 | r = radeon_bo_reserve(rbo, false); |
| 658 | if (r) { |
| 659 | args->operation = RADEON_VA_RESULT_ERROR; |
| 660 | drm_gem_object_unreference_unlocked(gobj); |
| 661 | return r; |
| 662 | } |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 663 | bo_va = radeon_vm_bo_find(&fpriv->vm, rbo); |
| 664 | if (!bo_va) { |
| 665 | args->operation = RADEON_VA_RESULT_ERROR; |
Matthew Dawson | 186bac8 | 2016-01-25 10:34:12 -0500 | [diff] [blame] | 666 | radeon_bo_unreserve(rbo); |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 667 | drm_gem_object_unreference_unlocked(gobj); |
| 668 | return -ENOENT; |
| 669 | } |
| 670 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 671 | switch (args->operation) { |
| 672 | case RADEON_VA_MAP: |
Alex Deucher | 0aea5e4 | 2014-07-30 11:49:56 -0400 | [diff] [blame] | 673 | if (bo_va->it.start) { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 674 | args->operation = RADEON_VA_RESULT_VA_EXIST; |
Alex Deucher | 0aea5e4 | 2014-07-30 11:49:56 -0400 | [diff] [blame] | 675 | args->offset = bo_va->it.start * RADEON_GPU_PAGE_SIZE; |
Christian König | 85761f6 | 2014-11-19 14:01:20 +0100 | [diff] [blame] | 676 | radeon_bo_unreserve(rbo); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 677 | goto out; |
| 678 | } |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 679 | r = radeon_vm_bo_set_addr(rdev, bo_va, args->offset, args->flags); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 680 | break; |
| 681 | case RADEON_VA_UNMAP: |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 682 | r = radeon_vm_bo_set_addr(rdev, bo_va, 0, 0); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 683 | break; |
| 684 | default: |
| 685 | break; |
| 686 | } |
Christian König | 2f2624c | 2014-09-12 12:25:45 +0200 | [diff] [blame] | 687 | if (!r) |
| 688 | radeon_gem_va_update_vm(rdev, bo_va); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 689 | args->operation = RADEON_VA_RESULT_OK; |
| 690 | if (r) { |
| 691 | args->operation = RADEON_VA_RESULT_ERROR; |
| 692 | } |
| 693 | out: |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 694 | drm_gem_object_unreference_unlocked(gobj); |
| 695 | return r; |
| 696 | } |
| 697 | |
Marek Olšák | bda72d5 | 2014-03-02 00:56:17 +0100 | [diff] [blame] | 698 | int radeon_gem_op_ioctl(struct drm_device *dev, void *data, |
| 699 | struct drm_file *filp) |
| 700 | { |
| 701 | struct drm_radeon_gem_op *args = data; |
| 702 | struct drm_gem_object *gobj; |
| 703 | struct radeon_bo *robj; |
| 704 | int r; |
| 705 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 706 | gobj = drm_gem_object_lookup(filp, args->handle); |
Marek Olšák | bda72d5 | 2014-03-02 00:56:17 +0100 | [diff] [blame] | 707 | if (gobj == NULL) { |
| 708 | return -ENOENT; |
| 709 | } |
| 710 | robj = gem_to_radeon_bo(gobj); |
Christian König | f72a113a | 2014-08-07 09:36:00 +0200 | [diff] [blame] | 711 | |
| 712 | r = -EPERM; |
| 713 | if (radeon_ttm_tt_has_userptr(robj->tbo.ttm)) |
| 714 | goto out; |
| 715 | |
Marek Olšák | bda72d5 | 2014-03-02 00:56:17 +0100 | [diff] [blame] | 716 | r = radeon_bo_reserve(robj, false); |
| 717 | if (unlikely(r)) |
| 718 | goto out; |
| 719 | |
| 720 | switch (args->op) { |
| 721 | case RADEON_GEM_OP_GET_INITIAL_DOMAIN: |
| 722 | args->value = robj->initial_domain; |
| 723 | break; |
| 724 | case RADEON_GEM_OP_SET_INITIAL_DOMAIN: |
| 725 | robj->initial_domain = args->value & (RADEON_GEM_DOMAIN_VRAM | |
| 726 | RADEON_GEM_DOMAIN_GTT | |
| 727 | RADEON_GEM_DOMAIN_CPU); |
| 728 | break; |
| 729 | default: |
| 730 | r = -EINVAL; |
| 731 | } |
| 732 | |
| 733 | radeon_bo_unreserve(robj); |
| 734 | out: |
| 735 | drm_gem_object_unreference_unlocked(gobj); |
| 736 | return r; |
| 737 | } |
| 738 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 739 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
| 740 | struct drm_device *dev, |
| 741 | struct drm_mode_create_dumb *args) |
| 742 | { |
| 743 | struct radeon_device *rdev = dev->dev_private; |
| 744 | struct drm_gem_object *gobj; |
Dave Airlie | c87a8d8 | 2011-03-17 13:58:34 +1000 | [diff] [blame] | 745 | uint32_t handle; |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 746 | int r; |
| 747 | |
| 748 | args->pitch = radeon_align_pitch(rdev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8); |
| 749 | args->size = args->pitch * args->height; |
| 750 | args->size = ALIGN(args->size, PAGE_SIZE); |
| 751 | |
| 752 | r = radeon_gem_object_create(rdev, args->size, 0, |
Michel Dänzer | 02376d8 | 2014-07-17 19:01:08 +0900 | [diff] [blame] | 753 | RADEON_GEM_DOMAIN_VRAM, 0, |
Christian König | ed5cb43 | 2014-07-21 13:27:27 +0200 | [diff] [blame] | 754 | false, &gobj); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 755 | if (r) |
| 756 | return -ENOMEM; |
| 757 | |
Dave Airlie | c87a8d8 | 2011-03-17 13:58:34 +1000 | [diff] [blame] | 758 | r = drm_gem_handle_create(file_priv, gobj, &handle); |
| 759 | /* drop reference from allocate - handle holds it now */ |
| 760 | drm_gem_object_unreference_unlocked(gobj); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 761 | if (r) { |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 762 | return r; |
| 763 | } |
Dave Airlie | c87a8d8 | 2011-03-17 13:58:34 +1000 | [diff] [blame] | 764 | args->handle = handle; |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 765 | return 0; |
| 766 | } |
| 767 | |
Jerome Glisse | 409851f | 2013-04-25 22:29:27 -0400 | [diff] [blame] | 768 | #if defined(CONFIG_DEBUG_FS) |
| 769 | static int radeon_debugfs_gem_info(struct seq_file *m, void *data) |
| 770 | { |
| 771 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
| 772 | struct drm_device *dev = node->minor->dev; |
| 773 | struct radeon_device *rdev = dev->dev_private; |
| 774 | struct radeon_bo *rbo; |
| 775 | unsigned i = 0; |
| 776 | |
| 777 | mutex_lock(&rdev->gem.mutex); |
| 778 | list_for_each_entry(rbo, &rdev->gem.objects, list) { |
| 779 | unsigned domain; |
| 780 | const char *placement; |
| 781 | |
| 782 | domain = radeon_mem_type_to_domain(rbo->tbo.mem.mem_type); |
| 783 | switch (domain) { |
| 784 | case RADEON_GEM_DOMAIN_VRAM: |
| 785 | placement = "VRAM"; |
| 786 | break; |
| 787 | case RADEON_GEM_DOMAIN_GTT: |
| 788 | placement = " GTT"; |
| 789 | break; |
| 790 | case RADEON_GEM_DOMAIN_CPU: |
| 791 | default: |
| 792 | placement = " CPU"; |
| 793 | break; |
| 794 | } |
| 795 | seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n", |
| 796 | i, radeon_bo_size(rbo) >> 10, radeon_bo_size(rbo) >> 20, |
| 797 | placement, (unsigned long)rbo->pid); |
| 798 | i++; |
| 799 | } |
| 800 | mutex_unlock(&rdev->gem.mutex); |
| 801 | return 0; |
| 802 | } |
| 803 | |
| 804 | static struct drm_info_list radeon_debugfs_gem_list[] = { |
| 805 | {"radeon_gem_info", &radeon_debugfs_gem_info, 0, NULL}, |
| 806 | }; |
| 807 | #endif |
| 808 | |
| 809 | int radeon_gem_debugfs_init(struct radeon_device *rdev) |
| 810 | { |
| 811 | #if defined(CONFIG_DEBUG_FS) |
| 812 | return radeon_debugfs_add_files(rdev, radeon_debugfs_gem_list, 1); |
| 813 | #endif |
| 814 | return 0; |
| 815 | } |