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Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_OBJECT_H__
29#define __RADEON_OBJECT_H__
30
Jerome Glisse4c788672009-11-20 14:29:23 +010031#include <drm/radeon_drm.h>
32#include "radeon.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020033
Jerome Glisse4c788672009-11-20 14:29:23 +010034/**
35 * radeon_mem_type_to_domain - return domain corresponding to mem_type
36 * @mem_type: ttm memory type
37 *
38 * Returns corresponding domain of the ttm mem_type
Jerome Glisse771fe6b2009-06-05 14:42:42 +020039 */
Jerome Glisse4c788672009-11-20 14:29:23 +010040static inline unsigned radeon_mem_type_to_domain(u32 mem_type)
41{
42 switch (mem_type) {
43 case TTM_PL_VRAM:
44 return RADEON_GEM_DOMAIN_VRAM;
45 case TTM_PL_TT:
46 return RADEON_GEM_DOMAIN_GTT;
47 case TTM_PL_SYSTEM:
48 return RADEON_GEM_DOMAIN_CPU;
49 default:
50 break;
51 }
52 return 0;
53}
54
Maarten Lankhorstc43f9b12013-06-27 13:48:23 +020055/**
56 * radeon_bo_reserve - reserve bo
57 * @bo: bo structure
58 * @no_intr: don't return -ERESTARTSYS on pending signal
59 *
60 * Returns:
61 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
62 * a signal. Release all buffer reservations and return to user-space.
63 */
64static inline int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
65{
66 int r;
67
Christian Königdfd5e502016-04-06 11:12:03 +020068 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
Maarten Lankhorstc43f9b12013-06-27 13:48:23 +020069 if (unlikely(r != 0)) {
70 if (r != -ERESTARTSYS)
71 dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
72 return r;
73 }
74 return 0;
75}
Jerome Glisse4c788672009-11-20 14:29:23 +010076
77static inline void radeon_bo_unreserve(struct radeon_bo *bo)
78{
79 ttm_bo_unreserve(&bo->tbo);
80}
81
82/**
83 * radeon_bo_gpu_offset - return GPU offset of bo
84 * @bo: radeon object for which we query the offset
85 *
86 * Returns current GPU offset of the object.
87 *
88 * Note: object should either be pinned or reserved when calling this
Lucas De Marchi25985ed2011-03-30 22:57:33 -030089 * function, it might be useful to add check for this for debugging.
Jerome Glisse4c788672009-11-20 14:29:23 +010090 */
91static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)
92{
93 return bo->tbo.offset;
94}
95
96static inline unsigned long radeon_bo_size(struct radeon_bo *bo)
97{
98 return bo->tbo.num_pages << PAGE_SHIFT;
99}
100
Jerome Glisse721604a2012-01-05 22:11:05 -0500101static inline unsigned radeon_bo_ngpu_pages(struct radeon_bo *bo)
102{
103 return (bo->tbo.num_pages << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
104}
105
106static inline unsigned radeon_bo_gpu_page_alignment(struct radeon_bo *bo)
107{
108 return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
109}
110
Jerome Glisse4c788672009-11-20 14:29:23 +0100111/**
112 * radeon_bo_mmap_offset - return mmap offset of bo
113 * @bo: radeon object for which we query the offset
114 *
115 * Returns mmap offset of the object.
Jerome Glisse4c788672009-11-20 14:29:23 +0100116 */
117static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo)
118{
David Herrmann72525b32013-07-24 21:08:53 +0200119 return drm_vma_node_offset_addr(&bo->tbo.vma_node);
Jerome Glisse4c788672009-11-20 14:29:23 +0100120}
121
Andi Kleence580fa2011-10-13 16:08:47 -0700122extern int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type,
Dave Airlie83f30d02011-10-27 18:15:10 +0200123 bool no_wait);
Jerome Glisse4c788672009-11-20 14:29:23 +0100124
125extern int radeon_bo_create(struct radeon_device *rdev,
Alex Deucher40f5cf92012-05-10 18:33:13 -0400126 unsigned long size, int byte_align,
Michel Dänzer02376d82014-07-17 19:01:08 +0900127 bool kernel, u32 domain, u32 flags,
Alex Deucher40f5cf92012-05-10 18:33:13 -0400128 struct sg_table *sg,
Maarten Lankhorst831b6962014-09-18 14:11:56 +0200129 struct reservation_object *resv,
Alex Deucher40f5cf92012-05-10 18:33:13 -0400130 struct radeon_bo **bo_ptr);
Jerome Glisse4c788672009-11-20 14:29:23 +0100131extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr);
132extern void radeon_bo_kunmap(struct radeon_bo *bo);
Christian König512d8af2014-07-30 21:04:56 +0200133extern struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo);
Jerome Glisse4c788672009-11-20 14:29:23 +0100134extern void radeon_bo_unref(struct radeon_bo **bo);
135extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);
Michel Dänzerc4353012012-03-14 17:12:41 +0100136extern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain,
137 u64 max_offset, u64 *gpu_addr);
Jerome Glisse4c788672009-11-20 14:29:23 +0100138extern int radeon_bo_unpin(struct radeon_bo *bo);
139extern int radeon_bo_evict_vram(struct radeon_device *rdev);
140extern void radeon_bo_force_delete(struct radeon_device *rdev);
141extern int radeon_bo_init(struct radeon_device *rdev);
142extern void radeon_bo_fini(struct radeon_device *rdev);
Marek Olšák19dff562014-03-02 00:56:22 +0100143extern int radeon_bo_list_validate(struct radeon_device *rdev,
144 struct ww_acquire_ctx *ticket,
Maarten Lankhorstecff6652013-06-27 13:48:17 +0200145 struct list_head *head, int ring);
Jerome Glisse4c788672009-11-20 14:29:23 +0100146extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
147 u32 tiling_flags, u32 pitch);
148extern void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
149 u32 *tiling_flags, u32 *pitch);
150extern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
151 bool force_drop);
152extern void radeon_bo_move_notify(struct ttm_buffer_object *bo,
Marek Olšák67e8e3f2014-03-02 00:56:18 +0100153 struct ttm_mem_reg *new_mem);
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200154extern int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
Dave Airlie550e2d92009-12-09 14:15:38 +1000155extern int radeon_bo_get_surface_reg(struct radeon_bo *bo);
Christian König587cdda2014-11-19 14:01:23 +0100156extern void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
157 bool shared);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500158
159/*
160 * sub allocation
161 */
Christian Königdd8bea22012-05-09 15:34:49 +0200162
163static inline uint64_t radeon_sa_bo_gpu_addr(struct radeon_sa_bo *sa_bo)
164{
Christian Könige6661a92012-05-09 15:34:52 +0200165 return sa_bo->manager->gpu_addr + sa_bo->soffset;
Christian Königdd8bea22012-05-09 15:34:49 +0200166}
167
168static inline void * radeon_sa_bo_cpu_addr(struct radeon_sa_bo *sa_bo)
169{
Christian Könige6661a92012-05-09 15:34:52 +0200170 return sa_bo->manager->cpu_ptr + sa_bo->soffset;
Christian Königdd8bea22012-05-09 15:34:49 +0200171}
172
Jerome Glisseb15ba512011-11-15 11:48:34 -0500173extern int radeon_sa_bo_manager_init(struct radeon_device *rdev,
174 struct radeon_sa_manager *sa_manager,
Michel Dänzer02376d82014-07-17 19:01:08 +0900175 unsigned size, u32 align, u32 domain,
176 u32 flags);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500177extern void radeon_sa_bo_manager_fini(struct radeon_device *rdev,
178 struct radeon_sa_manager *sa_manager);
179extern int radeon_sa_bo_manager_start(struct radeon_device *rdev,
180 struct radeon_sa_manager *sa_manager);
181extern int radeon_sa_bo_manager_suspend(struct radeon_device *rdev,
182 struct radeon_sa_manager *sa_manager);
183extern int radeon_sa_bo_new(struct radeon_device *rdev,
184 struct radeon_sa_manager *sa_manager,
Christian König2e0d9912012-05-09 15:34:53 +0200185 struct radeon_sa_bo **sa_bo,
Christian König4d152642014-02-20 21:48:00 +0100186 unsigned size, unsigned align);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500187extern void radeon_sa_bo_free(struct radeon_device *rdev,
Christian König557017a2012-05-09 15:34:54 +0200188 struct radeon_sa_bo **sa_bo,
189 struct radeon_fence *fence);
Christian König711a9722012-05-09 15:34:51 +0200190#if defined(CONFIG_DEBUG_FS)
191extern void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager,
192 struct seq_file *m);
193#endif
194
Jerome Glisseb15ba512011-11-15 11:48:34 -0500195
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200196#endif