Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include "drmP.h" |
| 25 | #include "radeon.h" |
Michele Curti | 01467a9 | 2014-10-14 18:25:09 +0200 | [diff] [blame] | 26 | #include "radeon_asic.h" |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 27 | #include "sid.h" |
| 28 | #include "r600_dpm.h" |
| 29 | #include "si_dpm.h" |
| 30 | #include "atom.h" |
| 31 | #include <linux/math64.h> |
Mike Lothian | bf0936e | 2013-07-02 17:38:11 -0400 | [diff] [blame] | 32 | #include <linux/seq_file.h> |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 33 | |
| 34 | #define MC_CG_ARB_FREQ_F0 0x0a |
| 35 | #define MC_CG_ARB_FREQ_F1 0x0b |
| 36 | #define MC_CG_ARB_FREQ_F2 0x0c |
| 37 | #define MC_CG_ARB_FREQ_F3 0x0d |
| 38 | |
| 39 | #define SMC_RAM_END 0x20000 |
| 40 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 41 | #define SCLK_MIN_DEEPSLEEP_FREQ 1350 |
| 42 | |
| 43 | static const struct si_cac_config_reg cac_weights_tahiti[] = |
| 44 | { |
| 45 | { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, |
| 46 | { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 47 | { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, |
| 48 | { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, |
| 49 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 50 | { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 51 | { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 52 | { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 53 | { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 54 | { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, |
| 55 | { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 56 | { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, |
| 57 | { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, |
| 58 | { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, |
| 59 | { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, |
| 60 | { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 61 | { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 62 | { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, |
| 63 | { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 64 | { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, |
| 65 | { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, |
| 66 | { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, |
| 67 | { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 68 | { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 69 | { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 70 | { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 71 | { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 72 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 73 | { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 74 | { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 75 | { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, |
| 76 | { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 77 | { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 78 | { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 79 | { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, |
| 80 | { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 81 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 82 | { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 83 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 84 | { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, |
| 85 | { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 86 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 87 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 88 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 89 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 90 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 91 | { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 92 | { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 93 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 94 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 95 | { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 96 | { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 97 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 98 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 99 | { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 100 | { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 101 | { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 102 | { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 103 | { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 104 | { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, |
| 105 | { 0xFFFFFFFF } |
| 106 | }; |
| 107 | |
| 108 | static const struct si_cac_config_reg lcac_tahiti[] = |
| 109 | { |
| 110 | { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 111 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 112 | { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 113 | { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 114 | { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 115 | { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 116 | { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 117 | { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 118 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 119 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 120 | { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 121 | { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 122 | { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 123 | { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 124 | { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 125 | { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 126 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 127 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 128 | { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 129 | { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 130 | { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 131 | { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 132 | { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 133 | { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 134 | { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, |
| 135 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 136 | { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, |
| 137 | { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 138 | { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, |
| 139 | { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 140 | { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, |
| 141 | { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 142 | { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, |
| 143 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 144 | { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, |
| 145 | { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 146 | { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, |
| 147 | { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 148 | { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, |
| 149 | { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 150 | { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, |
| 151 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 152 | { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, |
| 153 | { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 154 | { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, |
| 155 | { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 156 | { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, |
| 157 | { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 158 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 159 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 160 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 161 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 162 | { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 163 | { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 164 | { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 165 | { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 166 | { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 167 | { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 168 | { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 169 | { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 170 | { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 171 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 172 | { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 173 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 174 | { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 175 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 176 | { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 177 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 178 | { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 179 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 180 | { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 181 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 182 | { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 183 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 184 | { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 185 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 186 | { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 187 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 188 | { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 189 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 190 | { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 191 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 192 | { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 193 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 194 | { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 195 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 196 | { 0xFFFFFFFF } |
| 197 | |
| 198 | }; |
| 199 | |
| 200 | static const struct si_cac_config_reg cac_override_tahiti[] = |
| 201 | { |
| 202 | { 0xFFFFFFFF } |
| 203 | }; |
| 204 | |
| 205 | static const struct si_powertune_data powertune_data_tahiti = |
| 206 | { |
| 207 | ((1 << 16) | 27027), |
| 208 | 6, |
| 209 | 0, |
| 210 | 4, |
| 211 | 95, |
| 212 | { |
| 213 | 0UL, |
| 214 | 0UL, |
| 215 | 4521550UL, |
| 216 | 309631529UL, |
| 217 | -1270850L, |
| 218 | 4513710L, |
| 219 | 40 |
| 220 | }, |
| 221 | 595000000UL, |
| 222 | 12, |
| 223 | { |
| 224 | 0, |
| 225 | 0, |
| 226 | 0, |
| 227 | 0, |
| 228 | 0, |
| 229 | 0, |
| 230 | 0, |
| 231 | 0 |
| 232 | }, |
| 233 | true |
| 234 | }; |
| 235 | |
| 236 | static const struct si_dte_data dte_data_tahiti = |
| 237 | { |
| 238 | { 1159409, 0, 0, 0, 0 }, |
| 239 | { 777, 0, 0, 0, 0 }, |
| 240 | 2, |
| 241 | 54000, |
| 242 | 127000, |
| 243 | 25, |
| 244 | 2, |
| 245 | 10, |
| 246 | 13, |
| 247 | { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, |
| 248 | { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, |
| 249 | { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, |
| 250 | 85, |
| 251 | false |
| 252 | }; |
| 253 | |
| 254 | static const struct si_dte_data dte_data_tahiti_le = |
| 255 | { |
| 256 | { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, |
| 257 | { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, |
| 258 | 0x5, |
| 259 | 0xAFC8, |
| 260 | 0x64, |
| 261 | 0x32, |
| 262 | 1, |
| 263 | 0, |
| 264 | 0x10, |
| 265 | { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, |
| 266 | { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, |
| 267 | { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, |
| 268 | 85, |
| 269 | true |
| 270 | }; |
| 271 | |
| 272 | static const struct si_dte_data dte_data_tahiti_pro = |
| 273 | { |
| 274 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, |
| 275 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 276 | 5, |
| 277 | 45000, |
| 278 | 100, |
| 279 | 0xA, |
| 280 | 1, |
| 281 | 0, |
| 282 | 0x10, |
| 283 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, |
| 284 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, |
| 285 | { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 286 | 90, |
| 287 | true |
| 288 | }; |
| 289 | |
| 290 | static const struct si_dte_data dte_data_new_zealand = |
| 291 | { |
| 292 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, |
| 293 | { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, |
| 294 | 0x5, |
| 295 | 0xAFC8, |
| 296 | 0x69, |
| 297 | 0x32, |
| 298 | 1, |
| 299 | 0, |
| 300 | 0x10, |
| 301 | { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, |
| 302 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, |
| 303 | { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, |
| 304 | 85, |
| 305 | true |
| 306 | }; |
| 307 | |
| 308 | static const struct si_dte_data dte_data_aruba_pro = |
| 309 | { |
| 310 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, |
| 311 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 312 | 5, |
| 313 | 45000, |
| 314 | 100, |
| 315 | 0xA, |
| 316 | 1, |
| 317 | 0, |
| 318 | 0x10, |
| 319 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, |
| 320 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, |
| 321 | { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 322 | 90, |
| 323 | true |
| 324 | }; |
| 325 | |
| 326 | static const struct si_dte_data dte_data_malta = |
| 327 | { |
| 328 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, |
| 329 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 330 | 5, |
| 331 | 45000, |
| 332 | 100, |
| 333 | 0xA, |
| 334 | 1, |
| 335 | 0, |
| 336 | 0x10, |
| 337 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, |
| 338 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, |
| 339 | { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 340 | 90, |
| 341 | true |
| 342 | }; |
| 343 | |
| 344 | struct si_cac_config_reg cac_weights_pitcairn[] = |
| 345 | { |
| 346 | { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, |
| 347 | { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 348 | { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 349 | { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, |
| 350 | { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, |
| 351 | { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, |
| 352 | { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 353 | { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, |
| 354 | { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 355 | { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, |
| 356 | { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, |
| 357 | { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, |
| 358 | { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, |
| 359 | { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, |
| 360 | { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 361 | { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 362 | { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 363 | { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, |
| 364 | { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, |
| 365 | { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, |
| 366 | { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, |
| 367 | { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, |
| 368 | { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, |
| 369 | { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 370 | { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 371 | { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, |
| 372 | { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, |
| 373 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 374 | { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 375 | { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 376 | { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, |
| 377 | { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 378 | { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, |
| 379 | { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 380 | { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, |
| 381 | { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, |
| 382 | { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, |
| 383 | { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 384 | { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, |
| 385 | { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 386 | { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 387 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 388 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 389 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 390 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 391 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 392 | { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 393 | { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 394 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 395 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 396 | { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 397 | { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 398 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 399 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 400 | { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 401 | { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 402 | { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 403 | { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 404 | { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 405 | { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, |
| 406 | { 0xFFFFFFFF } |
| 407 | }; |
| 408 | |
| 409 | static const struct si_cac_config_reg lcac_pitcairn[] = |
| 410 | { |
| 411 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 412 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 413 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 414 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 415 | { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 416 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 417 | { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 418 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 419 | { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 420 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 421 | { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 422 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 423 | { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 424 | { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 425 | { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 426 | { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 427 | { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 428 | { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 429 | { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 430 | { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 431 | { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 432 | { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 433 | { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 434 | { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 435 | { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 436 | { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 437 | { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 438 | { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 439 | { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 440 | { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 441 | { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 442 | { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 443 | { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 444 | { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 445 | { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 446 | { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 447 | { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 448 | { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 449 | { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 450 | { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 451 | { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 452 | { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 453 | { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 454 | { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 455 | { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 456 | { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 457 | { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 458 | { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 459 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 460 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 461 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 462 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 463 | { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 464 | { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 465 | { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 466 | { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 467 | { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 468 | { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 469 | { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 470 | { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 471 | { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 472 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 473 | { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 474 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 475 | { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 476 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 477 | { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 478 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 479 | { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 480 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 481 | { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 482 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 483 | { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 484 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 485 | { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 486 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 487 | { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 488 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 489 | { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 490 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 491 | { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 492 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 493 | { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 494 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 495 | { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 496 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 497 | { 0xFFFFFFFF } |
| 498 | }; |
| 499 | |
| 500 | static const struct si_cac_config_reg cac_override_pitcairn[] = |
| 501 | { |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 502 | { 0xFFFFFFFF } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 503 | }; |
| 504 | |
| 505 | static const struct si_powertune_data powertune_data_pitcairn = |
| 506 | { |
| 507 | ((1 << 16) | 27027), |
| 508 | 5, |
| 509 | 0, |
| 510 | 6, |
| 511 | 100, |
| 512 | { |
| 513 | 51600000UL, |
| 514 | 1800000UL, |
| 515 | 7194395UL, |
| 516 | 309631529UL, |
| 517 | -1270850L, |
| 518 | 4513710L, |
| 519 | 100 |
| 520 | }, |
| 521 | 117830498UL, |
| 522 | 12, |
| 523 | { |
| 524 | 0, |
| 525 | 0, |
| 526 | 0, |
| 527 | 0, |
| 528 | 0, |
| 529 | 0, |
| 530 | 0, |
| 531 | 0 |
| 532 | }, |
| 533 | true |
| 534 | }; |
| 535 | |
| 536 | static const struct si_dte_data dte_data_pitcairn = |
| 537 | { |
| 538 | { 0, 0, 0, 0, 0 }, |
| 539 | { 0, 0, 0, 0, 0 }, |
| 540 | 0, |
| 541 | 0, |
| 542 | 0, |
| 543 | 0, |
| 544 | 0, |
| 545 | 0, |
| 546 | 0, |
| 547 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
| 548 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
| 549 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
| 550 | 0, |
| 551 | false |
| 552 | }; |
| 553 | |
| 554 | static const struct si_dte_data dte_data_curacao_xt = |
| 555 | { |
| 556 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, |
| 557 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 558 | 5, |
| 559 | 45000, |
| 560 | 100, |
| 561 | 0xA, |
| 562 | 1, |
| 563 | 0, |
| 564 | 0x10, |
| 565 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, |
| 566 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, |
| 567 | { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 568 | 90, |
| 569 | true |
| 570 | }; |
| 571 | |
| 572 | static const struct si_dte_data dte_data_curacao_pro = |
| 573 | { |
| 574 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, |
| 575 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 576 | 5, |
| 577 | 45000, |
| 578 | 100, |
| 579 | 0xA, |
| 580 | 1, |
| 581 | 0, |
| 582 | 0x10, |
| 583 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, |
| 584 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, |
| 585 | { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 586 | 90, |
| 587 | true |
| 588 | }; |
| 589 | |
| 590 | static const struct si_dte_data dte_data_neptune_xt = |
| 591 | { |
| 592 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, |
| 593 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 594 | 5, |
| 595 | 45000, |
| 596 | 100, |
| 597 | 0xA, |
| 598 | 1, |
| 599 | 0, |
| 600 | 0x10, |
| 601 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, |
| 602 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, |
| 603 | { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 604 | 90, |
| 605 | true |
| 606 | }; |
| 607 | |
| 608 | static const struct si_cac_config_reg cac_weights_chelsea_pro[] = |
| 609 | { |
| 610 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, |
| 611 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |
| 612 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, |
| 613 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, |
| 614 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 615 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, |
| 616 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |
| 617 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, |
| 618 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, |
| 619 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, |
| 620 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, |
| 621 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, |
| 622 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, |
| 623 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, |
| 624 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, |
| 625 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, |
| 626 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, |
| 627 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, |
| 628 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, |
| 629 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, |
| 630 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, |
| 631 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, |
| 632 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, |
| 633 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, |
| 634 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, |
| 635 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 636 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 637 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 638 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 639 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 640 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 641 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, |
| 642 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, |
| 643 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 644 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 645 | { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, |
| 646 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 647 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 648 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 649 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, |
| 650 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, |
| 651 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 652 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 653 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 654 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 655 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 656 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 657 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 658 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 659 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 660 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 661 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 662 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 663 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 664 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 665 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 666 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 667 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 668 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 669 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, |
| 670 | { 0xFFFFFFFF } |
| 671 | }; |
| 672 | |
| 673 | static const struct si_cac_config_reg cac_weights_chelsea_xt[] = |
| 674 | { |
| 675 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, |
| 676 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |
| 677 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, |
| 678 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, |
| 679 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 680 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, |
| 681 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |
| 682 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, |
| 683 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, |
| 684 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, |
| 685 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, |
| 686 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, |
| 687 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, |
| 688 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, |
| 689 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, |
| 690 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, |
| 691 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, |
| 692 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, |
| 693 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, |
| 694 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, |
| 695 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, |
| 696 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, |
| 697 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, |
| 698 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, |
| 699 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, |
| 700 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 701 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 702 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 703 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 704 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 705 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 706 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, |
| 707 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, |
| 708 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 709 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 710 | { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, |
| 711 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 712 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 713 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 714 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, |
| 715 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, |
| 716 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 717 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 718 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 719 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 720 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 721 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 722 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 723 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 724 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 725 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 726 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 727 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 728 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 729 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 730 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 731 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 732 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 733 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 734 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, |
| 735 | { 0xFFFFFFFF } |
| 736 | }; |
| 737 | |
| 738 | static const struct si_cac_config_reg cac_weights_heathrow[] = |
| 739 | { |
| 740 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, |
| 741 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |
| 742 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, |
| 743 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, |
| 744 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 745 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, |
| 746 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |
| 747 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, |
| 748 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, |
| 749 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, |
| 750 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, |
| 751 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, |
| 752 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, |
| 753 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, |
| 754 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, |
| 755 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, |
| 756 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, |
| 757 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, |
| 758 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, |
| 759 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, |
| 760 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, |
| 761 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, |
| 762 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, |
| 763 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, |
| 764 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, |
| 765 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 766 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 767 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 768 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 769 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 770 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 771 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, |
| 772 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, |
| 773 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 774 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 775 | { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, |
| 776 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 777 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 778 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 779 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, |
| 780 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, |
| 781 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 782 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 783 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 784 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 785 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 786 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 787 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 788 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 789 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 790 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 791 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 792 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 793 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 794 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 795 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 796 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 797 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 798 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 799 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, |
| 800 | { 0xFFFFFFFF } |
| 801 | }; |
| 802 | |
| 803 | static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = |
| 804 | { |
| 805 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, |
| 806 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |
| 807 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, |
| 808 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, |
| 809 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 810 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, |
| 811 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |
| 812 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, |
| 813 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, |
| 814 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, |
| 815 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, |
| 816 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, |
| 817 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, |
| 818 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, |
| 819 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, |
| 820 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, |
| 821 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, |
| 822 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, |
| 823 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, |
| 824 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, |
| 825 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, |
| 826 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, |
| 827 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, |
| 828 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, |
| 829 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, |
| 830 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 831 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 832 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 833 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 834 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 835 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 836 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, |
| 837 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, |
| 838 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 839 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 840 | { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, |
| 841 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 842 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 843 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 844 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, |
| 845 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, |
| 846 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 847 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 848 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 849 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 850 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 851 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 852 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 853 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 854 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 855 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 856 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 857 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 858 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 859 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 860 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 861 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 862 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 863 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 864 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, |
| 865 | { 0xFFFFFFFF } |
| 866 | }; |
| 867 | |
| 868 | static const struct si_cac_config_reg cac_weights_cape_verde[] = |
| 869 | { |
| 870 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, |
| 871 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |
| 872 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, |
| 873 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, |
| 874 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 875 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, |
| 876 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |
| 877 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, |
| 878 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, |
| 879 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, |
| 880 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, |
| 881 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, |
| 882 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, |
| 883 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, |
| 884 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, |
| 885 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, |
| 886 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, |
| 887 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, |
| 888 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, |
| 889 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, |
| 890 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, |
| 891 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, |
| 892 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, |
| 893 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, |
| 894 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, |
| 895 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 896 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 897 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 898 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 899 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 900 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 901 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, |
| 902 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, |
| 903 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 904 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 905 | { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, |
| 906 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 907 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 908 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 909 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, |
| 910 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, |
| 911 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 912 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 913 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 914 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 915 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 916 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 917 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 918 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 919 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 920 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 921 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 922 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 923 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 924 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 925 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 926 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 927 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 928 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 929 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, |
| 930 | { 0xFFFFFFFF } |
| 931 | }; |
| 932 | |
| 933 | static const struct si_cac_config_reg lcac_cape_verde[] = |
| 934 | { |
| 935 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 936 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 937 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 938 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 939 | { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 940 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 941 | { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 942 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 943 | { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 944 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 945 | { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 946 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 947 | { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 948 | { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 949 | { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 950 | { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 951 | { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 952 | { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 953 | { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 954 | { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 955 | { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 956 | { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 957 | { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 958 | { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 959 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 960 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 961 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 962 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 963 | { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 964 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 965 | { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 966 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 967 | { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 968 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 969 | { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 970 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 971 | { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 972 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 973 | { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 974 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 975 | { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 976 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 977 | { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 978 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 979 | { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 980 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 981 | { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 982 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 983 | { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 984 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 985 | { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 986 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 987 | { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 988 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 989 | { 0xFFFFFFFF } |
| 990 | }; |
| 991 | |
| 992 | static const struct si_cac_config_reg cac_override_cape_verde[] = |
| 993 | { |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 994 | { 0xFFFFFFFF } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 995 | }; |
| 996 | |
| 997 | static const struct si_powertune_data powertune_data_cape_verde = |
| 998 | { |
| 999 | ((1 << 16) | 0x6993), |
| 1000 | 5, |
| 1001 | 0, |
| 1002 | 7, |
| 1003 | 105, |
| 1004 | { |
| 1005 | 0UL, |
| 1006 | 0UL, |
| 1007 | 7194395UL, |
| 1008 | 309631529UL, |
| 1009 | -1270850L, |
| 1010 | 4513710L, |
| 1011 | 100 |
| 1012 | }, |
| 1013 | 117830498UL, |
| 1014 | 12, |
| 1015 | { |
| 1016 | 0, |
| 1017 | 0, |
| 1018 | 0, |
| 1019 | 0, |
| 1020 | 0, |
| 1021 | 0, |
| 1022 | 0, |
| 1023 | 0 |
| 1024 | }, |
| 1025 | true |
| 1026 | }; |
| 1027 | |
| 1028 | static const struct si_dte_data dte_data_cape_verde = |
| 1029 | { |
| 1030 | { 0, 0, 0, 0, 0 }, |
| 1031 | { 0, 0, 0, 0, 0 }, |
| 1032 | 0, |
| 1033 | 0, |
| 1034 | 0, |
| 1035 | 0, |
| 1036 | 0, |
| 1037 | 0, |
| 1038 | 0, |
| 1039 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
| 1040 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
| 1041 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
| 1042 | 0, |
| 1043 | false |
| 1044 | }; |
| 1045 | |
| 1046 | static const struct si_dte_data dte_data_venus_xtx = |
| 1047 | { |
| 1048 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, |
| 1049 | { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, |
| 1050 | 5, |
| 1051 | 55000, |
| 1052 | 0x69, |
| 1053 | 0xA, |
| 1054 | 1, |
| 1055 | 0, |
| 1056 | 0x3, |
| 1057 | { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1058 | { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1059 | { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1060 | 90, |
| 1061 | true |
| 1062 | }; |
| 1063 | |
| 1064 | static const struct si_dte_data dte_data_venus_xt = |
| 1065 | { |
| 1066 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, |
| 1067 | { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, |
| 1068 | 5, |
| 1069 | 55000, |
| 1070 | 0x69, |
| 1071 | 0xA, |
| 1072 | 1, |
| 1073 | 0, |
| 1074 | 0x3, |
| 1075 | { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1076 | { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1077 | { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1078 | 90, |
| 1079 | true |
| 1080 | }; |
| 1081 | |
| 1082 | static const struct si_dte_data dte_data_venus_pro = |
| 1083 | { |
| 1084 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, |
| 1085 | { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, |
| 1086 | 5, |
| 1087 | 55000, |
| 1088 | 0x69, |
| 1089 | 0xA, |
| 1090 | 1, |
| 1091 | 0, |
| 1092 | 0x3, |
| 1093 | { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1094 | { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1095 | { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1096 | 90, |
| 1097 | true |
| 1098 | }; |
| 1099 | |
| 1100 | struct si_cac_config_reg cac_weights_oland[] = |
| 1101 | { |
| 1102 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, |
| 1103 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |
| 1104 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, |
| 1105 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, |
| 1106 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1107 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, |
| 1108 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |
| 1109 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, |
| 1110 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, |
| 1111 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, |
| 1112 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, |
| 1113 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, |
| 1114 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, |
| 1115 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, |
| 1116 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, |
| 1117 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, |
| 1118 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, |
| 1119 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, |
| 1120 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, |
| 1121 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, |
| 1122 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, |
| 1123 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, |
| 1124 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, |
| 1125 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, |
| 1126 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, |
| 1127 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 1128 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 1129 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1130 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1131 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1132 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 1133 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, |
| 1134 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, |
| 1135 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 1136 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 1137 | { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, |
| 1138 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1139 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 1140 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1141 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, |
| 1142 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, |
| 1143 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1144 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1145 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1146 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1147 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1148 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1149 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1150 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1151 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1152 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1153 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1154 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1155 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1156 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1157 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1158 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1159 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1160 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1161 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, |
| 1162 | { 0xFFFFFFFF } |
| 1163 | }; |
| 1164 | |
| 1165 | static const struct si_cac_config_reg cac_weights_mars_pro[] = |
| 1166 | { |
| 1167 | { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, |
| 1168 | { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, |
| 1169 | { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, |
| 1170 | { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, |
| 1171 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1172 | { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, |
| 1173 | { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, |
| 1174 | { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, |
| 1175 | { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, |
| 1176 | { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, |
| 1177 | { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, |
| 1178 | { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, |
| 1179 | { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, |
| 1180 | { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, |
| 1181 | { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, |
| 1182 | { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, |
| 1183 | { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, |
| 1184 | { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, |
| 1185 | { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, |
| 1186 | { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, |
| 1187 | { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, |
| 1188 | { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, |
| 1189 | { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, |
| 1190 | { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 1191 | { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 1192 | { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, |
| 1193 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 1194 | { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1195 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1196 | { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 1197 | { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, |
| 1198 | { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, |
| 1199 | { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, |
| 1200 | { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, |
| 1201 | { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, |
| 1202 | { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1203 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1204 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 1205 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1206 | { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, |
| 1207 | { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, |
| 1208 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1209 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1210 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1211 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1212 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1213 | { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, |
| 1214 | { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, |
| 1215 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1216 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1217 | { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, |
| 1218 | { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, |
| 1219 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1220 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1221 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1222 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1223 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1224 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1225 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1226 | { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, |
| 1227 | { 0xFFFFFFFF } |
| 1228 | }; |
| 1229 | |
| 1230 | static const struct si_cac_config_reg cac_weights_mars_xt[] = |
| 1231 | { |
| 1232 | { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, |
| 1233 | { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, |
| 1234 | { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, |
| 1235 | { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, |
| 1236 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1237 | { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, |
| 1238 | { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, |
| 1239 | { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, |
| 1240 | { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, |
| 1241 | { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, |
| 1242 | { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, |
| 1243 | { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, |
| 1244 | { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, |
| 1245 | { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, |
| 1246 | { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, |
| 1247 | { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, |
| 1248 | { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, |
| 1249 | { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, |
| 1250 | { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, |
| 1251 | { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, |
| 1252 | { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, |
| 1253 | { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, |
| 1254 | { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, |
| 1255 | { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 1256 | { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 1257 | { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, |
| 1258 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 1259 | { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1260 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1261 | { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 1262 | { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, |
| 1263 | { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, |
| 1264 | { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, |
| 1265 | { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, |
| 1266 | { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, |
| 1267 | { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, |
| 1268 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1269 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 1270 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1271 | { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, |
| 1272 | { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, |
| 1273 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1274 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1275 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1276 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1277 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1278 | { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, |
| 1279 | { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, |
| 1280 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1281 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1282 | { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, |
| 1283 | { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, |
| 1284 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1285 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1286 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1287 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1288 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1289 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1290 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1291 | { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, |
| 1292 | { 0xFFFFFFFF } |
| 1293 | }; |
| 1294 | |
| 1295 | static const struct si_cac_config_reg cac_weights_oland_pro[] = |
| 1296 | { |
| 1297 | { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, |
| 1298 | { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, |
| 1299 | { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, |
| 1300 | { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, |
| 1301 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1302 | { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, |
| 1303 | { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, |
| 1304 | { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, |
| 1305 | { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, |
| 1306 | { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, |
| 1307 | { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, |
| 1308 | { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, |
| 1309 | { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, |
| 1310 | { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, |
| 1311 | { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, |
| 1312 | { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, |
| 1313 | { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, |
| 1314 | { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, |
| 1315 | { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, |
| 1316 | { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, |
| 1317 | { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, |
| 1318 | { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, |
| 1319 | { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, |
| 1320 | { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 1321 | { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 1322 | { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, |
| 1323 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 1324 | { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1325 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1326 | { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 1327 | { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, |
| 1328 | { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, |
| 1329 | { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, |
| 1330 | { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, |
| 1331 | { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, |
| 1332 | { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, |
| 1333 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1334 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 1335 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1336 | { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, |
| 1337 | { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, |
| 1338 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1339 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1340 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1341 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1342 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1343 | { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, |
| 1344 | { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, |
| 1345 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1346 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1347 | { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, |
| 1348 | { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, |
| 1349 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1350 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1351 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1352 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1353 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1354 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1355 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1356 | { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, |
| 1357 | { 0xFFFFFFFF } |
| 1358 | }; |
| 1359 | |
| 1360 | static const struct si_cac_config_reg cac_weights_oland_xt[] = |
| 1361 | { |
| 1362 | { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, |
| 1363 | { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, |
| 1364 | { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, |
| 1365 | { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, |
| 1366 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1367 | { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, |
| 1368 | { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, |
| 1369 | { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, |
| 1370 | { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, |
| 1371 | { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, |
| 1372 | { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, |
| 1373 | { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, |
| 1374 | { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, |
| 1375 | { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, |
| 1376 | { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, |
| 1377 | { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, |
| 1378 | { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, |
| 1379 | { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, |
| 1380 | { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, |
| 1381 | { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, |
| 1382 | { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, |
| 1383 | { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, |
| 1384 | { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, |
| 1385 | { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 1386 | { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, |
| 1387 | { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, |
| 1388 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, |
| 1389 | { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1390 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1391 | { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 1392 | { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, |
| 1393 | { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, |
| 1394 | { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, |
| 1395 | { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, |
| 1396 | { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, |
| 1397 | { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, |
| 1398 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1399 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 1400 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1401 | { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, |
| 1402 | { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, |
| 1403 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1404 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1405 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1406 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1407 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1408 | { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, |
| 1409 | { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, |
| 1410 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1411 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1412 | { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, |
| 1413 | { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, |
| 1414 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1415 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1416 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1417 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1418 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1419 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1420 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1421 | { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, |
| 1422 | { 0xFFFFFFFF } |
| 1423 | }; |
| 1424 | |
| 1425 | static const struct si_cac_config_reg lcac_oland[] = |
| 1426 | { |
| 1427 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1428 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1429 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1430 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1431 | { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 1432 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1433 | { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 1434 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1435 | { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 1436 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1437 | { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, |
| 1438 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1439 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1440 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1441 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1442 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1443 | { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1444 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1445 | { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1446 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1447 | { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1448 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1449 | { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1450 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1451 | { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1452 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1453 | { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1454 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1455 | { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1456 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1457 | { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1458 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1459 | { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1460 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1461 | { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1462 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1463 | { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1464 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1465 | { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1466 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1467 | { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1468 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1469 | { 0xFFFFFFFF } |
| 1470 | }; |
| 1471 | |
| 1472 | static const struct si_cac_config_reg lcac_mars_pro[] = |
| 1473 | { |
| 1474 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1475 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1476 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1477 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1478 | { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 1479 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1480 | { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 1481 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1482 | { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, |
| 1483 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1484 | { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1485 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1486 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1487 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1488 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1489 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1490 | { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1491 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1492 | { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1493 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1494 | { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1495 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1496 | { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1497 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1498 | { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1499 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1500 | { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1501 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1502 | { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, |
| 1503 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1504 | { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1505 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1506 | { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1507 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1508 | { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1509 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1510 | { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1511 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1512 | { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1513 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1514 | { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1515 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, |
| 1516 | { 0xFFFFFFFF } |
| 1517 | }; |
| 1518 | |
| 1519 | static const struct si_cac_config_reg cac_override_oland[] = |
| 1520 | { |
| 1521 | { 0xFFFFFFFF } |
| 1522 | }; |
| 1523 | |
| 1524 | static const struct si_powertune_data powertune_data_oland = |
| 1525 | { |
| 1526 | ((1 << 16) | 0x6993), |
| 1527 | 5, |
| 1528 | 0, |
| 1529 | 7, |
| 1530 | 105, |
| 1531 | { |
| 1532 | 0UL, |
| 1533 | 0UL, |
| 1534 | 7194395UL, |
| 1535 | 309631529UL, |
| 1536 | -1270850L, |
| 1537 | 4513710L, |
| 1538 | 100 |
| 1539 | }, |
| 1540 | 117830498UL, |
| 1541 | 12, |
| 1542 | { |
| 1543 | 0, |
| 1544 | 0, |
| 1545 | 0, |
| 1546 | 0, |
| 1547 | 0, |
| 1548 | 0, |
| 1549 | 0, |
| 1550 | 0 |
| 1551 | }, |
| 1552 | true |
| 1553 | }; |
| 1554 | |
| 1555 | static const struct si_powertune_data powertune_data_mars_pro = |
| 1556 | { |
| 1557 | ((1 << 16) | 0x6993), |
| 1558 | 5, |
| 1559 | 0, |
| 1560 | 7, |
| 1561 | 105, |
| 1562 | { |
| 1563 | 0UL, |
| 1564 | 0UL, |
| 1565 | 7194395UL, |
| 1566 | 309631529UL, |
| 1567 | -1270850L, |
| 1568 | 4513710L, |
| 1569 | 100 |
| 1570 | }, |
| 1571 | 117830498UL, |
| 1572 | 12, |
| 1573 | { |
| 1574 | 0, |
| 1575 | 0, |
| 1576 | 0, |
| 1577 | 0, |
| 1578 | 0, |
| 1579 | 0, |
| 1580 | 0, |
| 1581 | 0 |
| 1582 | }, |
| 1583 | true |
| 1584 | }; |
| 1585 | |
| 1586 | static const struct si_dte_data dte_data_oland = |
| 1587 | { |
| 1588 | { 0, 0, 0, 0, 0 }, |
| 1589 | { 0, 0, 0, 0, 0 }, |
| 1590 | 0, |
| 1591 | 0, |
| 1592 | 0, |
| 1593 | 0, |
| 1594 | 0, |
| 1595 | 0, |
| 1596 | 0, |
| 1597 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
| 1598 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
| 1599 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
| 1600 | 0, |
| 1601 | false |
| 1602 | }; |
| 1603 | |
| 1604 | static const struct si_dte_data dte_data_mars_pro = |
| 1605 | { |
| 1606 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, |
| 1607 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1608 | 5, |
| 1609 | 55000, |
| 1610 | 105, |
| 1611 | 0xA, |
| 1612 | 1, |
| 1613 | 0, |
| 1614 | 0x10, |
| 1615 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, |
| 1616 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, |
| 1617 | { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1618 | 90, |
| 1619 | true |
| 1620 | }; |
| 1621 | |
| 1622 | static const struct si_dte_data dte_data_sun_xt = |
| 1623 | { |
| 1624 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, |
| 1625 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1626 | 5, |
| 1627 | 55000, |
| 1628 | 105, |
| 1629 | 0xA, |
| 1630 | 1, |
| 1631 | 0, |
| 1632 | 0x10, |
| 1633 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, |
| 1634 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, |
| 1635 | { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |
| 1636 | 90, |
| 1637 | true |
| 1638 | }; |
| 1639 | |
| 1640 | |
| 1641 | static const struct si_cac_config_reg cac_weights_hainan[] = |
| 1642 | { |
| 1643 | { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, |
| 1644 | { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, |
| 1645 | { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, |
| 1646 | { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, |
| 1647 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1648 | { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, |
| 1649 | { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1650 | { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1651 | { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1652 | { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, |
| 1653 | { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, |
| 1654 | { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, |
| 1655 | { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, |
| 1656 | { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1657 | { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, |
| 1658 | { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1659 | { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1660 | { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, |
| 1661 | { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, |
| 1662 | { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, |
| 1663 | { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, |
| 1664 | { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, |
| 1665 | { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, |
| 1666 | { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, |
| 1667 | { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1668 | { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, |
| 1669 | { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, |
| 1670 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1671 | { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1672 | { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1673 | { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, |
| 1674 | { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1675 | { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1676 | { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1677 | { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, |
| 1678 | { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, |
| 1679 | { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, |
| 1680 | { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1681 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1682 | { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, |
| 1683 | { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1684 | { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, |
| 1685 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1686 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1687 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1688 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, |
| 1689 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1690 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1691 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1692 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1693 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1694 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1695 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1696 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1697 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1698 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1699 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1700 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1701 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, |
| 1702 | { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, |
| 1703 | { 0xFFFFFFFF } |
| 1704 | }; |
| 1705 | |
| 1706 | static const struct si_powertune_data powertune_data_hainan = |
| 1707 | { |
| 1708 | ((1 << 16) | 0x6993), |
| 1709 | 5, |
| 1710 | 0, |
| 1711 | 9, |
| 1712 | 105, |
| 1713 | { |
| 1714 | 0UL, |
| 1715 | 0UL, |
| 1716 | 7194395UL, |
| 1717 | 309631529UL, |
| 1718 | -1270850L, |
| 1719 | 4513710L, |
| 1720 | 100 |
| 1721 | }, |
| 1722 | 117830498UL, |
| 1723 | 12, |
| 1724 | { |
| 1725 | 0, |
| 1726 | 0, |
| 1727 | 0, |
| 1728 | 0, |
| 1729 | 0, |
| 1730 | 0, |
| 1731 | 0, |
| 1732 | 0 |
| 1733 | }, |
| 1734 | true |
| 1735 | }; |
| 1736 | |
| 1737 | struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); |
| 1738 | struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); |
| 1739 | struct ni_power_info *ni_get_pi(struct radeon_device *rdev); |
| 1740 | struct ni_ps *ni_get_ps(struct radeon_ps *rps); |
| 1741 | |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 1742 | extern int si_mc_load_microcode(struct radeon_device *rdev); |
Alex Deucher | 84bcd46 | 2015-05-11 22:01:55 +0200 | [diff] [blame] | 1743 | extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 1744 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1745 | static int si_populate_voltage_value(struct radeon_device *rdev, |
| 1746 | const struct atom_voltage_table *table, |
| 1747 | u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); |
| 1748 | static int si_get_std_voltage_value(struct radeon_device *rdev, |
| 1749 | SISLANDS_SMC_VOLTAGE_VALUE *voltage, |
| 1750 | u16 *std_voltage); |
| 1751 | static int si_write_smc_soft_register(struct radeon_device *rdev, |
| 1752 | u16 reg_offset, u32 value); |
| 1753 | static int si_convert_power_level_to_smc(struct radeon_device *rdev, |
| 1754 | struct rv7xx_pl *pl, |
| 1755 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); |
| 1756 | static int si_calculate_sclk_params(struct radeon_device *rdev, |
| 1757 | u32 engine_clock, |
| 1758 | SISLANDS_SMC_SCLK_VALUE *sclk); |
| 1759 | |
Alex Deucher | 5e8150a | 2015-01-07 15:29:06 -0500 | [diff] [blame] | 1760 | static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); |
| 1761 | static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); |
| 1762 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1763 | static struct si_power_info *si_get_pi(struct radeon_device *rdev) |
| 1764 | { |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 1765 | struct si_power_info *pi = rdev->pm.dpm.priv; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1766 | |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 1767 | return pi; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1768 | } |
| 1769 | |
| 1770 | static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, |
| 1771 | u16 v, s32 t, u32 ileakage, u32 *leakage) |
| 1772 | { |
| 1773 | s64 kt, kv, leakage_w, i_leakage, vddc; |
| 1774 | s64 temperature, t_slope, t_intercept, av, bv, t_ref; |
Alex Deucher | 31f731a | 2013-07-30 16:56:52 -0400 | [diff] [blame] | 1775 | s64 tmp; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1776 | |
Alex Deucher | adfb8e5 | 2013-08-01 09:03:29 -0400 | [diff] [blame] | 1777 | i_leakage = div64_s64(drm_int2fixp(ileakage), 100); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1778 | vddc = div64_s64(drm_int2fixp(v), 1000); |
| 1779 | temperature = div64_s64(drm_int2fixp(t), 1000); |
| 1780 | |
| 1781 | t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); |
| 1782 | t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); |
| 1783 | av = div64_s64(drm_int2fixp(coeff->av), 100000000); |
| 1784 | bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); |
| 1785 | t_ref = drm_int2fixp(coeff->t_ref); |
| 1786 | |
Alex Deucher | 31f731a | 2013-07-30 16:56:52 -0400 | [diff] [blame] | 1787 | tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; |
| 1788 | kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); |
| 1789 | kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1790 | kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); |
| 1791 | |
| 1792 | leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); |
| 1793 | |
| 1794 | *leakage = drm_fixp2int(leakage_w * 1000); |
| 1795 | } |
| 1796 | |
| 1797 | static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, |
| 1798 | const struct ni_leakage_coeffients *coeff, |
| 1799 | u16 v, |
| 1800 | s32 t, |
| 1801 | u32 i_leakage, |
| 1802 | u32 *leakage) |
| 1803 | { |
| 1804 | si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); |
| 1805 | } |
| 1806 | |
| 1807 | static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, |
| 1808 | const u32 fixed_kt, u16 v, |
| 1809 | u32 ileakage, u32 *leakage) |
| 1810 | { |
| 1811 | s64 kt, kv, leakage_w, i_leakage, vddc; |
| 1812 | |
| 1813 | i_leakage = div64_s64(drm_int2fixp(ileakage), 100); |
| 1814 | vddc = div64_s64(drm_int2fixp(v), 1000); |
| 1815 | |
| 1816 | kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); |
| 1817 | kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), |
| 1818 | drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); |
| 1819 | |
| 1820 | leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); |
| 1821 | |
| 1822 | *leakage = drm_fixp2int(leakage_w * 1000); |
| 1823 | } |
| 1824 | |
| 1825 | static void si_calculate_leakage_for_v(struct radeon_device *rdev, |
| 1826 | const struct ni_leakage_coeffients *coeff, |
| 1827 | const u32 fixed_kt, |
| 1828 | u16 v, |
| 1829 | u32 i_leakage, |
| 1830 | u32 *leakage) |
| 1831 | { |
| 1832 | si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); |
| 1833 | } |
| 1834 | |
| 1835 | |
| 1836 | static void si_update_dte_from_pl2(struct radeon_device *rdev, |
| 1837 | struct si_dte_data *dte_data) |
| 1838 | { |
| 1839 | u32 p_limit1 = rdev->pm.dpm.tdp_limit; |
| 1840 | u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; |
| 1841 | u32 k = dte_data->k; |
| 1842 | u32 t_max = dte_data->max_t; |
| 1843 | u32 t_split[5] = { 10, 15, 20, 25, 30 }; |
| 1844 | u32 t_0 = dte_data->t0; |
| 1845 | u32 i; |
| 1846 | |
| 1847 | if (p_limit2 != 0 && p_limit2 <= p_limit1) { |
| 1848 | dte_data->tdep_count = 3; |
| 1849 | |
| 1850 | for (i = 0; i < k; i++) { |
| 1851 | dte_data->r[i] = |
| 1852 | (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / |
| 1853 | (p_limit2 * (u32)100); |
| 1854 | } |
| 1855 | |
| 1856 | dte_data->tdep_r[1] = dte_data->r[4] * 2; |
| 1857 | |
| 1858 | for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { |
| 1859 | dte_data->tdep_r[i] = dte_data->r[4]; |
| 1860 | } |
| 1861 | } else { |
| 1862 | DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); |
| 1863 | } |
| 1864 | } |
| 1865 | |
| 1866 | static void si_initialize_powertune_defaults(struct radeon_device *rdev) |
| 1867 | { |
| 1868 | struct ni_power_info *ni_pi = ni_get_pi(rdev); |
| 1869 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 1870 | bool update_dte_from_pl2 = false; |
| 1871 | |
| 1872 | if (rdev->family == CHIP_TAHITI) { |
| 1873 | si_pi->cac_weights = cac_weights_tahiti; |
| 1874 | si_pi->lcac_config = lcac_tahiti; |
| 1875 | si_pi->cac_override = cac_override_tahiti; |
| 1876 | si_pi->powertune_data = &powertune_data_tahiti; |
| 1877 | si_pi->dte_data = dte_data_tahiti; |
| 1878 | |
| 1879 | switch (rdev->pdev->device) { |
| 1880 | case 0x6798: |
| 1881 | si_pi->dte_data.enable_dte_by_default = true; |
| 1882 | break; |
| 1883 | case 0x6799: |
| 1884 | si_pi->dte_data = dte_data_new_zealand; |
| 1885 | break; |
| 1886 | case 0x6790: |
| 1887 | case 0x6791: |
| 1888 | case 0x6792: |
| 1889 | case 0x679E: |
| 1890 | si_pi->dte_data = dte_data_aruba_pro; |
| 1891 | update_dte_from_pl2 = true; |
| 1892 | break; |
| 1893 | case 0x679B: |
| 1894 | si_pi->dte_data = dte_data_malta; |
| 1895 | update_dte_from_pl2 = true; |
| 1896 | break; |
| 1897 | case 0x679A: |
| 1898 | si_pi->dte_data = dte_data_tahiti_pro; |
| 1899 | update_dte_from_pl2 = true; |
| 1900 | break; |
| 1901 | default: |
| 1902 | if (si_pi->dte_data.enable_dte_by_default == true) |
| 1903 | DRM_ERROR("DTE is not enabled!\n"); |
| 1904 | break; |
| 1905 | } |
| 1906 | } else if (rdev->family == CHIP_PITCAIRN) { |
| 1907 | switch (rdev->pdev->device) { |
| 1908 | case 0x6810: |
| 1909 | case 0x6818: |
| 1910 | si_pi->cac_weights = cac_weights_pitcairn; |
| 1911 | si_pi->lcac_config = lcac_pitcairn; |
| 1912 | si_pi->cac_override = cac_override_pitcairn; |
| 1913 | si_pi->powertune_data = &powertune_data_pitcairn; |
| 1914 | si_pi->dte_data = dte_data_curacao_xt; |
| 1915 | update_dte_from_pl2 = true; |
| 1916 | break; |
| 1917 | case 0x6819: |
| 1918 | case 0x6811: |
| 1919 | si_pi->cac_weights = cac_weights_pitcairn; |
| 1920 | si_pi->lcac_config = lcac_pitcairn; |
| 1921 | si_pi->cac_override = cac_override_pitcairn; |
| 1922 | si_pi->powertune_data = &powertune_data_pitcairn; |
| 1923 | si_pi->dte_data = dte_data_curacao_pro; |
| 1924 | update_dte_from_pl2 = true; |
| 1925 | break; |
| 1926 | case 0x6800: |
| 1927 | case 0x6806: |
| 1928 | si_pi->cac_weights = cac_weights_pitcairn; |
| 1929 | si_pi->lcac_config = lcac_pitcairn; |
| 1930 | si_pi->cac_override = cac_override_pitcairn; |
| 1931 | si_pi->powertune_data = &powertune_data_pitcairn; |
| 1932 | si_pi->dte_data = dte_data_neptune_xt; |
| 1933 | update_dte_from_pl2 = true; |
| 1934 | break; |
| 1935 | default: |
| 1936 | si_pi->cac_weights = cac_weights_pitcairn; |
| 1937 | si_pi->lcac_config = lcac_pitcairn; |
| 1938 | si_pi->cac_override = cac_override_pitcairn; |
| 1939 | si_pi->powertune_data = &powertune_data_pitcairn; |
| 1940 | si_pi->dte_data = dte_data_pitcairn; |
Alex Deucher | d05f7e7 | 2013-07-28 18:26:38 -0400 | [diff] [blame] | 1941 | break; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1942 | } |
| 1943 | } else if (rdev->family == CHIP_VERDE) { |
| 1944 | si_pi->lcac_config = lcac_cape_verde; |
| 1945 | si_pi->cac_override = cac_override_cape_verde; |
| 1946 | si_pi->powertune_data = &powertune_data_cape_verde; |
| 1947 | |
| 1948 | switch (rdev->pdev->device) { |
| 1949 | case 0x683B: |
| 1950 | case 0x683F: |
| 1951 | case 0x6829: |
Alex Deucher | 46348dc | 2013-07-26 18:21:02 -0400 | [diff] [blame] | 1952 | case 0x6835: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1953 | si_pi->cac_weights = cac_weights_cape_verde_pro; |
| 1954 | si_pi->dte_data = dte_data_cape_verde; |
| 1955 | break; |
Alex Deucher | 8a30911 | 2014-06-06 18:58:10 -0400 | [diff] [blame] | 1956 | case 0x682C: |
| 1957 | si_pi->cac_weights = cac_weights_cape_verde_pro; |
| 1958 | si_pi->dte_data = dte_data_sun_xt; |
| 1959 | break; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1960 | case 0x6825: |
| 1961 | case 0x6827: |
| 1962 | si_pi->cac_weights = cac_weights_heathrow; |
| 1963 | si_pi->dte_data = dte_data_cape_verde; |
| 1964 | break; |
| 1965 | case 0x6824: |
| 1966 | case 0x682D: |
| 1967 | si_pi->cac_weights = cac_weights_chelsea_xt; |
| 1968 | si_pi->dte_data = dte_data_cape_verde; |
| 1969 | break; |
| 1970 | case 0x682F: |
| 1971 | si_pi->cac_weights = cac_weights_chelsea_pro; |
| 1972 | si_pi->dte_data = dte_data_cape_verde; |
| 1973 | break; |
| 1974 | case 0x6820: |
| 1975 | si_pi->cac_weights = cac_weights_heathrow; |
| 1976 | si_pi->dte_data = dte_data_venus_xtx; |
| 1977 | break; |
| 1978 | case 0x6821: |
| 1979 | si_pi->cac_weights = cac_weights_heathrow; |
| 1980 | si_pi->dte_data = dte_data_venus_xt; |
| 1981 | break; |
| 1982 | case 0x6823: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1983 | case 0x682B: |
Alex Deucher | 8a30911 | 2014-06-06 18:58:10 -0400 | [diff] [blame] | 1984 | case 0x6822: |
| 1985 | case 0x682A: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1986 | si_pi->cac_weights = cac_weights_chelsea_pro; |
| 1987 | si_pi->dte_data = dte_data_venus_pro; |
| 1988 | break; |
| 1989 | default: |
| 1990 | si_pi->cac_weights = cac_weights_cape_verde; |
| 1991 | si_pi->dte_data = dte_data_cape_verde; |
| 1992 | break; |
| 1993 | } |
| 1994 | } else if (rdev->family == CHIP_OLAND) { |
| 1995 | switch (rdev->pdev->device) { |
| 1996 | case 0x6601: |
| 1997 | case 0x6621: |
| 1998 | case 0x6603: |
Alex Deucher | 8a30911 | 2014-06-06 18:58:10 -0400 | [diff] [blame] | 1999 | case 0x6605: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 2000 | si_pi->cac_weights = cac_weights_mars_pro; |
| 2001 | si_pi->lcac_config = lcac_mars_pro; |
| 2002 | si_pi->cac_override = cac_override_oland; |
| 2003 | si_pi->powertune_data = &powertune_data_mars_pro; |
| 2004 | si_pi->dte_data = dte_data_mars_pro; |
| 2005 | update_dte_from_pl2 = true; |
| 2006 | break; |
| 2007 | case 0x6600: |
| 2008 | case 0x6606: |
| 2009 | case 0x6620: |
Alex Deucher | 8a30911 | 2014-06-06 18:58:10 -0400 | [diff] [blame] | 2010 | case 0x6604: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 2011 | si_pi->cac_weights = cac_weights_mars_xt; |
| 2012 | si_pi->lcac_config = lcac_mars_pro; |
| 2013 | si_pi->cac_override = cac_override_oland; |
| 2014 | si_pi->powertune_data = &powertune_data_mars_pro; |
| 2015 | si_pi->dte_data = dte_data_mars_pro; |
| 2016 | update_dte_from_pl2 = true; |
| 2017 | break; |
| 2018 | case 0x6611: |
Alex Deucher | 8a30911 | 2014-06-06 18:58:10 -0400 | [diff] [blame] | 2019 | case 0x6613: |
| 2020 | case 0x6608: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 2021 | si_pi->cac_weights = cac_weights_oland_pro; |
| 2022 | si_pi->lcac_config = lcac_mars_pro; |
| 2023 | si_pi->cac_override = cac_override_oland; |
| 2024 | si_pi->powertune_data = &powertune_data_mars_pro; |
| 2025 | si_pi->dte_data = dte_data_mars_pro; |
| 2026 | update_dte_from_pl2 = true; |
| 2027 | break; |
| 2028 | case 0x6610: |
| 2029 | si_pi->cac_weights = cac_weights_oland_xt; |
| 2030 | si_pi->lcac_config = lcac_mars_pro; |
| 2031 | si_pi->cac_override = cac_override_oland; |
| 2032 | si_pi->powertune_data = &powertune_data_mars_pro; |
| 2033 | si_pi->dte_data = dte_data_mars_pro; |
| 2034 | update_dte_from_pl2 = true; |
| 2035 | break; |
| 2036 | default: |
| 2037 | si_pi->cac_weights = cac_weights_oland; |
| 2038 | si_pi->lcac_config = lcac_oland; |
| 2039 | si_pi->cac_override = cac_override_oland; |
| 2040 | si_pi->powertune_data = &powertune_data_oland; |
| 2041 | si_pi->dte_data = dte_data_oland; |
| 2042 | break; |
| 2043 | } |
| 2044 | } else if (rdev->family == CHIP_HAINAN) { |
| 2045 | si_pi->cac_weights = cac_weights_hainan; |
| 2046 | si_pi->lcac_config = lcac_oland; |
| 2047 | si_pi->cac_override = cac_override_oland; |
| 2048 | si_pi->powertune_data = &powertune_data_hainan; |
| 2049 | si_pi->dte_data = dte_data_sun_xt; |
| 2050 | update_dte_from_pl2 = true; |
| 2051 | } else { |
| 2052 | DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); |
| 2053 | return; |
| 2054 | } |
| 2055 | |
| 2056 | ni_pi->enable_power_containment = false; |
| 2057 | ni_pi->enable_cac = false; |
| 2058 | ni_pi->enable_sq_ramping = false; |
| 2059 | si_pi->enable_dte = false; |
| 2060 | |
Alex Deucher | 5a344dd | 2013-07-30 17:02:29 -0400 | [diff] [blame] | 2061 | if (si_pi->powertune_data->enable_powertune_by_default) { |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 2062 | ni_pi->enable_power_containment= true; |
| 2063 | ni_pi->enable_cac = true; |
| 2064 | if (si_pi->dte_data.enable_dte_by_default) { |
| 2065 | si_pi->enable_dte = true; |
| 2066 | if (update_dte_from_pl2) |
| 2067 | si_update_dte_from_pl2(rdev, &si_pi->dte_data); |
| 2068 | |
| 2069 | } |
| 2070 | ni_pi->enable_sq_ramping = true; |
| 2071 | } |
| 2072 | |
| 2073 | ni_pi->driver_calculate_cac_leakage = true; |
| 2074 | ni_pi->cac_configuration_required = true; |
| 2075 | |
| 2076 | if (ni_pi->cac_configuration_required) { |
| 2077 | ni_pi->support_cac_long_term_average = true; |
| 2078 | si_pi->dyn_powertune_data.l2_lta_window_size = |
| 2079 | si_pi->powertune_data->l2_lta_window_size_default; |
| 2080 | si_pi->dyn_powertune_data.lts_truncate = |
| 2081 | si_pi->powertune_data->lts_truncate_default; |
| 2082 | } else { |
| 2083 | ni_pi->support_cac_long_term_average = false; |
| 2084 | si_pi->dyn_powertune_data.l2_lta_window_size = 0; |
| 2085 | si_pi->dyn_powertune_data.lts_truncate = 0; |
| 2086 | } |
| 2087 | |
| 2088 | si_pi->dyn_powertune_data.disable_uvd_powertune = false; |
| 2089 | } |
| 2090 | |
| 2091 | static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) |
| 2092 | { |
| 2093 | return 1; |
| 2094 | } |
| 2095 | |
| 2096 | static u32 si_calculate_cac_wintime(struct radeon_device *rdev) |
| 2097 | { |
| 2098 | u32 xclk; |
| 2099 | u32 wintime; |
| 2100 | u32 cac_window; |
| 2101 | u32 cac_window_size; |
| 2102 | |
| 2103 | xclk = radeon_get_xclk(rdev); |
| 2104 | |
| 2105 | if (xclk == 0) |
| 2106 | return 0; |
| 2107 | |
| 2108 | cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; |
| 2109 | cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); |
| 2110 | |
| 2111 | wintime = (cac_window_size * 100) / xclk; |
| 2112 | |
| 2113 | return wintime; |
| 2114 | } |
| 2115 | |
| 2116 | static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) |
| 2117 | { |
| 2118 | return power_in_watts; |
| 2119 | } |
| 2120 | |
| 2121 | static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, |
| 2122 | bool adjust_polarity, |
| 2123 | u32 tdp_adjustment, |
| 2124 | u32 *tdp_limit, |
| 2125 | u32 *near_tdp_limit) |
| 2126 | { |
| 2127 | u32 adjustment_delta, max_tdp_limit; |
| 2128 | |
| 2129 | if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) |
| 2130 | return -EINVAL; |
| 2131 | |
| 2132 | max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; |
| 2133 | |
| 2134 | if (adjust_polarity) { |
| 2135 | *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; |
| 2136 | *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); |
| 2137 | } else { |
| 2138 | *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; |
| 2139 | adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; |
| 2140 | if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) |
| 2141 | *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; |
| 2142 | else |
| 2143 | *near_tdp_limit = 0; |
| 2144 | } |
| 2145 | |
| 2146 | if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) |
| 2147 | return -EINVAL; |
| 2148 | if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) |
| 2149 | return -EINVAL; |
| 2150 | |
| 2151 | return 0; |
| 2152 | } |
| 2153 | |
| 2154 | static int si_populate_smc_tdp_limits(struct radeon_device *rdev, |
| 2155 | struct radeon_ps *radeon_state) |
| 2156 | { |
| 2157 | struct ni_power_info *ni_pi = ni_get_pi(rdev); |
| 2158 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 2159 | |
| 2160 | if (ni_pi->enable_power_containment) { |
| 2161 | SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; |
| 2162 | PP_SIslands_PAPMParameters *papm_parm; |
| 2163 | struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; |
| 2164 | u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); |
| 2165 | u32 tdp_limit; |
| 2166 | u32 near_tdp_limit; |
| 2167 | int ret; |
| 2168 | |
| 2169 | if (scaling_factor == 0) |
| 2170 | return -EINVAL; |
| 2171 | |
| 2172 | memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); |
| 2173 | |
| 2174 | ret = si_calculate_adjusted_tdp_limits(rdev, |
| 2175 | false, /* ??? */ |
| 2176 | rdev->pm.dpm.tdp_adjustment, |
| 2177 | &tdp_limit, |
| 2178 | &near_tdp_limit); |
| 2179 | if (ret) |
| 2180 | return ret; |
| 2181 | |
| 2182 | smc_table->dpm2Params.TDPLimit = |
| 2183 | cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); |
| 2184 | smc_table->dpm2Params.NearTDPLimit = |
| 2185 | cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); |
| 2186 | smc_table->dpm2Params.SafePowerLimit = |
| 2187 | cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); |
| 2188 | |
| 2189 | ret = si_copy_bytes_to_smc(rdev, |
| 2190 | (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + |
| 2191 | offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), |
| 2192 | (u8 *)(&(smc_table->dpm2Params.TDPLimit)), |
| 2193 | sizeof(u32) * 3, |
| 2194 | si_pi->sram_end); |
| 2195 | if (ret) |
| 2196 | return ret; |
| 2197 | |
| 2198 | if (si_pi->enable_ppm) { |
| 2199 | papm_parm = &si_pi->papm_parm; |
| 2200 | memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); |
| 2201 | papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); |
| 2202 | papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); |
| 2203 | papm_parm->dGPU_T_Warning = cpu_to_be32(95); |
| 2204 | papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); |
| 2205 | papm_parm->PlatformPowerLimit = 0xffffffff; |
| 2206 | papm_parm->NearTDPLimitPAPM = 0xffffffff; |
| 2207 | |
| 2208 | ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, |
| 2209 | (u8 *)papm_parm, |
| 2210 | sizeof(PP_SIslands_PAPMParameters), |
| 2211 | si_pi->sram_end); |
| 2212 | if (ret) |
| 2213 | return ret; |
| 2214 | } |
| 2215 | } |
| 2216 | return 0; |
| 2217 | } |
| 2218 | |
| 2219 | static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, |
| 2220 | struct radeon_ps *radeon_state) |
| 2221 | { |
| 2222 | struct ni_power_info *ni_pi = ni_get_pi(rdev); |
| 2223 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 2224 | |
| 2225 | if (ni_pi->enable_power_containment) { |
| 2226 | SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; |
| 2227 | u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); |
| 2228 | int ret; |
| 2229 | |
| 2230 | memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); |
| 2231 | |
| 2232 | smc_table->dpm2Params.NearTDPLimit = |
| 2233 | cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); |
| 2234 | smc_table->dpm2Params.SafePowerLimit = |
| 2235 | cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); |
| 2236 | |
| 2237 | ret = si_copy_bytes_to_smc(rdev, |
| 2238 | (si_pi->state_table_start + |
| 2239 | offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + |
| 2240 | offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), |
| 2241 | (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), |
| 2242 | sizeof(u32) * 2, |
| 2243 | si_pi->sram_end); |
| 2244 | if (ret) |
| 2245 | return ret; |
| 2246 | } |
| 2247 | |
| 2248 | return 0; |
| 2249 | } |
| 2250 | |
| 2251 | static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, |
| 2252 | const u16 prev_std_vddc, |
| 2253 | const u16 curr_std_vddc) |
| 2254 | { |
| 2255 | u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; |
| 2256 | u64 prev_vddc = (u64)prev_std_vddc; |
| 2257 | u64 curr_vddc = (u64)curr_std_vddc; |
| 2258 | u64 pwr_efficiency_ratio, n, d; |
| 2259 | |
| 2260 | if ((prev_vddc == 0) || (curr_vddc == 0)) |
| 2261 | return 0; |
| 2262 | |
| 2263 | n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); |
| 2264 | d = prev_vddc * prev_vddc; |
| 2265 | pwr_efficiency_ratio = div64_u64(n, d); |
| 2266 | |
| 2267 | if (pwr_efficiency_ratio > (u64)0xFFFF) |
| 2268 | return 0; |
| 2269 | |
| 2270 | return (u16)pwr_efficiency_ratio; |
| 2271 | } |
| 2272 | |
| 2273 | static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, |
| 2274 | struct radeon_ps *radeon_state) |
| 2275 | { |
| 2276 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 2277 | |
| 2278 | if (si_pi->dyn_powertune_data.disable_uvd_powertune && |
| 2279 | radeon_state->vclk && radeon_state->dclk) |
| 2280 | return true; |
| 2281 | |
| 2282 | return false; |
| 2283 | } |
| 2284 | |
| 2285 | static int si_populate_power_containment_values(struct radeon_device *rdev, |
| 2286 | struct radeon_ps *radeon_state, |
| 2287 | SISLANDS_SMC_SWSTATE *smc_state) |
| 2288 | { |
| 2289 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 2290 | struct ni_power_info *ni_pi = ni_get_pi(rdev); |
| 2291 | struct ni_ps *state = ni_get_ps(radeon_state); |
| 2292 | SISLANDS_SMC_VOLTAGE_VALUE vddc; |
| 2293 | u32 prev_sclk; |
| 2294 | u32 max_sclk; |
| 2295 | u32 min_sclk; |
| 2296 | u16 prev_std_vddc; |
| 2297 | u16 curr_std_vddc; |
| 2298 | int i; |
| 2299 | u16 pwr_efficiency_ratio; |
| 2300 | u8 max_ps_percent; |
| 2301 | bool disable_uvd_power_tune; |
| 2302 | int ret; |
| 2303 | |
| 2304 | if (ni_pi->enable_power_containment == false) |
| 2305 | return 0; |
| 2306 | |
| 2307 | if (state->performance_level_count == 0) |
| 2308 | return -EINVAL; |
| 2309 | |
| 2310 | if (smc_state->levelCount != state->performance_level_count) |
| 2311 | return -EINVAL; |
| 2312 | |
| 2313 | disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); |
| 2314 | |
| 2315 | smc_state->levels[0].dpm2.MaxPS = 0; |
| 2316 | smc_state->levels[0].dpm2.NearTDPDec = 0; |
| 2317 | smc_state->levels[0].dpm2.AboveSafeInc = 0; |
| 2318 | smc_state->levels[0].dpm2.BelowSafeInc = 0; |
| 2319 | smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; |
| 2320 | |
| 2321 | for (i = 1; i < state->performance_level_count; i++) { |
| 2322 | prev_sclk = state->performance_levels[i-1].sclk; |
| 2323 | max_sclk = state->performance_levels[i].sclk; |
| 2324 | if (i == 1) |
| 2325 | max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; |
| 2326 | else |
| 2327 | max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; |
| 2328 | |
| 2329 | if (prev_sclk > max_sclk) |
| 2330 | return -EINVAL; |
| 2331 | |
| 2332 | if ((max_ps_percent == 0) || |
| 2333 | (prev_sclk == max_sclk) || |
| 2334 | disable_uvd_power_tune) { |
| 2335 | min_sclk = max_sclk; |
| 2336 | } else if (i == 1) { |
| 2337 | min_sclk = prev_sclk; |
| 2338 | } else { |
| 2339 | min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; |
| 2340 | } |
| 2341 | |
| 2342 | if (min_sclk < state->performance_levels[0].sclk) |
| 2343 | min_sclk = state->performance_levels[0].sclk; |
| 2344 | |
| 2345 | if (min_sclk == 0) |
| 2346 | return -EINVAL; |
| 2347 | |
| 2348 | ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, |
| 2349 | state->performance_levels[i-1].vddc, &vddc); |
| 2350 | if (ret) |
| 2351 | return ret; |
| 2352 | |
| 2353 | ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); |
| 2354 | if (ret) |
| 2355 | return ret; |
| 2356 | |
| 2357 | ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, |
| 2358 | state->performance_levels[i].vddc, &vddc); |
| 2359 | if (ret) |
| 2360 | return ret; |
| 2361 | |
| 2362 | ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); |
| 2363 | if (ret) |
| 2364 | return ret; |
| 2365 | |
| 2366 | pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, |
| 2367 | prev_std_vddc, curr_std_vddc); |
| 2368 | |
| 2369 | smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); |
| 2370 | smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; |
| 2371 | smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; |
| 2372 | smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; |
| 2373 | smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); |
| 2374 | } |
| 2375 | |
| 2376 | return 0; |
| 2377 | } |
| 2378 | |
| 2379 | static int si_populate_sq_ramping_values(struct radeon_device *rdev, |
| 2380 | struct radeon_ps *radeon_state, |
| 2381 | SISLANDS_SMC_SWSTATE *smc_state) |
| 2382 | { |
| 2383 | struct ni_power_info *ni_pi = ni_get_pi(rdev); |
| 2384 | struct ni_ps *state = ni_get_ps(radeon_state); |
| 2385 | u32 sq_power_throttle, sq_power_throttle2; |
| 2386 | bool enable_sq_ramping = ni_pi->enable_sq_ramping; |
| 2387 | int i; |
| 2388 | |
| 2389 | if (state->performance_level_count == 0) |
| 2390 | return -EINVAL; |
| 2391 | |
| 2392 | if (smc_state->levelCount != state->performance_level_count) |
| 2393 | return -EINVAL; |
| 2394 | |
| 2395 | if (rdev->pm.dpm.sq_ramping_threshold == 0) |
| 2396 | return -EINVAL; |
| 2397 | |
| 2398 | if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) |
| 2399 | enable_sq_ramping = false; |
| 2400 | |
| 2401 | if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) |
| 2402 | enable_sq_ramping = false; |
| 2403 | |
| 2404 | if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) |
| 2405 | enable_sq_ramping = false; |
| 2406 | |
| 2407 | if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) |
| 2408 | enable_sq_ramping = false; |
| 2409 | |
Alex Deucher | 5b43c3c | 2014-02-18 10:14:46 -0500 | [diff] [blame] | 2410 | if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 2411 | enable_sq_ramping = false; |
| 2412 | |
| 2413 | for (i = 0; i < state->performance_level_count; i++) { |
| 2414 | sq_power_throttle = 0; |
| 2415 | sq_power_throttle2 = 0; |
| 2416 | |
| 2417 | if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && |
| 2418 | enable_sq_ramping) { |
| 2419 | sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); |
| 2420 | sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); |
| 2421 | sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); |
| 2422 | sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); |
| 2423 | sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); |
| 2424 | } else { |
| 2425 | sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; |
| 2426 | sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; |
| 2427 | } |
| 2428 | |
| 2429 | smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); |
| 2430 | smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); |
| 2431 | } |
| 2432 | |
| 2433 | return 0; |
| 2434 | } |
| 2435 | |
| 2436 | static int si_enable_power_containment(struct radeon_device *rdev, |
| 2437 | struct radeon_ps *radeon_new_state, |
| 2438 | bool enable) |
| 2439 | { |
| 2440 | struct ni_power_info *ni_pi = ni_get_pi(rdev); |
| 2441 | PPSMC_Result smc_result; |
| 2442 | int ret = 0; |
| 2443 | |
| 2444 | if (ni_pi->enable_power_containment) { |
| 2445 | if (enable) { |
| 2446 | if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { |
| 2447 | smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); |
| 2448 | if (smc_result != PPSMC_Result_OK) { |
| 2449 | ret = -EINVAL; |
| 2450 | ni_pi->pc_enabled = false; |
| 2451 | } else { |
| 2452 | ni_pi->pc_enabled = true; |
| 2453 | } |
| 2454 | } |
| 2455 | } else { |
| 2456 | smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); |
| 2457 | if (smc_result != PPSMC_Result_OK) |
| 2458 | ret = -EINVAL; |
| 2459 | ni_pi->pc_enabled = false; |
| 2460 | } |
| 2461 | } |
| 2462 | |
| 2463 | return ret; |
| 2464 | } |
| 2465 | |
| 2466 | static int si_initialize_smc_dte_tables(struct radeon_device *rdev) |
| 2467 | { |
| 2468 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 2469 | int ret = 0; |
| 2470 | struct si_dte_data *dte_data = &si_pi->dte_data; |
| 2471 | Smc_SIslands_DTE_Configuration *dte_tables = NULL; |
| 2472 | u32 table_size; |
| 2473 | u8 tdep_count; |
| 2474 | u32 i; |
| 2475 | |
| 2476 | if (dte_data == NULL) |
| 2477 | si_pi->enable_dte = false; |
| 2478 | |
| 2479 | if (si_pi->enable_dte == false) |
| 2480 | return 0; |
| 2481 | |
| 2482 | if (dte_data->k <= 0) |
| 2483 | return -EINVAL; |
| 2484 | |
| 2485 | dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); |
| 2486 | if (dte_tables == NULL) { |
| 2487 | si_pi->enable_dte = false; |
| 2488 | return -ENOMEM; |
| 2489 | } |
| 2490 | |
| 2491 | table_size = dte_data->k; |
| 2492 | |
| 2493 | if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) |
| 2494 | table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; |
| 2495 | |
| 2496 | tdep_count = dte_data->tdep_count; |
| 2497 | if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) |
| 2498 | tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; |
| 2499 | |
| 2500 | dte_tables->K = cpu_to_be32(table_size); |
| 2501 | dte_tables->T0 = cpu_to_be32(dte_data->t0); |
| 2502 | dte_tables->MaxT = cpu_to_be32(dte_data->max_t); |
| 2503 | dte_tables->WindowSize = dte_data->window_size; |
| 2504 | dte_tables->temp_select = dte_data->temp_select; |
| 2505 | dte_tables->DTE_mode = dte_data->dte_mode; |
| 2506 | dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); |
| 2507 | |
| 2508 | if (tdep_count > 0) |
| 2509 | table_size--; |
| 2510 | |
| 2511 | for (i = 0; i < table_size; i++) { |
| 2512 | dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); |
| 2513 | dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); |
| 2514 | } |
| 2515 | |
| 2516 | dte_tables->Tdep_count = tdep_count; |
| 2517 | |
| 2518 | for (i = 0; i < (u32)tdep_count; i++) { |
| 2519 | dte_tables->T_limits[i] = dte_data->t_limits[i]; |
| 2520 | dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); |
| 2521 | dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); |
| 2522 | } |
| 2523 | |
| 2524 | ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, |
| 2525 | sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); |
| 2526 | kfree(dte_tables); |
| 2527 | |
| 2528 | return ret; |
| 2529 | } |
| 2530 | |
| 2531 | static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, |
| 2532 | u16 *max, u16 *min) |
| 2533 | { |
| 2534 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 2535 | struct radeon_cac_leakage_table *table = |
| 2536 | &rdev->pm.dpm.dyn_state.cac_leakage_table; |
| 2537 | u32 i; |
| 2538 | u32 v0_loadline; |
| 2539 | |
| 2540 | |
| 2541 | if (table == NULL) |
| 2542 | return -EINVAL; |
| 2543 | |
| 2544 | *max = 0; |
| 2545 | *min = 0xFFFF; |
| 2546 | |
| 2547 | for (i = 0; i < table->count; i++) { |
| 2548 | if (table->entries[i].vddc > *max) |
| 2549 | *max = table->entries[i].vddc; |
| 2550 | if (table->entries[i].vddc < *min) |
| 2551 | *min = table->entries[i].vddc; |
| 2552 | } |
| 2553 | |
| 2554 | if (si_pi->powertune_data->lkge_lut_v0_percent > 100) |
| 2555 | return -EINVAL; |
| 2556 | |
| 2557 | v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; |
| 2558 | |
| 2559 | if (v0_loadline > 0xFFFFUL) |
| 2560 | return -EINVAL; |
| 2561 | |
| 2562 | *min = (u16)v0_loadline; |
| 2563 | |
| 2564 | if ((*min > *max) || (*max == 0) || (*min == 0)) |
| 2565 | return -EINVAL; |
| 2566 | |
| 2567 | return 0; |
| 2568 | } |
| 2569 | |
| 2570 | static u16 si_get_cac_std_voltage_step(u16 max, u16 min) |
| 2571 | { |
| 2572 | return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / |
| 2573 | SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; |
| 2574 | } |
| 2575 | |
| 2576 | static int si_init_dte_leakage_table(struct radeon_device *rdev, |
| 2577 | PP_SIslands_CacConfig *cac_tables, |
| 2578 | u16 vddc_max, u16 vddc_min, u16 vddc_step, |
| 2579 | u16 t0, u16 t_step) |
| 2580 | { |
| 2581 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 2582 | u32 leakage; |
| 2583 | unsigned int i, j; |
| 2584 | s32 t; |
| 2585 | u32 smc_leakage; |
| 2586 | u32 scaling_factor; |
| 2587 | u16 voltage; |
| 2588 | |
| 2589 | scaling_factor = si_get_smc_power_scaling_factor(rdev); |
| 2590 | |
| 2591 | for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { |
| 2592 | t = (1000 * (i * t_step + t0)); |
| 2593 | |
| 2594 | for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { |
| 2595 | voltage = vddc_max - (vddc_step * j); |
| 2596 | |
| 2597 | si_calculate_leakage_for_v_and_t(rdev, |
| 2598 | &si_pi->powertune_data->leakage_coefficients, |
| 2599 | voltage, |
| 2600 | t, |
| 2601 | si_pi->dyn_powertune_data.cac_leakage, |
| 2602 | &leakage); |
| 2603 | |
| 2604 | smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; |
| 2605 | |
| 2606 | if (smc_leakage > 0xFFFF) |
| 2607 | smc_leakage = 0xFFFF; |
| 2608 | |
| 2609 | cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = |
| 2610 | cpu_to_be16((u16)smc_leakage); |
| 2611 | } |
| 2612 | } |
| 2613 | return 0; |
| 2614 | } |
| 2615 | |
| 2616 | static int si_init_simplified_leakage_table(struct radeon_device *rdev, |
| 2617 | PP_SIslands_CacConfig *cac_tables, |
| 2618 | u16 vddc_max, u16 vddc_min, u16 vddc_step) |
| 2619 | { |
| 2620 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 2621 | u32 leakage; |
| 2622 | unsigned int i, j; |
| 2623 | u32 smc_leakage; |
| 2624 | u32 scaling_factor; |
| 2625 | u16 voltage; |
| 2626 | |
| 2627 | scaling_factor = si_get_smc_power_scaling_factor(rdev); |
| 2628 | |
| 2629 | for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { |
| 2630 | voltage = vddc_max - (vddc_step * j); |
| 2631 | |
| 2632 | si_calculate_leakage_for_v(rdev, |
| 2633 | &si_pi->powertune_data->leakage_coefficients, |
| 2634 | si_pi->powertune_data->fixed_kt, |
| 2635 | voltage, |
| 2636 | si_pi->dyn_powertune_data.cac_leakage, |
| 2637 | &leakage); |
| 2638 | |
| 2639 | smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; |
| 2640 | |
| 2641 | if (smc_leakage > 0xFFFF) |
| 2642 | smc_leakage = 0xFFFF; |
| 2643 | |
| 2644 | for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) |
| 2645 | cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = |
| 2646 | cpu_to_be16((u16)smc_leakage); |
| 2647 | } |
| 2648 | return 0; |
| 2649 | } |
| 2650 | |
| 2651 | static int si_initialize_smc_cac_tables(struct radeon_device *rdev) |
| 2652 | { |
| 2653 | struct ni_power_info *ni_pi = ni_get_pi(rdev); |
| 2654 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 2655 | PP_SIslands_CacConfig *cac_tables = NULL; |
| 2656 | u16 vddc_max, vddc_min, vddc_step; |
| 2657 | u16 t0, t_step; |
| 2658 | u32 load_line_slope, reg; |
| 2659 | int ret = 0; |
| 2660 | u32 ticks_per_us = radeon_get_xclk(rdev) / 100; |
| 2661 | |
| 2662 | if (ni_pi->enable_cac == false) |
| 2663 | return 0; |
| 2664 | |
| 2665 | cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); |
| 2666 | if (!cac_tables) |
| 2667 | return -ENOMEM; |
| 2668 | |
| 2669 | reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; |
| 2670 | reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); |
| 2671 | WREG32(CG_CAC_CTRL, reg); |
| 2672 | |
| 2673 | si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; |
| 2674 | si_pi->dyn_powertune_data.dc_pwr_value = |
| 2675 | si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; |
| 2676 | si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); |
| 2677 | si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; |
| 2678 | |
| 2679 | si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; |
| 2680 | |
| 2681 | ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); |
| 2682 | if (ret) |
| 2683 | goto done_free; |
| 2684 | |
| 2685 | vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); |
| 2686 | vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); |
| 2687 | t_step = 4; |
| 2688 | t0 = 60; |
| 2689 | |
| 2690 | if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) |
| 2691 | ret = si_init_dte_leakage_table(rdev, cac_tables, |
| 2692 | vddc_max, vddc_min, vddc_step, |
| 2693 | t0, t_step); |
| 2694 | else |
| 2695 | ret = si_init_simplified_leakage_table(rdev, cac_tables, |
| 2696 | vddc_max, vddc_min, vddc_step); |
| 2697 | if (ret) |
| 2698 | goto done_free; |
| 2699 | |
| 2700 | load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; |
| 2701 | |
| 2702 | cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); |
| 2703 | cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; |
| 2704 | cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; |
| 2705 | cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); |
| 2706 | cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); |
| 2707 | cac_tables->R_LL = cpu_to_be32(load_line_slope); |
| 2708 | cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); |
| 2709 | cac_tables->calculation_repeats = cpu_to_be32(2); |
| 2710 | cac_tables->dc_cac = cpu_to_be32(0); |
| 2711 | cac_tables->log2_PG_LKG_SCALE = 12; |
| 2712 | cac_tables->cac_temp = si_pi->powertune_data->operating_temp; |
| 2713 | cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); |
| 2714 | cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); |
| 2715 | |
| 2716 | ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, |
| 2717 | sizeof(PP_SIslands_CacConfig), si_pi->sram_end); |
| 2718 | |
| 2719 | if (ret) |
| 2720 | goto done_free; |
| 2721 | |
| 2722 | ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); |
| 2723 | |
| 2724 | done_free: |
| 2725 | if (ret) { |
| 2726 | ni_pi->enable_cac = false; |
| 2727 | ni_pi->enable_power_containment = false; |
| 2728 | } |
| 2729 | |
| 2730 | kfree(cac_tables); |
| 2731 | |
| 2732 | return 0; |
| 2733 | } |
| 2734 | |
| 2735 | static int si_program_cac_config_registers(struct radeon_device *rdev, |
| 2736 | const struct si_cac_config_reg *cac_config_regs) |
| 2737 | { |
| 2738 | const struct si_cac_config_reg *config_regs = cac_config_regs; |
| 2739 | u32 data = 0, offset; |
| 2740 | |
| 2741 | if (!config_regs) |
| 2742 | return -EINVAL; |
| 2743 | |
| 2744 | while (config_regs->offset != 0xFFFFFFFF) { |
| 2745 | switch (config_regs->type) { |
| 2746 | case SISLANDS_CACCONFIG_CGIND: |
| 2747 | offset = SMC_CG_IND_START + config_regs->offset; |
| 2748 | if (offset < SMC_CG_IND_END) |
| 2749 | data = RREG32_SMC(offset); |
| 2750 | break; |
| 2751 | default: |
| 2752 | data = RREG32(config_regs->offset << 2); |
| 2753 | break; |
| 2754 | } |
| 2755 | |
| 2756 | data &= ~config_regs->mask; |
| 2757 | data |= ((config_regs->value << config_regs->shift) & config_regs->mask); |
| 2758 | |
| 2759 | switch (config_regs->type) { |
| 2760 | case SISLANDS_CACCONFIG_CGIND: |
| 2761 | offset = SMC_CG_IND_START + config_regs->offset; |
| 2762 | if (offset < SMC_CG_IND_END) |
| 2763 | WREG32_SMC(offset, data); |
| 2764 | break; |
| 2765 | default: |
| 2766 | WREG32(config_regs->offset << 2, data); |
| 2767 | break; |
| 2768 | } |
| 2769 | config_regs++; |
| 2770 | } |
| 2771 | return 0; |
| 2772 | } |
| 2773 | |
| 2774 | static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) |
| 2775 | { |
| 2776 | struct ni_power_info *ni_pi = ni_get_pi(rdev); |
| 2777 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 2778 | int ret; |
| 2779 | |
| 2780 | if ((ni_pi->enable_cac == false) || |
| 2781 | (ni_pi->cac_configuration_required == false)) |
| 2782 | return 0; |
| 2783 | |
| 2784 | ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); |
| 2785 | if (ret) |
| 2786 | return ret; |
| 2787 | ret = si_program_cac_config_registers(rdev, si_pi->cac_override); |
| 2788 | if (ret) |
| 2789 | return ret; |
| 2790 | ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); |
| 2791 | if (ret) |
| 2792 | return ret; |
| 2793 | |
| 2794 | return 0; |
| 2795 | } |
| 2796 | |
| 2797 | static int si_enable_smc_cac(struct radeon_device *rdev, |
| 2798 | struct radeon_ps *radeon_new_state, |
| 2799 | bool enable) |
| 2800 | { |
| 2801 | struct ni_power_info *ni_pi = ni_get_pi(rdev); |
| 2802 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 2803 | PPSMC_Result smc_result; |
| 2804 | int ret = 0; |
| 2805 | |
| 2806 | if (ni_pi->enable_cac) { |
| 2807 | if (enable) { |
| 2808 | if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { |
| 2809 | if (ni_pi->support_cac_long_term_average) { |
| 2810 | smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); |
| 2811 | if (smc_result != PPSMC_Result_OK) |
| 2812 | ni_pi->support_cac_long_term_average = false; |
| 2813 | } |
| 2814 | |
| 2815 | smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); |
| 2816 | if (smc_result != PPSMC_Result_OK) { |
| 2817 | ret = -EINVAL; |
| 2818 | ni_pi->cac_enabled = false; |
| 2819 | } else { |
| 2820 | ni_pi->cac_enabled = true; |
| 2821 | } |
| 2822 | |
| 2823 | if (si_pi->enable_dte) { |
| 2824 | smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); |
| 2825 | if (smc_result != PPSMC_Result_OK) |
| 2826 | ret = -EINVAL; |
| 2827 | } |
| 2828 | } |
| 2829 | } else if (ni_pi->cac_enabled) { |
| 2830 | if (si_pi->enable_dte) |
| 2831 | smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); |
| 2832 | |
| 2833 | smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); |
| 2834 | |
| 2835 | ni_pi->cac_enabled = false; |
| 2836 | |
| 2837 | if (ni_pi->support_cac_long_term_average) |
| 2838 | smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); |
| 2839 | } |
| 2840 | } |
| 2841 | return ret; |
| 2842 | } |
| 2843 | |
| 2844 | static int si_init_smc_spll_table(struct radeon_device *rdev) |
| 2845 | { |
| 2846 | struct ni_power_info *ni_pi = ni_get_pi(rdev); |
| 2847 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 2848 | SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; |
| 2849 | SISLANDS_SMC_SCLK_VALUE sclk_params; |
| 2850 | u32 fb_div, p_div; |
| 2851 | u32 clk_s, clk_v; |
| 2852 | u32 sclk = 0; |
| 2853 | int ret = 0; |
| 2854 | u32 tmp; |
| 2855 | int i; |
| 2856 | |
| 2857 | if (si_pi->spll_table_start == 0) |
| 2858 | return -EINVAL; |
| 2859 | |
| 2860 | spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); |
| 2861 | if (spll_table == NULL) |
| 2862 | return -ENOMEM; |
| 2863 | |
| 2864 | for (i = 0; i < 256; i++) { |
| 2865 | ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); |
| 2866 | if (ret) |
| 2867 | break; |
| 2868 | |
| 2869 | p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; |
| 2870 | fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; |
| 2871 | clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; |
| 2872 | clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; |
| 2873 | |
| 2874 | fb_div &= ~0x00001FFF; |
| 2875 | fb_div >>= 1; |
| 2876 | clk_v >>= 6; |
| 2877 | |
| 2878 | if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) |
| 2879 | ret = -EINVAL; |
| 2880 | if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) |
| 2881 | ret = -EINVAL; |
| 2882 | if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) |
| 2883 | ret = -EINVAL; |
| 2884 | if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) |
| 2885 | ret = -EINVAL; |
| 2886 | |
| 2887 | if (ret) |
| 2888 | break; |
| 2889 | |
| 2890 | tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | |
| 2891 | ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); |
| 2892 | spll_table->freq[i] = cpu_to_be32(tmp); |
| 2893 | |
| 2894 | tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | |
| 2895 | ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); |
| 2896 | spll_table->ss[i] = cpu_to_be32(tmp); |
| 2897 | |
| 2898 | sclk += 512; |
| 2899 | } |
| 2900 | |
| 2901 | |
| 2902 | if (!ret) |
| 2903 | ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, |
| 2904 | (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), |
| 2905 | si_pi->sram_end); |
| 2906 | |
| 2907 | if (ret) |
| 2908 | ni_pi->enable_power_containment = false; |
| 2909 | |
| 2910 | kfree(spll_table); |
| 2911 | |
| 2912 | return ret; |
| 2913 | } |
| 2914 | |
Alex Deucher | 5615f89 | 2015-01-12 17:15:12 -0500 | [diff] [blame] | 2915 | struct si_dpm_quirk { |
| 2916 | u32 chip_vendor; |
| 2917 | u32 chip_device; |
| 2918 | u32 subsys_vendor; |
| 2919 | u32 subsys_device; |
| 2920 | u32 max_sclk; |
| 2921 | u32 max_mclk; |
| 2922 | }; |
| 2923 | |
| 2924 | /* cards with dpm stability problems */ |
| 2925 | static struct si_dpm_quirk si_dpm_quirk_list[] = { |
| 2926 | /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */ |
| 2927 | { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 }, |
Alex Deucher | cd17e02 | 2015-04-27 09:51:43 -0400 | [diff] [blame] | 2928 | { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 }, |
Alex Deucher | f971f22 | 2016-03-25 10:31:04 -0400 | [diff] [blame] | 2929 | { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 }, |
Alex Deucher | 5dfc71b | 2015-07-09 21:08:17 -0400 | [diff] [blame] | 2930 | { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 }, |
Maxim Sheviakov | 515c752 | 2015-11-10 13:09:13 -0500 | [diff] [blame] | 2931 | { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 }, |
Alex Deucher | 2b02ec7 | 2015-10-02 16:12:07 -0400 | [diff] [blame] | 2932 | { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 }, |
Alex Deucher | a64663d | 2016-03-28 10:16:40 -0400 | [diff] [blame] | 2933 | { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 }, |
Alex Deucher | bcb31eb | 2016-04-14 14:15:16 -0400 | [diff] [blame] | 2934 | { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 }, |
Alex Deucher | 5615f89 | 2015-01-12 17:15:12 -0500 | [diff] [blame] | 2935 | { 0, 0, 0, 0 }, |
| 2936 | }; |
| 2937 | |
Alex Deucher | 11586cf | 2015-05-11 22:01:52 +0200 | [diff] [blame] | 2938 | static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, |
| 2939 | u16 vce_voltage) |
| 2940 | { |
| 2941 | u16 highest_leakage = 0; |
| 2942 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 2943 | int i; |
| 2944 | |
| 2945 | for (i = 0; i < si_pi->leakage_voltage.count; i++){ |
| 2946 | if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) |
| 2947 | highest_leakage = si_pi->leakage_voltage.entries[i].voltage; |
| 2948 | } |
| 2949 | |
| 2950 | if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) |
| 2951 | return highest_leakage; |
| 2952 | |
| 2953 | return vce_voltage; |
| 2954 | } |
| 2955 | |
| 2956 | static int si_get_vce_clock_voltage(struct radeon_device *rdev, |
| 2957 | u32 evclk, u32 ecclk, u16 *voltage) |
| 2958 | { |
| 2959 | u32 i; |
| 2960 | int ret = -EINVAL; |
| 2961 | struct radeon_vce_clock_voltage_dependency_table *table = |
| 2962 | &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; |
| 2963 | |
| 2964 | if (((evclk == 0) && (ecclk == 0)) || |
| 2965 | (table && (table->count == 0))) { |
| 2966 | *voltage = 0; |
| 2967 | return 0; |
| 2968 | } |
| 2969 | |
| 2970 | for (i = 0; i < table->count; i++) { |
| 2971 | if ((evclk <= table->entries[i].evclk) && |
| 2972 | (ecclk <= table->entries[i].ecclk)) { |
| 2973 | *voltage = table->entries[i].v; |
| 2974 | ret = 0; |
| 2975 | break; |
| 2976 | } |
| 2977 | } |
| 2978 | |
| 2979 | /* if no match return the highest voltage */ |
| 2980 | if (ret) |
| 2981 | *voltage = table->entries[table->count - 1].v; |
| 2982 | |
| 2983 | *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); |
| 2984 | |
| 2985 | return ret; |
| 2986 | } |
| 2987 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 2988 | static void si_apply_state_adjust_rules(struct radeon_device *rdev, |
| 2989 | struct radeon_ps *rps) |
| 2990 | { |
| 2991 | struct ni_ps *ps = ni_get_ps(rps); |
| 2992 | struct radeon_clock_and_voltage_limits *max_limits; |
Alex Deucher | 797f203 | 2013-08-01 11:54:07 -0400 | [diff] [blame] | 2993 | bool disable_mclk_switching = false; |
| 2994 | bool disable_sclk_switching = false; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 2995 | u32 mclk, sclk; |
Alex Deucher | 11586cf | 2015-05-11 22:01:52 +0200 | [diff] [blame] | 2996 | u16 vddc, vddci, min_vce_voltage = 0; |
Alex Deucher | 1db7802 | 2014-10-13 11:35:06 -0400 | [diff] [blame] | 2997 | u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; |
Alex Deucher | 5615f89 | 2015-01-12 17:15:12 -0500 | [diff] [blame] | 2998 | u32 max_sclk = 0, max_mclk = 0; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 2999 | int i; |
Alex Deucher | 5615f89 | 2015-01-12 17:15:12 -0500 | [diff] [blame] | 3000 | struct si_dpm_quirk *p = si_dpm_quirk_list; |
| 3001 | |
Alex Deucher | 7dc86ef | 2016-10-14 16:38:02 -0400 | [diff] [blame] | 3002 | /* limit all SI kickers */ |
| 3003 | if (rdev->family == CHIP_PITCAIRN) { |
| 3004 | if ((rdev->pdev->revision == 0x81) || |
| 3005 | (rdev->pdev->device == 0x6810) || |
| 3006 | (rdev->pdev->device == 0x6811) || |
| 3007 | (rdev->pdev->device == 0x6816) || |
| 3008 | (rdev->pdev->device == 0x6817) || |
| 3009 | (rdev->pdev->device == 0x6806)) |
| 3010 | max_mclk = 120000; |
Alex Deucher | 7dc86ef | 2016-10-14 16:38:02 -0400 | [diff] [blame] | 3011 | } else if (rdev->family == CHIP_OLAND) { |
| 3012 | if ((rdev->pdev->revision == 0xC7) || |
| 3013 | (rdev->pdev->revision == 0x80) || |
| 3014 | (rdev->pdev->revision == 0x81) || |
| 3015 | (rdev->pdev->revision == 0x83) || |
Alex Deucher | 851bedd | 2016-12-02 00:21:48 -0500 | [diff] [blame] | 3016 | (rdev->pdev->revision == 0x87) || |
Alex Deucher | 7dc86ef | 2016-10-14 16:38:02 -0400 | [diff] [blame] | 3017 | (rdev->pdev->device == 0x6604) || |
| 3018 | (rdev->pdev->device == 0x6605)) { |
| 3019 | max_sclk = 75000; |
| 3020 | max_mclk = 80000; |
| 3021 | } |
| 3022 | } else if (rdev->family == CHIP_HAINAN) { |
| 3023 | if ((rdev->pdev->revision == 0x81) || |
| 3024 | (rdev->pdev->revision == 0x83) || |
| 3025 | (rdev->pdev->revision == 0xC3) || |
| 3026 | (rdev->pdev->device == 0x6664) || |
| 3027 | (rdev->pdev->device == 0x6665) || |
| 3028 | (rdev->pdev->device == 0x6667)) { |
| 3029 | max_sclk = 75000; |
| 3030 | max_mclk = 80000; |
| 3031 | } |
| 3032 | } |
Alex Deucher | 5615f89 | 2015-01-12 17:15:12 -0500 | [diff] [blame] | 3033 | /* Apply dpm quirks */ |
| 3034 | while (p && p->chip_device != 0) { |
| 3035 | if (rdev->pdev->vendor == p->chip_vendor && |
| 3036 | rdev->pdev->device == p->chip_device && |
| 3037 | rdev->pdev->subsystem_vendor == p->subsys_vendor && |
| 3038 | rdev->pdev->subsystem_device == p->subsys_device) { |
| 3039 | max_sclk = p->max_sclk; |
| 3040 | max_mclk = p->max_mclk; |
| 3041 | break; |
| 3042 | } |
| 3043 | ++p; |
| 3044 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3045 | |
Alex Deucher | 11586cf | 2015-05-11 22:01:52 +0200 | [diff] [blame] | 3046 | if (rps->vce_active) { |
| 3047 | rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; |
| 3048 | rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; |
| 3049 | si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, |
| 3050 | &min_vce_voltage); |
| 3051 | } else { |
| 3052 | rps->evclk = 0; |
| 3053 | rps->ecclk = 0; |
| 3054 | } |
| 3055 | |
Alex Deucher | f4dec31 | 2013-07-08 12:15:11 -0400 | [diff] [blame] | 3056 | if ((rdev->pm.dpm.new_active_crtc_count > 1) || |
| 3057 | ni_dpm_vblank_too_short(rdev)) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3058 | disable_mclk_switching = true; |
Alex Deucher | 797f203 | 2013-08-01 11:54:07 -0400 | [diff] [blame] | 3059 | |
| 3060 | if (rps->vclk || rps->dclk) { |
| 3061 | disable_mclk_switching = true; |
| 3062 | disable_sclk_switching = true; |
| 3063 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3064 | |
| 3065 | if (rdev->pm.dpm.ac_power) |
| 3066 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
| 3067 | else |
| 3068 | max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; |
| 3069 | |
| 3070 | for (i = ps->performance_level_count - 2; i >= 0; i--) { |
| 3071 | if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) |
| 3072 | ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; |
| 3073 | } |
| 3074 | if (rdev->pm.dpm.ac_power == false) { |
| 3075 | for (i = 0; i < ps->performance_level_count; i++) { |
| 3076 | if (ps->performance_levels[i].mclk > max_limits->mclk) |
| 3077 | ps->performance_levels[i].mclk = max_limits->mclk; |
| 3078 | if (ps->performance_levels[i].sclk > max_limits->sclk) |
| 3079 | ps->performance_levels[i].sclk = max_limits->sclk; |
| 3080 | if (ps->performance_levels[i].vddc > max_limits->vddc) |
| 3081 | ps->performance_levels[i].vddc = max_limits->vddc; |
| 3082 | if (ps->performance_levels[i].vddci > max_limits->vddci) |
| 3083 | ps->performance_levels[i].vddci = max_limits->vddci; |
| 3084 | } |
| 3085 | } |
| 3086 | |
Alex Deucher | 1db7802 | 2014-10-13 11:35:06 -0400 | [diff] [blame] | 3087 | /* limit clocks to max supported clocks based on voltage dependency tables */ |
| 3088 | btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, |
| 3089 | &max_sclk_vddc); |
| 3090 | btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, |
| 3091 | &max_mclk_vddci); |
| 3092 | btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, |
| 3093 | &max_mclk_vddc); |
| 3094 | |
| 3095 | for (i = 0; i < ps->performance_level_count; i++) { |
| 3096 | if (max_sclk_vddc) { |
| 3097 | if (ps->performance_levels[i].sclk > max_sclk_vddc) |
| 3098 | ps->performance_levels[i].sclk = max_sclk_vddc; |
| 3099 | } |
| 3100 | if (max_mclk_vddci) { |
| 3101 | if (ps->performance_levels[i].mclk > max_mclk_vddci) |
| 3102 | ps->performance_levels[i].mclk = max_mclk_vddci; |
| 3103 | } |
| 3104 | if (max_mclk_vddc) { |
| 3105 | if (ps->performance_levels[i].mclk > max_mclk_vddc) |
| 3106 | ps->performance_levels[i].mclk = max_mclk_vddc; |
| 3107 | } |
Alex Deucher | 5615f89 | 2015-01-12 17:15:12 -0500 | [diff] [blame] | 3108 | if (max_mclk) { |
| 3109 | if (ps->performance_levels[i].mclk > max_mclk) |
| 3110 | ps->performance_levels[i].mclk = max_mclk; |
| 3111 | } |
| 3112 | if (max_sclk) { |
| 3113 | if (ps->performance_levels[i].sclk > max_sclk) |
| 3114 | ps->performance_levels[i].sclk = max_sclk; |
| 3115 | } |
Alex Deucher | 1db7802 | 2014-10-13 11:35:06 -0400 | [diff] [blame] | 3116 | } |
| 3117 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3118 | /* XXX validate the min clocks required for display */ |
| 3119 | |
| 3120 | if (disable_mclk_switching) { |
| 3121 | mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3122 | vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; |
| 3123 | } else { |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3124 | mclk = ps->performance_levels[0].mclk; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3125 | vddci = ps->performance_levels[0].vddci; |
| 3126 | } |
| 3127 | |
Alex Deucher | 797f203 | 2013-08-01 11:54:07 -0400 | [diff] [blame] | 3128 | if (disable_sclk_switching) { |
| 3129 | sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; |
| 3130 | vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; |
| 3131 | } else { |
| 3132 | sclk = ps->performance_levels[0].sclk; |
| 3133 | vddc = ps->performance_levels[0].vddc; |
| 3134 | } |
| 3135 | |
Alex Deucher | 11586cf | 2015-05-11 22:01:52 +0200 | [diff] [blame] | 3136 | if (rps->vce_active) { |
| 3137 | if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) |
| 3138 | sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; |
| 3139 | if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) |
| 3140 | mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; |
| 3141 | } |
| 3142 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3143 | /* adjusted low state */ |
| 3144 | ps->performance_levels[0].sclk = sclk; |
| 3145 | ps->performance_levels[0].mclk = mclk; |
| 3146 | ps->performance_levels[0].vddc = vddc; |
| 3147 | ps->performance_levels[0].vddci = vddci; |
| 3148 | |
Alex Deucher | 797f203 | 2013-08-01 11:54:07 -0400 | [diff] [blame] | 3149 | if (disable_sclk_switching) { |
| 3150 | sclk = ps->performance_levels[0].sclk; |
| 3151 | for (i = 1; i < ps->performance_level_count; i++) { |
| 3152 | if (sclk < ps->performance_levels[i].sclk) |
| 3153 | sclk = ps->performance_levels[i].sclk; |
| 3154 | } |
| 3155 | for (i = 0; i < ps->performance_level_count; i++) { |
| 3156 | ps->performance_levels[i].sclk = sclk; |
| 3157 | ps->performance_levels[i].vddc = vddc; |
| 3158 | } |
| 3159 | } else { |
| 3160 | for (i = 1; i < ps->performance_level_count; i++) { |
| 3161 | if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) |
| 3162 | ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; |
| 3163 | if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) |
| 3164 | ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; |
| 3165 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3166 | } |
| 3167 | |
| 3168 | if (disable_mclk_switching) { |
| 3169 | mclk = ps->performance_levels[0].mclk; |
| 3170 | for (i = 1; i < ps->performance_level_count; i++) { |
| 3171 | if (mclk < ps->performance_levels[i].mclk) |
| 3172 | mclk = ps->performance_levels[i].mclk; |
| 3173 | } |
| 3174 | for (i = 0; i < ps->performance_level_count; i++) { |
| 3175 | ps->performance_levels[i].mclk = mclk; |
| 3176 | ps->performance_levels[i].vddci = vddci; |
| 3177 | } |
| 3178 | } else { |
| 3179 | for (i = 1; i < ps->performance_level_count; i++) { |
| 3180 | if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) |
| 3181 | ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; |
| 3182 | if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) |
| 3183 | ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; |
| 3184 | } |
| 3185 | } |
| 3186 | |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 3187 | for (i = 0; i < ps->performance_level_count; i++) |
| 3188 | btc_adjust_clock_combinations(rdev, max_limits, |
| 3189 | &ps->performance_levels[i]); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3190 | |
| 3191 | for (i = 0; i < ps->performance_level_count; i++) { |
Alex Deucher | 11586cf | 2015-05-11 22:01:52 +0200 | [diff] [blame] | 3192 | if (ps->performance_levels[i].vddc < min_vce_voltage) |
| 3193 | ps->performance_levels[i].vddc = min_vce_voltage; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3194 | btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, |
| 3195 | ps->performance_levels[i].sclk, |
| 3196 | max_limits->vddc, &ps->performance_levels[i].vddc); |
| 3197 | btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, |
| 3198 | ps->performance_levels[i].mclk, |
| 3199 | max_limits->vddci, &ps->performance_levels[i].vddci); |
| 3200 | btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, |
| 3201 | ps->performance_levels[i].mclk, |
| 3202 | max_limits->vddc, &ps->performance_levels[i].vddc); |
| 3203 | btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, |
| 3204 | rdev->clock.current_dispclk, |
| 3205 | max_limits->vddc, &ps->performance_levels[i].vddc); |
| 3206 | } |
| 3207 | |
| 3208 | for (i = 0; i < ps->performance_level_count; i++) { |
| 3209 | btc_apply_voltage_delta_rules(rdev, |
| 3210 | max_limits->vddc, max_limits->vddci, |
| 3211 | &ps->performance_levels[i].vddc, |
| 3212 | &ps->performance_levels[i].vddci); |
| 3213 | } |
| 3214 | |
| 3215 | ps->dc_compatible = true; |
| 3216 | for (i = 0; i < ps->performance_level_count; i++) { |
| 3217 | if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) |
| 3218 | ps->dc_compatible = false; |
| 3219 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3220 | } |
| 3221 | |
| 3222 | #if 0 |
| 3223 | static int si_read_smc_soft_register(struct radeon_device *rdev, |
| 3224 | u16 reg_offset, u32 *value) |
| 3225 | { |
| 3226 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 3227 | |
| 3228 | return si_read_smc_sram_dword(rdev, |
| 3229 | si_pi->soft_regs_start + reg_offset, value, |
| 3230 | si_pi->sram_end); |
| 3231 | } |
| 3232 | #endif |
| 3233 | |
| 3234 | static int si_write_smc_soft_register(struct radeon_device *rdev, |
| 3235 | u16 reg_offset, u32 value) |
| 3236 | { |
| 3237 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 3238 | |
| 3239 | return si_write_smc_sram_dword(rdev, |
| 3240 | si_pi->soft_regs_start + reg_offset, |
| 3241 | value, si_pi->sram_end); |
| 3242 | } |
| 3243 | |
| 3244 | static bool si_is_special_1gb_platform(struct radeon_device *rdev) |
| 3245 | { |
| 3246 | bool ret = false; |
| 3247 | u32 tmp, width, row, column, bank, density; |
| 3248 | bool is_memory_gddr5, is_special; |
| 3249 | |
| 3250 | tmp = RREG32(MC_SEQ_MISC0); |
| 3251 | is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); |
| 3252 | is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) |
| 3253 | & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); |
| 3254 | |
| 3255 | WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); |
| 3256 | width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; |
| 3257 | |
| 3258 | tmp = RREG32(MC_ARB_RAMCFG); |
| 3259 | row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; |
| 3260 | column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; |
| 3261 | bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; |
| 3262 | |
| 3263 | density = (1 << (row + column - 20 + bank)) * width; |
| 3264 | |
| 3265 | if ((rdev->pdev->device == 0x6819) && |
| 3266 | is_memory_gddr5 && is_special && (density == 0x400)) |
| 3267 | ret = true; |
| 3268 | |
| 3269 | return ret; |
| 3270 | } |
| 3271 | |
| 3272 | static void si_get_leakage_vddc(struct radeon_device *rdev) |
| 3273 | { |
| 3274 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 3275 | u16 vddc, count = 0; |
| 3276 | int i, ret; |
| 3277 | |
| 3278 | for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { |
| 3279 | ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); |
| 3280 | |
| 3281 | if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { |
| 3282 | si_pi->leakage_voltage.entries[count].voltage = vddc; |
| 3283 | si_pi->leakage_voltage.entries[count].leakage_index = |
| 3284 | SISLANDS_LEAKAGE_INDEX0 + i; |
| 3285 | count++; |
| 3286 | } |
| 3287 | } |
| 3288 | si_pi->leakage_voltage.count = count; |
| 3289 | } |
| 3290 | |
| 3291 | static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, |
| 3292 | u32 index, u16 *leakage_voltage) |
| 3293 | { |
| 3294 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 3295 | int i; |
| 3296 | |
| 3297 | if (leakage_voltage == NULL) |
| 3298 | return -EINVAL; |
| 3299 | |
| 3300 | if ((index & 0xff00) != 0xff00) |
| 3301 | return -EINVAL; |
| 3302 | |
| 3303 | if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) |
| 3304 | return -EINVAL; |
| 3305 | |
| 3306 | if (index < SISLANDS_LEAKAGE_INDEX0) |
| 3307 | return -EINVAL; |
| 3308 | |
| 3309 | for (i = 0; i < si_pi->leakage_voltage.count; i++) { |
| 3310 | if (si_pi->leakage_voltage.entries[i].leakage_index == index) { |
| 3311 | *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; |
| 3312 | return 0; |
| 3313 | } |
| 3314 | } |
| 3315 | return -EAGAIN; |
| 3316 | } |
| 3317 | |
| 3318 | static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) |
| 3319 | { |
| 3320 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 3321 | bool want_thermal_protection; |
| 3322 | enum radeon_dpm_event_src dpm_event_src; |
| 3323 | |
| 3324 | switch (sources) { |
| 3325 | case 0: |
| 3326 | default: |
| 3327 | want_thermal_protection = false; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 3328 | break; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3329 | case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): |
| 3330 | want_thermal_protection = true; |
| 3331 | dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; |
| 3332 | break; |
| 3333 | case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): |
| 3334 | want_thermal_protection = true; |
| 3335 | dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; |
| 3336 | break; |
| 3337 | case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | |
| 3338 | (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): |
| 3339 | want_thermal_protection = true; |
| 3340 | dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; |
| 3341 | break; |
| 3342 | } |
| 3343 | |
| 3344 | if (want_thermal_protection) { |
| 3345 | WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); |
| 3346 | if (pi->thermal_protection) |
| 3347 | WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); |
| 3348 | } else { |
| 3349 | WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); |
| 3350 | } |
| 3351 | } |
| 3352 | |
| 3353 | static void si_enable_auto_throttle_source(struct radeon_device *rdev, |
| 3354 | enum radeon_dpm_auto_throttle_src source, |
| 3355 | bool enable) |
| 3356 | { |
| 3357 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 3358 | |
| 3359 | if (enable) { |
| 3360 | if (!(pi->active_auto_throttle_sources & (1 << source))) { |
| 3361 | pi->active_auto_throttle_sources |= 1 << source; |
| 3362 | si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); |
| 3363 | } |
| 3364 | } else { |
| 3365 | if (pi->active_auto_throttle_sources & (1 << source)) { |
| 3366 | pi->active_auto_throttle_sources &= ~(1 << source); |
| 3367 | si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); |
| 3368 | } |
| 3369 | } |
| 3370 | } |
| 3371 | |
| 3372 | static void si_start_dpm(struct radeon_device *rdev) |
| 3373 | { |
| 3374 | WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); |
| 3375 | } |
| 3376 | |
| 3377 | static void si_stop_dpm(struct radeon_device *rdev) |
| 3378 | { |
| 3379 | WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); |
| 3380 | } |
| 3381 | |
| 3382 | static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) |
| 3383 | { |
| 3384 | if (enable) |
| 3385 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); |
| 3386 | else |
| 3387 | WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); |
| 3388 | |
| 3389 | } |
| 3390 | |
| 3391 | #if 0 |
| 3392 | static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, |
| 3393 | u32 thermal_level) |
| 3394 | { |
| 3395 | PPSMC_Result ret; |
| 3396 | |
| 3397 | if (thermal_level == 0) { |
| 3398 | ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); |
| 3399 | if (ret == PPSMC_Result_OK) |
| 3400 | return 0; |
| 3401 | else |
| 3402 | return -EINVAL; |
| 3403 | } |
| 3404 | return 0; |
| 3405 | } |
| 3406 | |
| 3407 | static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) |
| 3408 | { |
| 3409 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); |
| 3410 | } |
| 3411 | #endif |
| 3412 | |
| 3413 | #if 0 |
| 3414 | static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) |
| 3415 | { |
| 3416 | if (ac_power) |
| 3417 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? |
| 3418 | 0 : -EINVAL; |
| 3419 | |
| 3420 | return 0; |
| 3421 | } |
| 3422 | #endif |
| 3423 | |
| 3424 | static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, |
| 3425 | PPSMC_Msg msg, u32 parameter) |
| 3426 | { |
| 3427 | WREG32(SMC_SCRATCH0, parameter); |
| 3428 | return si_send_msg_to_smc(rdev, msg); |
| 3429 | } |
| 3430 | |
| 3431 | static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) |
| 3432 | { |
| 3433 | if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) |
| 3434 | return -EINVAL; |
| 3435 | |
| 3436 | return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? |
| 3437 | 0 : -EINVAL; |
| 3438 | } |
| 3439 | |
Alex Deucher | a160a6a | 2013-07-02 18:46:28 -0400 | [diff] [blame] | 3440 | int si_dpm_force_performance_level(struct radeon_device *rdev, |
| 3441 | enum radeon_dpm_forced_level level) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3442 | { |
Alex Deucher | a160a6a | 2013-07-02 18:46:28 -0400 | [diff] [blame] | 3443 | struct radeon_ps *rps = rdev->pm.dpm.current_ps; |
| 3444 | struct ni_ps *ps = ni_get_ps(rps); |
Alex Deucher | 63f22d0 | 2013-07-27 17:50:26 -0400 | [diff] [blame] | 3445 | u32 levels = ps->performance_level_count; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3446 | |
Alex Deucher | a160a6a | 2013-07-02 18:46:28 -0400 | [diff] [blame] | 3447 | if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { |
Alex Deucher | 63f22d0 | 2013-07-27 17:50:26 -0400 | [diff] [blame] | 3448 | if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) |
Alex Deucher | a160a6a | 2013-07-02 18:46:28 -0400 | [diff] [blame] | 3449 | return -EINVAL; |
| 3450 | |
| 3451 | if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) |
| 3452 | return -EINVAL; |
| 3453 | } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { |
| 3454 | if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) |
| 3455 | return -EINVAL; |
| 3456 | |
Alex Deucher | 63f22d0 | 2013-07-27 17:50:26 -0400 | [diff] [blame] | 3457 | if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) |
Alex Deucher | a160a6a | 2013-07-02 18:46:28 -0400 | [diff] [blame] | 3458 | return -EINVAL; |
| 3459 | } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { |
| 3460 | if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) |
| 3461 | return -EINVAL; |
| 3462 | |
Alex Deucher | 63f22d0 | 2013-07-27 17:50:26 -0400 | [diff] [blame] | 3463 | if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) |
Alex Deucher | a160a6a | 2013-07-02 18:46:28 -0400 | [diff] [blame] | 3464 | return -EINVAL; |
| 3465 | } |
| 3466 | |
| 3467 | rdev->pm.dpm.forced_level = level; |
| 3468 | |
| 3469 | return 0; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3470 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3471 | |
Alex Deucher | 9876913 | 2015-01-14 16:18:32 -0500 | [diff] [blame] | 3472 | #if 0 |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3473 | static int si_set_boot_state(struct radeon_device *rdev) |
| 3474 | { |
| 3475 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? |
| 3476 | 0 : -EINVAL; |
| 3477 | } |
Alex Deucher | 9876913 | 2015-01-14 16:18:32 -0500 | [diff] [blame] | 3478 | #endif |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3479 | |
| 3480 | static int si_set_sw_state(struct radeon_device *rdev) |
| 3481 | { |
| 3482 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? |
| 3483 | 0 : -EINVAL; |
| 3484 | } |
| 3485 | |
| 3486 | static int si_halt_smc(struct radeon_device *rdev) |
| 3487 | { |
| 3488 | if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) |
| 3489 | return -EINVAL; |
| 3490 | |
| 3491 | return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? |
| 3492 | 0 : -EINVAL; |
| 3493 | } |
| 3494 | |
| 3495 | static int si_resume_smc(struct radeon_device *rdev) |
| 3496 | { |
| 3497 | if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) |
| 3498 | return -EINVAL; |
| 3499 | |
| 3500 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? |
| 3501 | 0 : -EINVAL; |
| 3502 | } |
| 3503 | |
| 3504 | static void si_dpm_start_smc(struct radeon_device *rdev) |
| 3505 | { |
| 3506 | si_program_jump_on_start(rdev); |
| 3507 | si_start_smc(rdev); |
| 3508 | si_start_smc_clock(rdev); |
| 3509 | } |
| 3510 | |
| 3511 | static void si_dpm_stop_smc(struct radeon_device *rdev) |
| 3512 | { |
| 3513 | si_reset_smc(rdev); |
| 3514 | si_stop_smc_clock(rdev); |
| 3515 | } |
| 3516 | |
| 3517 | static int si_process_firmware_header(struct radeon_device *rdev) |
| 3518 | { |
| 3519 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 3520 | u32 tmp; |
| 3521 | int ret; |
| 3522 | |
| 3523 | ret = si_read_smc_sram_dword(rdev, |
| 3524 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + |
| 3525 | SISLANDS_SMC_FIRMWARE_HEADER_stateTable, |
| 3526 | &tmp, si_pi->sram_end); |
| 3527 | if (ret) |
| 3528 | return ret; |
| 3529 | |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 3530 | si_pi->state_table_start = tmp; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3531 | |
| 3532 | ret = si_read_smc_sram_dword(rdev, |
| 3533 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + |
| 3534 | SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, |
| 3535 | &tmp, si_pi->sram_end); |
| 3536 | if (ret) |
| 3537 | return ret; |
| 3538 | |
| 3539 | si_pi->soft_regs_start = tmp; |
| 3540 | |
| 3541 | ret = si_read_smc_sram_dword(rdev, |
| 3542 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + |
| 3543 | SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, |
| 3544 | &tmp, si_pi->sram_end); |
| 3545 | if (ret) |
| 3546 | return ret; |
| 3547 | |
| 3548 | si_pi->mc_reg_table_start = tmp; |
| 3549 | |
| 3550 | ret = si_read_smc_sram_dword(rdev, |
| 3551 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 3552 | SISLANDS_SMC_FIRMWARE_HEADER_fanTable, |
| 3553 | &tmp, si_pi->sram_end); |
| 3554 | if (ret) |
| 3555 | return ret; |
| 3556 | |
| 3557 | si_pi->fan_table_start = tmp; |
| 3558 | |
| 3559 | ret = si_read_smc_sram_dword(rdev, |
| 3560 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3561 | SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, |
| 3562 | &tmp, si_pi->sram_end); |
| 3563 | if (ret) |
| 3564 | return ret; |
| 3565 | |
| 3566 | si_pi->arb_table_start = tmp; |
| 3567 | |
| 3568 | ret = si_read_smc_sram_dword(rdev, |
| 3569 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + |
| 3570 | SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, |
| 3571 | &tmp, si_pi->sram_end); |
| 3572 | if (ret) |
| 3573 | return ret; |
| 3574 | |
| 3575 | si_pi->cac_table_start = tmp; |
| 3576 | |
| 3577 | ret = si_read_smc_sram_dword(rdev, |
| 3578 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + |
| 3579 | SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, |
| 3580 | &tmp, si_pi->sram_end); |
| 3581 | if (ret) |
| 3582 | return ret; |
| 3583 | |
| 3584 | si_pi->dte_table_start = tmp; |
| 3585 | |
| 3586 | ret = si_read_smc_sram_dword(rdev, |
| 3587 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + |
| 3588 | SISLANDS_SMC_FIRMWARE_HEADER_spllTable, |
| 3589 | &tmp, si_pi->sram_end); |
| 3590 | if (ret) |
| 3591 | return ret; |
| 3592 | |
| 3593 | si_pi->spll_table_start = tmp; |
| 3594 | |
| 3595 | ret = si_read_smc_sram_dword(rdev, |
| 3596 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + |
| 3597 | SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, |
| 3598 | &tmp, si_pi->sram_end); |
| 3599 | if (ret) |
| 3600 | return ret; |
| 3601 | |
| 3602 | si_pi->papm_cfg_table_start = tmp; |
| 3603 | |
| 3604 | return ret; |
| 3605 | } |
| 3606 | |
| 3607 | static void si_read_clock_registers(struct radeon_device *rdev) |
| 3608 | { |
| 3609 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 3610 | |
| 3611 | si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); |
| 3612 | si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); |
| 3613 | si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); |
| 3614 | si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); |
| 3615 | si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); |
| 3616 | si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); |
| 3617 | si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); |
| 3618 | si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); |
| 3619 | si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); |
| 3620 | si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); |
| 3621 | si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); |
| 3622 | si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); |
| 3623 | si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); |
| 3624 | si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); |
| 3625 | si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); |
| 3626 | } |
| 3627 | |
| 3628 | static void si_enable_thermal_protection(struct radeon_device *rdev, |
| 3629 | bool enable) |
| 3630 | { |
| 3631 | if (enable) |
| 3632 | WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); |
| 3633 | else |
| 3634 | WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); |
| 3635 | } |
| 3636 | |
| 3637 | static void si_enable_acpi_power_management(struct radeon_device *rdev) |
| 3638 | { |
| 3639 | WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); |
| 3640 | } |
| 3641 | |
| 3642 | #if 0 |
| 3643 | static int si_enter_ulp_state(struct radeon_device *rdev) |
| 3644 | { |
| 3645 | WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); |
| 3646 | |
| 3647 | udelay(25000); |
| 3648 | |
| 3649 | return 0; |
| 3650 | } |
| 3651 | |
| 3652 | static int si_exit_ulp_state(struct radeon_device *rdev) |
| 3653 | { |
| 3654 | int i; |
| 3655 | |
| 3656 | WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); |
| 3657 | |
| 3658 | udelay(7000); |
| 3659 | |
| 3660 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 3661 | if (RREG32(SMC_RESP_0) == 1) |
| 3662 | break; |
| 3663 | udelay(1000); |
| 3664 | } |
| 3665 | |
| 3666 | return 0; |
| 3667 | } |
| 3668 | #endif |
| 3669 | |
| 3670 | static int si_notify_smc_display_change(struct radeon_device *rdev, |
| 3671 | bool has_display) |
| 3672 | { |
| 3673 | PPSMC_Msg msg = has_display ? |
| 3674 | PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; |
| 3675 | |
| 3676 | return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? |
| 3677 | 0 : -EINVAL; |
| 3678 | } |
| 3679 | |
| 3680 | static void si_program_response_times(struct radeon_device *rdev) |
| 3681 | { |
| 3682 | u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; |
| 3683 | u32 vddc_dly, acpi_dly, vbi_dly; |
| 3684 | u32 reference_clock; |
| 3685 | |
| 3686 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); |
| 3687 | |
| 3688 | voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 3689 | backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3690 | |
| 3691 | if (voltage_response_time == 0) |
| 3692 | voltage_response_time = 1000; |
| 3693 | |
| 3694 | acpi_delay_time = 15000; |
| 3695 | vbi_time_out = 100000; |
| 3696 | |
| 3697 | reference_clock = radeon_get_xclk(rdev); |
| 3698 | |
| 3699 | vddc_dly = (voltage_response_time * reference_clock) / 100; |
| 3700 | acpi_dly = (acpi_delay_time * reference_clock) / 100; |
| 3701 | vbi_dly = (vbi_time_out * reference_clock) / 100; |
| 3702 | |
| 3703 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); |
| 3704 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); |
| 3705 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); |
| 3706 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); |
| 3707 | } |
| 3708 | |
| 3709 | static void si_program_ds_registers(struct radeon_device *rdev) |
| 3710 | { |
| 3711 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 3712 | u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ |
| 3713 | |
| 3714 | if (eg_pi->sclk_deep_sleep) { |
| 3715 | WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); |
| 3716 | WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, |
| 3717 | ~AUTOSCALE_ON_SS_CLEAR); |
| 3718 | } |
| 3719 | } |
| 3720 | |
| 3721 | static void si_program_display_gap(struct radeon_device *rdev) |
| 3722 | { |
| 3723 | u32 tmp, pipe; |
| 3724 | int i; |
| 3725 | |
| 3726 | tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); |
| 3727 | if (rdev->pm.dpm.new_active_crtc_count > 0) |
| 3728 | tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); |
| 3729 | else |
| 3730 | tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); |
| 3731 | |
| 3732 | if (rdev->pm.dpm.new_active_crtc_count > 1) |
| 3733 | tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); |
| 3734 | else |
| 3735 | tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); |
| 3736 | |
| 3737 | WREG32(CG_DISPLAY_GAP_CNTL, tmp); |
| 3738 | |
| 3739 | tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); |
| 3740 | pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; |
| 3741 | |
| 3742 | if ((rdev->pm.dpm.new_active_crtc_count > 0) && |
| 3743 | (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { |
| 3744 | /* find the first active crtc */ |
| 3745 | for (i = 0; i < rdev->num_crtc; i++) { |
| 3746 | if (rdev->pm.dpm.new_active_crtcs & (1 << i)) |
| 3747 | break; |
| 3748 | } |
| 3749 | if (i == rdev->num_crtc) |
| 3750 | pipe = 0; |
| 3751 | else |
| 3752 | pipe = i; |
| 3753 | |
| 3754 | tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; |
| 3755 | tmp |= DCCG_DISP1_SLOW_SELECT(pipe); |
| 3756 | WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); |
| 3757 | } |
| 3758 | |
Alex Deucher | 4573388 | 2013-10-10 12:31:43 -0400 | [diff] [blame] | 3759 | /* Setting this to false forces the performance state to low if the crtcs are disabled. |
| 3760 | * This can be a problem on PowerXpress systems or if you want to use the card |
Alex Deucher | ffcda35 | 2014-01-27 13:04:56 -0500 | [diff] [blame] | 3761 | * for offscreen rendering or compute if there are no crtcs enabled. |
Alex Deucher | 4573388 | 2013-10-10 12:31:43 -0400 | [diff] [blame] | 3762 | */ |
Alex Deucher | ffcda35 | 2014-01-27 13:04:56 -0500 | [diff] [blame] | 3763 | si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3764 | } |
| 3765 | |
| 3766 | static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) |
| 3767 | { |
| 3768 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 3769 | |
| 3770 | if (enable) { |
| 3771 | if (pi->sclk_ss) |
| 3772 | WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); |
| 3773 | } else { |
| 3774 | WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); |
| 3775 | WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); |
| 3776 | } |
| 3777 | } |
| 3778 | |
| 3779 | static void si_setup_bsp(struct radeon_device *rdev) |
| 3780 | { |
| 3781 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 3782 | u32 xclk = radeon_get_xclk(rdev); |
| 3783 | |
| 3784 | r600_calculate_u_and_p(pi->asi, |
| 3785 | xclk, |
| 3786 | 16, |
| 3787 | &pi->bsp, |
| 3788 | &pi->bsu); |
| 3789 | |
| 3790 | r600_calculate_u_and_p(pi->pasi, |
| 3791 | xclk, |
| 3792 | 16, |
| 3793 | &pi->pbsp, |
| 3794 | &pi->pbsu); |
| 3795 | |
| 3796 | |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 3797 | pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3798 | pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); |
| 3799 | |
| 3800 | WREG32(CG_BSP, pi->dsp); |
| 3801 | } |
| 3802 | |
| 3803 | static void si_program_git(struct radeon_device *rdev) |
| 3804 | { |
| 3805 | WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); |
| 3806 | } |
| 3807 | |
| 3808 | static void si_program_tp(struct radeon_device *rdev) |
| 3809 | { |
| 3810 | int i; |
| 3811 | enum r600_td td = R600_TD_DFLT; |
| 3812 | |
| 3813 | for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) |
| 3814 | WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); |
| 3815 | |
| 3816 | if (td == R600_TD_AUTO) |
| 3817 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); |
| 3818 | else |
| 3819 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); |
| 3820 | |
| 3821 | if (td == R600_TD_UP) |
| 3822 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); |
| 3823 | |
| 3824 | if (td == R600_TD_DOWN) |
| 3825 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); |
| 3826 | } |
| 3827 | |
| 3828 | static void si_program_tpp(struct radeon_device *rdev) |
| 3829 | { |
| 3830 | WREG32(CG_TPC, R600_TPC_DFLT); |
| 3831 | } |
| 3832 | |
| 3833 | static void si_program_sstp(struct radeon_device *rdev) |
| 3834 | { |
| 3835 | WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); |
| 3836 | } |
| 3837 | |
| 3838 | static void si_enable_display_gap(struct radeon_device *rdev) |
| 3839 | { |
| 3840 | u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); |
| 3841 | |
Alex Deucher | 489bc47 | 2013-07-26 18:05:07 -0400 | [diff] [blame] | 3842 | tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); |
| 3843 | tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | |
| 3844 | DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); |
| 3845 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3846 | tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); |
Alex Deucher | 489bc47 | 2013-07-26 18:05:07 -0400 | [diff] [blame] | 3847 | tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3848 | DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); |
| 3849 | WREG32(CG_DISPLAY_GAP_CNTL, tmp); |
| 3850 | } |
| 3851 | |
| 3852 | static void si_program_vc(struct radeon_device *rdev) |
| 3853 | { |
| 3854 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 3855 | |
| 3856 | WREG32(CG_FTV, pi->vrc); |
| 3857 | } |
| 3858 | |
| 3859 | static void si_clear_vc(struct radeon_device *rdev) |
| 3860 | { |
| 3861 | WREG32(CG_FTV, 0); |
| 3862 | } |
| 3863 | |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 3864 | u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3865 | { |
| 3866 | u8 mc_para_index; |
| 3867 | |
| 3868 | if (memory_clock < 10000) |
| 3869 | mc_para_index = 0; |
| 3870 | else if (memory_clock >= 80000) |
| 3871 | mc_para_index = 0x0f; |
| 3872 | else |
| 3873 | mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); |
| 3874 | return mc_para_index; |
| 3875 | } |
| 3876 | |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 3877 | u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3878 | { |
| 3879 | u8 mc_para_index; |
| 3880 | |
| 3881 | if (strobe_mode) { |
| 3882 | if (memory_clock < 12500) |
| 3883 | mc_para_index = 0x00; |
| 3884 | else if (memory_clock > 47500) |
| 3885 | mc_para_index = 0x0f; |
| 3886 | else |
| 3887 | mc_para_index = (u8)((memory_clock - 10000) / 2500); |
| 3888 | } else { |
| 3889 | if (memory_clock < 65000) |
| 3890 | mc_para_index = 0x00; |
| 3891 | else if (memory_clock > 135000) |
| 3892 | mc_para_index = 0x0f; |
| 3893 | else |
| 3894 | mc_para_index = (u8)((memory_clock - 60000) / 5000); |
| 3895 | } |
| 3896 | return mc_para_index; |
| 3897 | } |
| 3898 | |
| 3899 | static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) |
| 3900 | { |
| 3901 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 3902 | bool strobe_mode = false; |
| 3903 | u8 result = 0; |
| 3904 | |
| 3905 | if (mclk <= pi->mclk_strobe_mode_threshold) |
| 3906 | strobe_mode = true; |
| 3907 | |
| 3908 | if (pi->mem_gddr5) |
| 3909 | result = si_get_mclk_frequency_ratio(mclk, strobe_mode); |
| 3910 | else |
| 3911 | result = si_get_ddr3_mclk_frequency_ratio(mclk); |
| 3912 | |
| 3913 | if (strobe_mode) |
| 3914 | result |= SISLANDS_SMC_STROBE_ENABLE; |
| 3915 | |
| 3916 | return result; |
| 3917 | } |
| 3918 | |
| 3919 | static int si_upload_firmware(struct radeon_device *rdev) |
| 3920 | { |
| 3921 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 3922 | int ret; |
| 3923 | |
| 3924 | si_reset_smc(rdev); |
| 3925 | si_stop_smc_clock(rdev); |
| 3926 | |
| 3927 | ret = si_load_smc_ucode(rdev, si_pi->sram_end); |
| 3928 | |
| 3929 | return ret; |
| 3930 | } |
| 3931 | |
| 3932 | static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, |
| 3933 | const struct atom_voltage_table *table, |
| 3934 | const struct radeon_phase_shedding_limits_table *limits) |
| 3935 | { |
| 3936 | u32 data, num_bits, num_levels; |
| 3937 | |
| 3938 | if ((table == NULL) || (limits == NULL)) |
| 3939 | return false; |
| 3940 | |
| 3941 | data = table->mask_low; |
| 3942 | |
| 3943 | num_bits = hweight32(data); |
| 3944 | |
| 3945 | if (num_bits == 0) |
| 3946 | return false; |
| 3947 | |
| 3948 | num_levels = (1 << num_bits); |
| 3949 | |
| 3950 | if (table->count != num_levels) |
| 3951 | return false; |
| 3952 | |
| 3953 | if (limits->count != (num_levels - 1)) |
| 3954 | return false; |
| 3955 | |
| 3956 | return true; |
| 3957 | } |
| 3958 | |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 3959 | void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, |
| 3960 | u32 max_voltage_steps, |
| 3961 | struct atom_voltage_table *voltage_table) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3962 | { |
| 3963 | unsigned int i, diff; |
| 3964 | |
Alex Deucher | 9dd9333 | 2013-04-29 18:53:52 -0400 | [diff] [blame] | 3965 | if (voltage_table->count <= max_voltage_steps) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3966 | return; |
| 3967 | |
Alex Deucher | 9dd9333 | 2013-04-29 18:53:52 -0400 | [diff] [blame] | 3968 | diff = voltage_table->count - max_voltage_steps; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3969 | |
Alex Deucher | 9dd9333 | 2013-04-29 18:53:52 -0400 | [diff] [blame] | 3970 | for (i= 0; i < max_voltage_steps; i++) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3971 | voltage_table->entries[i] = voltage_table->entries[i + diff]; |
| 3972 | |
Alex Deucher | 9dd9333 | 2013-04-29 18:53:52 -0400 | [diff] [blame] | 3973 | voltage_table->count = max_voltage_steps; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3974 | } |
| 3975 | |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 3976 | static int si_get_svi2_voltage_table(struct radeon_device *rdev, |
| 3977 | struct radeon_clock_voltage_dependency_table *voltage_dependency_table, |
| 3978 | struct atom_voltage_table *voltage_table) |
| 3979 | { |
| 3980 | u32 i; |
| 3981 | |
| 3982 | if (voltage_dependency_table == NULL) |
| 3983 | return -EINVAL; |
| 3984 | |
| 3985 | voltage_table->mask_low = 0; |
| 3986 | voltage_table->phase_delay = 0; |
| 3987 | |
| 3988 | voltage_table->count = voltage_dependency_table->count; |
| 3989 | for (i = 0; i < voltage_table->count; i++) { |
| 3990 | voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; |
| 3991 | voltage_table->entries[i].smio_low = 0; |
| 3992 | } |
| 3993 | |
| 3994 | return 0; |
| 3995 | } |
| 3996 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 3997 | static int si_construct_voltage_tables(struct radeon_device *rdev) |
| 3998 | { |
| 3999 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 4000 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 4001 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4002 | int ret; |
| 4003 | |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 4004 | if (pi->voltage_control) { |
| 4005 | ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, |
| 4006 | VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); |
| 4007 | if (ret) |
| 4008 | return ret; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4009 | |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 4010 | if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) |
| 4011 | si_trim_voltage_table_to_fit_state_table(rdev, |
| 4012 | SISLANDS_MAX_NO_VREG_STEPS, |
| 4013 | &eg_pi->vddc_voltage_table); |
| 4014 | } else if (si_pi->voltage_control_svi2) { |
| 4015 | ret = si_get_svi2_voltage_table(rdev, |
| 4016 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, |
| 4017 | &eg_pi->vddc_voltage_table); |
| 4018 | if (ret) |
| 4019 | return ret; |
| 4020 | } else { |
| 4021 | return -EINVAL; |
| 4022 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4023 | |
| 4024 | if (eg_pi->vddci_control) { |
| 4025 | ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, |
| 4026 | VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); |
| 4027 | if (ret) |
| 4028 | return ret; |
| 4029 | |
| 4030 | if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) |
Alex Deucher | 9dd9333 | 2013-04-29 18:53:52 -0400 | [diff] [blame] | 4031 | si_trim_voltage_table_to_fit_state_table(rdev, |
| 4032 | SISLANDS_MAX_NO_VREG_STEPS, |
| 4033 | &eg_pi->vddci_voltage_table); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4034 | } |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 4035 | if (si_pi->vddci_control_svi2) { |
| 4036 | ret = si_get_svi2_voltage_table(rdev, |
| 4037 | &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, |
| 4038 | &eg_pi->vddci_voltage_table); |
| 4039 | if (ret) |
| 4040 | return ret; |
| 4041 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4042 | |
| 4043 | if (pi->mvdd_control) { |
| 4044 | ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, |
| 4045 | VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); |
| 4046 | |
| 4047 | if (ret) { |
| 4048 | pi->mvdd_control = false; |
| 4049 | return ret; |
| 4050 | } |
| 4051 | |
| 4052 | if (si_pi->mvdd_voltage_table.count == 0) { |
| 4053 | pi->mvdd_control = false; |
| 4054 | return -EINVAL; |
| 4055 | } |
| 4056 | |
| 4057 | if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) |
Alex Deucher | 9dd9333 | 2013-04-29 18:53:52 -0400 | [diff] [blame] | 4058 | si_trim_voltage_table_to_fit_state_table(rdev, |
| 4059 | SISLANDS_MAX_NO_VREG_STEPS, |
| 4060 | &si_pi->mvdd_voltage_table); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4061 | } |
| 4062 | |
| 4063 | if (si_pi->vddc_phase_shed_control) { |
| 4064 | ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, |
| 4065 | VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); |
| 4066 | if (ret) |
| 4067 | si_pi->vddc_phase_shed_control = false; |
| 4068 | |
| 4069 | if ((si_pi->vddc_phase_shed_table.count == 0) || |
| 4070 | (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) |
| 4071 | si_pi->vddc_phase_shed_control = false; |
| 4072 | } |
| 4073 | |
| 4074 | return 0; |
| 4075 | } |
| 4076 | |
| 4077 | static void si_populate_smc_voltage_table(struct radeon_device *rdev, |
| 4078 | const struct atom_voltage_table *voltage_table, |
| 4079 | SISLANDS_SMC_STATETABLE *table) |
| 4080 | { |
| 4081 | unsigned int i; |
| 4082 | |
| 4083 | for (i = 0; i < voltage_table->count; i++) |
| 4084 | table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); |
| 4085 | } |
| 4086 | |
| 4087 | static int si_populate_smc_voltage_tables(struct radeon_device *rdev, |
| 4088 | SISLANDS_SMC_STATETABLE *table) |
| 4089 | { |
| 4090 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 4091 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 4092 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4093 | u8 i; |
| 4094 | |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 4095 | if (si_pi->voltage_control_svi2) { |
| 4096 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, |
| 4097 | si_pi->svc_gpio_id); |
| 4098 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, |
| 4099 | si_pi->svd_gpio_id); |
| 4100 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, |
| 4101 | 2); |
| 4102 | } else { |
| 4103 | if (eg_pi->vddc_voltage_table.count) { |
| 4104 | si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); |
| 4105 | table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = |
| 4106 | cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4107 | |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 4108 | for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { |
| 4109 | if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { |
| 4110 | table->maxVDDCIndexInPPTable = i; |
| 4111 | break; |
| 4112 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4113 | } |
| 4114 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4115 | |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 4116 | if (eg_pi->vddci_voltage_table.count) { |
| 4117 | si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4118 | |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 4119 | table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = |
| 4120 | cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); |
| 4121 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4122 | |
| 4123 | |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 4124 | if (si_pi->mvdd_voltage_table.count) { |
| 4125 | si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4126 | |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 4127 | table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = |
| 4128 | cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); |
| 4129 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4130 | |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 4131 | if (si_pi->vddc_phase_shed_control) { |
| 4132 | if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, |
| 4133 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { |
| 4134 | si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4135 | |
Alex Deucher | 4279202 | 2016-09-27 14:51:53 -0400 | [diff] [blame] | 4136 | table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 4137 | cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4138 | |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 4139 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, |
| 4140 | (u32)si_pi->vddc_phase_shed_table.phase_delay); |
| 4141 | } else { |
| 4142 | si_pi->vddc_phase_shed_control = false; |
| 4143 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4144 | } |
| 4145 | } |
| 4146 | |
| 4147 | return 0; |
| 4148 | } |
| 4149 | |
| 4150 | static int si_populate_voltage_value(struct radeon_device *rdev, |
| 4151 | const struct atom_voltage_table *table, |
| 4152 | u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) |
| 4153 | { |
| 4154 | unsigned int i; |
| 4155 | |
| 4156 | for (i = 0; i < table->count; i++) { |
| 4157 | if (value <= table->entries[i].value) { |
| 4158 | voltage->index = (u8)i; |
| 4159 | voltage->value = cpu_to_be16(table->entries[i].value); |
| 4160 | break; |
| 4161 | } |
| 4162 | } |
| 4163 | |
| 4164 | if (i >= table->count) |
| 4165 | return -EINVAL; |
| 4166 | |
| 4167 | return 0; |
| 4168 | } |
| 4169 | |
| 4170 | static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, |
| 4171 | SISLANDS_SMC_VOLTAGE_VALUE *voltage) |
| 4172 | { |
| 4173 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 4174 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4175 | |
| 4176 | if (pi->mvdd_control) { |
| 4177 | if (mclk <= pi->mvdd_split_frequency) |
| 4178 | voltage->index = 0; |
| 4179 | else |
| 4180 | voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; |
| 4181 | |
| 4182 | voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); |
| 4183 | } |
| 4184 | return 0; |
| 4185 | } |
| 4186 | |
| 4187 | static int si_get_std_voltage_value(struct radeon_device *rdev, |
| 4188 | SISLANDS_SMC_VOLTAGE_VALUE *voltage, |
| 4189 | u16 *std_voltage) |
| 4190 | { |
| 4191 | u16 v_index; |
| 4192 | bool voltage_found = false; |
| 4193 | *std_voltage = be16_to_cpu(voltage->value); |
| 4194 | |
| 4195 | if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { |
| 4196 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { |
| 4197 | if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) |
| 4198 | return -EINVAL; |
| 4199 | |
| 4200 | for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { |
| 4201 | if (be16_to_cpu(voltage->value) == |
| 4202 | (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { |
| 4203 | voltage_found = true; |
| 4204 | if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) |
| 4205 | *std_voltage = |
| 4206 | rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; |
| 4207 | else |
| 4208 | *std_voltage = |
| 4209 | rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; |
| 4210 | break; |
| 4211 | } |
| 4212 | } |
| 4213 | |
| 4214 | if (!voltage_found) { |
| 4215 | for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { |
| 4216 | if (be16_to_cpu(voltage->value) <= |
| 4217 | (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { |
| 4218 | voltage_found = true; |
| 4219 | if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) |
| 4220 | *std_voltage = |
| 4221 | rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; |
| 4222 | else |
| 4223 | *std_voltage = |
| 4224 | rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; |
| 4225 | break; |
| 4226 | } |
| 4227 | } |
| 4228 | } |
| 4229 | } else { |
| 4230 | if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) |
| 4231 | *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; |
| 4232 | } |
| 4233 | } |
| 4234 | |
| 4235 | return 0; |
| 4236 | } |
| 4237 | |
| 4238 | static int si_populate_std_voltage_value(struct radeon_device *rdev, |
| 4239 | u16 value, u8 index, |
| 4240 | SISLANDS_SMC_VOLTAGE_VALUE *voltage) |
| 4241 | { |
| 4242 | voltage->index = index; |
| 4243 | voltage->value = cpu_to_be16(value); |
| 4244 | |
| 4245 | return 0; |
| 4246 | } |
| 4247 | |
| 4248 | static int si_populate_phase_shedding_value(struct radeon_device *rdev, |
| 4249 | const struct radeon_phase_shedding_limits_table *limits, |
| 4250 | u16 voltage, u32 sclk, u32 mclk, |
| 4251 | SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) |
| 4252 | { |
| 4253 | unsigned int i; |
| 4254 | |
| 4255 | for (i = 0; i < limits->count; i++) { |
| 4256 | if ((voltage <= limits->entries[i].voltage) && |
| 4257 | (sclk <= limits->entries[i].sclk) && |
| 4258 | (mclk <= limits->entries[i].mclk)) |
| 4259 | break; |
| 4260 | } |
| 4261 | |
| 4262 | smc_voltage->phase_settings = (u8)i; |
| 4263 | |
| 4264 | return 0; |
| 4265 | } |
| 4266 | |
| 4267 | static int si_init_arb_table_index(struct radeon_device *rdev) |
| 4268 | { |
| 4269 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4270 | u32 tmp; |
| 4271 | int ret; |
| 4272 | |
| 4273 | ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); |
| 4274 | if (ret) |
| 4275 | return ret; |
| 4276 | |
| 4277 | tmp &= 0x00FFFFFF; |
| 4278 | tmp |= MC_CG_ARB_FREQ_F1 << 24; |
| 4279 | |
| 4280 | return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); |
| 4281 | } |
| 4282 | |
| 4283 | static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) |
| 4284 | { |
| 4285 | return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); |
| 4286 | } |
| 4287 | |
| 4288 | static int si_reset_to_default(struct radeon_device *rdev) |
| 4289 | { |
| 4290 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? |
| 4291 | 0 : -EINVAL; |
| 4292 | } |
| 4293 | |
| 4294 | static int si_force_switch_to_arb_f0(struct radeon_device *rdev) |
| 4295 | { |
| 4296 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4297 | u32 tmp; |
| 4298 | int ret; |
| 4299 | |
| 4300 | ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, |
| 4301 | &tmp, si_pi->sram_end); |
| 4302 | if (ret) |
| 4303 | return ret; |
| 4304 | |
| 4305 | tmp = (tmp >> 24) & 0xff; |
| 4306 | |
| 4307 | if (tmp == MC_CG_ARB_FREQ_F0) |
| 4308 | return 0; |
| 4309 | |
| 4310 | return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); |
| 4311 | } |
| 4312 | |
| 4313 | static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, |
| 4314 | u32 engine_clock) |
| 4315 | { |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4316 | u32 dram_rows; |
| 4317 | u32 dram_refresh_rate; |
| 4318 | u32 mc_arb_rfsh_rate; |
| 4319 | u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
| 4320 | |
Alex Deucher | f44a012 | 2013-07-26 18:18:32 -0400 | [diff] [blame] | 4321 | if (tmp >= 4) |
| 4322 | dram_rows = 16384; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4323 | else |
Alex Deucher | f44a012 | 2013-07-26 18:18:32 -0400 | [diff] [blame] | 4324 | dram_rows = 1 << (tmp + 10); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4325 | |
| 4326 | dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); |
| 4327 | mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; |
| 4328 | |
| 4329 | return mc_arb_rfsh_rate; |
| 4330 | } |
| 4331 | |
| 4332 | static int si_populate_memory_timing_parameters(struct radeon_device *rdev, |
| 4333 | struct rv7xx_pl *pl, |
| 4334 | SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) |
| 4335 | { |
| 4336 | u32 dram_timing; |
| 4337 | u32 dram_timing2; |
| 4338 | u32 burst_time; |
| 4339 | |
| 4340 | arb_regs->mc_arb_rfsh_rate = |
| 4341 | (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); |
| 4342 | |
| 4343 | radeon_atom_set_engine_dram_timings(rdev, |
| 4344 | pl->sclk, |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 4345 | pl->mclk); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4346 | |
| 4347 | dram_timing = RREG32(MC_ARB_DRAM_TIMING); |
| 4348 | dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); |
| 4349 | burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; |
| 4350 | |
| 4351 | arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); |
| 4352 | arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); |
| 4353 | arb_regs->mc_arb_burst_time = (u8)burst_time; |
| 4354 | |
| 4355 | return 0; |
| 4356 | } |
| 4357 | |
| 4358 | static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, |
| 4359 | struct radeon_ps *radeon_state, |
| 4360 | unsigned int first_arb_set) |
| 4361 | { |
| 4362 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4363 | struct ni_ps *state = ni_get_ps(radeon_state); |
| 4364 | SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; |
| 4365 | int i, ret = 0; |
| 4366 | |
| 4367 | for (i = 0; i < state->performance_level_count; i++) { |
| 4368 | ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); |
| 4369 | if (ret) |
| 4370 | break; |
| 4371 | ret = si_copy_bytes_to_smc(rdev, |
| 4372 | si_pi->arb_table_start + |
| 4373 | offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + |
| 4374 | sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), |
| 4375 | (u8 *)&arb_regs, |
| 4376 | sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), |
| 4377 | si_pi->sram_end); |
| 4378 | if (ret) |
| 4379 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 4380 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4381 | |
| 4382 | return ret; |
| 4383 | } |
| 4384 | |
| 4385 | static int si_program_memory_timing_parameters(struct radeon_device *rdev, |
| 4386 | struct radeon_ps *radeon_new_state) |
| 4387 | { |
| 4388 | return si_do_program_memory_timing_parameters(rdev, radeon_new_state, |
| 4389 | SISLANDS_DRIVER_STATE_ARB_INDEX); |
| 4390 | } |
| 4391 | |
| 4392 | static int si_populate_initial_mvdd_value(struct radeon_device *rdev, |
| 4393 | struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) |
| 4394 | { |
| 4395 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 4396 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4397 | |
| 4398 | if (pi->mvdd_control) |
| 4399 | return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, |
| 4400 | si_pi->mvdd_bootup_value, voltage); |
| 4401 | |
| 4402 | return 0; |
| 4403 | } |
| 4404 | |
| 4405 | static int si_populate_smc_initial_state(struct radeon_device *rdev, |
| 4406 | struct radeon_ps *radeon_initial_state, |
| 4407 | SISLANDS_SMC_STATETABLE *table) |
| 4408 | { |
| 4409 | struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); |
| 4410 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 4411 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 4412 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4413 | u32 reg; |
| 4414 | int ret; |
| 4415 | |
| 4416 | table->initialState.levels[0].mclk.vDLL_CNTL = |
| 4417 | cpu_to_be32(si_pi->clock_registers.dll_cntl); |
| 4418 | table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = |
| 4419 | cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); |
| 4420 | table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = |
| 4421 | cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); |
| 4422 | table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = |
| 4423 | cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); |
| 4424 | table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = |
| 4425 | cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); |
| 4426 | table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = |
| 4427 | cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); |
| 4428 | table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = |
| 4429 | cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); |
| 4430 | table->initialState.levels[0].mclk.vMPLL_SS = |
| 4431 | cpu_to_be32(si_pi->clock_registers.mpll_ss1); |
| 4432 | table->initialState.levels[0].mclk.vMPLL_SS2 = |
| 4433 | cpu_to_be32(si_pi->clock_registers.mpll_ss2); |
| 4434 | |
| 4435 | table->initialState.levels[0].mclk.mclk_value = |
| 4436 | cpu_to_be32(initial_state->performance_levels[0].mclk); |
| 4437 | |
| 4438 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = |
| 4439 | cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); |
| 4440 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = |
| 4441 | cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); |
| 4442 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = |
| 4443 | cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); |
| 4444 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = |
| 4445 | cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); |
| 4446 | table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = |
| 4447 | cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); |
| 4448 | table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = |
| 4449 | cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); |
| 4450 | |
| 4451 | table->initialState.levels[0].sclk.sclk_value = |
| 4452 | cpu_to_be32(initial_state->performance_levels[0].sclk); |
| 4453 | |
| 4454 | table->initialState.levels[0].arbRefreshState = |
| 4455 | SISLANDS_INITIAL_STATE_ARB_INDEX; |
| 4456 | |
| 4457 | table->initialState.levels[0].ACIndex = 0; |
| 4458 | |
| 4459 | ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, |
| 4460 | initial_state->performance_levels[0].vddc, |
| 4461 | &table->initialState.levels[0].vddc); |
| 4462 | |
| 4463 | if (!ret) { |
| 4464 | u16 std_vddc; |
| 4465 | |
| 4466 | ret = si_get_std_voltage_value(rdev, |
| 4467 | &table->initialState.levels[0].vddc, |
| 4468 | &std_vddc); |
| 4469 | if (!ret) |
| 4470 | si_populate_std_voltage_value(rdev, std_vddc, |
| 4471 | table->initialState.levels[0].vddc.index, |
| 4472 | &table->initialState.levels[0].std_vddc); |
| 4473 | } |
| 4474 | |
| 4475 | if (eg_pi->vddci_control) |
| 4476 | si_populate_voltage_value(rdev, |
| 4477 | &eg_pi->vddci_voltage_table, |
| 4478 | initial_state->performance_levels[0].vddci, |
| 4479 | &table->initialState.levels[0].vddci); |
| 4480 | |
| 4481 | if (si_pi->vddc_phase_shed_control) |
| 4482 | si_populate_phase_shedding_value(rdev, |
| 4483 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, |
| 4484 | initial_state->performance_levels[0].vddc, |
| 4485 | initial_state->performance_levels[0].sclk, |
| 4486 | initial_state->performance_levels[0].mclk, |
| 4487 | &table->initialState.levels[0].vddc); |
| 4488 | |
| 4489 | si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); |
| 4490 | |
| 4491 | reg = CG_R(0xffff) | CG_L(0); |
| 4492 | table->initialState.levels[0].aT = cpu_to_be32(reg); |
| 4493 | |
| 4494 | table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); |
| 4495 | |
| 4496 | table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; |
| 4497 | |
| 4498 | if (pi->mem_gddr5) { |
| 4499 | table->initialState.levels[0].strobeMode = |
| 4500 | si_get_strobe_mode_settings(rdev, |
| 4501 | initial_state->performance_levels[0].mclk); |
| 4502 | |
| 4503 | if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) |
| 4504 | table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; |
| 4505 | else |
| 4506 | table->initialState.levels[0].mcFlags = 0; |
| 4507 | } |
| 4508 | |
| 4509 | table->initialState.levelCount = 1; |
| 4510 | |
| 4511 | table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; |
| 4512 | |
| 4513 | table->initialState.levels[0].dpm2.MaxPS = 0; |
| 4514 | table->initialState.levels[0].dpm2.NearTDPDec = 0; |
| 4515 | table->initialState.levels[0].dpm2.AboveSafeInc = 0; |
| 4516 | table->initialState.levels[0].dpm2.BelowSafeInc = 0; |
| 4517 | table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; |
| 4518 | |
| 4519 | reg = MIN_POWER_MASK | MAX_POWER_MASK; |
| 4520 | table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); |
| 4521 | |
| 4522 | reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; |
| 4523 | table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); |
| 4524 | |
| 4525 | return 0; |
| 4526 | } |
| 4527 | |
| 4528 | static int si_populate_smc_acpi_state(struct radeon_device *rdev, |
| 4529 | SISLANDS_SMC_STATETABLE *table) |
| 4530 | { |
| 4531 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 4532 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 4533 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4534 | u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; |
| 4535 | u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; |
| 4536 | u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; |
| 4537 | u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; |
| 4538 | u32 dll_cntl = si_pi->clock_registers.dll_cntl; |
| 4539 | u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; |
| 4540 | u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; |
| 4541 | u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; |
| 4542 | u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; |
| 4543 | u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; |
| 4544 | u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; |
| 4545 | u32 reg; |
| 4546 | int ret; |
| 4547 | |
| 4548 | table->ACPIState = table->initialState; |
| 4549 | |
| 4550 | table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; |
| 4551 | |
| 4552 | if (pi->acpi_vddc) { |
| 4553 | ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, |
| 4554 | pi->acpi_vddc, &table->ACPIState.levels[0].vddc); |
| 4555 | if (!ret) { |
| 4556 | u16 std_vddc; |
| 4557 | |
| 4558 | ret = si_get_std_voltage_value(rdev, |
| 4559 | &table->ACPIState.levels[0].vddc, &std_vddc); |
| 4560 | if (!ret) |
| 4561 | si_populate_std_voltage_value(rdev, std_vddc, |
| 4562 | table->ACPIState.levels[0].vddc.index, |
| 4563 | &table->ACPIState.levels[0].std_vddc); |
| 4564 | } |
| 4565 | table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; |
| 4566 | |
| 4567 | if (si_pi->vddc_phase_shed_control) { |
| 4568 | si_populate_phase_shedding_value(rdev, |
| 4569 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, |
| 4570 | pi->acpi_vddc, |
| 4571 | 0, |
| 4572 | 0, |
| 4573 | &table->ACPIState.levels[0].vddc); |
| 4574 | } |
| 4575 | } else { |
| 4576 | ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, |
| 4577 | pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); |
| 4578 | if (!ret) { |
| 4579 | u16 std_vddc; |
| 4580 | |
| 4581 | ret = si_get_std_voltage_value(rdev, |
| 4582 | &table->ACPIState.levels[0].vddc, &std_vddc); |
| 4583 | |
| 4584 | if (!ret) |
| 4585 | si_populate_std_voltage_value(rdev, std_vddc, |
| 4586 | table->ACPIState.levels[0].vddc.index, |
| 4587 | &table->ACPIState.levels[0].std_vddc); |
| 4588 | } |
| 4589 | table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, |
| 4590 | si_pi->sys_pcie_mask, |
| 4591 | si_pi->boot_pcie_gen, |
| 4592 | RADEON_PCIE_GEN1); |
| 4593 | |
| 4594 | if (si_pi->vddc_phase_shed_control) |
| 4595 | si_populate_phase_shedding_value(rdev, |
| 4596 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, |
| 4597 | pi->min_vddc_in_table, |
| 4598 | 0, |
| 4599 | 0, |
| 4600 | &table->ACPIState.levels[0].vddc); |
| 4601 | } |
| 4602 | |
| 4603 | if (pi->acpi_vddc) { |
| 4604 | if (eg_pi->acpi_vddci) |
| 4605 | si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, |
| 4606 | eg_pi->acpi_vddci, |
| 4607 | &table->ACPIState.levels[0].vddci); |
| 4608 | } |
| 4609 | |
| 4610 | mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; |
| 4611 | mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); |
| 4612 | |
| 4613 | dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); |
| 4614 | |
| 4615 | spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; |
| 4616 | spll_func_cntl_2 |= SCLK_MUX_SEL(4); |
| 4617 | |
| 4618 | table->ACPIState.levels[0].mclk.vDLL_CNTL = |
| 4619 | cpu_to_be32(dll_cntl); |
| 4620 | table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = |
| 4621 | cpu_to_be32(mclk_pwrmgt_cntl); |
| 4622 | table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = |
| 4623 | cpu_to_be32(mpll_ad_func_cntl); |
| 4624 | table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = |
| 4625 | cpu_to_be32(mpll_dq_func_cntl); |
| 4626 | table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = |
| 4627 | cpu_to_be32(mpll_func_cntl); |
| 4628 | table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = |
| 4629 | cpu_to_be32(mpll_func_cntl_1); |
| 4630 | table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = |
| 4631 | cpu_to_be32(mpll_func_cntl_2); |
| 4632 | table->ACPIState.levels[0].mclk.vMPLL_SS = |
| 4633 | cpu_to_be32(si_pi->clock_registers.mpll_ss1); |
| 4634 | table->ACPIState.levels[0].mclk.vMPLL_SS2 = |
| 4635 | cpu_to_be32(si_pi->clock_registers.mpll_ss2); |
| 4636 | |
| 4637 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = |
| 4638 | cpu_to_be32(spll_func_cntl); |
| 4639 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = |
| 4640 | cpu_to_be32(spll_func_cntl_2); |
| 4641 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = |
| 4642 | cpu_to_be32(spll_func_cntl_3); |
| 4643 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = |
| 4644 | cpu_to_be32(spll_func_cntl_4); |
| 4645 | |
| 4646 | table->ACPIState.levels[0].mclk.mclk_value = 0; |
| 4647 | table->ACPIState.levels[0].sclk.sclk_value = 0; |
| 4648 | |
| 4649 | si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); |
| 4650 | |
| 4651 | if (eg_pi->dynamic_ac_timing) |
| 4652 | table->ACPIState.levels[0].ACIndex = 0; |
| 4653 | |
| 4654 | table->ACPIState.levels[0].dpm2.MaxPS = 0; |
| 4655 | table->ACPIState.levels[0].dpm2.NearTDPDec = 0; |
| 4656 | table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; |
| 4657 | table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; |
| 4658 | table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; |
| 4659 | |
| 4660 | reg = MIN_POWER_MASK | MAX_POWER_MASK; |
| 4661 | table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); |
| 4662 | |
| 4663 | reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; |
| 4664 | table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); |
| 4665 | |
| 4666 | return 0; |
| 4667 | } |
| 4668 | |
| 4669 | static int si_populate_ulv_state(struct radeon_device *rdev, |
| 4670 | SISLANDS_SMC_SWSTATE *state) |
| 4671 | { |
| 4672 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 4673 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4674 | struct si_ulv_param *ulv = &si_pi->ulv; |
| 4675 | u32 sclk_in_sr = 1350; /* ??? */ |
| 4676 | int ret; |
| 4677 | |
| 4678 | ret = si_convert_power_level_to_smc(rdev, &ulv->pl, |
| 4679 | &state->levels[0]); |
| 4680 | if (!ret) { |
| 4681 | if (eg_pi->sclk_deep_sleep) { |
| 4682 | if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) |
| 4683 | state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; |
| 4684 | else |
| 4685 | state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; |
| 4686 | } |
| 4687 | if (ulv->one_pcie_lane_in_ulv) |
| 4688 | state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; |
| 4689 | state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); |
| 4690 | state->levels[0].ACIndex = 1; |
| 4691 | state->levels[0].std_vddc = state->levels[0].vddc; |
| 4692 | state->levelCount = 1; |
| 4693 | |
| 4694 | state->flags |= PPSMC_SWSTATE_FLAG_DC; |
| 4695 | } |
| 4696 | |
| 4697 | return ret; |
| 4698 | } |
| 4699 | |
| 4700 | static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) |
| 4701 | { |
| 4702 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4703 | struct si_ulv_param *ulv = &si_pi->ulv; |
| 4704 | SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; |
| 4705 | int ret; |
| 4706 | |
| 4707 | ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, |
| 4708 | &arb_regs); |
| 4709 | if (ret) |
| 4710 | return ret; |
| 4711 | |
| 4712 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, |
| 4713 | ulv->volt_change_delay); |
| 4714 | |
| 4715 | ret = si_copy_bytes_to_smc(rdev, |
| 4716 | si_pi->arb_table_start + |
| 4717 | offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + |
| 4718 | sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, |
| 4719 | (u8 *)&arb_regs, |
| 4720 | sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), |
| 4721 | si_pi->sram_end); |
| 4722 | |
| 4723 | return ret; |
| 4724 | } |
| 4725 | |
| 4726 | static void si_get_mvdd_configuration(struct radeon_device *rdev) |
| 4727 | { |
| 4728 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 4729 | |
| 4730 | pi->mvdd_split_frequency = 30000; |
| 4731 | } |
| 4732 | |
| 4733 | static int si_init_smc_table(struct radeon_device *rdev) |
| 4734 | { |
| 4735 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 4736 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4737 | struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; |
| 4738 | const struct si_ulv_param *ulv = &si_pi->ulv; |
| 4739 | SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; |
| 4740 | int ret; |
| 4741 | u32 lane_width; |
| 4742 | u32 vr_hot_gpio; |
| 4743 | |
| 4744 | si_populate_smc_voltage_tables(rdev, table); |
| 4745 | |
| 4746 | switch (rdev->pm.int_thermal_type) { |
| 4747 | case THERMAL_TYPE_SI: |
| 4748 | case THERMAL_TYPE_EMC2103_WITH_INTERNAL: |
| 4749 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; |
| 4750 | break; |
| 4751 | case THERMAL_TYPE_NONE: |
| 4752 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; |
| 4753 | break; |
| 4754 | default: |
| 4755 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; |
| 4756 | break; |
| 4757 | } |
| 4758 | |
| 4759 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) |
| 4760 | table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; |
| 4761 | |
| 4762 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { |
| 4763 | if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) |
| 4764 | table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; |
| 4765 | } |
| 4766 | |
| 4767 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) |
| 4768 | table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; |
| 4769 | |
| 4770 | if (pi->mem_gddr5) |
| 4771 | table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; |
| 4772 | |
| 4773 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) |
Alex Deucher | 6960394 | 2013-11-01 13:30:55 -0400 | [diff] [blame] | 4774 | table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4775 | |
| 4776 | if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { |
| 4777 | table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; |
| 4778 | vr_hot_gpio = rdev->pm.dpm.backbias_response_time; |
| 4779 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, |
| 4780 | vr_hot_gpio); |
| 4781 | } |
| 4782 | |
| 4783 | ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); |
| 4784 | if (ret) |
| 4785 | return ret; |
| 4786 | |
| 4787 | ret = si_populate_smc_acpi_state(rdev, table); |
| 4788 | if (ret) |
| 4789 | return ret; |
| 4790 | |
| 4791 | table->driverState = table->initialState; |
| 4792 | |
| 4793 | ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, |
| 4794 | SISLANDS_INITIAL_STATE_ARB_INDEX); |
| 4795 | if (ret) |
| 4796 | return ret; |
| 4797 | |
| 4798 | if (ulv->supported && ulv->pl.vddc) { |
| 4799 | ret = si_populate_ulv_state(rdev, &table->ULVState); |
| 4800 | if (ret) |
| 4801 | return ret; |
| 4802 | |
| 4803 | ret = si_program_ulv_memory_timing_parameters(rdev); |
| 4804 | if (ret) |
| 4805 | return ret; |
| 4806 | |
| 4807 | WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); |
| 4808 | WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); |
| 4809 | |
| 4810 | lane_width = radeon_get_pcie_lanes(rdev); |
| 4811 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); |
| 4812 | } else { |
| 4813 | table->ULVState = table->initialState; |
| 4814 | } |
| 4815 | |
| 4816 | return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, |
| 4817 | (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), |
| 4818 | si_pi->sram_end); |
| 4819 | } |
| 4820 | |
| 4821 | static int si_calculate_sclk_params(struct radeon_device *rdev, |
| 4822 | u32 engine_clock, |
| 4823 | SISLANDS_SMC_SCLK_VALUE *sclk) |
| 4824 | { |
| 4825 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 4826 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4827 | struct atom_clock_dividers dividers; |
| 4828 | u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; |
| 4829 | u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; |
| 4830 | u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; |
| 4831 | u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; |
| 4832 | u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; |
| 4833 | u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; |
| 4834 | u64 tmp; |
| 4835 | u32 reference_clock = rdev->clock.spll.reference_freq; |
| 4836 | u32 reference_divider; |
| 4837 | u32 fbdiv; |
| 4838 | int ret; |
| 4839 | |
| 4840 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
| 4841 | engine_clock, false, ÷rs); |
| 4842 | if (ret) |
| 4843 | return ret; |
| 4844 | |
| 4845 | reference_divider = 1 + dividers.ref_div; |
| 4846 | |
| 4847 | tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; |
| 4848 | do_div(tmp, reference_clock); |
| 4849 | fbdiv = (u32) tmp; |
| 4850 | |
| 4851 | spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); |
| 4852 | spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); |
| 4853 | spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); |
| 4854 | |
| 4855 | spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; |
| 4856 | spll_func_cntl_2 |= SCLK_MUX_SEL(2); |
| 4857 | |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 4858 | spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; |
| 4859 | spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); |
| 4860 | spll_func_cntl_3 |= SPLL_DITHEN; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4861 | |
| 4862 | if (pi->sclk_ss) { |
| 4863 | struct radeon_atom_ss ss; |
| 4864 | u32 vco_freq = engine_clock * dividers.post_div; |
| 4865 | |
| 4866 | if (radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 4867 | ASIC_INTERNAL_ENGINE_SS, vco_freq)) { |
| 4868 | u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); |
| 4869 | u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); |
| 4870 | |
| 4871 | cg_spll_spread_spectrum &= ~CLK_S_MASK; |
| 4872 | cg_spll_spread_spectrum |= CLK_S(clk_s); |
| 4873 | cg_spll_spread_spectrum |= SSEN; |
| 4874 | |
| 4875 | cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; |
| 4876 | cg_spll_spread_spectrum_2 |= CLK_V(clk_v); |
| 4877 | } |
| 4878 | } |
| 4879 | |
| 4880 | sclk->sclk_value = engine_clock; |
| 4881 | sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; |
| 4882 | sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; |
| 4883 | sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; |
| 4884 | sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; |
| 4885 | sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; |
| 4886 | sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; |
| 4887 | |
| 4888 | return 0; |
| 4889 | } |
| 4890 | |
| 4891 | static int si_populate_sclk_value(struct radeon_device *rdev, |
| 4892 | u32 engine_clock, |
| 4893 | SISLANDS_SMC_SCLK_VALUE *sclk) |
| 4894 | { |
| 4895 | SISLANDS_SMC_SCLK_VALUE sclk_tmp; |
| 4896 | int ret; |
| 4897 | |
| 4898 | ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); |
| 4899 | if (!ret) { |
| 4900 | sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); |
| 4901 | sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); |
| 4902 | sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); |
| 4903 | sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); |
| 4904 | sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); |
| 4905 | sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); |
| 4906 | sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); |
| 4907 | } |
| 4908 | |
| 4909 | return ret; |
| 4910 | } |
| 4911 | |
| 4912 | static int si_populate_mclk_value(struct radeon_device *rdev, |
| 4913 | u32 engine_clock, |
| 4914 | u32 memory_clock, |
| 4915 | SISLANDS_SMC_MCLK_VALUE *mclk, |
| 4916 | bool strobe_mode, |
| 4917 | bool dll_state_on) |
| 4918 | { |
| 4919 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 4920 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 4921 | u32 dll_cntl = si_pi->clock_registers.dll_cntl; |
| 4922 | u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; |
| 4923 | u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; |
| 4924 | u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; |
| 4925 | u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; |
| 4926 | u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; |
| 4927 | u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; |
| 4928 | u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; |
| 4929 | u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; |
| 4930 | struct atom_mpll_param mpll_param; |
| 4931 | int ret; |
| 4932 | |
| 4933 | ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); |
| 4934 | if (ret) |
| 4935 | return ret; |
| 4936 | |
| 4937 | mpll_func_cntl &= ~BWCTRL_MASK; |
| 4938 | mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); |
| 4939 | |
| 4940 | mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); |
| 4941 | mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | |
| 4942 | CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); |
| 4943 | |
| 4944 | mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; |
| 4945 | mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); |
| 4946 | |
| 4947 | if (pi->mem_gddr5) { |
| 4948 | mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); |
| 4949 | mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | |
| 4950 | YCLK_POST_DIV(mpll_param.post_div); |
| 4951 | } |
| 4952 | |
| 4953 | if (pi->mclk_ss) { |
| 4954 | struct radeon_atom_ss ss; |
| 4955 | u32 freq_nom; |
| 4956 | u32 tmp; |
| 4957 | u32 reference_clock = rdev->clock.mpll.reference_freq; |
| 4958 | |
| 4959 | if (pi->mem_gddr5) |
| 4960 | freq_nom = memory_clock * 4; |
| 4961 | else |
| 4962 | freq_nom = memory_clock * 2; |
| 4963 | |
| 4964 | tmp = freq_nom / reference_clock; |
| 4965 | tmp = tmp * tmp; |
| 4966 | if (radeon_atombios_get_asic_ss_info(rdev, &ss, |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 4967 | ASIC_INTERNAL_MEMORY_SS, freq_nom)) { |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4968 | u32 clks = reference_clock * 5 / ss.rate; |
| 4969 | u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); |
| 4970 | |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 4971 | mpll_ss1 &= ~CLKV_MASK; |
| 4972 | mpll_ss1 |= CLKV(clkv); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4973 | |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 4974 | mpll_ss2 &= ~CLKS_MASK; |
| 4975 | mpll_ss2 |= CLKS(clks); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 4976 | } |
| 4977 | } |
| 4978 | |
| 4979 | mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; |
| 4980 | mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); |
| 4981 | |
| 4982 | if (dll_state_on) |
| 4983 | mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; |
| 4984 | else |
| 4985 | mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); |
| 4986 | |
| 4987 | mclk->mclk_value = cpu_to_be32(memory_clock); |
| 4988 | mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); |
| 4989 | mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); |
| 4990 | mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); |
| 4991 | mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); |
| 4992 | mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); |
| 4993 | mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); |
| 4994 | mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); |
| 4995 | mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); |
| 4996 | mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); |
| 4997 | |
| 4998 | return 0; |
| 4999 | } |
| 5000 | |
| 5001 | static void si_populate_smc_sp(struct radeon_device *rdev, |
| 5002 | struct radeon_ps *radeon_state, |
| 5003 | SISLANDS_SMC_SWSTATE *smc_state) |
| 5004 | { |
| 5005 | struct ni_ps *ps = ni_get_ps(radeon_state); |
| 5006 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 5007 | int i; |
| 5008 | |
| 5009 | for (i = 0; i < ps->performance_level_count - 1; i++) |
| 5010 | smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); |
| 5011 | |
| 5012 | smc_state->levels[ps->performance_level_count - 1].bSP = |
| 5013 | cpu_to_be32(pi->psp); |
| 5014 | } |
| 5015 | |
| 5016 | static int si_convert_power_level_to_smc(struct radeon_device *rdev, |
| 5017 | struct rv7xx_pl *pl, |
| 5018 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) |
| 5019 | { |
| 5020 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 5021 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 5022 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5023 | int ret; |
| 5024 | bool dll_state_on; |
| 5025 | u16 std_vddc; |
| 5026 | bool gmc_pg = false; |
| 5027 | |
| 5028 | if (eg_pi->pcie_performance_request && |
| 5029 | (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) |
| 5030 | level->gen2PCIE = (u8)si_pi->force_pcie_gen; |
| 5031 | else |
| 5032 | level->gen2PCIE = (u8)pl->pcie_gen; |
| 5033 | |
| 5034 | ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); |
| 5035 | if (ret) |
| 5036 | return ret; |
| 5037 | |
| 5038 | level->mcFlags = 0; |
| 5039 | |
| 5040 | if (pi->mclk_stutter_mode_threshold && |
| 5041 | (pl->mclk <= pi->mclk_stutter_mode_threshold) && |
| 5042 | !eg_pi->uvd_enabled && |
| 5043 | (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && |
| 5044 | (rdev->pm.dpm.new_active_crtc_count <= 2)) { |
| 5045 | level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; |
| 5046 | |
| 5047 | if (gmc_pg) |
| 5048 | level->mcFlags |= SISLANDS_SMC_MC_PG_EN; |
| 5049 | } |
| 5050 | |
| 5051 | if (pi->mem_gddr5) { |
| 5052 | if (pl->mclk > pi->mclk_edc_enable_threshold) |
| 5053 | level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; |
| 5054 | |
| 5055 | if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) |
| 5056 | level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; |
| 5057 | |
| 5058 | level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); |
| 5059 | |
| 5060 | if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { |
| 5061 | if (si_get_mclk_frequency_ratio(pl->mclk, true) >= |
| 5062 | ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) |
| 5063 | dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; |
| 5064 | else |
| 5065 | dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; |
| 5066 | } else { |
| 5067 | dll_state_on = false; |
| 5068 | } |
| 5069 | } else { |
| 5070 | level->strobeMode = si_get_strobe_mode_settings(rdev, |
| 5071 | pl->mclk); |
| 5072 | |
| 5073 | dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; |
| 5074 | } |
| 5075 | |
| 5076 | ret = si_populate_mclk_value(rdev, |
| 5077 | pl->sclk, |
| 5078 | pl->mclk, |
| 5079 | &level->mclk, |
| 5080 | (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); |
| 5081 | if (ret) |
| 5082 | return ret; |
| 5083 | |
| 5084 | ret = si_populate_voltage_value(rdev, |
| 5085 | &eg_pi->vddc_voltage_table, |
| 5086 | pl->vddc, &level->vddc); |
| 5087 | if (ret) |
| 5088 | return ret; |
| 5089 | |
| 5090 | |
| 5091 | ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); |
| 5092 | if (ret) |
| 5093 | return ret; |
| 5094 | |
| 5095 | ret = si_populate_std_voltage_value(rdev, std_vddc, |
| 5096 | level->vddc.index, &level->std_vddc); |
| 5097 | if (ret) |
| 5098 | return ret; |
| 5099 | |
| 5100 | if (eg_pi->vddci_control) { |
| 5101 | ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, |
| 5102 | pl->vddci, &level->vddci); |
| 5103 | if (ret) |
| 5104 | return ret; |
| 5105 | } |
| 5106 | |
| 5107 | if (si_pi->vddc_phase_shed_control) { |
| 5108 | ret = si_populate_phase_shedding_value(rdev, |
| 5109 | &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, |
| 5110 | pl->vddc, |
| 5111 | pl->sclk, |
| 5112 | pl->mclk, |
| 5113 | &level->vddc); |
| 5114 | if (ret) |
| 5115 | return ret; |
| 5116 | } |
| 5117 | |
| 5118 | level->MaxPoweredUpCU = si_pi->max_cu; |
| 5119 | |
| 5120 | ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); |
| 5121 | |
| 5122 | return ret; |
| 5123 | } |
| 5124 | |
| 5125 | static int si_populate_smc_t(struct radeon_device *rdev, |
| 5126 | struct radeon_ps *radeon_state, |
| 5127 | SISLANDS_SMC_SWSTATE *smc_state) |
| 5128 | { |
| 5129 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 5130 | struct ni_ps *state = ni_get_ps(radeon_state); |
| 5131 | u32 a_t; |
| 5132 | u32 t_l, t_h; |
| 5133 | u32 high_bsp; |
| 5134 | int i, ret; |
| 5135 | |
| 5136 | if (state->performance_level_count >= 9) |
| 5137 | return -EINVAL; |
| 5138 | |
| 5139 | if (state->performance_level_count < 2) { |
| 5140 | a_t = CG_R(0xffff) | CG_L(0); |
| 5141 | smc_state->levels[0].aT = cpu_to_be32(a_t); |
| 5142 | return 0; |
| 5143 | } |
| 5144 | |
| 5145 | smc_state->levels[0].aT = cpu_to_be32(0); |
| 5146 | |
| 5147 | for (i = 0; i <= state->performance_level_count - 2; i++) { |
| 5148 | ret = r600_calculate_at( |
| 5149 | (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), |
| 5150 | 100 * R600_AH_DFLT, |
| 5151 | state->performance_levels[i + 1].sclk, |
| 5152 | state->performance_levels[i].sclk, |
| 5153 | &t_l, |
| 5154 | &t_h); |
| 5155 | |
| 5156 | if (ret) { |
| 5157 | t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; |
| 5158 | t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; |
| 5159 | } |
| 5160 | |
| 5161 | a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; |
| 5162 | a_t |= CG_R(t_l * pi->bsp / 20000); |
| 5163 | smc_state->levels[i].aT = cpu_to_be32(a_t); |
| 5164 | |
| 5165 | high_bsp = (i == state->performance_level_count - 2) ? |
| 5166 | pi->pbsp : pi->bsp; |
| 5167 | a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); |
| 5168 | smc_state->levels[i + 1].aT = cpu_to_be32(a_t); |
| 5169 | } |
| 5170 | |
| 5171 | return 0; |
| 5172 | } |
| 5173 | |
| 5174 | static int si_disable_ulv(struct radeon_device *rdev) |
| 5175 | { |
| 5176 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5177 | struct si_ulv_param *ulv = &si_pi->ulv; |
| 5178 | |
| 5179 | if (ulv->supported) |
| 5180 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? |
| 5181 | 0 : -EINVAL; |
| 5182 | |
| 5183 | return 0; |
| 5184 | } |
| 5185 | |
| 5186 | static bool si_is_state_ulv_compatible(struct radeon_device *rdev, |
| 5187 | struct radeon_ps *radeon_state) |
| 5188 | { |
| 5189 | const struct si_power_info *si_pi = si_get_pi(rdev); |
| 5190 | const struct si_ulv_param *ulv = &si_pi->ulv; |
| 5191 | const struct ni_ps *state = ni_get_ps(radeon_state); |
| 5192 | int i; |
| 5193 | |
| 5194 | if (state->performance_levels[0].mclk != ulv->pl.mclk) |
| 5195 | return false; |
| 5196 | |
| 5197 | /* XXX validate against display requirements! */ |
| 5198 | |
| 5199 | for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { |
| 5200 | if (rdev->clock.current_dispclk <= |
| 5201 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { |
| 5202 | if (ulv->pl.vddc < |
| 5203 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) |
| 5204 | return false; |
| 5205 | } |
| 5206 | } |
| 5207 | |
| 5208 | if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) |
| 5209 | return false; |
| 5210 | |
| 5211 | return true; |
| 5212 | } |
| 5213 | |
| 5214 | static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, |
| 5215 | struct radeon_ps *radeon_new_state) |
| 5216 | { |
| 5217 | const struct si_power_info *si_pi = si_get_pi(rdev); |
| 5218 | const struct si_ulv_param *ulv = &si_pi->ulv; |
| 5219 | |
| 5220 | if (ulv->supported) { |
| 5221 | if (si_is_state_ulv_compatible(rdev, radeon_new_state)) |
| 5222 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? |
| 5223 | 0 : -EINVAL; |
| 5224 | } |
| 5225 | return 0; |
| 5226 | } |
| 5227 | |
| 5228 | static int si_convert_power_state_to_smc(struct radeon_device *rdev, |
| 5229 | struct radeon_ps *radeon_state, |
| 5230 | SISLANDS_SMC_SWSTATE *smc_state) |
| 5231 | { |
| 5232 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 5233 | struct ni_power_info *ni_pi = ni_get_pi(rdev); |
| 5234 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5235 | struct ni_ps *state = ni_get_ps(radeon_state); |
| 5236 | int i, ret; |
| 5237 | u32 threshold; |
| 5238 | u32 sclk_in_sr = 1350; /* ??? */ |
| 5239 | |
| 5240 | if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) |
| 5241 | return -EINVAL; |
| 5242 | |
| 5243 | threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; |
| 5244 | |
| 5245 | if (radeon_state->vclk && radeon_state->dclk) { |
| 5246 | eg_pi->uvd_enabled = true; |
| 5247 | if (eg_pi->smu_uvd_hs) |
| 5248 | smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; |
| 5249 | } else { |
| 5250 | eg_pi->uvd_enabled = false; |
| 5251 | } |
| 5252 | |
| 5253 | if (state->dc_compatible) |
| 5254 | smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; |
| 5255 | |
| 5256 | smc_state->levelCount = 0; |
| 5257 | for (i = 0; i < state->performance_level_count; i++) { |
| 5258 | if (eg_pi->sclk_deep_sleep) { |
| 5259 | if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { |
| 5260 | if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) |
| 5261 | smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; |
| 5262 | else |
| 5263 | smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; |
| 5264 | } |
| 5265 | } |
| 5266 | |
| 5267 | ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], |
| 5268 | &smc_state->levels[i]); |
| 5269 | smc_state->levels[i].arbRefreshState = |
| 5270 | (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); |
| 5271 | |
| 5272 | if (ret) |
| 5273 | return ret; |
| 5274 | |
| 5275 | if (ni_pi->enable_power_containment) |
| 5276 | smc_state->levels[i].displayWatermark = |
| 5277 | (state->performance_levels[i].sclk < threshold) ? |
| 5278 | PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; |
| 5279 | else |
| 5280 | smc_state->levels[i].displayWatermark = (i < 2) ? |
| 5281 | PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; |
| 5282 | |
| 5283 | if (eg_pi->dynamic_ac_timing) |
| 5284 | smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; |
| 5285 | else |
| 5286 | smc_state->levels[i].ACIndex = 0; |
| 5287 | |
| 5288 | smc_state->levelCount++; |
| 5289 | } |
| 5290 | |
| 5291 | si_write_smc_soft_register(rdev, |
| 5292 | SI_SMC_SOFT_REGISTER_watermark_threshold, |
| 5293 | threshold / 512); |
| 5294 | |
| 5295 | si_populate_smc_sp(rdev, radeon_state, smc_state); |
| 5296 | |
| 5297 | ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); |
| 5298 | if (ret) |
| 5299 | ni_pi->enable_power_containment = false; |
| 5300 | |
| 5301 | ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5302 | if (ret) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5303 | ni_pi->enable_sq_ramping = false; |
| 5304 | |
| 5305 | return si_populate_smc_t(rdev, radeon_state, smc_state); |
| 5306 | } |
| 5307 | |
| 5308 | static int si_upload_sw_state(struct radeon_device *rdev, |
| 5309 | struct radeon_ps *radeon_new_state) |
| 5310 | { |
| 5311 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5312 | struct ni_ps *new_state = ni_get_ps(radeon_new_state); |
| 5313 | int ret; |
| 5314 | u32 address = si_pi->state_table_start + |
| 5315 | offsetof(SISLANDS_SMC_STATETABLE, driverState); |
| 5316 | u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + |
| 5317 | ((new_state->performance_level_count - 1) * |
| 5318 | sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); |
| 5319 | SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; |
| 5320 | |
| 5321 | memset(smc_state, 0, state_size); |
| 5322 | |
| 5323 | ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); |
| 5324 | if (ret) |
| 5325 | return ret; |
| 5326 | |
| 5327 | ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, |
| 5328 | state_size, si_pi->sram_end); |
| 5329 | |
| 5330 | return ret; |
| 5331 | } |
| 5332 | |
| 5333 | static int si_upload_ulv_state(struct radeon_device *rdev) |
| 5334 | { |
| 5335 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5336 | struct si_ulv_param *ulv = &si_pi->ulv; |
| 5337 | int ret = 0; |
| 5338 | |
| 5339 | if (ulv->supported && ulv->pl.vddc) { |
| 5340 | u32 address = si_pi->state_table_start + |
| 5341 | offsetof(SISLANDS_SMC_STATETABLE, ULVState); |
| 5342 | SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; |
| 5343 | u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); |
| 5344 | |
| 5345 | memset(smc_state, 0, state_size); |
| 5346 | |
| 5347 | ret = si_populate_ulv_state(rdev, smc_state); |
| 5348 | if (!ret) |
| 5349 | ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, |
| 5350 | state_size, si_pi->sram_end); |
| 5351 | } |
| 5352 | |
| 5353 | return ret; |
| 5354 | } |
| 5355 | |
| 5356 | static int si_upload_smc_data(struct radeon_device *rdev) |
| 5357 | { |
| 5358 | struct radeon_crtc *radeon_crtc = NULL; |
| 5359 | int i; |
| 5360 | |
| 5361 | if (rdev->pm.dpm.new_active_crtc_count == 0) |
| 5362 | return 0; |
| 5363 | |
| 5364 | for (i = 0; i < rdev->num_crtc; i++) { |
| 5365 | if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { |
| 5366 | radeon_crtc = rdev->mode_info.crtcs[i]; |
| 5367 | break; |
| 5368 | } |
| 5369 | } |
| 5370 | |
| 5371 | if (radeon_crtc == NULL) |
| 5372 | return 0; |
| 5373 | |
| 5374 | if (radeon_crtc->line_time <= 0) |
| 5375 | return 0; |
| 5376 | |
| 5377 | if (si_write_smc_soft_register(rdev, |
| 5378 | SI_SMC_SOFT_REGISTER_crtc_index, |
| 5379 | radeon_crtc->crtc_id) != PPSMC_Result_OK) |
| 5380 | return 0; |
| 5381 | |
| 5382 | if (si_write_smc_soft_register(rdev, |
| 5383 | SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, |
| 5384 | radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) |
| 5385 | return 0; |
| 5386 | |
| 5387 | if (si_write_smc_soft_register(rdev, |
| 5388 | SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, |
| 5389 | radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) |
| 5390 | return 0; |
| 5391 | |
| 5392 | return 0; |
| 5393 | } |
| 5394 | |
| 5395 | static int si_set_mc_special_registers(struct radeon_device *rdev, |
| 5396 | struct si_mc_reg_table *table) |
| 5397 | { |
| 5398 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 5399 | u8 i, j, k; |
| 5400 | u32 temp_reg; |
| 5401 | |
| 5402 | for (i = 0, j = table->last; i < table->last; i++) { |
| 5403 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
| 5404 | return -EINVAL; |
| 5405 | switch (table->mc_reg_address[i].s1 << 2) { |
| 5406 | case MC_SEQ_MISC1: |
| 5407 | temp_reg = RREG32(MC_PMG_CMD_EMRS); |
| 5408 | table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; |
| 5409 | table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; |
| 5410 | for (k = 0; k < table->num_entries; k++) |
| 5411 | table->mc_reg_table_entry[k].mc_data[j] = |
| 5412 | ((temp_reg & 0xffff0000)) | |
| 5413 | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); |
| 5414 | j++; |
| 5415 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
| 5416 | return -EINVAL; |
| 5417 | |
| 5418 | temp_reg = RREG32(MC_PMG_CMD_MRS); |
| 5419 | table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; |
| 5420 | table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; |
| 5421 | for (k = 0; k < table->num_entries; k++) { |
| 5422 | table->mc_reg_table_entry[k].mc_data[j] = |
| 5423 | (temp_reg & 0xffff0000) | |
| 5424 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); |
| 5425 | if (!pi->mem_gddr5) |
| 5426 | table->mc_reg_table_entry[k].mc_data[j] |= 0x100; |
| 5427 | } |
| 5428 | j++; |
Dan Carpenter | 5fd9c58 | 2013-09-28 12:35:31 +0300 | [diff] [blame] | 5429 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5430 | return -EINVAL; |
| 5431 | |
| 5432 | if (!pi->mem_gddr5) { |
| 5433 | table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; |
| 5434 | table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; |
| 5435 | for (k = 0; k < table->num_entries; k++) |
| 5436 | table->mc_reg_table_entry[k].mc_data[j] = |
| 5437 | (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; |
| 5438 | j++; |
Dan Carpenter | 5fd9c58 | 2013-09-28 12:35:31 +0300 | [diff] [blame] | 5439 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5440 | return -EINVAL; |
| 5441 | } |
| 5442 | break; |
| 5443 | case MC_SEQ_RESERVE_M: |
| 5444 | temp_reg = RREG32(MC_PMG_CMD_MRS1); |
| 5445 | table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; |
| 5446 | table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; |
| 5447 | for(k = 0; k < table->num_entries; k++) |
| 5448 | table->mc_reg_table_entry[k].mc_data[j] = |
| 5449 | (temp_reg & 0xffff0000) | |
| 5450 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); |
| 5451 | j++; |
Dan Carpenter | 5fd9c58 | 2013-09-28 12:35:31 +0300 | [diff] [blame] | 5452 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5453 | return -EINVAL; |
| 5454 | break; |
| 5455 | default: |
| 5456 | break; |
| 5457 | } |
| 5458 | } |
| 5459 | |
| 5460 | table->last = j; |
| 5461 | |
| 5462 | return 0; |
| 5463 | } |
| 5464 | |
| 5465 | static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) |
| 5466 | { |
| 5467 | bool result = true; |
| 5468 | |
| 5469 | switch (in_reg) { |
| 5470 | case MC_SEQ_RAS_TIMING >> 2: |
| 5471 | *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; |
| 5472 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5473 | case MC_SEQ_CAS_TIMING >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5474 | *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; |
| 5475 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5476 | case MC_SEQ_MISC_TIMING >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5477 | *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; |
| 5478 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5479 | case MC_SEQ_MISC_TIMING2 >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5480 | *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; |
| 5481 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5482 | case MC_SEQ_RD_CTL_D0 >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5483 | *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; |
| 5484 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5485 | case MC_SEQ_RD_CTL_D1 >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5486 | *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; |
| 5487 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5488 | case MC_SEQ_WR_CTL_D0 >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5489 | *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; |
| 5490 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5491 | case MC_SEQ_WR_CTL_D1 >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5492 | *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; |
| 5493 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5494 | case MC_PMG_CMD_EMRS >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5495 | *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; |
| 5496 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5497 | case MC_PMG_CMD_MRS >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5498 | *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; |
| 5499 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5500 | case MC_PMG_CMD_MRS1 >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5501 | *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; |
| 5502 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5503 | case MC_SEQ_PMG_TIMING >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5504 | *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; |
| 5505 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5506 | case MC_PMG_CMD_MRS2 >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5507 | *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; |
| 5508 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5509 | case MC_SEQ_WR_CTL_2 >> 2: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5510 | *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; |
| 5511 | break; |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5512 | default: |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5513 | result = false; |
| 5514 | break; |
| 5515 | } |
| 5516 | |
| 5517 | return result; |
| 5518 | } |
| 5519 | |
| 5520 | static void si_set_valid_flag(struct si_mc_reg_table *table) |
| 5521 | { |
| 5522 | u8 i, j; |
| 5523 | |
| 5524 | for (i = 0; i < table->last; i++) { |
| 5525 | for (j = 1; j < table->num_entries; j++) { |
| 5526 | if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { |
| 5527 | table->valid_flag |= 1 << i; |
| 5528 | break; |
| 5529 | } |
| 5530 | } |
| 5531 | } |
| 5532 | } |
| 5533 | |
| 5534 | static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) |
| 5535 | { |
| 5536 | u32 i; |
| 5537 | u16 address; |
| 5538 | |
| 5539 | for (i = 0; i < table->last; i++) |
| 5540 | table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? |
| 5541 | address : table->mc_reg_address[i].s1; |
| 5542 | |
| 5543 | } |
| 5544 | |
| 5545 | static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, |
| 5546 | struct si_mc_reg_table *si_table) |
| 5547 | { |
| 5548 | u8 i, j; |
| 5549 | |
| 5550 | if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
| 5551 | return -EINVAL; |
| 5552 | if (table->num_entries > MAX_AC_TIMING_ENTRIES) |
| 5553 | return -EINVAL; |
| 5554 | |
| 5555 | for (i = 0; i < table->last; i++) |
| 5556 | si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; |
| 5557 | si_table->last = table->last; |
| 5558 | |
| 5559 | for (i = 0; i < table->num_entries; i++) { |
| 5560 | si_table->mc_reg_table_entry[i].mclk_max = |
| 5561 | table->mc_reg_table_entry[i].mclk_max; |
| 5562 | for (j = 0; j < table->last; j++) { |
| 5563 | si_table->mc_reg_table_entry[i].mc_data[j] = |
| 5564 | table->mc_reg_table_entry[i].mc_data[j]; |
| 5565 | } |
| 5566 | } |
| 5567 | si_table->num_entries = table->num_entries; |
| 5568 | |
| 5569 | return 0; |
| 5570 | } |
| 5571 | |
| 5572 | static int si_initialize_mc_reg_table(struct radeon_device *rdev) |
| 5573 | { |
| 5574 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5575 | struct atom_mc_reg_table *table; |
| 5576 | struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; |
| 5577 | u8 module_index = rv770_get_memory_module_index(rdev); |
| 5578 | int ret; |
| 5579 | |
| 5580 | table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); |
| 5581 | if (!table) |
| 5582 | return -ENOMEM; |
| 5583 | |
| 5584 | WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); |
| 5585 | WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); |
| 5586 | WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); |
| 5587 | WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); |
| 5588 | WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); |
| 5589 | WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); |
| 5590 | WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); |
| 5591 | WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); |
| 5592 | WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); |
| 5593 | WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); |
| 5594 | WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); |
| 5595 | WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); |
| 5596 | WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); |
| 5597 | WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); |
| 5598 | |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5599 | ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); |
| 5600 | if (ret) |
| 5601 | goto init_mc_done; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5602 | |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5603 | ret = si_copy_vbios_mc_reg_table(table, si_table); |
| 5604 | if (ret) |
| 5605 | goto init_mc_done; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5606 | |
| 5607 | si_set_s0_mc_reg_index(si_table); |
| 5608 | |
| 5609 | ret = si_set_mc_special_registers(rdev, si_table); |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5610 | if (ret) |
| 5611 | goto init_mc_done; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5612 | |
| 5613 | si_set_valid_flag(si_table); |
| 5614 | |
| 5615 | init_mc_done: |
| 5616 | kfree(table); |
| 5617 | |
| 5618 | return ret; |
| 5619 | |
| 5620 | } |
| 5621 | |
| 5622 | static void si_populate_mc_reg_addresses(struct radeon_device *rdev, |
| 5623 | SMC_SIslands_MCRegisters *mc_reg_table) |
| 5624 | { |
| 5625 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5626 | u32 i, j; |
| 5627 | |
| 5628 | for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { |
| 5629 | if (si_pi->mc_reg_table.valid_flag & (1 << j)) { |
Alex Deucher | 407b6df | 2014-01-17 12:34:55 -0500 | [diff] [blame] | 5630 | if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5631 | break; |
| 5632 | mc_reg_table->address[i].s0 = |
| 5633 | cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); |
| 5634 | mc_reg_table->address[i].s1 = |
| 5635 | cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); |
| 5636 | i++; |
| 5637 | } |
| 5638 | } |
| 5639 | mc_reg_table->last = (u8)i; |
| 5640 | } |
| 5641 | |
| 5642 | static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, |
| 5643 | SMC_SIslands_MCRegisterSet *data, |
| 5644 | u32 num_entries, u32 valid_flag) |
| 5645 | { |
| 5646 | u32 i, j; |
| 5647 | |
| 5648 | for(i = 0, j = 0; j < num_entries; j++) { |
| 5649 | if (valid_flag & (1 << j)) { |
| 5650 | data->value[i] = cpu_to_be32(entry->mc_data[j]); |
| 5651 | i++; |
| 5652 | } |
| 5653 | } |
| 5654 | } |
| 5655 | |
| 5656 | static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, |
| 5657 | struct rv7xx_pl *pl, |
| 5658 | SMC_SIslands_MCRegisterSet *mc_reg_table_data) |
| 5659 | { |
| 5660 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5661 | u32 i = 0; |
| 5662 | |
| 5663 | for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { |
| 5664 | if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) |
| 5665 | break; |
| 5666 | } |
| 5667 | |
| 5668 | if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) |
| 5669 | --i; |
| 5670 | |
| 5671 | si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], |
| 5672 | mc_reg_table_data, si_pi->mc_reg_table.last, |
| 5673 | si_pi->mc_reg_table.valid_flag); |
| 5674 | } |
| 5675 | |
| 5676 | static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, |
| 5677 | struct radeon_ps *radeon_state, |
| 5678 | SMC_SIslands_MCRegisters *mc_reg_table) |
| 5679 | { |
| 5680 | struct ni_ps *state = ni_get_ps(radeon_state); |
| 5681 | int i; |
| 5682 | |
| 5683 | for (i = 0; i < state->performance_level_count; i++) { |
| 5684 | si_convert_mc_reg_table_entry_to_smc(rdev, |
| 5685 | &state->performance_levels[i], |
| 5686 | &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); |
| 5687 | } |
| 5688 | } |
| 5689 | |
| 5690 | static int si_populate_mc_reg_table(struct radeon_device *rdev, |
| 5691 | struct radeon_ps *radeon_boot_state) |
| 5692 | { |
| 5693 | struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); |
| 5694 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5695 | struct si_ulv_param *ulv = &si_pi->ulv; |
| 5696 | SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; |
| 5697 | |
| 5698 | memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); |
| 5699 | |
| 5700 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); |
| 5701 | |
| 5702 | si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); |
| 5703 | |
| 5704 | si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], |
| 5705 | &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); |
| 5706 | |
| 5707 | si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], |
| 5708 | &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], |
| 5709 | si_pi->mc_reg_table.last, |
| 5710 | si_pi->mc_reg_table.valid_flag); |
| 5711 | |
| 5712 | if (ulv->supported && ulv->pl.vddc != 0) |
| 5713 | si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, |
| 5714 | &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); |
| 5715 | else |
| 5716 | si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], |
| 5717 | &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], |
| 5718 | si_pi->mc_reg_table.last, |
| 5719 | si_pi->mc_reg_table.valid_flag); |
| 5720 | |
| 5721 | si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); |
| 5722 | |
| 5723 | return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, |
| 5724 | (u8 *)smc_mc_reg_table, |
| 5725 | sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); |
| 5726 | } |
| 5727 | |
| 5728 | static int si_upload_mc_reg_table(struct radeon_device *rdev, |
| 5729 | struct radeon_ps *radeon_new_state) |
| 5730 | { |
| 5731 | struct ni_ps *new_state = ni_get_ps(radeon_new_state); |
| 5732 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5733 | u32 address = si_pi->mc_reg_table_start + |
| 5734 | offsetof(SMC_SIslands_MCRegisters, |
| 5735 | data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); |
| 5736 | SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; |
| 5737 | |
| 5738 | memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); |
| 5739 | |
| 5740 | si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); |
| 5741 | |
| 5742 | |
| 5743 | return si_copy_bytes_to_smc(rdev, address, |
| 5744 | (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], |
| 5745 | sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, |
| 5746 | si_pi->sram_end); |
| 5747 | |
| 5748 | } |
| 5749 | |
| 5750 | static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) |
| 5751 | { |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 5752 | if (enable) |
| 5753 | WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); |
| 5754 | else |
| 5755 | WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5756 | } |
| 5757 | |
| 5758 | static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, |
| 5759 | struct radeon_ps *radeon_state) |
| 5760 | { |
| 5761 | struct ni_ps *state = ni_get_ps(radeon_state); |
| 5762 | int i; |
| 5763 | u16 pcie_speed, max_speed = 0; |
| 5764 | |
| 5765 | for (i = 0; i < state->performance_level_count; i++) { |
| 5766 | pcie_speed = state->performance_levels[i].pcie_gen; |
| 5767 | if (max_speed < pcie_speed) |
| 5768 | max_speed = pcie_speed; |
| 5769 | } |
| 5770 | return max_speed; |
| 5771 | } |
| 5772 | |
| 5773 | static u16 si_get_current_pcie_speed(struct radeon_device *rdev) |
| 5774 | { |
| 5775 | u32 speed_cntl; |
| 5776 | |
| 5777 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; |
| 5778 | speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; |
| 5779 | |
| 5780 | return (u16)speed_cntl; |
| 5781 | } |
| 5782 | |
| 5783 | static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, |
| 5784 | struct radeon_ps *radeon_new_state, |
| 5785 | struct radeon_ps *radeon_current_state) |
| 5786 | { |
| 5787 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5788 | enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); |
| 5789 | enum radeon_pcie_gen current_link_speed; |
| 5790 | |
| 5791 | if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) |
| 5792 | current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); |
| 5793 | else |
| 5794 | current_link_speed = si_pi->force_pcie_gen; |
| 5795 | |
| 5796 | si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; |
| 5797 | si_pi->pspp_notify_required = false; |
| 5798 | if (target_link_speed > current_link_speed) { |
| 5799 | switch (target_link_speed) { |
| 5800 | #if defined(CONFIG_ACPI) |
| 5801 | case RADEON_PCIE_GEN3: |
| 5802 | if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) |
| 5803 | break; |
| 5804 | si_pi->force_pcie_gen = RADEON_PCIE_GEN2; |
| 5805 | if (current_link_speed == RADEON_PCIE_GEN2) |
| 5806 | break; |
| 5807 | case RADEON_PCIE_GEN2: |
| 5808 | if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) |
| 5809 | break; |
| 5810 | #endif |
| 5811 | default: |
| 5812 | si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); |
| 5813 | break; |
| 5814 | } |
| 5815 | } else { |
| 5816 | if (target_link_speed < current_link_speed) |
| 5817 | si_pi->pspp_notify_required = true; |
| 5818 | } |
| 5819 | } |
| 5820 | |
| 5821 | static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, |
| 5822 | struct radeon_ps *radeon_new_state, |
| 5823 | struct radeon_ps *radeon_current_state) |
| 5824 | { |
| 5825 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5826 | enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); |
| 5827 | u8 request; |
| 5828 | |
| 5829 | if (si_pi->pspp_notify_required) { |
| 5830 | if (target_link_speed == RADEON_PCIE_GEN3) |
| 5831 | request = PCIE_PERF_REQ_PECI_GEN3; |
| 5832 | else if (target_link_speed == RADEON_PCIE_GEN2) |
| 5833 | request = PCIE_PERF_REQ_PECI_GEN2; |
| 5834 | else |
| 5835 | request = PCIE_PERF_REQ_PECI_GEN1; |
| 5836 | |
| 5837 | if ((request == PCIE_PERF_REQ_PECI_GEN1) && |
| 5838 | (si_get_current_pcie_speed(rdev) > 0)) |
| 5839 | return; |
| 5840 | |
| 5841 | #if defined(CONFIG_ACPI) |
| 5842 | radeon_acpi_pcie_performance_request(rdev, request, false); |
| 5843 | #endif |
| 5844 | } |
| 5845 | } |
| 5846 | |
| 5847 | #if 0 |
| 5848 | static int si_ds_request(struct radeon_device *rdev, |
| 5849 | bool ds_status_on, u32 count_write) |
| 5850 | { |
| 5851 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 5852 | |
| 5853 | if (eg_pi->sclk_deep_sleep) { |
| 5854 | if (ds_status_on) |
| 5855 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == |
| 5856 | PPSMC_Result_OK) ? |
| 5857 | 0 : -EINVAL; |
| 5858 | else |
| 5859 | return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == |
| 5860 | PPSMC_Result_OK) ? 0 : -EINVAL; |
| 5861 | } |
| 5862 | return 0; |
| 5863 | } |
| 5864 | #endif |
| 5865 | |
| 5866 | static void si_set_max_cu_value(struct radeon_device *rdev) |
| 5867 | { |
| 5868 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 5869 | |
| 5870 | if (rdev->family == CHIP_VERDE) { |
| 5871 | switch (rdev->pdev->device) { |
| 5872 | case 0x6820: |
| 5873 | case 0x6825: |
| 5874 | case 0x6821: |
| 5875 | case 0x6823: |
| 5876 | case 0x6827: |
| 5877 | si_pi->max_cu = 10; |
| 5878 | break; |
| 5879 | case 0x682D: |
| 5880 | case 0x6824: |
| 5881 | case 0x682F: |
| 5882 | case 0x6826: |
| 5883 | si_pi->max_cu = 8; |
| 5884 | break; |
| 5885 | case 0x6828: |
| 5886 | case 0x6830: |
| 5887 | case 0x6831: |
| 5888 | case 0x6838: |
| 5889 | case 0x6839: |
| 5890 | case 0x683D: |
| 5891 | si_pi->max_cu = 10; |
| 5892 | break; |
| 5893 | case 0x683B: |
| 5894 | case 0x683F: |
| 5895 | case 0x6829: |
| 5896 | si_pi->max_cu = 8; |
| 5897 | break; |
| 5898 | default: |
| 5899 | si_pi->max_cu = 0; |
| 5900 | break; |
| 5901 | } |
| 5902 | } else { |
| 5903 | si_pi->max_cu = 0; |
| 5904 | } |
| 5905 | } |
| 5906 | |
| 5907 | static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, |
| 5908 | struct radeon_clock_voltage_dependency_table *table) |
| 5909 | { |
| 5910 | u32 i; |
| 5911 | int j; |
| 5912 | u16 leakage_voltage; |
| 5913 | |
| 5914 | if (table) { |
| 5915 | for (i = 0; i < table->count; i++) { |
| 5916 | switch (si_get_leakage_voltage_from_leakage_index(rdev, |
| 5917 | table->entries[i].v, |
| 5918 | &leakage_voltage)) { |
| 5919 | case 0: |
| 5920 | table->entries[i].v = leakage_voltage; |
| 5921 | break; |
| 5922 | case -EAGAIN: |
| 5923 | return -EINVAL; |
| 5924 | case -EINVAL: |
| 5925 | default: |
| 5926 | break; |
| 5927 | } |
| 5928 | } |
| 5929 | |
| 5930 | for (j = (table->count - 2); j >= 0; j--) { |
| 5931 | table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? |
| 5932 | table->entries[j].v : table->entries[j + 1].v; |
| 5933 | } |
| 5934 | } |
| 5935 | return 0; |
| 5936 | } |
| 5937 | |
| 5938 | static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) |
| 5939 | { |
| 5940 | int ret = 0; |
| 5941 | |
| 5942 | ret = si_patch_single_dependency_table_based_on_leakage(rdev, |
| 5943 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); |
| 5944 | ret = si_patch_single_dependency_table_based_on_leakage(rdev, |
| 5945 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); |
| 5946 | ret = si_patch_single_dependency_table_based_on_leakage(rdev, |
| 5947 | &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); |
| 5948 | return ret; |
| 5949 | } |
| 5950 | |
| 5951 | static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, |
| 5952 | struct radeon_ps *radeon_new_state, |
| 5953 | struct radeon_ps *radeon_current_state) |
| 5954 | { |
| 5955 | u32 lane_width; |
| 5956 | u32 new_lane_width = |
| 5957 | (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; |
| 5958 | u32 current_lane_width = |
| 5959 | (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; |
| 5960 | |
| 5961 | if (new_lane_width != current_lane_width) { |
| 5962 | radeon_set_pcie_lanes(rdev, new_lane_width); |
| 5963 | lane_width = radeon_get_pcie_lanes(rdev); |
| 5964 | si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); |
| 5965 | } |
| 5966 | } |
| 5967 | |
Alex Deucher | 11586cf | 2015-05-11 22:01:52 +0200 | [diff] [blame] | 5968 | static void si_set_vce_clock(struct radeon_device *rdev, |
| 5969 | struct radeon_ps *new_rps, |
| 5970 | struct radeon_ps *old_rps) |
| 5971 | { |
| 5972 | if ((old_rps->evclk != new_rps->evclk) || |
Alex Deucher | 84bcd46 | 2015-05-11 22:01:55 +0200 | [diff] [blame] | 5973 | (old_rps->ecclk != new_rps->ecclk)) { |
| 5974 | /* turn the clocks on when encoding, off otherwise */ |
| 5975 | if (new_rps->evclk || new_rps->ecclk) |
| 5976 | vce_v1_0_enable_mgcg(rdev, false); |
| 5977 | else |
| 5978 | vce_v1_0_enable_mgcg(rdev, true); |
Alex Deucher | 11586cf | 2015-05-11 22:01:52 +0200 | [diff] [blame] | 5979 | radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); |
Alex Deucher | 84bcd46 | 2015-05-11 22:01:55 +0200 | [diff] [blame] | 5980 | } |
Alex Deucher | 11586cf | 2015-05-11 22:01:52 +0200 | [diff] [blame] | 5981 | } |
| 5982 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5983 | void si_dpm_setup_asic(struct radeon_device *rdev) |
| 5984 | { |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 5985 | int r; |
| 5986 | |
| 5987 | r = si_mc_load_microcode(rdev); |
| 5988 | if (r) |
| 5989 | DRM_ERROR("Failed to load MC firmware!\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 5990 | rv770_get_memory_type(rdev); |
| 5991 | si_read_clock_registers(rdev); |
| 5992 | si_enable_acpi_power_management(rdev); |
| 5993 | } |
| 5994 | |
Alex Deucher | 2271e2e | 2014-09-08 03:35:17 -0400 | [diff] [blame] | 5995 | static int si_thermal_enable_alert(struct radeon_device *rdev, |
| 5996 | bool enable) |
| 5997 | { |
| 5998 | u32 thermal_int = RREG32(CG_THERMAL_INT); |
| 5999 | |
| 6000 | if (enable) { |
| 6001 | PPSMC_Result result; |
| 6002 | |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6003 | thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); |
| 6004 | WREG32(CG_THERMAL_INT, thermal_int); |
| 6005 | rdev->irq.dpm_thermal = false; |
Alex Deucher | 2271e2e | 2014-09-08 03:35:17 -0400 | [diff] [blame] | 6006 | result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); |
| 6007 | if (result != PPSMC_Result_OK) { |
| 6008 | DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); |
| 6009 | return -EINVAL; |
| 6010 | } |
| 6011 | } else { |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6012 | thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; |
| 6013 | WREG32(CG_THERMAL_INT, thermal_int); |
| 6014 | rdev->irq.dpm_thermal = true; |
Alex Deucher | 2271e2e | 2014-09-08 03:35:17 -0400 | [diff] [blame] | 6015 | } |
| 6016 | |
Alex Deucher | 2271e2e | 2014-09-08 03:35:17 -0400 | [diff] [blame] | 6017 | return 0; |
| 6018 | } |
| 6019 | |
| 6020 | static int si_thermal_set_temperature_range(struct radeon_device *rdev, |
| 6021 | int min_temp, int max_temp) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6022 | { |
| 6023 | int low_temp = 0 * 1000; |
| 6024 | int high_temp = 255 * 1000; |
| 6025 | |
| 6026 | if (low_temp < min_temp) |
| 6027 | low_temp = min_temp; |
| 6028 | if (high_temp > max_temp) |
| 6029 | high_temp = max_temp; |
| 6030 | if (high_temp < low_temp) { |
| 6031 | DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); |
| 6032 | return -EINVAL; |
| 6033 | } |
| 6034 | |
| 6035 | WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); |
| 6036 | WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); |
| 6037 | WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); |
| 6038 | |
| 6039 | rdev->pm.dpm.thermal.min_temp = low_temp; |
| 6040 | rdev->pm.dpm.thermal.max_temp = high_temp; |
| 6041 | |
| 6042 | return 0; |
| 6043 | } |
| 6044 | |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6045 | static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) |
| 6046 | { |
| 6047 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 6048 | u32 tmp; |
| 6049 | |
| 6050 | if (si_pi->fan_ctrl_is_in_default_mode) { |
| 6051 | tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; |
| 6052 | si_pi->fan_ctrl_default_mode = tmp; |
| 6053 | tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; |
| 6054 | si_pi->t_min = tmp; |
| 6055 | si_pi->fan_ctrl_is_in_default_mode = false; |
| 6056 | } |
| 6057 | |
| 6058 | tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; |
| 6059 | tmp |= TMIN(0); |
| 6060 | WREG32(CG_FDO_CTRL2, tmp); |
| 6061 | |
Alex Deucher | 6554d9a | 2014-12-01 17:18:53 -0500 | [diff] [blame] | 6062 | tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6063 | tmp |= FDO_PWM_MODE(mode); |
| 6064 | WREG32(CG_FDO_CTRL2, tmp); |
| 6065 | } |
| 6066 | |
| 6067 | static int si_thermal_setup_fan_table(struct radeon_device *rdev) |
| 6068 | { |
| 6069 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 6070 | PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; |
| 6071 | u32 duty100; |
| 6072 | u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; |
| 6073 | u16 fdo_min, slope1, slope2; |
| 6074 | u32 reference_clock, tmp; |
| 6075 | int ret; |
| 6076 | u64 tmp64; |
| 6077 | |
| 6078 | if (!si_pi->fan_table_start) { |
| 6079 | rdev->pm.dpm.fan.ucode_fan_control = false; |
| 6080 | return 0; |
| 6081 | } |
| 6082 | |
| 6083 | duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; |
| 6084 | |
| 6085 | if (duty100 == 0) { |
| 6086 | rdev->pm.dpm.fan.ucode_fan_control = false; |
| 6087 | return 0; |
| 6088 | } |
| 6089 | |
| 6090 | tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; |
| 6091 | do_div(tmp64, 10000); |
| 6092 | fdo_min = (u16)tmp64; |
| 6093 | |
| 6094 | t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; |
| 6095 | t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; |
| 6096 | |
| 6097 | pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; |
| 6098 | pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; |
| 6099 | |
| 6100 | slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); |
| 6101 | slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); |
| 6102 | |
Oleg Chernovskiy | 47fd97c | 2015-01-17 21:10:39 +0300 | [diff] [blame] | 6103 | fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); |
| 6104 | fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); |
| 6105 | fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); |
| 6106 | |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6107 | fan_table.slope1 = cpu_to_be16(slope1); |
| 6108 | fan_table.slope2 = cpu_to_be16(slope2); |
| 6109 | |
| 6110 | fan_table.fdo_min = cpu_to_be16(fdo_min); |
| 6111 | |
| 6112 | fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); |
| 6113 | |
| 6114 | fan_table.hys_up = cpu_to_be16(1); |
| 6115 | |
| 6116 | fan_table.hys_slope = cpu_to_be16(1); |
| 6117 | |
| 6118 | fan_table.temp_resp_lim = cpu_to_be16(5); |
| 6119 | |
| 6120 | reference_clock = radeon_get_xclk(rdev); |
| 6121 | |
| 6122 | fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * |
| 6123 | reference_clock) / 1600); |
| 6124 | |
| 6125 | fan_table.fdo_max = cpu_to_be16((u16)duty100); |
| 6126 | |
| 6127 | tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; |
| 6128 | fan_table.temp_src = (uint8_t)tmp; |
| 6129 | |
| 6130 | ret = si_copy_bytes_to_smc(rdev, |
| 6131 | si_pi->fan_table_start, |
| 6132 | (u8 *)(&fan_table), |
| 6133 | sizeof(fan_table), |
| 6134 | si_pi->sram_end); |
| 6135 | |
| 6136 | if (ret) { |
| 6137 | DRM_ERROR("Failed to load fan table to the SMC."); |
| 6138 | rdev->pm.dpm.fan.ucode_fan_control = false; |
| 6139 | } |
| 6140 | |
| 6141 | return 0; |
| 6142 | } |
| 6143 | |
| 6144 | static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) |
| 6145 | { |
Alex Deucher | 5e8150a | 2015-01-07 15:29:06 -0500 | [diff] [blame] | 6146 | struct si_power_info *si_pi = si_get_pi(rdev); |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6147 | PPSMC_Result ret; |
| 6148 | |
| 6149 | ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); |
Alex Deucher | 5e8150a | 2015-01-07 15:29:06 -0500 | [diff] [blame] | 6150 | if (ret == PPSMC_Result_OK) { |
| 6151 | si_pi->fan_is_controlled_by_smc = true; |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6152 | return 0; |
Alex Deucher | 5e8150a | 2015-01-07 15:29:06 -0500 | [diff] [blame] | 6153 | } else { |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6154 | return -EINVAL; |
Alex Deucher | 5e8150a | 2015-01-07 15:29:06 -0500 | [diff] [blame] | 6155 | } |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6156 | } |
| 6157 | |
| 6158 | static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) |
| 6159 | { |
Alex Deucher | 5e8150a | 2015-01-07 15:29:06 -0500 | [diff] [blame] | 6160 | struct si_power_info *si_pi = si_get_pi(rdev); |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6161 | PPSMC_Result ret; |
| 6162 | |
| 6163 | ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); |
Alex Deucher | 5e8150a | 2015-01-07 15:29:06 -0500 | [diff] [blame] | 6164 | |
| 6165 | if (ret == PPSMC_Result_OK) { |
| 6166 | si_pi->fan_is_controlled_by_smc = false; |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6167 | return 0; |
Alex Deucher | 5e8150a | 2015-01-07 15:29:06 -0500 | [diff] [blame] | 6168 | } else { |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6169 | return -EINVAL; |
Alex Deucher | 5e8150a | 2015-01-07 15:29:06 -0500 | [diff] [blame] | 6170 | } |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6171 | } |
| 6172 | |
Alex Deucher | 5e8150a | 2015-01-07 15:29:06 -0500 | [diff] [blame] | 6173 | int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, |
| 6174 | u32 *speed) |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6175 | { |
| 6176 | u32 duty, duty100; |
| 6177 | u64 tmp64; |
| 6178 | |
| 6179 | if (rdev->pm.no_fan) |
| 6180 | return -ENOENT; |
| 6181 | |
| 6182 | duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; |
| 6183 | duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; |
| 6184 | |
| 6185 | if (duty100 == 0) |
| 6186 | return -EINVAL; |
| 6187 | |
| 6188 | tmp64 = (u64)duty * 100; |
| 6189 | do_div(tmp64, duty100); |
| 6190 | *speed = (u32)tmp64; |
| 6191 | |
| 6192 | if (*speed > 100) |
| 6193 | *speed = 100; |
| 6194 | |
| 6195 | return 0; |
| 6196 | } |
| 6197 | |
Alex Deucher | 5e8150a | 2015-01-07 15:29:06 -0500 | [diff] [blame] | 6198 | int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, |
| 6199 | u32 speed) |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6200 | { |
Oleg Chernovskiy | 47fd97c | 2015-01-17 21:10:39 +0300 | [diff] [blame] | 6201 | struct si_power_info *si_pi = si_get_pi(rdev); |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6202 | u32 tmp; |
| 6203 | u32 duty, duty100; |
| 6204 | u64 tmp64; |
| 6205 | |
| 6206 | if (rdev->pm.no_fan) |
| 6207 | return -ENOENT; |
| 6208 | |
Oleg Chernovskiy | 47fd97c | 2015-01-17 21:10:39 +0300 | [diff] [blame] | 6209 | if (si_pi->fan_is_controlled_by_smc) |
| 6210 | return -EINVAL; |
| 6211 | |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6212 | if (speed > 100) |
| 6213 | return -EINVAL; |
| 6214 | |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6215 | duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; |
| 6216 | |
| 6217 | if (duty100 == 0) |
| 6218 | return -EINVAL; |
| 6219 | |
| 6220 | tmp64 = (u64)speed * duty100; |
| 6221 | do_div(tmp64, 100); |
| 6222 | duty = (u32)tmp64; |
| 6223 | |
| 6224 | tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; |
| 6225 | tmp |= FDO_STATIC_DUTY(duty); |
| 6226 | WREG32(CG_FDO_CTRL0, tmp); |
| 6227 | |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6228 | return 0; |
| 6229 | } |
| 6230 | |
Alex Deucher | 5e8150a | 2015-01-07 15:29:06 -0500 | [diff] [blame] | 6231 | void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) |
| 6232 | { |
| 6233 | if (mode) { |
| 6234 | /* stop auto-manage */ |
| 6235 | if (rdev->pm.dpm.fan.ucode_fan_control) |
| 6236 | si_fan_ctrl_stop_smc_fan_control(rdev); |
| 6237 | si_fan_ctrl_set_static_mode(rdev, mode); |
| 6238 | } else { |
| 6239 | /* restart auto-manage */ |
| 6240 | if (rdev->pm.dpm.fan.ucode_fan_control) |
| 6241 | si_thermal_start_smc_fan_control(rdev); |
| 6242 | else |
| 6243 | si_fan_ctrl_set_default_mode(rdev); |
| 6244 | } |
| 6245 | } |
| 6246 | |
| 6247 | u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) |
| 6248 | { |
| 6249 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 6250 | u32 tmp; |
| 6251 | |
| 6252 | if (si_pi->fan_is_controlled_by_smc) |
| 6253 | return 0; |
| 6254 | |
| 6255 | tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; |
| 6256 | return (tmp >> FDO_PWM_MODE_SHIFT); |
| 6257 | } |
| 6258 | |
| 6259 | #if 0 |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6260 | static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, |
| 6261 | u32 *speed) |
| 6262 | { |
| 6263 | u32 tach_period; |
| 6264 | u32 xclk = radeon_get_xclk(rdev); |
| 6265 | |
| 6266 | if (rdev->pm.no_fan) |
| 6267 | return -ENOENT; |
| 6268 | |
| 6269 | if (rdev->pm.fan_pulses_per_revolution == 0) |
| 6270 | return -ENOENT; |
| 6271 | |
| 6272 | tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; |
| 6273 | if (tach_period == 0) |
| 6274 | return -ENOENT; |
| 6275 | |
| 6276 | *speed = 60 * xclk * 10000 / tach_period; |
| 6277 | |
| 6278 | return 0; |
| 6279 | } |
| 6280 | |
| 6281 | static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, |
| 6282 | u32 speed) |
| 6283 | { |
| 6284 | u32 tach_period, tmp; |
| 6285 | u32 xclk = radeon_get_xclk(rdev); |
| 6286 | |
| 6287 | if (rdev->pm.no_fan) |
| 6288 | return -ENOENT; |
| 6289 | |
| 6290 | if (rdev->pm.fan_pulses_per_revolution == 0) |
| 6291 | return -ENOENT; |
| 6292 | |
| 6293 | if ((speed < rdev->pm.fan_min_rpm) || |
| 6294 | (speed > rdev->pm.fan_max_rpm)) |
| 6295 | return -EINVAL; |
| 6296 | |
| 6297 | if (rdev->pm.dpm.fan.ucode_fan_control) |
| 6298 | si_fan_ctrl_stop_smc_fan_control(rdev); |
| 6299 | |
| 6300 | tach_period = 60 * xclk * 10000 / (8 * speed); |
| 6301 | tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; |
| 6302 | tmp |= TARGET_PERIOD(tach_period); |
| 6303 | WREG32(CG_TACH_CTRL, tmp); |
| 6304 | |
Alex Deucher | 6554d9a | 2014-12-01 17:18:53 -0500 | [diff] [blame] | 6305 | si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6306 | |
| 6307 | return 0; |
| 6308 | } |
| 6309 | #endif |
| 6310 | |
| 6311 | static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) |
| 6312 | { |
| 6313 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 6314 | u32 tmp; |
| 6315 | |
| 6316 | if (!si_pi->fan_ctrl_is_in_default_mode) { |
| 6317 | tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; |
| 6318 | tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); |
| 6319 | WREG32(CG_FDO_CTRL2, tmp); |
| 6320 | |
Alex Deucher | 6554d9a | 2014-12-01 17:18:53 -0500 | [diff] [blame] | 6321 | tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6322 | tmp |= TMIN(si_pi->t_min); |
| 6323 | WREG32(CG_FDO_CTRL2, tmp); |
| 6324 | si_pi->fan_ctrl_is_in_default_mode = true; |
| 6325 | } |
| 6326 | } |
| 6327 | |
| 6328 | static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) |
| 6329 | { |
| 6330 | if (rdev->pm.dpm.fan.ucode_fan_control) { |
| 6331 | si_fan_ctrl_start_smc_fan_control(rdev); |
| 6332 | si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); |
| 6333 | } |
| 6334 | } |
| 6335 | |
| 6336 | static void si_thermal_initialize(struct radeon_device *rdev) |
| 6337 | { |
| 6338 | u32 tmp; |
| 6339 | |
| 6340 | if (rdev->pm.fan_pulses_per_revolution) { |
| 6341 | tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; |
| 6342 | tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); |
| 6343 | WREG32(CG_TACH_CTRL, tmp); |
| 6344 | } |
| 6345 | |
| 6346 | tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; |
| 6347 | tmp |= TACH_PWM_RESP_RATE(0x28); |
| 6348 | WREG32(CG_FDO_CTRL2, tmp); |
| 6349 | } |
| 6350 | |
| 6351 | static int si_thermal_start_thermal_controller(struct radeon_device *rdev) |
| 6352 | { |
| 6353 | int ret; |
| 6354 | |
| 6355 | si_thermal_initialize(rdev); |
| 6356 | ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); |
| 6357 | if (ret) |
| 6358 | return ret; |
| 6359 | ret = si_thermal_enable_alert(rdev, true); |
| 6360 | if (ret) |
| 6361 | return ret; |
| 6362 | if (rdev->pm.dpm.fan.ucode_fan_control) { |
| 6363 | ret = si_halt_smc(rdev); |
| 6364 | if (ret) |
| 6365 | return ret; |
| 6366 | ret = si_thermal_setup_fan_table(rdev); |
| 6367 | if (ret) |
| 6368 | return ret; |
| 6369 | ret = si_resume_smc(rdev); |
| 6370 | if (ret) |
| 6371 | return ret; |
| 6372 | si_thermal_start_smc_fan_control(rdev); |
| 6373 | } |
| 6374 | |
| 6375 | return 0; |
| 6376 | } |
| 6377 | |
| 6378 | static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) |
| 6379 | { |
| 6380 | if (!rdev->pm.no_fan) { |
| 6381 | si_fan_ctrl_set_default_mode(rdev); |
| 6382 | si_fan_ctrl_stop_smc_fan_control(rdev); |
| 6383 | } |
| 6384 | } |
| 6385 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6386 | int si_dpm_enable(struct radeon_device *rdev) |
| 6387 | { |
| 6388 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 6389 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 6390 | struct si_power_info *si_pi = si_get_pi(rdev); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6391 | struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; |
| 6392 | int ret; |
| 6393 | |
| 6394 | if (si_is_smc_running(rdev)) |
| 6395 | return -EINVAL; |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 6396 | if (pi->voltage_control || si_pi->voltage_control_svi2) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6397 | si_enable_voltage_control(rdev, true); |
| 6398 | if (pi->mvdd_control) |
| 6399 | si_get_mvdd_configuration(rdev); |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 6400 | if (pi->voltage_control || si_pi->voltage_control_svi2) { |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6401 | ret = si_construct_voltage_tables(rdev); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6402 | if (ret) { |
| 6403 | DRM_ERROR("si_construct_voltage_tables failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6404 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6405 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6406 | } |
| 6407 | if (eg_pi->dynamic_ac_timing) { |
| 6408 | ret = si_initialize_mc_reg_table(rdev); |
| 6409 | if (ret) |
| 6410 | eg_pi->dynamic_ac_timing = false; |
| 6411 | } |
| 6412 | if (pi->dynamic_ss) |
| 6413 | si_enable_spread_spectrum(rdev, true); |
| 6414 | if (pi->thermal_protection) |
| 6415 | si_enable_thermal_protection(rdev, true); |
| 6416 | si_setup_bsp(rdev); |
| 6417 | si_program_git(rdev); |
| 6418 | si_program_tp(rdev); |
| 6419 | si_program_tpp(rdev); |
| 6420 | si_program_sstp(rdev); |
| 6421 | si_enable_display_gap(rdev); |
| 6422 | si_program_vc(rdev); |
| 6423 | ret = si_upload_firmware(rdev); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6424 | if (ret) { |
| 6425 | DRM_ERROR("si_upload_firmware failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6426 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6427 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6428 | ret = si_process_firmware_header(rdev); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6429 | if (ret) { |
| 6430 | DRM_ERROR("si_process_firmware_header failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6431 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6432 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6433 | ret = si_initial_switch_from_arb_f0_to_f1(rdev); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6434 | if (ret) { |
| 6435 | DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6436 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6437 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6438 | ret = si_init_smc_table(rdev); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6439 | if (ret) { |
| 6440 | DRM_ERROR("si_init_smc_table failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6441 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6442 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6443 | ret = si_init_smc_spll_table(rdev); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6444 | if (ret) { |
| 6445 | DRM_ERROR("si_init_smc_spll_table failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6446 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6447 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6448 | ret = si_init_arb_table_index(rdev); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6449 | if (ret) { |
| 6450 | DRM_ERROR("si_init_arb_table_index failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6451 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6452 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6453 | if (eg_pi->dynamic_ac_timing) { |
| 6454 | ret = si_populate_mc_reg_table(rdev, boot_ps); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6455 | if (ret) { |
| 6456 | DRM_ERROR("si_populate_mc_reg_table failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6457 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6458 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6459 | } |
| 6460 | ret = si_initialize_smc_cac_tables(rdev); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6461 | if (ret) { |
| 6462 | DRM_ERROR("si_initialize_smc_cac_tables failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6463 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6464 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6465 | ret = si_initialize_hardware_cac_manager(rdev); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6466 | if (ret) { |
| 6467 | DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6468 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6469 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6470 | ret = si_initialize_smc_dte_tables(rdev); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6471 | if (ret) { |
| 6472 | DRM_ERROR("si_initialize_smc_dte_tables failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6473 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6474 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6475 | ret = si_populate_smc_tdp_limits(rdev, boot_ps); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6476 | if (ret) { |
| 6477 | DRM_ERROR("si_populate_smc_tdp_limits failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6478 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6479 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6480 | ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6481 | if (ret) { |
| 6482 | DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6483 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6484 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6485 | si_program_response_times(rdev); |
| 6486 | si_program_ds_registers(rdev); |
| 6487 | si_dpm_start_smc(rdev); |
| 6488 | ret = si_notify_smc_display_change(rdev, false); |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6489 | if (ret) { |
| 6490 | DRM_ERROR("si_notify_smc_display_change failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6491 | return ret; |
Alex Deucher | 2c48feb | 2013-03-28 10:45:50 -0400 | [diff] [blame] | 6492 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6493 | si_enable_sclk_control(rdev, true); |
| 6494 | si_start_dpm(rdev); |
| 6495 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6496 | si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); |
| 6497 | |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6498 | si_thermal_start_thermal_controller(rdev); |
| 6499 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6500 | ni_update_current_ps(rdev, boot_ps); |
| 6501 | |
| 6502 | return 0; |
| 6503 | } |
| 6504 | |
Alex Deucher | 2271e2e | 2014-09-08 03:35:17 -0400 | [diff] [blame] | 6505 | static int si_set_temperature_range(struct radeon_device *rdev) |
| 6506 | { |
| 6507 | int ret; |
| 6508 | |
| 6509 | ret = si_thermal_enable_alert(rdev, false); |
| 6510 | if (ret) |
| 6511 | return ret; |
| 6512 | ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); |
| 6513 | if (ret) |
| 6514 | return ret; |
| 6515 | ret = si_thermal_enable_alert(rdev, true); |
| 6516 | if (ret) |
| 6517 | return ret; |
| 6518 | |
| 6519 | return ret; |
| 6520 | } |
| 6521 | |
Alex Deucher | 963c115 | 2013-12-19 13:54:35 -0500 | [diff] [blame] | 6522 | int si_dpm_late_enable(struct radeon_device *rdev) |
| 6523 | { |
| 6524 | int ret; |
| 6525 | |
Alex Deucher | 2271e2e | 2014-09-08 03:35:17 -0400 | [diff] [blame] | 6526 | ret = si_set_temperature_range(rdev); |
| 6527 | if (ret) |
| 6528 | return ret; |
Alex Deucher | 963c115 | 2013-12-19 13:54:35 -0500 | [diff] [blame] | 6529 | |
Alex Deucher | 2271e2e | 2014-09-08 03:35:17 -0400 | [diff] [blame] | 6530 | return ret; |
Alex Deucher | 963c115 | 2013-12-19 13:54:35 -0500 | [diff] [blame] | 6531 | } |
| 6532 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6533 | void si_dpm_disable(struct radeon_device *rdev) |
| 6534 | { |
| 6535 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 6536 | struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; |
| 6537 | |
| 6538 | if (!si_is_smc_running(rdev)) |
| 6539 | return; |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 6540 | si_thermal_stop_thermal_controller(rdev); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6541 | si_disable_ulv(rdev); |
| 6542 | si_clear_vc(rdev); |
| 6543 | if (pi->thermal_protection) |
| 6544 | si_enable_thermal_protection(rdev, false); |
| 6545 | si_enable_power_containment(rdev, boot_ps, false); |
| 6546 | si_enable_smc_cac(rdev, boot_ps, false); |
| 6547 | si_enable_spread_spectrum(rdev, false); |
| 6548 | si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); |
| 6549 | si_stop_dpm(rdev); |
| 6550 | si_reset_to_default(rdev); |
| 6551 | si_dpm_stop_smc(rdev); |
| 6552 | si_force_switch_to_arb_f0(rdev); |
| 6553 | |
| 6554 | ni_update_current_ps(rdev, boot_ps); |
| 6555 | } |
| 6556 | |
| 6557 | int si_dpm_pre_set_power_state(struct radeon_device *rdev) |
| 6558 | { |
| 6559 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 6560 | struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; |
| 6561 | struct radeon_ps *new_ps = &requested_ps; |
| 6562 | |
| 6563 | ni_update_requested_ps(rdev, new_ps); |
| 6564 | |
| 6565 | si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); |
| 6566 | |
| 6567 | return 0; |
| 6568 | } |
| 6569 | |
Alex Deucher | a144acb | 2013-06-27 19:37:12 -0400 | [diff] [blame] | 6570 | static int si_power_control_set_level(struct radeon_device *rdev) |
| 6571 | { |
| 6572 | struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; |
| 6573 | int ret; |
| 6574 | |
| 6575 | ret = si_restrict_performance_levels_before_switch(rdev); |
| 6576 | if (ret) |
| 6577 | return ret; |
| 6578 | ret = si_halt_smc(rdev); |
| 6579 | if (ret) |
| 6580 | return ret; |
| 6581 | ret = si_populate_smc_tdp_limits(rdev, new_ps); |
| 6582 | if (ret) |
| 6583 | return ret; |
| 6584 | ret = si_populate_smc_tdp_limits_2(rdev, new_ps); |
| 6585 | if (ret) |
| 6586 | return ret; |
| 6587 | ret = si_resume_smc(rdev); |
| 6588 | if (ret) |
| 6589 | return ret; |
| 6590 | ret = si_set_sw_state(rdev); |
| 6591 | if (ret) |
| 6592 | return ret; |
| 6593 | return 0; |
| 6594 | } |
| 6595 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6596 | int si_dpm_set_power_state(struct radeon_device *rdev) |
| 6597 | { |
| 6598 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 6599 | struct radeon_ps *new_ps = &eg_pi->requested_rps; |
| 6600 | struct radeon_ps *old_ps = &eg_pi->current_rps; |
| 6601 | int ret; |
| 6602 | |
| 6603 | ret = si_disable_ulv(rdev); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6604 | if (ret) { |
| 6605 | DRM_ERROR("si_disable_ulv failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6606 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6607 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6608 | ret = si_restrict_performance_levels_before_switch(rdev); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6609 | if (ret) { |
| 6610 | DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6611 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6612 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6613 | if (eg_pi->pcie_performance_request) |
| 6614 | si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); |
Alex Deucher | e34568b | 2013-05-14 18:24:34 -0400 | [diff] [blame] | 6615 | ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6616 | ret = si_enable_power_containment(rdev, new_ps, false); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6617 | if (ret) { |
| 6618 | DRM_ERROR("si_enable_power_containment failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6619 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6620 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6621 | ret = si_enable_smc_cac(rdev, new_ps, false); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6622 | if (ret) { |
| 6623 | DRM_ERROR("si_enable_smc_cac failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6624 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6625 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6626 | ret = si_halt_smc(rdev); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6627 | if (ret) { |
| 6628 | DRM_ERROR("si_halt_smc failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6629 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6630 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6631 | ret = si_upload_sw_state(rdev, new_ps); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6632 | if (ret) { |
| 6633 | DRM_ERROR("si_upload_sw_state failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6634 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6635 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6636 | ret = si_upload_smc_data(rdev); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6637 | if (ret) { |
| 6638 | DRM_ERROR("si_upload_smc_data failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6639 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6640 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6641 | ret = si_upload_ulv_state(rdev); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6642 | if (ret) { |
| 6643 | DRM_ERROR("si_upload_ulv_state failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6644 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6645 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6646 | if (eg_pi->dynamic_ac_timing) { |
| 6647 | ret = si_upload_mc_reg_table(rdev, new_ps); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6648 | if (ret) { |
| 6649 | DRM_ERROR("si_upload_mc_reg_table failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6650 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6651 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6652 | } |
| 6653 | ret = si_program_memory_timing_parameters(rdev, new_ps); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6654 | if (ret) { |
| 6655 | DRM_ERROR("si_program_memory_timing_parameters failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6656 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6657 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6658 | si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); |
| 6659 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6660 | ret = si_resume_smc(rdev); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6661 | if (ret) { |
| 6662 | DRM_ERROR("si_resume_smc failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6663 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6664 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6665 | ret = si_set_sw_state(rdev); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6666 | if (ret) { |
| 6667 | DRM_ERROR("si_set_sw_state failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6668 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6669 | } |
Alex Deucher | e34568b | 2013-05-14 18:24:34 -0400 | [diff] [blame] | 6670 | ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); |
Alex Deucher | 11586cf | 2015-05-11 22:01:52 +0200 | [diff] [blame] | 6671 | si_set_vce_clock(rdev, new_ps, old_ps); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6672 | if (eg_pi->pcie_performance_request) |
| 6673 | si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); |
| 6674 | ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6675 | if (ret) { |
| 6676 | DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6677 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6678 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6679 | ret = si_enable_smc_cac(rdev, new_ps, true); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6680 | if (ret) { |
| 6681 | DRM_ERROR("si_enable_smc_cac failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6682 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6683 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6684 | ret = si_enable_power_containment(rdev, new_ps, true); |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6685 | if (ret) { |
| 6686 | DRM_ERROR("si_enable_power_containment failed\n"); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6687 | return ret; |
Alex Deucher | cc833b6 | 2013-06-27 19:33:58 -0400 | [diff] [blame] | 6688 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6689 | |
Alex Deucher | a144acb | 2013-06-27 19:37:12 -0400 | [diff] [blame] | 6690 | ret = si_power_control_set_level(rdev); |
| 6691 | if (ret) { |
| 6692 | DRM_ERROR("si_power_control_set_level failed\n"); |
| 6693 | return ret; |
| 6694 | } |
| 6695 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6696 | return 0; |
| 6697 | } |
| 6698 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6699 | void si_dpm_post_set_power_state(struct radeon_device *rdev) |
| 6700 | { |
| 6701 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 6702 | struct radeon_ps *new_ps = &eg_pi->requested_rps; |
| 6703 | |
| 6704 | ni_update_current_ps(rdev, new_ps); |
| 6705 | } |
| 6706 | |
Alex Deucher | 9876913 | 2015-01-14 16:18:32 -0500 | [diff] [blame] | 6707 | #if 0 |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6708 | void si_dpm_reset_asic(struct radeon_device *rdev) |
| 6709 | { |
| 6710 | si_restrict_performance_levels_before_switch(rdev); |
| 6711 | si_disable_ulv(rdev); |
| 6712 | si_set_boot_state(rdev); |
| 6713 | } |
Alex Deucher | 9876913 | 2015-01-14 16:18:32 -0500 | [diff] [blame] | 6714 | #endif |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6715 | |
| 6716 | void si_dpm_display_configuration_changed(struct radeon_device *rdev) |
| 6717 | { |
| 6718 | si_program_display_gap(rdev); |
| 6719 | } |
| 6720 | |
| 6721 | union power_info { |
| 6722 | struct _ATOM_POWERPLAY_INFO info; |
| 6723 | struct _ATOM_POWERPLAY_INFO_V2 info_2; |
| 6724 | struct _ATOM_POWERPLAY_INFO_V3 info_3; |
| 6725 | struct _ATOM_PPLIB_POWERPLAYTABLE pplib; |
| 6726 | struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; |
| 6727 | struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; |
| 6728 | }; |
| 6729 | |
| 6730 | union pplib_clock_info { |
| 6731 | struct _ATOM_PPLIB_R600_CLOCK_INFO r600; |
| 6732 | struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; |
| 6733 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; |
| 6734 | struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; |
| 6735 | struct _ATOM_PPLIB_SI_CLOCK_INFO si; |
| 6736 | }; |
| 6737 | |
| 6738 | union pplib_power_state { |
| 6739 | struct _ATOM_PPLIB_STATE v1; |
| 6740 | struct _ATOM_PPLIB_STATE_V2 v2; |
| 6741 | }; |
| 6742 | |
| 6743 | static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, |
| 6744 | struct radeon_ps *rps, |
| 6745 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, |
| 6746 | u8 table_rev) |
| 6747 | { |
| 6748 | rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); |
| 6749 | rps->class = le16_to_cpu(non_clock_info->usClassification); |
| 6750 | rps->class2 = le16_to_cpu(non_clock_info->usClassification2); |
| 6751 | |
| 6752 | if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { |
| 6753 | rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); |
| 6754 | rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); |
| 6755 | } else if (r600_is_uvd_state(rps->class, rps->class2)) { |
| 6756 | rps->vclk = RV770_DEFAULT_VCLK_FREQ; |
| 6757 | rps->dclk = RV770_DEFAULT_DCLK_FREQ; |
| 6758 | } else { |
| 6759 | rps->vclk = 0; |
| 6760 | rps->dclk = 0; |
| 6761 | } |
| 6762 | |
| 6763 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) |
| 6764 | rdev->pm.dpm.boot_ps = rps; |
| 6765 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) |
| 6766 | rdev->pm.dpm.uvd_ps = rps; |
| 6767 | } |
| 6768 | |
| 6769 | static void si_parse_pplib_clock_info(struct radeon_device *rdev, |
| 6770 | struct radeon_ps *rps, int index, |
| 6771 | union pplib_clock_info *clock_info) |
| 6772 | { |
| 6773 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
| 6774 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 6775 | struct si_power_info *si_pi = si_get_pi(rdev); |
| 6776 | struct ni_ps *ps = ni_get_ps(rps); |
| 6777 | u16 leakage_voltage; |
| 6778 | struct rv7xx_pl *pl = &ps->performance_levels[index]; |
| 6779 | int ret; |
| 6780 | |
| 6781 | ps->performance_level_count = index + 1; |
| 6782 | |
| 6783 | pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); |
| 6784 | pl->sclk |= clock_info->si.ucEngineClockHigh << 16; |
| 6785 | pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); |
| 6786 | pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; |
| 6787 | |
| 6788 | pl->vddc = le16_to_cpu(clock_info->si.usVDDC); |
| 6789 | pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); |
| 6790 | pl->flags = le32_to_cpu(clock_info->si.ulFlags); |
| 6791 | pl->pcie_gen = r600_get_pcie_gen_support(rdev, |
| 6792 | si_pi->sys_pcie_mask, |
| 6793 | si_pi->boot_pcie_gen, |
| 6794 | clock_info->si.ucPCIEGen); |
| 6795 | |
| 6796 | /* patch up vddc if necessary */ |
| 6797 | ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, |
| 6798 | &leakage_voltage); |
| 6799 | if (ret == 0) |
| 6800 | pl->vddc = leakage_voltage; |
| 6801 | |
| 6802 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { |
| 6803 | pi->acpi_vddc = pl->vddc; |
| 6804 | eg_pi->acpi_vddci = pl->vddci; |
| 6805 | si_pi->acpi_pcie_gen = pl->pcie_gen; |
| 6806 | } |
| 6807 | |
| 6808 | if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && |
| 6809 | index == 0) { |
| 6810 | /* XXX disable for A0 tahiti */ |
Alex Deucher | 6fa4559 | 2014-10-13 12:44:49 -0400 | [diff] [blame] | 6811 | si_pi->ulv.supported = false; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6812 | si_pi->ulv.pl = *pl; |
| 6813 | si_pi->ulv.one_pcie_lane_in_ulv = false; |
| 6814 | si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; |
| 6815 | si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; |
| 6816 | si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; |
| 6817 | } |
| 6818 | |
| 6819 | if (pi->min_vddc_in_table > pl->vddc) |
| 6820 | pi->min_vddc_in_table = pl->vddc; |
| 6821 | |
| 6822 | if (pi->max_vddc_in_table < pl->vddc) |
| 6823 | pi->max_vddc_in_table = pl->vddc; |
| 6824 | |
| 6825 | /* patch up boot state */ |
| 6826 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { |
| 6827 | u16 vddc, vddci, mvdd; |
| 6828 | radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); |
| 6829 | pl->mclk = rdev->clock.default_mclk; |
| 6830 | pl->sclk = rdev->clock.default_sclk; |
| 6831 | pl->vddc = vddc; |
| 6832 | pl->vddci = vddci; |
| 6833 | si_pi->mvdd_bootup_value = mvdd; |
| 6834 | } |
| 6835 | |
| 6836 | if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == |
| 6837 | ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { |
| 6838 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; |
| 6839 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; |
| 6840 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; |
| 6841 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; |
| 6842 | } |
| 6843 | } |
| 6844 | |
| 6845 | static int si_parse_power_table(struct radeon_device *rdev) |
| 6846 | { |
| 6847 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 6848 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; |
| 6849 | union pplib_power_state *power_state; |
| 6850 | int i, j, k, non_clock_array_index, clock_array_index; |
| 6851 | union pplib_clock_info *clock_info; |
| 6852 | struct _StateArray *state_array; |
| 6853 | struct _ClockInfoArray *clock_info_array; |
| 6854 | struct _NonClockInfoArray *non_clock_info_array; |
| 6855 | union power_info *power_info; |
| 6856 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
Jérome Glisse | 3cf8bb1 | 2016-03-16 12:56:45 +0100 | [diff] [blame] | 6857 | u16 data_offset; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6858 | u8 frev, crev; |
| 6859 | u8 *power_state_offset; |
| 6860 | struct ni_ps *ps; |
| 6861 | |
| 6862 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 6863 | &frev, &crev, &data_offset)) |
| 6864 | return -EINVAL; |
| 6865 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); |
| 6866 | |
| 6867 | state_array = (struct _StateArray *) |
| 6868 | (mode_info->atom_context->bios + data_offset + |
| 6869 | le16_to_cpu(power_info->pplib.usStateArrayOffset)); |
| 6870 | clock_info_array = (struct _ClockInfoArray *) |
| 6871 | (mode_info->atom_context->bios + data_offset + |
| 6872 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); |
| 6873 | non_clock_info_array = (struct _NonClockInfoArray *) |
| 6874 | (mode_info->atom_context->bios + data_offset + |
| 6875 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); |
| 6876 | |
| 6877 | rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * |
| 6878 | state_array->ucNumEntries, GFP_KERNEL); |
| 6879 | if (!rdev->pm.dpm.ps) |
| 6880 | return -ENOMEM; |
| 6881 | power_state_offset = (u8 *)state_array->states; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6882 | for (i = 0; i < state_array->ucNumEntries; i++) { |
Alex Deucher | 53f3b25 | 2013-08-20 19:06:54 -0400 | [diff] [blame] | 6883 | u8 *idx; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6884 | power_state = (union pplib_power_state *)power_state_offset; |
| 6885 | non_clock_array_index = power_state->v2.nonClockInfoIndex; |
| 6886 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) |
| 6887 | &non_clock_info_array->nonClockInfo[non_clock_array_index]; |
| 6888 | if (!rdev->pm.power_state[i].clock_info) |
| 6889 | return -EINVAL; |
| 6890 | ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); |
| 6891 | if (ps == NULL) { |
| 6892 | kfree(rdev->pm.dpm.ps); |
| 6893 | return -ENOMEM; |
| 6894 | } |
| 6895 | rdev->pm.dpm.ps[i].ps_priv = ps; |
| 6896 | si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], |
| 6897 | non_clock_info, |
| 6898 | non_clock_info_array->ucEntrySize); |
| 6899 | k = 0; |
Alex Deucher | 53f3b25 | 2013-08-20 19:06:54 -0400 | [diff] [blame] | 6900 | idx = (u8 *)&power_state->v2.clockInfoIndex[0]; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6901 | for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { |
Alex Deucher | 53f3b25 | 2013-08-20 19:06:54 -0400 | [diff] [blame] | 6902 | clock_array_index = idx[j]; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6903 | if (clock_array_index >= clock_info_array->ucNumEntries) |
| 6904 | continue; |
| 6905 | if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) |
| 6906 | break; |
| 6907 | clock_info = (union pplib_clock_info *) |
Alex Deucher | 53f3b25 | 2013-08-20 19:06:54 -0400 | [diff] [blame] | 6908 | ((u8 *)&clock_info_array->clockInfo[0] + |
| 6909 | (clock_array_index * clock_info_array->ucEntrySize)); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6910 | si_parse_pplib_clock_info(rdev, |
| 6911 | &rdev->pm.dpm.ps[i], k, |
| 6912 | clock_info); |
| 6913 | k++; |
| 6914 | } |
| 6915 | power_state_offset += 2 + power_state->v2.ucNumDPMLevels; |
| 6916 | } |
| 6917 | rdev->pm.dpm.num_ps = state_array->ucNumEntries; |
Alex Deucher | 11586cf | 2015-05-11 22:01:52 +0200 | [diff] [blame] | 6918 | |
| 6919 | /* fill in the vce power states */ |
| 6920 | for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { |
| 6921 | u32 sclk, mclk; |
| 6922 | clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; |
| 6923 | clock_info = (union pplib_clock_info *) |
| 6924 | &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; |
| 6925 | sclk = le16_to_cpu(clock_info->si.usEngineClockLow); |
| 6926 | sclk |= clock_info->si.ucEngineClockHigh << 16; |
| 6927 | mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); |
| 6928 | mclk |= clock_info->si.ucMemoryClockHigh << 16; |
| 6929 | rdev->pm.dpm.vce_states[i].sclk = sclk; |
| 6930 | rdev->pm.dpm.vce_states[i].mclk = mclk; |
| 6931 | } |
| 6932 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6933 | return 0; |
| 6934 | } |
| 6935 | |
| 6936 | int si_dpm_init(struct radeon_device *rdev) |
| 6937 | { |
| 6938 | struct rv7xx_power_info *pi; |
| 6939 | struct evergreen_power_info *eg_pi; |
| 6940 | struct ni_power_info *ni_pi; |
| 6941 | struct si_power_info *si_pi; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6942 | struct atom_clock_dividers dividers; |
| 6943 | int ret; |
| 6944 | u32 mask; |
| 6945 | |
| 6946 | si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); |
| 6947 | if (si_pi == NULL) |
| 6948 | return -ENOMEM; |
| 6949 | rdev->pm.dpm.priv = si_pi; |
| 6950 | ni_pi = &si_pi->ni; |
| 6951 | eg_pi = &ni_pi->eg; |
| 6952 | pi = &eg_pi->rv7xx; |
| 6953 | |
| 6954 | ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); |
| 6955 | if (ret) |
| 6956 | si_pi->sys_pcie_mask = 0; |
| 6957 | else |
| 6958 | si_pi->sys_pcie_mask = mask; |
| 6959 | si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; |
| 6960 | si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); |
| 6961 | |
| 6962 | si_set_max_cu_value(rdev); |
| 6963 | |
| 6964 | rv770_get_max_vddc(rdev); |
| 6965 | si_get_leakage_vddc(rdev); |
| 6966 | si_patch_dependency_tables_based_on_leakage(rdev); |
| 6967 | |
| 6968 | pi->acpi_vddc = 0; |
| 6969 | eg_pi->acpi_vddci = 0; |
| 6970 | pi->min_vddc_in_table = 0; |
| 6971 | pi->max_vddc_in_table = 0; |
| 6972 | |
Alex Deucher | 82f79cc | 2013-08-21 10:02:32 -0400 | [diff] [blame] | 6973 | ret = r600_get_platform_caps(rdev); |
| 6974 | if (ret) |
| 6975 | return ret; |
| 6976 | |
Alex Deucher | 11586cf | 2015-05-11 22:01:52 +0200 | [diff] [blame] | 6977 | ret = r600_parse_extended_power_table(rdev); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6978 | if (ret) |
| 6979 | return ret; |
Alex Deucher | 11586cf | 2015-05-11 22:01:52 +0200 | [diff] [blame] | 6980 | |
| 6981 | ret = si_parse_power_table(rdev); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 6982 | if (ret) |
| 6983 | return ret; |
| 6984 | |
| 6985 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = |
| 6986 | kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); |
| 6987 | if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { |
| 6988 | r600_free_extended_power_table(rdev); |
| 6989 | return -ENOMEM; |
| 6990 | } |
| 6991 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; |
| 6992 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; |
| 6993 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; |
| 6994 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; |
| 6995 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; |
| 6996 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; |
| 6997 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; |
| 6998 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; |
| 6999 | rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; |
| 7000 | |
| 7001 | if (rdev->pm.dpm.voltage_response_time == 0) |
| 7002 | rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; |
| 7003 | if (rdev->pm.dpm.backbias_response_time == 0) |
| 7004 | rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; |
| 7005 | |
| 7006 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
| 7007 | 0, false, ÷rs); |
| 7008 | if (ret) |
| 7009 | pi->ref_div = dividers.ref_div + 1; |
| 7010 | else |
| 7011 | pi->ref_div = R600_REFERENCEDIVIDER_DFLT; |
| 7012 | |
| 7013 | eg_pi->smu_uvd_hs = false; |
| 7014 | |
| 7015 | pi->mclk_strobe_mode_threshold = 40000; |
| 7016 | if (si_is_special_1gb_platform(rdev)) |
| 7017 | pi->mclk_stutter_mode_threshold = 0; |
| 7018 | else |
| 7019 | pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; |
| 7020 | pi->mclk_edc_enable_threshold = 40000; |
| 7021 | eg_pi->mclk_edc_wr_enable_threshold = 40000; |
| 7022 | |
| 7023 | ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; |
| 7024 | |
| 7025 | pi->voltage_control = |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 7026 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, |
| 7027 | VOLTAGE_OBJ_GPIO_LUT); |
| 7028 | if (!pi->voltage_control) { |
| 7029 | si_pi->voltage_control_svi2 = |
| 7030 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, |
| 7031 | VOLTAGE_OBJ_SVID2); |
| 7032 | if (si_pi->voltage_control_svi2) |
| 7033 | radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, |
| 7034 | &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); |
| 7035 | } |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 7036 | |
| 7037 | pi->mvdd_control = |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 7038 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, |
| 7039 | VOLTAGE_OBJ_GPIO_LUT); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 7040 | |
| 7041 | eg_pi->vddci_control = |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 7042 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, |
| 7043 | VOLTAGE_OBJ_GPIO_LUT); |
| 7044 | if (!eg_pi->vddci_control) |
| 7045 | si_pi->vddci_control_svi2 = |
| 7046 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, |
| 7047 | VOLTAGE_OBJ_SVID2); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 7048 | |
| 7049 | si_pi->vddc_phase_shed_control = |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 7050 | radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, |
| 7051 | VOLTAGE_OBJ_PHASE_LUT); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 7052 | |
Alex Deucher | b841ce7 | 2013-07-31 18:32:33 -0400 | [diff] [blame] | 7053 | rv770_get_engine_memory_ss(rdev); |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 7054 | |
| 7055 | pi->asi = RV770_ASI_DFLT; |
| 7056 | pi->pasi = CYPRESS_HASI_DFLT; |
| 7057 | pi->vrc = SISLANDS_VRC_DFLT; |
| 7058 | |
| 7059 | pi->gfx_clock_gating = true; |
| 7060 | |
| 7061 | eg_pi->sclk_deep_sleep = true; |
| 7062 | si_pi->sclk_deep_sleep_above_low = false; |
| 7063 | |
Alex Deucher | fda8372 | 2013-07-31 12:41:35 -0400 | [diff] [blame] | 7064 | if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 7065 | pi->thermal_protection = true; |
| 7066 | else |
| 7067 | pi->thermal_protection = false; |
| 7068 | |
| 7069 | eg_pi->dynamic_ac_timing = true; |
| 7070 | |
| 7071 | eg_pi->light_sleep = true; |
| 7072 | #if defined(CONFIG_ACPI) |
| 7073 | eg_pi->pcie_performance_request = |
| 7074 | radeon_acpi_is_pcie_performance_request_supported(rdev); |
| 7075 | #else |
| 7076 | eg_pi->pcie_performance_request = false; |
| 7077 | #endif |
| 7078 | |
| 7079 | si_pi->sram_end = SMC_RAM_END; |
| 7080 | |
| 7081 | rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; |
| 7082 | rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; |
| 7083 | rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; |
| 7084 | rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; |
| 7085 | rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; |
| 7086 | rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; |
| 7087 | rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; |
| 7088 | |
| 7089 | si_initialize_powertune_defaults(rdev); |
| 7090 | |
Alex Deucher | 1ff60dd | 2013-08-30 16:18:35 -0400 | [diff] [blame] | 7091 | /* make sure dc limits are valid */ |
| 7092 | if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || |
| 7093 | (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) |
| 7094 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = |
| 7095 | rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
| 7096 | |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 7097 | si_pi->fan_ctrl_is_in_default_mode = true; |
Alex Deucher | 39471ad | 2014-09-14 21:14:14 -0400 | [diff] [blame] | 7098 | |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 7099 | return 0; |
| 7100 | } |
| 7101 | |
| 7102 | void si_dpm_fini(struct radeon_device *rdev) |
| 7103 | { |
| 7104 | int i; |
| 7105 | |
| 7106 | for (i = 0; i < rdev->pm.dpm.num_ps; i++) { |
| 7107 | kfree(rdev->pm.dpm.ps[i].ps_priv); |
| 7108 | } |
| 7109 | kfree(rdev->pm.dpm.ps); |
| 7110 | kfree(rdev->pm.dpm.priv); |
| 7111 | kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); |
| 7112 | r600_free_extended_power_table(rdev); |
| 7113 | } |
| 7114 | |
Alex Deucher | 7982128 | 2013-06-28 18:02:19 -0400 | [diff] [blame] | 7115 | void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 7116 | struct seq_file *m) |
| 7117 | { |
Alex Deucher | 9f3f63f | 2014-01-30 11:19:22 -0500 | [diff] [blame] | 7118 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 7119 | struct radeon_ps *rps = &eg_pi->current_rps; |
Alex Deucher | 7982128 | 2013-06-28 18:02:19 -0400 | [diff] [blame] | 7120 | struct ni_ps *ps = ni_get_ps(rps); |
| 7121 | struct rv7xx_pl *pl; |
| 7122 | u32 current_index = |
| 7123 | (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> |
| 7124 | CURRENT_STATE_INDEX_SHIFT; |
| 7125 | |
| 7126 | if (current_index >= ps->performance_level_count) { |
| 7127 | seq_printf(m, "invalid dpm profile %d\n", current_index); |
| 7128 | } else { |
| 7129 | pl = &ps->performance_levels[current_index]; |
| 7130 | seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); |
| 7131 | seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", |
| 7132 | current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); |
| 7133 | } |
| 7134 | } |
Alex Deucher | ca1110b | 2014-09-30 10:50:07 -0400 | [diff] [blame] | 7135 | |
| 7136 | u32 si_dpm_get_current_sclk(struct radeon_device *rdev) |
| 7137 | { |
| 7138 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 7139 | struct radeon_ps *rps = &eg_pi->current_rps; |
| 7140 | struct ni_ps *ps = ni_get_ps(rps); |
| 7141 | struct rv7xx_pl *pl; |
| 7142 | u32 current_index = |
| 7143 | (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> |
| 7144 | CURRENT_STATE_INDEX_SHIFT; |
| 7145 | |
| 7146 | if (current_index >= ps->performance_level_count) { |
| 7147 | return 0; |
| 7148 | } else { |
| 7149 | pl = &ps->performance_levels[current_index]; |
| 7150 | return pl->sclk; |
| 7151 | } |
| 7152 | } |
| 7153 | |
| 7154 | u32 si_dpm_get_current_mclk(struct radeon_device *rdev) |
| 7155 | { |
| 7156 | struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); |
| 7157 | struct radeon_ps *rps = &eg_pi->current_rps; |
| 7158 | struct ni_ps *ps = ni_get_ps(rps); |
| 7159 | struct rv7xx_pl *pl; |
| 7160 | u32 current_index = |
| 7161 | (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> |
| 7162 | CURRENT_STATE_INDEX_SHIFT; |
| 7163 | |
| 7164 | if (current_index >= ps->performance_level_count) { |
| 7165 | return 0; |
| 7166 | } else { |
| 7167 | pl = &ps->performance_levels[current_index]; |
| 7168 | return pl->mclk; |
| 7169 | } |
| 7170 | } |