Thierry Reding | e6fff4a | 2013-11-15 14:58:05 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013 NVIDIA Corporation. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | /* |
| 19 | * Function naming determines intended use: |
| 20 | * |
| 21 | * <x>_r(void) : Returns the offset for register <x>. |
| 22 | * |
| 23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. |
| 24 | * |
| 25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. |
| 26 | * |
| 27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted |
| 28 | * and masked to place it at field <y> of register <x>. This value |
| 29 | * can be |'d with others to produce a full register value for |
| 30 | * register <x>. |
| 31 | * |
| 32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This |
| 33 | * value can be ~'d and then &'d to clear the value of field <y> for |
| 34 | * register <x>. |
| 35 | * |
| 36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted |
| 37 | * to place it at field <y> of register <x>. This value can be |'d |
| 38 | * with others to produce a full register value for <x>. |
| 39 | * |
| 40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register |
| 41 | * <x> value 'r' after being shifted to place its LSB at bit 0. |
| 42 | * This value is suitable for direct comparison with other unshifted |
| 43 | * values appropriate for use in field <y> of register <x>. |
| 44 | * |
| 45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for |
| 46 | * field <y> of register <x>. This value is suitable for direct |
| 47 | * comparison with unshifted values appropriate for use in field <y> |
| 48 | * of register <x>. |
| 49 | */ |
| 50 | |
| 51 | #ifndef HOST1X_HW_HOST1X04_SYNC_H |
| 52 | #define HOST1X_HW_HOST1X04_SYNC_H |
| 53 | |
| 54 | #define REGISTER_STRIDE 4 |
| 55 | |
| 56 | static inline u32 host1x_sync_syncpt_r(unsigned int id) |
| 57 | { |
| 58 | return 0xf80 + id * REGISTER_STRIDE; |
| 59 | } |
| 60 | #define HOST1X_SYNC_SYNCPT(id) \ |
| 61 | host1x_sync_syncpt_r(id) |
| 62 | static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) |
| 63 | { |
| 64 | return 0xe80 + id * REGISTER_STRIDE; |
| 65 | } |
| 66 | #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ |
| 67 | host1x_sync_syncpt_thresh_cpu0_int_status_r(id) |
| 68 | static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) |
| 69 | { |
| 70 | return 0xf00 + id * REGISTER_STRIDE; |
| 71 | } |
| 72 | #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ |
| 73 | host1x_sync_syncpt_thresh_int_disable_r(id) |
| 74 | static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) |
| 75 | { |
| 76 | return 0xf20 + id * REGISTER_STRIDE; |
| 77 | } |
| 78 | #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ |
| 79 | host1x_sync_syncpt_thresh_int_enable_cpu0_r(id) |
| 80 | static inline u32 host1x_sync_cf_setup_r(unsigned int channel) |
| 81 | { |
| 82 | return 0xc00 + channel * REGISTER_STRIDE; |
| 83 | } |
| 84 | #define HOST1X_SYNC_CF_SETUP(channel) \ |
| 85 | host1x_sync_cf_setup_r(channel) |
| 86 | static inline u32 host1x_sync_cf_setup_base_v(u32 r) |
| 87 | { |
| 88 | return (r >> 0) & 0x3ff; |
| 89 | } |
| 90 | #define HOST1X_SYNC_CF_SETUP_BASE_V(r) \ |
| 91 | host1x_sync_cf_setup_base_v(r) |
| 92 | static inline u32 host1x_sync_cf_setup_limit_v(u32 r) |
| 93 | { |
| 94 | return (r >> 16) & 0x3ff; |
| 95 | } |
| 96 | #define HOST1X_SYNC_CF_SETUP_LIMIT_V(r) \ |
| 97 | host1x_sync_cf_setup_limit_v(r) |
| 98 | static inline u32 host1x_sync_cmdproc_stop_r(void) |
| 99 | { |
| 100 | return 0xac; |
| 101 | } |
| 102 | #define HOST1X_SYNC_CMDPROC_STOP \ |
| 103 | host1x_sync_cmdproc_stop_r() |
| 104 | static inline u32 host1x_sync_ch_teardown_r(void) |
| 105 | { |
| 106 | return 0xb0; |
| 107 | } |
| 108 | #define HOST1X_SYNC_CH_TEARDOWN \ |
| 109 | host1x_sync_ch_teardown_r() |
| 110 | static inline u32 host1x_sync_usec_clk_r(void) |
| 111 | { |
| 112 | return 0x1a4; |
| 113 | } |
| 114 | #define HOST1X_SYNC_USEC_CLK \ |
| 115 | host1x_sync_usec_clk_r() |
| 116 | static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void) |
| 117 | { |
| 118 | return 0x1a8; |
| 119 | } |
| 120 | #define HOST1X_SYNC_CTXSW_TIMEOUT_CFG \ |
| 121 | host1x_sync_ctxsw_timeout_cfg_r() |
| 122 | static inline u32 host1x_sync_ip_busy_timeout_r(void) |
| 123 | { |
| 124 | return 0x1bc; |
| 125 | } |
| 126 | #define HOST1X_SYNC_IP_BUSY_TIMEOUT \ |
| 127 | host1x_sync_ip_busy_timeout_r() |
| 128 | static inline u32 host1x_sync_mlock_owner_r(unsigned int id) |
| 129 | { |
| 130 | return 0x340 + id * REGISTER_STRIDE; |
| 131 | } |
| 132 | #define HOST1X_SYNC_MLOCK_OWNER(id) \ |
| 133 | host1x_sync_mlock_owner_r(id) |
Dmitry Osipenko | 3fe2c7d | 2015-06-28 22:27:02 +0300 | [diff] [blame] | 134 | static inline u32 host1x_sync_mlock_owner_chid_v(u32 v) |
Thierry Reding | e6fff4a | 2013-11-15 14:58:05 +0100 | [diff] [blame] | 135 | { |
Dmitry Osipenko | 3fe2c7d | 2015-06-28 22:27:02 +0300 | [diff] [blame] | 136 | return (v >> 8) & 0xf; |
Thierry Reding | e6fff4a | 2013-11-15 14:58:05 +0100 | [diff] [blame] | 137 | } |
Dmitry Osipenko | 3fe2c7d | 2015-06-28 22:27:02 +0300 | [diff] [blame] | 138 | #define HOST1X_SYNC_MLOCK_OWNER_CHID_V(v) \ |
| 139 | host1x_sync_mlock_owner_chid_v(v) |
Thierry Reding | e6fff4a | 2013-11-15 14:58:05 +0100 | [diff] [blame] | 140 | static inline u32 host1x_sync_mlock_owner_cpu_owns_v(u32 r) |
| 141 | { |
| 142 | return (r >> 1) & 0x1; |
| 143 | } |
| 144 | #define HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(r) \ |
| 145 | host1x_sync_mlock_owner_cpu_owns_v(r) |
| 146 | static inline u32 host1x_sync_mlock_owner_ch_owns_v(u32 r) |
| 147 | { |
| 148 | return (r >> 0) & 0x1; |
| 149 | } |
| 150 | #define HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(r) \ |
| 151 | host1x_sync_mlock_owner_ch_owns_v(r) |
| 152 | static inline u32 host1x_sync_syncpt_int_thresh_r(unsigned int id) |
| 153 | { |
| 154 | return 0x1380 + id * REGISTER_STRIDE; |
| 155 | } |
| 156 | #define HOST1X_SYNC_SYNCPT_INT_THRESH(id) \ |
| 157 | host1x_sync_syncpt_int_thresh_r(id) |
| 158 | static inline u32 host1x_sync_syncpt_base_r(unsigned int id) |
| 159 | { |
| 160 | return 0x600 + id * REGISTER_STRIDE; |
| 161 | } |
| 162 | #define HOST1X_SYNC_SYNCPT_BASE(id) \ |
| 163 | host1x_sync_syncpt_base_r(id) |
| 164 | static inline u32 host1x_sync_syncpt_cpu_incr_r(unsigned int id) |
| 165 | { |
| 166 | return 0xf60 + id * REGISTER_STRIDE; |
| 167 | } |
| 168 | #define HOST1X_SYNC_SYNCPT_CPU_INCR(id) \ |
| 169 | host1x_sync_syncpt_cpu_incr_r(id) |
| 170 | static inline u32 host1x_sync_cbread_r(unsigned int channel) |
| 171 | { |
| 172 | return 0xc80 + channel * REGISTER_STRIDE; |
| 173 | } |
| 174 | #define HOST1X_SYNC_CBREAD(channel) \ |
| 175 | host1x_sync_cbread_r(channel) |
| 176 | static inline u32 host1x_sync_cfpeek_ctrl_r(void) |
| 177 | { |
| 178 | return 0x74c; |
| 179 | } |
| 180 | #define HOST1X_SYNC_CFPEEK_CTRL \ |
| 181 | host1x_sync_cfpeek_ctrl_r() |
| 182 | static inline u32 host1x_sync_cfpeek_ctrl_addr_f(u32 v) |
| 183 | { |
| 184 | return (v & 0x3ff) << 0; |
| 185 | } |
| 186 | #define HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(v) \ |
| 187 | host1x_sync_cfpeek_ctrl_addr_f(v) |
| 188 | static inline u32 host1x_sync_cfpeek_ctrl_channr_f(u32 v) |
| 189 | { |
| 190 | return (v & 0xf) << 16; |
| 191 | } |
| 192 | #define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(v) \ |
| 193 | host1x_sync_cfpeek_ctrl_channr_f(v) |
| 194 | static inline u32 host1x_sync_cfpeek_ctrl_ena_f(u32 v) |
| 195 | { |
| 196 | return (v & 0x1) << 31; |
| 197 | } |
| 198 | #define HOST1X_SYNC_CFPEEK_CTRL_ENA_F(v) \ |
| 199 | host1x_sync_cfpeek_ctrl_ena_f(v) |
| 200 | static inline u32 host1x_sync_cfpeek_read_r(void) |
| 201 | { |
| 202 | return 0x750; |
| 203 | } |
| 204 | #define HOST1X_SYNC_CFPEEK_READ \ |
| 205 | host1x_sync_cfpeek_read_r() |
| 206 | static inline u32 host1x_sync_cfpeek_ptrs_r(void) |
| 207 | { |
| 208 | return 0x754; |
| 209 | } |
| 210 | #define HOST1X_SYNC_CFPEEK_PTRS \ |
| 211 | host1x_sync_cfpeek_ptrs_r() |
| 212 | static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(u32 r) |
| 213 | { |
| 214 | return (r >> 0) & 0x3ff; |
| 215 | } |
| 216 | #define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(r) \ |
| 217 | host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(r) |
| 218 | static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(u32 r) |
| 219 | { |
| 220 | return (r >> 16) & 0x3ff; |
| 221 | } |
| 222 | #define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(r) \ |
| 223 | host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(r) |
| 224 | static inline u32 host1x_sync_cbstat_r(unsigned int channel) |
| 225 | { |
| 226 | return 0xcc0 + channel * REGISTER_STRIDE; |
| 227 | } |
| 228 | #define HOST1X_SYNC_CBSTAT(channel) \ |
| 229 | host1x_sync_cbstat_r(channel) |
| 230 | static inline u32 host1x_sync_cbstat_cboffset_v(u32 r) |
| 231 | { |
| 232 | return (r >> 0) & 0xffff; |
| 233 | } |
| 234 | #define HOST1X_SYNC_CBSTAT_CBOFFSET_V(r) \ |
| 235 | host1x_sync_cbstat_cboffset_v(r) |
| 236 | static inline u32 host1x_sync_cbstat_cbclass_v(u32 r) |
| 237 | { |
| 238 | return (r >> 16) & 0x3ff; |
| 239 | } |
| 240 | #define HOST1X_SYNC_CBSTAT_CBCLASS_V(r) \ |
| 241 | host1x_sync_cbstat_cbclass_v(r) |
| 242 | |
| 243 | #endif |