| Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Malta Platform-specific hooks for SMP operation |
| 3 | */ |
| 4 | |
| 5 | #include <linux/kernel.h> |
| 6 | #include <linux/sched.h> |
| 7 | #include <linux/cpumask.h> |
| 8 | #include <linux/interrupt.h> |
| 9 | |
| 10 | #include <asm/atomic.h> |
| 11 | #include <asm/cpu.h> |
| 12 | #include <asm/processor.h> |
| 13 | #include <asm/system.h> |
| 14 | #include <asm/hardirq.h> |
| 15 | #include <asm/mmu_context.h> |
| 16 | #include <asm/smp.h> |
| 17 | #ifdef CONFIG_MIPS_MT_SMTC |
| 18 | #include <asm/smtc_ipi.h> |
| 19 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 20 | |
| 21 | /* VPE/SMP Prototype implements platform interfaces directly */ |
| 22 | #if !defined(CONFIG_MIPS_MT_SMP) |
| 23 | |
| 24 | /* |
| 25 | * Cause the specified action to be performed on a targeted "CPU" |
| 26 | */ |
| 27 | |
| 28 | void core_send_ipi(int cpu, unsigned int action) |
| 29 | { |
| 30 | /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ |
| 31 | #ifdef CONFIG_MIPS_MT_SMTC |
| 32 | smtc_send_ipi(cpu, LINUX_SMP_IPI, action); |
| 33 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 34 | } |
| 35 | |
| 36 | /* |
| 37 | * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map |
| 38 | */ |
| 39 | |
| 40 | void __init prom_build_cpu_map(void) |
| 41 | { |
| 42 | int nextslot; |
| 43 | |
| 44 | /* |
| 45 | * As of November, 2004, MIPSsim only simulates one core |
| 46 | * at a time. However, that core may be a MIPS MT core |
| 47 | * with multiple virtual processors and thread contexts. |
| 48 | */ |
| 49 | |
| 50 | if (read_c0_config3() & (1<<2)) { |
| 51 | nextslot = mipsmt_build_cpu_map(1); |
| 52 | } |
| 53 | } |
| 54 | |
| 55 | /* |
| 56 | * Platform "CPU" startup hook |
| 57 | */ |
| 58 | |
| 59 | void prom_boot_secondary(int cpu, struct task_struct *idle) |
| 60 | { |
| 61 | #ifdef CONFIG_MIPS_MT_SMTC |
| 62 | smtc_boot_secondary(cpu, idle); |
| 63 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 64 | } |
| 65 | |
| 66 | /* |
| 67 | * Post-config but pre-boot cleanup entry point |
| 68 | */ |
| 69 | |
| 70 | void prom_init_secondary(void) |
| 71 | { |
| 72 | #ifdef CONFIG_MIPS_MT_SMTC |
| 73 | void smtc_init_secondary(void); |
| 74 | int myvpe; |
| 75 | |
| 76 | /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ |
| 77 | myvpe = read_c0_tcbind() & TCBIND_CURVPE; |
| 78 | if (myvpe != 0) { |
| 79 | /* Ideally, this should be done only once per VPE, but... */ |
| 80 | clear_c0_status(STATUSF_IP2); |
| 81 | set_c0_status(STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP3 |
| 82 | | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6 |
| 83 | | STATUSF_IP7); |
| 84 | } |
| 85 | |
| 86 | smtc_init_secondary(); |
| 87 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 88 | } |
| 89 | |
| 90 | /* |
| 91 | * Platform SMP pre-initialization |
| 92 | * |
| 93 | * As noted above, we can assume a single CPU for now |
| 94 | * but it may be multithreaded. |
| 95 | */ |
| 96 | |
| 97 | void plat_smp_setup(void) |
| 98 | { |
| 99 | if (read_c0_config3() & (1<<2)) |
| 100 | mipsmt_build_cpu_map(0); |
| 101 | } |
| 102 | |
| 103 | void __init plat_prepare_cpus(unsigned int max_cpus) |
| 104 | { |
| 105 | if (read_c0_config3() & (1<<2)) |
| 106 | mipsmt_prepare_cpus(); |
| 107 | } |
| 108 | |
| 109 | /* |
| 110 | * SMP initialization finalization entry point |
| 111 | */ |
| 112 | |
| 113 | void prom_smp_finish(void) |
| 114 | { |
| 115 | #ifdef CONFIG_MIPS_MT_SMTC |
| 116 | smtc_smp_finish(); |
| 117 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 118 | } |
| 119 | |
| 120 | /* |
| 121 | * Hook for after all CPUs are online |
| 122 | */ |
| 123 | |
| 124 | void prom_cpus_done(void) |
| 125 | { |
| 126 | } |
| 127 | |
| 128 | #endif /* CONFIG_MIPS32R2_MT_SMP */ |