Stephen Boyd | 6e0ad1b | 2014-01-15 10:47:26 -0800 | [diff] [blame] | 1 | /* |
Taniya Das | 41f3781 | 2016-09-29 13:28:59 +0530 | [diff] [blame^] | 2 | * Copyright (c) 2013, 2016-2017, The Linux Foundation. All rights reserved. |
Stephen Boyd | 6e0ad1b | 2014-01-15 10:47:26 -0800 | [diff] [blame] | 3 | * |
| 4 | * This software is licensed under the terms of the GNU General Public |
| 5 | * License version 2, as published by the Free Software Foundation, and |
| 6 | * may be copied, distributed, and modified under those terms. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #ifndef __QCOM_CLK_BRANCH_H__ |
| 15 | #define __QCOM_CLK_BRANCH_H__ |
| 16 | |
| 17 | #include <linux/clk-provider.h> |
| 18 | |
| 19 | #include "clk-regmap.h" |
| 20 | |
| 21 | /** |
| 22 | * struct clk_branch - gating clock with status bit and dynamic hardware gating |
| 23 | * |
| 24 | * @hwcg_reg: dynamic hardware clock gating register |
| 25 | * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating |
| 26 | * @halt_reg: halt register |
| 27 | * @halt_bit: ANDed with @halt_reg to test for clock halted |
| 28 | * @halt_check: type of halt checking to perform |
Deepak Katragadda | 9caf899 | 2016-12-21 11:12:55 -0800 | [diff] [blame] | 29 | * @aggr_sibling_rates: set if the branch clock's parent needs to be scaled |
| 30 | * based on an aggregation of its siblings votes. |
Stephen Boyd | 6e0ad1b | 2014-01-15 10:47:26 -0800 | [diff] [blame] | 31 | * @clkr: handle between common and hardware-specific interfaces |
| 32 | * |
| 33 | * Clock which can gate its output. |
| 34 | */ |
| 35 | struct clk_branch { |
| 36 | u32 hwcg_reg; |
| 37 | u32 halt_reg; |
| 38 | u8 hwcg_bit; |
| 39 | u8 halt_bit; |
| 40 | u8 halt_check; |
Deepak Katragadda | 9caf899 | 2016-12-21 11:12:55 -0800 | [diff] [blame] | 41 | bool aggr_sibling_rates; |
| 42 | unsigned long rate; |
Stephen Boyd | 6e0ad1b | 2014-01-15 10:47:26 -0800 | [diff] [blame] | 43 | #define BRANCH_VOTED BIT(7) /* Delay on disable */ |
| 44 | #define BRANCH_HALT 0 /* pol: 1 = halt */ |
| 45 | #define BRANCH_HALT_VOTED (BRANCH_HALT | BRANCH_VOTED) |
| 46 | #define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */ |
| 47 | #define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE | BRANCH_VOTED) |
| 48 | #define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */ |
| 49 | |
| 50 | struct clk_regmap clkr; |
| 51 | }; |
| 52 | |
Odelu Kukatla | 0d94153 | 2016-06-06 22:19:53 +0530 | [diff] [blame] | 53 | /** |
| 54 | * struct clk_gate2 - gating clock with status bit and dynamic hardware gating |
| 55 | * @udelay: halt delay in microseconds on clock branch Enable/Disable |
| 56 | * @clkr: handle between common and hardware-specific interfaces |
| 57 | * |
| 58 | * Clock which can gate its output. |
| 59 | */ |
| 60 | struct clk_gate2 { |
| 61 | u32 udelay; |
| 62 | struct clk_regmap clkr; |
| 63 | }; |
| 64 | |
Stephen Boyd | 6e0ad1b | 2014-01-15 10:47:26 -0800 | [diff] [blame] | 65 | extern const struct clk_ops clk_branch_ops; |
| 66 | extern const struct clk_ops clk_branch2_ops; |
Taniya Das | 41f3781 | 2016-09-29 13:28:59 +0530 | [diff] [blame^] | 67 | extern const struct clk_ops clk_branch2_hw_ctl_ops; |
Odelu Kukatla | 0d94153 | 2016-06-06 22:19:53 +0530 | [diff] [blame] | 68 | extern const struct clk_ops clk_gate2_ops; |
Stephen Boyd | 6e0ad1b | 2014-01-15 10:47:26 -0800 | [diff] [blame] | 69 | extern const struct clk_ops clk_branch_simple_ops; |
| 70 | |
| 71 | #define to_clk_branch(_hw) \ |
| 72 | container_of(to_clk_regmap(_hw), struct clk_branch, clkr) |
| 73 | |
Odelu Kukatla | 0d94153 | 2016-06-06 22:19:53 +0530 | [diff] [blame] | 74 | #define to_clk_gate2(_hw) \ |
| 75 | container_of(to_clk_regmap(_hw), struct clk_gate2, clkr) |
| 76 | |
Stephen Boyd | 6e0ad1b | 2014-01-15 10:47:26 -0800 | [diff] [blame] | 77 | #endif |