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Stephen Boyd6e0ad1b2014-01-15 10:47:26 -08001/*
Taniya Das41f37812016-09-29 13:28:59 +05302 * Copyright (c) 2013, 2016-2017, The Linux Foundation. All rights reserved.
Stephen Boyd6e0ad1b2014-01-15 10:47:26 -08003 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_BRANCH_H__
15#define __QCOM_CLK_BRANCH_H__
16
17#include <linux/clk-provider.h>
18
19#include "clk-regmap.h"
20
21/**
22 * struct clk_branch - gating clock with status bit and dynamic hardware gating
23 *
24 * @hwcg_reg: dynamic hardware clock gating register
25 * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
26 * @halt_reg: halt register
27 * @halt_bit: ANDed with @halt_reg to test for clock halted
28 * @halt_check: type of halt checking to perform
Deepak Katragadda9caf8992016-12-21 11:12:55 -080029 * @aggr_sibling_rates: set if the branch clock's parent needs to be scaled
30 * based on an aggregation of its siblings votes.
Stephen Boyd6e0ad1b2014-01-15 10:47:26 -080031 * @clkr: handle between common and hardware-specific interfaces
32 *
33 * Clock which can gate its output.
34 */
35struct clk_branch {
36 u32 hwcg_reg;
37 u32 halt_reg;
38 u8 hwcg_bit;
39 u8 halt_bit;
40 u8 halt_check;
Deepak Katragadda9caf8992016-12-21 11:12:55 -080041 bool aggr_sibling_rates;
42 unsigned long rate;
Stephen Boyd6e0ad1b2014-01-15 10:47:26 -080043#define BRANCH_VOTED BIT(7) /* Delay on disable */
44#define BRANCH_HALT 0 /* pol: 1 = halt */
45#define BRANCH_HALT_VOTED (BRANCH_HALT | BRANCH_VOTED)
46#define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */
47#define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE | BRANCH_VOTED)
48#define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */
49
50 struct clk_regmap clkr;
51};
52
Odelu Kukatla0d941532016-06-06 22:19:53 +053053/**
54 * struct clk_gate2 - gating clock with status bit and dynamic hardware gating
55 * @udelay: halt delay in microseconds on clock branch Enable/Disable
56 * @clkr: handle between common and hardware-specific interfaces
57 *
58 * Clock which can gate its output.
59 */
60struct clk_gate2 {
61 u32 udelay;
62 struct clk_regmap clkr;
63};
64
Stephen Boyd6e0ad1b2014-01-15 10:47:26 -080065extern const struct clk_ops clk_branch_ops;
66extern const struct clk_ops clk_branch2_ops;
Taniya Das41f37812016-09-29 13:28:59 +053067extern const struct clk_ops clk_branch2_hw_ctl_ops;
Odelu Kukatla0d941532016-06-06 22:19:53 +053068extern const struct clk_ops clk_gate2_ops;
Stephen Boyd6e0ad1b2014-01-15 10:47:26 -080069extern const struct clk_ops clk_branch_simple_ops;
70
71#define to_clk_branch(_hw) \
72 container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
73
Odelu Kukatla0d941532016-06-06 22:19:53 +053074#define to_clk_gate2(_hw) \
75 container_of(to_clk_regmap(_hw), struct clk_gate2, clkr)
76
Stephen Boyd6e0ad1b2014-01-15 10:47:26 -080077#endif