Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 1 | /* |
| 2 | * S3C24XX IRQ handling |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 3 | * |
Ben Dooks | e02f866 | 2009-11-13 22:54:13 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2004 Simtec Electronics |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 5 | * Ben Dooks <ben@simtec.co.uk> |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 6 | * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de> |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <linux/init.h> |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 20 | #include <linux/slab.h> |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 21 | #include <linux/module.h> |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 22 | #include <linux/io.h> |
| 23 | #include <linux/err.h> |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/ioport.h> |
Kay Sievers | edbaa60 | 2011-12-21 16:26:03 -0800 | [diff] [blame] | 26 | #include <linux/device.h> |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 27 | #include <linux/irqdomain.h> |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 28 | |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 29 | #include <asm/mach/irq.h> |
| 30 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 31 | #include <mach/regs-irq.h> |
| 32 | #include <mach/regs-gpio.h> |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 33 | |
Ben Dooks | a2b7ba9 | 2008-10-07 22:26:09 +0100 | [diff] [blame] | 34 | #include <plat/cpu.h> |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 35 | #include <plat/regs-irqtype.h> |
Ben Dooks | a2b7ba9 | 2008-10-07 22:26:09 +0100 | [diff] [blame] | 36 | #include <plat/pm.h> |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 37 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 38 | #define S3C_IRQTYPE_NONE 0 |
| 39 | #define S3C_IRQTYPE_EINT 1 |
| 40 | #define S3C_IRQTYPE_EDGE 2 |
| 41 | #define S3C_IRQTYPE_LEVEL 3 |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 42 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 43 | struct s3c_irq_data { |
| 44 | unsigned int type; |
| 45 | unsigned long parent_irq; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 46 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 47 | /* data gets filled during init */ |
| 48 | struct s3c_irq_intc *intc; |
| 49 | unsigned long sub_bits; |
| 50 | struct s3c_irq_intc *sub_intc; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 51 | }; |
| 52 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 53 | /* |
| 54 | * Sructure holding the controller data |
| 55 | * @reg_pending register holding pending irqs |
| 56 | * @reg_intpnd special register intpnd in main intc |
| 57 | * @reg_mask mask register |
| 58 | * @domain irq_domain of the controller |
| 59 | * @parent parent controller for ext and sub irqs |
| 60 | * @irqs irq-data, always s3c_irq_data[32] |
| 61 | */ |
| 62 | struct s3c_irq_intc { |
| 63 | void __iomem *reg_pending; |
| 64 | void __iomem *reg_intpnd; |
| 65 | void __iomem *reg_mask; |
| 66 | struct irq_domain *domain; |
| 67 | struct s3c_irq_intc *parent; |
| 68 | struct s3c_irq_data *irqs; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 69 | }; |
| 70 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 71 | static void s3c_irq_mask(struct irq_data *data) |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 72 | { |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 73 | struct s3c_irq_intc *intc = data->domain->host_data; |
| 74 | struct s3c_irq_intc *parent_intc = intc->parent; |
| 75 | struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq]; |
| 76 | struct s3c_irq_data *parent_data; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 77 | unsigned long mask; |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 78 | unsigned int irqno; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 79 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 80 | mask = __raw_readl(intc->reg_mask); |
| 81 | mask |= (1UL << data->hwirq); |
| 82 | __raw_writel(mask, intc->reg_mask); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 83 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 84 | if (parent_intc && irq_data->parent_irq) { |
| 85 | parent_data = &parent_intc->irqs[irq_data->parent_irq]; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 86 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 87 | /* check to see if we need to mask the parent IRQ */ |
| 88 | if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { |
| 89 | irqno = irq_find_mapping(parent_intc->domain, |
| 90 | irq_data->parent_irq); |
| 91 | s3c_irq_mask(irq_get_irq_data(irqno)); |
| 92 | } |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 93 | } |
| 94 | } |
| 95 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 96 | static void s3c_irq_unmask(struct irq_data *data) |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 97 | { |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 98 | struct s3c_irq_intc *intc = data->domain->host_data; |
| 99 | struct s3c_irq_intc *parent_intc = intc->parent; |
| 100 | struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq]; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 101 | unsigned long mask; |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 102 | unsigned int irqno; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 103 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 104 | mask = __raw_readl(intc->reg_mask); |
| 105 | mask &= ~(1UL << data->hwirq); |
| 106 | __raw_writel(mask, intc->reg_mask); |
| 107 | |
| 108 | if (parent_intc && irq_data->parent_irq) { |
| 109 | irqno = irq_find_mapping(parent_intc->domain, |
| 110 | irq_data->parent_irq); |
| 111 | s3c_irq_unmask(irq_get_irq_data(irqno)); |
| 112 | } |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 113 | } |
| 114 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 115 | static inline void s3c_irq_ack(struct irq_data *data) |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 116 | { |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 117 | struct s3c_irq_intc *intc = data->domain->host_data; |
| 118 | unsigned long bitval = 1UL << data->hwirq; |
| 119 | |
| 120 | __raw_writel(bitval, intc->reg_pending); |
| 121 | if (intc->reg_intpnd) |
| 122 | __raw_writel(bitval, intc->reg_intpnd); |
| 123 | } |
| 124 | |
| 125 | static int s3c_irqext_type_set(void __iomem *gpcon_reg, |
| 126 | void __iomem *extint_reg, |
| 127 | unsigned long gpcon_offset, |
| 128 | unsigned long extint_offset, |
| 129 | unsigned int type) |
| 130 | { |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 131 | unsigned long newvalue = 0, value; |
| 132 | |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 133 | /* Set the GPIO to external interrupt mode */ |
| 134 | value = __raw_readl(gpcon_reg); |
| 135 | value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); |
| 136 | __raw_writel(value, gpcon_reg); |
| 137 | |
| 138 | /* Set the external interrupt to pointed trigger type */ |
| 139 | switch (type) |
| 140 | { |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 141 | case IRQ_TYPE_NONE: |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 142 | pr_warn("No edge setting!\n"); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 143 | break; |
| 144 | |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 145 | case IRQ_TYPE_EDGE_RISING: |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 146 | newvalue = S3C2410_EXTINT_RISEEDGE; |
| 147 | break; |
| 148 | |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 149 | case IRQ_TYPE_EDGE_FALLING: |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 150 | newvalue = S3C2410_EXTINT_FALLEDGE; |
| 151 | break; |
| 152 | |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 153 | case IRQ_TYPE_EDGE_BOTH: |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 154 | newvalue = S3C2410_EXTINT_BOTHEDGE; |
| 155 | break; |
| 156 | |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 157 | case IRQ_TYPE_LEVEL_LOW: |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 158 | newvalue = S3C2410_EXTINT_LOWLEV; |
| 159 | break; |
| 160 | |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 161 | case IRQ_TYPE_LEVEL_HIGH: |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 162 | newvalue = S3C2410_EXTINT_HILEV; |
| 163 | break; |
| 164 | |
| 165 | default: |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 166 | pr_err("No such irq type %d", type); |
| 167 | return -EINVAL; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | value = __raw_readl(extint_reg); |
| 171 | value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); |
| 172 | __raw_writel(value, extint_reg); |
| 173 | |
| 174 | return 0; |
| 175 | } |
| 176 | |
Heiko Stuebner | dc1a353 | 2013-02-12 14:23:01 -0800 | [diff] [blame] | 177 | static int s3c_irqext_type(struct irq_data *data, unsigned int type) |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 178 | { |
| 179 | void __iomem *extint_reg; |
| 180 | void __iomem *gpcon_reg; |
| 181 | unsigned long gpcon_offset, extint_offset; |
| 182 | |
| 183 | if ((data->hwirq >= 4) && (data->hwirq <= 7)) { |
| 184 | gpcon_reg = S3C2410_GPFCON; |
| 185 | extint_reg = S3C24XX_EXTINT0; |
| 186 | gpcon_offset = (data->hwirq) * 2; |
| 187 | extint_offset = (data->hwirq) * 4; |
| 188 | } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) { |
| 189 | gpcon_reg = S3C2410_GPGCON; |
| 190 | extint_reg = S3C24XX_EXTINT1; |
| 191 | gpcon_offset = (data->hwirq - 8) * 2; |
| 192 | extint_offset = (data->hwirq - 8) * 4; |
| 193 | } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) { |
| 194 | gpcon_reg = S3C2410_GPGCON; |
| 195 | extint_reg = S3C24XX_EXTINT2; |
| 196 | gpcon_offset = (data->hwirq - 8) * 2; |
| 197 | extint_offset = (data->hwirq - 16) * 4; |
| 198 | } else { |
| 199 | return -EINVAL; |
| 200 | } |
| 201 | |
| 202 | return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, |
| 203 | extint_offset, type); |
| 204 | } |
| 205 | |
| 206 | static int s3c_irqext0_type(struct irq_data *data, unsigned int type) |
| 207 | { |
| 208 | void __iomem *extint_reg; |
| 209 | void __iomem *gpcon_reg; |
| 210 | unsigned long gpcon_offset, extint_offset; |
| 211 | |
| 212 | if ((data->hwirq >= 0) && (data->hwirq <= 3)) { |
| 213 | gpcon_reg = S3C2410_GPFCON; |
| 214 | extint_reg = S3C24XX_EXTINT0; |
| 215 | gpcon_offset = (data->hwirq) * 2; |
| 216 | extint_offset = (data->hwirq) * 4; |
| 217 | } else { |
| 218 | return -EINVAL; |
| 219 | } |
| 220 | |
| 221 | return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, |
| 222 | extint_offset, type); |
| 223 | } |
| 224 | |
Heiko Stuebner | dc1a353 | 2013-02-12 14:23:01 -0800 | [diff] [blame] | 225 | static struct irq_chip s3c_irq_chip = { |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 226 | .name = "s3c", |
| 227 | .irq_ack = s3c_irq_ack, |
| 228 | .irq_mask = s3c_irq_mask, |
| 229 | .irq_unmask = s3c_irq_unmask, |
| 230 | .irq_set_wake = s3c_irq_wake |
| 231 | }; |
| 232 | |
Heiko Stuebner | dc1a353 | 2013-02-12 14:23:01 -0800 | [diff] [blame] | 233 | static struct irq_chip s3c_irq_level_chip = { |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 234 | .name = "s3c-level", |
| 235 | .irq_mask = s3c_irq_mask, |
| 236 | .irq_unmask = s3c_irq_unmask, |
| 237 | .irq_ack = s3c_irq_ack, |
| 238 | }; |
| 239 | |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 240 | static struct irq_chip s3c_irqext_chip = { |
| 241 | .name = "s3c-ext", |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 242 | .irq_mask = s3c_irq_mask, |
| 243 | .irq_unmask = s3c_irq_unmask, |
| 244 | .irq_ack = s3c_irq_ack, |
Lennert Buytenhek | 57436c2d | 2011-01-03 19:15:54 +0900 | [diff] [blame] | 245 | .irq_set_type = s3c_irqext_type, |
Mark Brown | f5aeffb | 2010-12-02 14:35:38 +0900 | [diff] [blame] | 246 | .irq_set_wake = s3c_irqext_wake |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 247 | }; |
| 248 | |
| 249 | static struct irq_chip s3c_irq_eint0t4 = { |
| 250 | .name = "s3c-ext0", |
Lennert Buytenhek | 57436c2d | 2011-01-03 19:15:54 +0900 | [diff] [blame] | 251 | .irq_ack = s3c_irq_ack, |
| 252 | .irq_mask = s3c_irq_mask, |
| 253 | .irq_unmask = s3c_irq_unmask, |
| 254 | .irq_set_wake = s3c_irq_wake, |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 255 | .irq_set_type = s3c_irqext0_type, |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 256 | }; |
| 257 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 258 | static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc) |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 259 | { |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 260 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 261 | struct s3c_irq_intc *intc = desc->irq_data.domain->host_data; |
| 262 | struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq]; |
| 263 | struct s3c_irq_intc *sub_intc = irq_data->sub_intc; |
| 264 | unsigned long src; |
| 265 | unsigned long msk; |
| 266 | unsigned int n; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 267 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 268 | chained_irq_enter(chip, desc); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 269 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 270 | src = __raw_readl(sub_intc->reg_pending); |
| 271 | msk = __raw_readl(sub_intc->reg_mask); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 272 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 273 | src &= ~msk; |
| 274 | src &= irq_data->sub_bits; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 275 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 276 | while (src) { |
| 277 | n = __ffs(src); |
| 278 | src &= ~(1 << n); |
| 279 | generic_handle_irq(irq_find_mapping(sub_intc->domain, n)); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 280 | } |
| 281 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 282 | chained_irq_exit(chip, desc); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 283 | } |
| 284 | |
Ben Dooks | 229fd8f | 2009-08-03 17:26:57 +0100 | [diff] [blame] | 285 | #ifdef CONFIG_FIQ |
| 286 | /** |
| 287 | * s3c24xx_set_fiq - set the FIQ routing |
| 288 | * @irq: IRQ number to route to FIQ on processor. |
| 289 | * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing. |
| 290 | * |
| 291 | * Change the state of the IRQ to FIQ routing depending on @irq and @on. If |
| 292 | * @on is true, the @irq is checked to see if it can be routed and the |
| 293 | * interrupt controller updated to route the IRQ. If @on is false, the FIQ |
| 294 | * routing is cleared, regardless of which @irq is specified. |
| 295 | */ |
| 296 | int s3c24xx_set_fiq(unsigned int irq, bool on) |
| 297 | { |
| 298 | u32 intmod; |
| 299 | unsigned offs; |
| 300 | |
| 301 | if (on) { |
| 302 | offs = irq - FIQ_START; |
| 303 | if (offs > 31) |
| 304 | return -EINVAL; |
| 305 | |
| 306 | intmod = 1 << offs; |
| 307 | } else { |
| 308 | intmod = 0; |
| 309 | } |
| 310 | |
| 311 | __raw_writel(intmod, S3C2410_INTMOD); |
| 312 | return 0; |
| 313 | } |
Ben Dooks | 0f13c82 | 2009-12-07 14:51:38 +0000 | [diff] [blame] | 314 | |
| 315 | EXPORT_SYMBOL_GPL(s3c24xx_set_fiq); |
Ben Dooks | 229fd8f | 2009-08-03 17:26:57 +0100 | [diff] [blame] | 316 | #endif |
| 317 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 318 | static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, |
| 319 | irq_hw_number_t hw) |
| 320 | { |
| 321 | struct s3c_irq_intc *intc = h->host_data; |
| 322 | struct s3c_irq_data *irq_data = &intc->irqs[hw]; |
| 323 | struct s3c_irq_intc *parent_intc; |
| 324 | struct s3c_irq_data *parent_irq_data; |
| 325 | unsigned int irqno; |
| 326 | |
| 327 | if (!intc) { |
| 328 | pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw); |
| 329 | return -EINVAL; |
| 330 | } |
| 331 | |
| 332 | if (!irq_data) { |
| 333 | pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw); |
| 334 | return -EINVAL; |
| 335 | } |
| 336 | |
| 337 | /* attach controller pointer to irq_data */ |
| 338 | irq_data->intc = intc; |
| 339 | |
| 340 | /* set handler and flags */ |
| 341 | switch (irq_data->type) { |
| 342 | case S3C_IRQTYPE_NONE: |
| 343 | return 0; |
| 344 | case S3C_IRQTYPE_EINT: |
| 345 | if (irq_data->parent_irq) |
| 346 | irq_set_chip_and_handler(virq, &s3c_irqext_chip, |
| 347 | handle_edge_irq); |
| 348 | else |
| 349 | irq_set_chip_and_handler(virq, &s3c_irq_eint0t4, |
| 350 | handle_edge_irq); |
| 351 | break; |
| 352 | case S3C_IRQTYPE_EDGE: |
Heiko Stuebner | 20f6c78 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 353 | if (irq_data->parent_irq || |
| 354 | intc->reg_pending == S3C2416_SRCPND2) |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 355 | irq_set_chip_and_handler(virq, &s3c_irq_level_chip, |
| 356 | handle_edge_irq); |
| 357 | else |
| 358 | irq_set_chip_and_handler(virq, &s3c_irq_chip, |
| 359 | handle_edge_irq); |
| 360 | break; |
| 361 | case S3C_IRQTYPE_LEVEL: |
| 362 | if (irq_data->parent_irq) |
| 363 | irq_set_chip_and_handler(virq, &s3c_irq_level_chip, |
| 364 | handle_level_irq); |
| 365 | else |
| 366 | irq_set_chip_and_handler(virq, &s3c_irq_chip, |
| 367 | handle_level_irq); |
| 368 | break; |
| 369 | default: |
| 370 | pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type); |
| 371 | return -EINVAL; |
| 372 | } |
| 373 | set_irq_flags(virq, IRQF_VALID); |
| 374 | |
| 375 | if (irq_data->parent_irq) { |
| 376 | parent_intc = intc->parent; |
| 377 | if (!parent_intc) { |
| 378 | pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n", |
| 379 | hw); |
| 380 | goto err; |
| 381 | } |
| 382 | |
| 383 | parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; |
| 384 | if (!irq_data) { |
| 385 | pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", |
| 386 | hw); |
| 387 | goto err; |
| 388 | } |
| 389 | |
| 390 | parent_irq_data->sub_intc = intc; |
| 391 | parent_irq_data->sub_bits |= (1UL << hw); |
| 392 | |
| 393 | /* attach the demuxer to the parent irq */ |
| 394 | irqno = irq_find_mapping(parent_intc->domain, |
| 395 | irq_data->parent_irq); |
| 396 | if (!irqno) { |
| 397 | pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n", |
| 398 | irq_data->parent_irq); |
| 399 | goto err; |
| 400 | } |
| 401 | irq_set_chained_handler(irqno, s3c_irq_demux); |
| 402 | } |
| 403 | |
| 404 | return 0; |
| 405 | |
| 406 | err: |
| 407 | set_irq_flags(virq, 0); |
| 408 | |
| 409 | /* the only error can result from bad mapping data*/ |
| 410 | return -EINVAL; |
| 411 | } |
| 412 | |
| 413 | static struct irq_domain_ops s3c24xx_irq_ops = { |
| 414 | .map = s3c24xx_irq_map, |
| 415 | .xlate = irq_domain_xlate_twocell, |
| 416 | }; |
| 417 | |
| 418 | static void s3c24xx_clear_intc(struct s3c_irq_intc *intc) |
| 419 | { |
| 420 | void __iomem *reg_source; |
| 421 | unsigned long pend; |
| 422 | unsigned long last; |
| 423 | int i; |
| 424 | |
| 425 | /* if intpnd is set, read the next pending irq from there */ |
| 426 | reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending; |
| 427 | |
| 428 | last = 0; |
| 429 | for (i = 0; i < 4; i++) { |
| 430 | pend = __raw_readl(reg_source); |
| 431 | |
| 432 | if (pend == 0 || pend == last) |
| 433 | break; |
| 434 | |
| 435 | __raw_writel(pend, intc->reg_pending); |
| 436 | if (intc->reg_intpnd) |
| 437 | __raw_writel(pend, intc->reg_intpnd); |
| 438 | |
| 439 | pr_info("irq: clearing pending status %08x\n", (int)pend); |
| 440 | last = pend; |
| 441 | } |
| 442 | } |
| 443 | |
| 444 | struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, |
| 445 | struct s3c_irq_data *irq_data, |
| 446 | struct s3c_irq_intc *parent, |
| 447 | unsigned long address) |
| 448 | { |
| 449 | struct s3c_irq_intc *intc; |
| 450 | void __iomem *base = (void *)0xf6000000; /* static mapping */ |
| 451 | int irq_num; |
| 452 | int irq_start; |
| 453 | int irq_offset; |
| 454 | int ret; |
| 455 | |
| 456 | intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); |
| 457 | if (!intc) |
| 458 | return ERR_PTR(-ENOMEM); |
| 459 | |
| 460 | intc->irqs = irq_data; |
| 461 | |
| 462 | if (parent) |
| 463 | intc->parent = parent; |
| 464 | |
| 465 | /* select the correct data for the controller. |
| 466 | * Need to hard code the irq num start and offset |
| 467 | * to preserve the static mapping for now |
| 468 | */ |
| 469 | switch (address) { |
| 470 | case 0x4a000000: |
| 471 | pr_debug("irq: found main intc\n"); |
| 472 | intc->reg_pending = base; |
| 473 | intc->reg_mask = base + 0x08; |
| 474 | intc->reg_intpnd = base + 0x10; |
| 475 | irq_num = 32; |
| 476 | irq_start = S3C2410_IRQ(0); |
| 477 | irq_offset = 0; |
| 478 | break; |
| 479 | case 0x4a000018: |
| 480 | pr_debug("irq: found subintc\n"); |
| 481 | intc->reg_pending = base + 0x18; |
| 482 | intc->reg_mask = base + 0x1c; |
| 483 | irq_num = 29; |
| 484 | irq_start = S3C2410_IRQSUB(0); |
| 485 | irq_offset = 0; |
| 486 | break; |
| 487 | case 0x4a000040: |
| 488 | pr_debug("irq: found intc2\n"); |
| 489 | intc->reg_pending = base + 0x40; |
| 490 | intc->reg_mask = base + 0x48; |
| 491 | intc->reg_intpnd = base + 0x50; |
| 492 | irq_num = 8; |
| 493 | irq_start = S3C2416_IRQ(0); |
| 494 | irq_offset = 0; |
| 495 | break; |
| 496 | case 0x560000a4: |
| 497 | pr_debug("irq: found eintc\n"); |
| 498 | base = (void *)0xfd000000; |
| 499 | |
| 500 | intc->reg_mask = base + 0xa4; |
| 501 | intc->reg_pending = base + 0x08; |
| 502 | irq_num = 20; |
| 503 | irq_start = S3C2410_IRQ(32); |
| 504 | irq_offset = 4; |
| 505 | break; |
| 506 | default: |
| 507 | pr_err("irq: unsupported controller address\n"); |
| 508 | ret = -EINVAL; |
| 509 | goto err; |
| 510 | } |
| 511 | |
| 512 | /* now that all the data is complete, init the irq-domain */ |
| 513 | s3c24xx_clear_intc(intc); |
| 514 | intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, |
| 515 | irq_offset, &s3c24xx_irq_ops, |
| 516 | intc); |
| 517 | if (!intc->domain) { |
| 518 | pr_err("irq: could not create irq-domain\n"); |
| 519 | ret = -EINVAL; |
| 520 | goto err; |
| 521 | } |
| 522 | |
| 523 | return intc; |
| 524 | |
| 525 | err: |
| 526 | kfree(intc); |
| 527 | return ERR_PTR(ret); |
| 528 | } |
Ben Dooks | 229fd8f | 2009-08-03 17:26:57 +0100 | [diff] [blame] | 529 | |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 530 | /* s3c24xx_init_irq |
| 531 | * |
| 532 | * Initialise S3C2410 IRQ system |
| 533 | */ |
| 534 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 535 | static struct s3c_irq_data init_base[32] = { |
| 536 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ |
| 537 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ |
| 538 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ |
| 539 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ |
| 540 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ |
| 541 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ |
| 542 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 543 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ |
| 544 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ |
| 545 | { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ |
| 546 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ |
| 547 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ |
| 548 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ |
| 549 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ |
| 550 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ |
| 551 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ |
| 552 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ |
| 553 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ |
| 554 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ |
| 555 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ |
| 556 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ |
| 557 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ |
| 558 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ |
| 559 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ |
| 560 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 561 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ |
| 562 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ |
| 563 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ |
| 564 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ |
| 565 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ |
| 566 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ |
| 567 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ |
| 568 | }; |
| 569 | |
| 570 | static struct s3c_irq_data init_eint[32] = { |
| 571 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 572 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 573 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 574 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 575 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ |
| 576 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ |
| 577 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ |
| 578 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ |
| 579 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ |
| 580 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ |
| 581 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ |
| 582 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ |
| 583 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ |
| 584 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ |
| 585 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ |
| 586 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ |
| 587 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ |
| 588 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ |
| 589 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ |
| 590 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ |
| 591 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ |
| 592 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ |
| 593 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ |
| 594 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ |
| 595 | }; |
| 596 | |
| 597 | static struct s3c_irq_data init_subint[32] = { |
| 598 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ |
| 599 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ |
| 600 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ |
| 601 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ |
| 602 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ |
| 603 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ |
| 604 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ |
| 605 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ |
| 606 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ |
| 607 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ |
| 608 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ |
| 609 | }; |
| 610 | |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 611 | void __init s3c24xx_init_irq(void) |
| 612 | { |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 613 | struct s3c_irq_intc *main_intc; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 614 | |
Ben Dooks | 229fd8f | 2009-08-03 17:26:57 +0100 | [diff] [blame] | 615 | #ifdef CONFIG_FIQ |
Shawn Guo | bc89663 | 2012-06-28 14:42:08 +0800 | [diff] [blame] | 616 | init_FIQ(FIQ_START); |
Ben Dooks | 229fd8f | 2009-08-03 17:26:57 +0100 | [diff] [blame] | 617 | #endif |
| 618 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 619 | main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000); |
| 620 | if (IS_ERR(main_intc)) { |
| 621 | pr_err("irq: could not create main interrupt controller\n"); |
| 622 | return; |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 623 | } |
| 624 | |
Heiko Stuebner | 1f629b7 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 625 | s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018); |
| 626 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); |
Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 627 | } |
Heiko Stuebner | ef602eb | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 628 | |
Heiko Stuebner | d3d5a2c | 2013-02-12 10:09:13 -0800 | [diff] [blame] | 629 | #ifdef CONFIG_CPU_S3C2412 |
| 630 | |
| 631 | #define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) |
| 632 | #define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0)))) |
| 633 | |
| 634 | /* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by |
| 635 | * having them turn up in both the INT* and the EINT* registers. Whilst |
| 636 | * both show the status, they both now need to be acked when the IRQs |
| 637 | * go off. |
| 638 | */ |
| 639 | |
| 640 | static void |
| 641 | s3c2412_irq_mask(struct irq_data *data) |
| 642 | { |
| 643 | unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); |
| 644 | unsigned long mask; |
| 645 | |
| 646 | mask = __raw_readl(S3C2410_INTMSK); |
| 647 | __raw_writel(mask | bitval, S3C2410_INTMSK); |
| 648 | |
| 649 | mask = __raw_readl(S3C2412_EINTMASK); |
| 650 | __raw_writel(mask | bitval, S3C2412_EINTMASK); |
| 651 | } |
| 652 | |
| 653 | static inline void |
| 654 | s3c2412_irq_ack(struct irq_data *data) |
| 655 | { |
| 656 | unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); |
| 657 | |
| 658 | __raw_writel(bitval, S3C2412_EINTPEND); |
| 659 | __raw_writel(bitval, S3C2410_SRCPND); |
| 660 | __raw_writel(bitval, S3C2410_INTPND); |
| 661 | } |
| 662 | |
| 663 | static inline void |
| 664 | s3c2412_irq_maskack(struct irq_data *data) |
| 665 | { |
| 666 | unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); |
| 667 | unsigned long mask; |
| 668 | |
| 669 | mask = __raw_readl(S3C2410_INTMSK); |
| 670 | __raw_writel(mask|bitval, S3C2410_INTMSK); |
| 671 | |
| 672 | mask = __raw_readl(S3C2412_EINTMASK); |
| 673 | __raw_writel(mask | bitval, S3C2412_EINTMASK); |
| 674 | |
| 675 | __raw_writel(bitval, S3C2412_EINTPEND); |
| 676 | __raw_writel(bitval, S3C2410_SRCPND); |
| 677 | __raw_writel(bitval, S3C2410_INTPND); |
| 678 | } |
| 679 | |
| 680 | static void |
| 681 | s3c2412_irq_unmask(struct irq_data *data) |
| 682 | { |
| 683 | unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); |
| 684 | unsigned long mask; |
| 685 | |
| 686 | mask = __raw_readl(S3C2412_EINTMASK); |
| 687 | __raw_writel(mask & ~bitval, S3C2412_EINTMASK); |
| 688 | |
| 689 | mask = __raw_readl(S3C2410_INTMSK); |
| 690 | __raw_writel(mask & ~bitval, S3C2410_INTMSK); |
| 691 | } |
| 692 | |
| 693 | static struct irq_chip s3c2412_irq_eint0t4 = { |
| 694 | .irq_ack = s3c2412_irq_ack, |
| 695 | .irq_mask = s3c2412_irq_mask, |
| 696 | .irq_unmask = s3c2412_irq_unmask, |
| 697 | .irq_set_wake = s3c_irq_wake, |
| 698 | .irq_set_type = s3c_irqext_type, |
| 699 | }; |
| 700 | |
| 701 | #define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0))) |
| 702 | |
| 703 | /* CF and SDI sub interrupts */ |
| 704 | |
| 705 | static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc) |
| 706 | { |
| 707 | unsigned int subsrc, submsk; |
| 708 | |
| 709 | subsrc = __raw_readl(S3C2410_SUBSRCPND); |
| 710 | submsk = __raw_readl(S3C2410_INTSUBMSK); |
| 711 | |
| 712 | subsrc &= ~submsk; |
| 713 | |
| 714 | if (subsrc & INTBIT(IRQ_S3C2412_SDI)) |
| 715 | generic_handle_irq(IRQ_S3C2412_SDI); |
| 716 | |
| 717 | if (subsrc & INTBIT(IRQ_S3C2412_CF)) |
| 718 | generic_handle_irq(IRQ_S3C2412_CF); |
| 719 | } |
| 720 | |
| 721 | #define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0)) |
| 722 | #define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF) |
| 723 | |
| 724 | static void s3c2412_irq_cfsdi_mask(struct irq_data *data) |
| 725 | { |
| 726 | s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI); |
| 727 | } |
| 728 | |
| 729 | static void s3c2412_irq_cfsdi_unmask(struct irq_data *data) |
| 730 | { |
| 731 | s3c_irqsub_unmask(data->irq, INTMSK_CFSDI); |
| 732 | } |
| 733 | |
| 734 | static void s3c2412_irq_cfsdi_ack(struct irq_data *data) |
| 735 | { |
| 736 | s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI); |
| 737 | } |
| 738 | |
| 739 | static struct irq_chip s3c2412_irq_cfsdi = { |
| 740 | .name = "s3c2412-cfsdi", |
| 741 | .irq_ack = s3c2412_irq_cfsdi_ack, |
| 742 | .irq_mask = s3c2412_irq_cfsdi_mask, |
| 743 | .irq_unmask = s3c2412_irq_cfsdi_unmask, |
| 744 | }; |
| 745 | |
Heiko Stuebner | 0da0993 | 2013-02-12 10:09:18 -0800 | [diff] [blame^] | 746 | void s3c2412_init_irq(void) |
Heiko Stuebner | d3d5a2c | 2013-02-12 10:09:13 -0800 | [diff] [blame] | 747 | { |
| 748 | unsigned int irqno; |
| 749 | |
Heiko Stuebner | 0da0993 | 2013-02-12 10:09:18 -0800 | [diff] [blame^] | 750 | s3c24xx_init_irq(); |
| 751 | |
Heiko Stuebner | d3d5a2c | 2013-02-12 10:09:13 -0800 | [diff] [blame] | 752 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { |
| 753 | irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4, |
| 754 | handle_edge_irq); |
| 755 | set_irq_flags(irqno, IRQF_VALID); |
| 756 | } |
| 757 | |
| 758 | /* add demux support for CF/SDI */ |
| 759 | |
| 760 | irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); |
| 761 | |
| 762 | for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { |
| 763 | irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi, |
| 764 | handle_level_irq); |
| 765 | set_irq_flags(irqno, IRQF_VALID); |
| 766 | } |
Heiko Stuebner | d3d5a2c | 2013-02-12 10:09:13 -0800 | [diff] [blame] | 767 | } |
Heiko Stuebner | d3d5a2c | 2013-02-12 10:09:13 -0800 | [diff] [blame] | 768 | #endif |
| 769 | |
Heiko Stuebner | ef602eb | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 770 | #ifdef CONFIG_CPU_S3C2416 |
Heiko Stuebner | 20f6c78 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 771 | static struct s3c_irq_data init_s3c2416base[32] = { |
| 772 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ |
| 773 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ |
| 774 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ |
| 775 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ |
| 776 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ |
| 777 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ |
| 778 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 779 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ |
| 780 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ |
| 781 | { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ |
| 782 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ |
| 783 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ |
| 784 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ |
| 785 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ |
| 786 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ |
| 787 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ |
| 788 | { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ |
| 789 | { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ |
| 790 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ |
| 791 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
| 792 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ |
| 793 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ |
| 794 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ |
| 795 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ |
| 796 | { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ |
| 797 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ |
| 798 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ |
| 799 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ |
| 800 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ |
| 801 | { .type = S3C_IRQTYPE_NONE, }, |
| 802 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ |
| 803 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ |
Heiko Stuebner | ef602eb | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 804 | }; |
| 805 | |
Heiko Stuebner | 20f6c78 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 806 | static struct s3c_irq_data init_s3c2416subint[32] = { |
| 807 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ |
| 808 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ |
| 809 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ |
| 810 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ |
| 811 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ |
| 812 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ |
| 813 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ |
| 814 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ |
| 815 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ |
| 816 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ |
| 817 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ |
| 818 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ |
| 819 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ |
| 820 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ |
| 821 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ |
| 822 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ |
| 823 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ |
| 824 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ |
| 825 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ |
| 826 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ |
| 827 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ |
| 828 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ |
| 829 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ |
| 830 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ |
| 831 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ |
| 832 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ |
| 833 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ |
| 834 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ |
| 835 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ |
Heiko Stuebner | ef602eb | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 836 | }; |
| 837 | |
Heiko Stuebner | 20f6c78 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 838 | static struct s3c_irq_data init_s3c2416_second[32] = { |
| 839 | { .type = S3C_IRQTYPE_EDGE }, /* 2D */ |
| 840 | { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */ |
| 841 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ |
| 842 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ |
| 843 | { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */ |
| 844 | { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */ |
| 845 | { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */ |
| 846 | { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */ |
Heiko Stuebner | ef602eb | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 847 | }; |
| 848 | |
Heiko Stuebner | 4a282dd | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 849 | void __init s3c2416_init_irq(void) |
Heiko Stuebner | ef602eb | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 850 | { |
Heiko Stuebner | 20f6c78 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 851 | struct s3c_irq_intc *main_intc; |
| 852 | |
Heiko Stuebner | 4a282dd | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 853 | pr_info("S3C2416: IRQ Support\n"); |
| 854 | |
Heiko Stuebner | 20f6c78 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 855 | #ifdef CONFIG_FIQ |
| 856 | init_FIQ(FIQ_START); |
| 857 | #endif |
Heiko Stuebner | ef602eb | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 858 | |
Heiko Stuebner | 20f6c78 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 859 | main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000); |
| 860 | if (IS_ERR(main_intc)) { |
| 861 | pr_err("irq: could not create main interrupt controller\n"); |
| 862 | return; |
| 863 | } |
Heiko Stuebner | ef602eb | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 864 | |
Heiko Stuebner | 20f6c78 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 865 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); |
| 866 | s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018); |
Heiko Stuebner | ef602eb | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 867 | |
Heiko Stuebner | 20f6c78 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 868 | s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040); |
Heiko Stuebner | ef602eb | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 869 | } |
| 870 | |
Heiko Stuebner | ef602eb | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 871 | #endif |
Heiko Stuebner | 6b62891 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 872 | |
Heiko Stuebner | f030167 | 2013-02-12 09:59:35 -0800 | [diff] [blame] | 873 | #ifdef CONFIG_CPU_S3C2440 |
| 874 | static struct s3c_irq_data init_s3c2440base[32] = { |
| 875 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ |
| 876 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ |
| 877 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ |
| 878 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ |
| 879 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ |
| 880 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ |
| 881 | { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ |
| 882 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ |
| 883 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ |
| 884 | { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ |
| 885 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ |
| 886 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ |
| 887 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ |
| 888 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ |
| 889 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ |
| 890 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ |
| 891 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ |
| 892 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ |
| 893 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ |
| 894 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ |
| 895 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ |
| 896 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ |
| 897 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ |
| 898 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ |
| 899 | { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ |
| 900 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ |
| 901 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ |
| 902 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ |
| 903 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ |
| 904 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ |
| 905 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ |
| 906 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ |
Heiko Stuebner | 6f8d7ea | 2013-02-12 09:59:17 -0800 | [diff] [blame] | 907 | }; |
| 908 | |
Heiko Stuebner | f030167 | 2013-02-12 09:59:35 -0800 | [diff] [blame] | 909 | static struct s3c_irq_data init_s3c2440subint[32] = { |
| 910 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ |
| 911 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ |
| 912 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ |
| 913 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ |
| 914 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ |
| 915 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ |
| 916 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ |
| 917 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ |
| 918 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ |
| 919 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ |
| 920 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ |
| 921 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* TC */ |
| 922 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* ADC */ |
| 923 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ |
| 924 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ |
Heiko Stuebner | 2286cf4 | 2013-02-12 09:59:24 -0800 | [diff] [blame] | 925 | }; |
| 926 | |
Heiko Stuebner | 7cefed5 | 2013-02-12 09:59:27 -0800 | [diff] [blame] | 927 | void __init s3c2440_init_irq(void) |
Heiko Stuebner | 2286cf4 | 2013-02-12 09:59:24 -0800 | [diff] [blame] | 928 | { |
Heiko Stuebner | f030167 | 2013-02-12 09:59:35 -0800 | [diff] [blame] | 929 | struct s3c_irq_intc *main_intc; |
Heiko Stuebner | 2286cf4 | 2013-02-12 09:59:24 -0800 | [diff] [blame] | 930 | |
Heiko Stuebner | f030167 | 2013-02-12 09:59:35 -0800 | [diff] [blame] | 931 | pr_info("S3C2440: IRQ Support\n"); |
Heiko Stuebner | 2286cf4 | 2013-02-12 09:59:24 -0800 | [diff] [blame] | 932 | |
Heiko Stuebner | f030167 | 2013-02-12 09:59:35 -0800 | [diff] [blame] | 933 | #ifdef CONFIG_FIQ |
| 934 | init_FIQ(FIQ_START); |
| 935 | #endif |
Heiko Stuebner | ce6c164 | 2013-02-12 09:59:20 -0800 | [diff] [blame] | 936 | |
Heiko Stuebner | f030167 | 2013-02-12 09:59:35 -0800 | [diff] [blame] | 937 | main_intc = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL, 0x4a000000); |
| 938 | if (IS_ERR(main_intc)) { |
| 939 | pr_err("irq: could not create main interrupt controller\n"); |
| 940 | return; |
Heiko Stuebner | 6f8d7ea | 2013-02-12 09:59:17 -0800 | [diff] [blame] | 941 | } |
Heiko Stuebner | 7cefed5 | 2013-02-12 09:59:27 -0800 | [diff] [blame] | 942 | |
Heiko Stuebner | f030167 | 2013-02-12 09:59:35 -0800 | [diff] [blame] | 943 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); |
| 944 | s3c24xx_init_intc(NULL, &init_s3c2440subint[0], main_intc, 0x4a000018); |
Heiko Stuebner | 6f8d7ea | 2013-02-12 09:59:17 -0800 | [diff] [blame] | 945 | } |
Heiko Stuebner | ce6c164 | 2013-02-12 09:59:20 -0800 | [diff] [blame] | 946 | #endif |
Heiko Stuebner | 6f8d7ea | 2013-02-12 09:59:17 -0800 | [diff] [blame] | 947 | |
Heiko Stuebner | ce6c164 | 2013-02-12 09:59:20 -0800 | [diff] [blame] | 948 | #ifdef CONFIG_CPU_S3C2442 |
Heiko Stuebner | 70644ad | 2013-02-12 09:59:31 -0800 | [diff] [blame] | 949 | static struct s3c_irq_data init_s3c2442base[32] = { |
| 950 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ |
| 951 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ |
| 952 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ |
| 953 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ |
| 954 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ |
| 955 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ |
| 956 | { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ |
| 957 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ |
| 958 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ |
| 959 | { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ |
| 960 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ |
| 961 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ |
| 962 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ |
| 963 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ |
| 964 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ |
| 965 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ |
| 966 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ |
| 967 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ |
| 968 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ |
| 969 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ |
| 970 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ |
| 971 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ |
| 972 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ |
| 973 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ |
| 974 | { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ |
| 975 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ |
| 976 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ |
| 977 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ |
| 978 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ |
| 979 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ |
| 980 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ |
| 981 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ |
| 982 | }; |
| 983 | |
| 984 | static struct s3c_irq_data init_s3c2442subint[32] = { |
| 985 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ |
| 986 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ |
| 987 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ |
| 988 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ |
| 989 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ |
| 990 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ |
| 991 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ |
| 992 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ |
| 993 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ |
| 994 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ |
| 995 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ |
| 996 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* TC */ |
| 997 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* ADC */ |
| 998 | }; |
| 999 | |
Heiko Stuebner | ce6c164 | 2013-02-12 09:59:20 -0800 | [diff] [blame] | 1000 | void __init s3c2442_init_irq(void) |
Heiko Stuebner | 6f8d7ea | 2013-02-12 09:59:17 -0800 | [diff] [blame] | 1001 | { |
Heiko Stuebner | 70644ad | 2013-02-12 09:59:31 -0800 | [diff] [blame] | 1002 | struct s3c_irq_intc *main_intc; |
Heiko Stuebner | ce6c164 | 2013-02-12 09:59:20 -0800 | [diff] [blame] | 1003 | |
Heiko Stuebner | 70644ad | 2013-02-12 09:59:31 -0800 | [diff] [blame] | 1004 | pr_info("S3C2442: IRQ Support\n"); |
Heiko Stuebner | ce6c164 | 2013-02-12 09:59:20 -0800 | [diff] [blame] | 1005 | |
Heiko Stuebner | 70644ad | 2013-02-12 09:59:31 -0800 | [diff] [blame] | 1006 | #ifdef CONFIG_FIQ |
| 1007 | init_FIQ(FIQ_START); |
| 1008 | #endif |
Heiko Stuebner | ce6c164 | 2013-02-12 09:59:20 -0800 | [diff] [blame] | 1009 | |
Heiko Stuebner | 70644ad | 2013-02-12 09:59:31 -0800 | [diff] [blame] | 1010 | main_intc = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, 0x4a000000); |
| 1011 | if (IS_ERR(main_intc)) { |
| 1012 | pr_err("irq: could not create main interrupt controller\n"); |
| 1013 | return; |
Heiko Stuebner | ce6c164 | 2013-02-12 09:59:20 -0800 | [diff] [blame] | 1014 | } |
Heiko Stuebner | 70644ad | 2013-02-12 09:59:31 -0800 | [diff] [blame] | 1015 | |
| 1016 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); |
| 1017 | s3c24xx_init_intc(NULL, &init_s3c2442subint[0], main_intc, 0x4a000018); |
Heiko Stuebner | 6f8d7ea | 2013-02-12 09:59:17 -0800 | [diff] [blame] | 1018 | } |
Heiko Stuebner | ce6c164 | 2013-02-12 09:59:20 -0800 | [diff] [blame] | 1019 | #endif |
Heiko Stuebner | 6f8d7ea | 2013-02-12 09:59:17 -0800 | [diff] [blame] | 1020 | |
Heiko Stuebner | 6b62891 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 1021 | #ifdef CONFIG_CPU_S3C2443 |
Heiko Stuebner | f44ddba | 2013-01-29 10:25:23 -0800 | [diff] [blame] | 1022 | static struct s3c_irq_data init_s3c2443base[32] = { |
| 1023 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ |
| 1024 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ |
| 1025 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ |
| 1026 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ |
| 1027 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ |
| 1028 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ |
| 1029 | { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ |
| 1030 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ |
| 1031 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ |
| 1032 | { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ |
| 1033 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ |
| 1034 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ |
| 1035 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ |
| 1036 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ |
| 1037 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ |
| 1038 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ |
| 1039 | { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ |
| 1040 | { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ |
| 1041 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ |
| 1042 | { .type = S3C_IRQTYPE_EDGE, }, /* CFON */ |
| 1043 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ |
| 1044 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ |
| 1045 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ |
| 1046 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ |
| 1047 | { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ |
| 1048 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ |
| 1049 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ |
| 1050 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ |
| 1051 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ |
| 1052 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ |
| 1053 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ |
| 1054 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ |
Heiko Stuebner | 6b62891 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 1055 | }; |
| 1056 | |
Heiko Stuebner | 6b62891 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 1057 | |
Heiko Stuebner | f44ddba | 2013-01-29 10:25:23 -0800 | [diff] [blame] | 1058 | static struct s3c_irq_data init_s3c2443subint[32] = { |
| 1059 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ |
| 1060 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ |
| 1061 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ |
| 1062 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ |
| 1063 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ |
| 1064 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ |
| 1065 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ |
| 1066 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ |
| 1067 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ |
| 1068 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ |
| 1069 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ |
| 1070 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ |
| 1071 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ |
| 1072 | { .type = S3C_IRQTYPE_NONE }, /* reserved */ |
| 1073 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */ |
| 1074 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ |
| 1075 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ |
| 1076 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ |
| 1077 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ |
| 1078 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ |
| 1079 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ |
| 1080 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ |
| 1081 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ |
| 1082 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ |
| 1083 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ |
| 1084 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ |
| 1085 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ |
| 1086 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ |
| 1087 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ |
Heiko Stuebner | 6b62891 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 1088 | }; |
| 1089 | |
Heiko Stuebner | b499b7a | 2013-01-29 10:25:23 -0800 | [diff] [blame] | 1090 | void __init s3c2443_init_irq(void) |
Heiko Stuebner | 6b62891 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 1091 | { |
Heiko Stuebner | f44ddba | 2013-01-29 10:25:23 -0800 | [diff] [blame] | 1092 | struct s3c_irq_intc *main_intc; |
| 1093 | |
Heiko Stuebner | b499b7a | 2013-01-29 10:25:23 -0800 | [diff] [blame] | 1094 | pr_info("S3C2443: IRQ Support\n"); |
| 1095 | |
Heiko Stuebner | f44ddba | 2013-01-29 10:25:23 -0800 | [diff] [blame] | 1096 | #ifdef CONFIG_FIQ |
| 1097 | init_FIQ(FIQ_START); |
| 1098 | #endif |
Heiko Stuebner | 6b62891 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 1099 | |
Heiko Stuebner | f44ddba | 2013-01-29 10:25:23 -0800 | [diff] [blame] | 1100 | main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000); |
| 1101 | if (IS_ERR(main_intc)) { |
| 1102 | pr_err("irq: could not create main interrupt controller\n"); |
| 1103 | return; |
| 1104 | } |
Heiko Stuebner | 6b62891 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 1105 | |
Heiko Stuebner | f44ddba | 2013-01-29 10:25:23 -0800 | [diff] [blame] | 1106 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); |
| 1107 | s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018); |
Heiko Stuebner | 6b62891 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 1108 | } |
Heiko Stuebner | 6b62891 | 2013-01-29 10:25:22 -0800 | [diff] [blame] | 1109 | #endif |