H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_I8259_H |
| 2 | #define _ASM_X86_I8259_H |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | |
David P. Reed | bc0a733 | 2008-02-18 13:58:34 -0500 | [diff] [blame] | 4 | #include <linux/delay.h> |
| 5 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | extern unsigned int cached_irq_mask; |
| 7 | |
Joe Perches | ace4fdb | 2008-03-23 01:02:19 -0700 | [diff] [blame] | 8 | #define __byte(x, y) (((unsigned char *)&(y))[x]) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | #define cached_master_mask (__byte(0, cached_irq_mask)) |
| 10 | #define cached_slave_mask (__byte(1, cached_irq_mask)) |
| 11 | |
Thomas Gleixner | f20ebee | 2008-01-30 13:30:29 +0100 | [diff] [blame] | 12 | /* i8259A PIC registers */ |
| 13 | #define PIC_MASTER_CMD 0x20 |
| 14 | #define PIC_MASTER_IMR 0x21 |
| 15 | #define PIC_MASTER_ISR PIC_MASTER_CMD |
| 16 | #define PIC_MASTER_POLL PIC_MASTER_ISR |
| 17 | #define PIC_MASTER_OCW3 PIC_MASTER_ISR |
| 18 | #define PIC_SLAVE_CMD 0xa0 |
| 19 | #define PIC_SLAVE_IMR 0xa1 |
| 20 | |
| 21 | /* i8259A PIC related value */ |
| 22 | #define PIC_CASCADE_IR 2 |
| 23 | #define MASTER_ICW4_DEFAULT 0x01 |
| 24 | #define SLAVE_ICW4_DEFAULT 0x01 |
| 25 | #define PIC_ICW4_AEOI 2 |
| 26 | |
Thomas Gleixner | 5619c28 | 2009-07-25 18:35:11 +0200 | [diff] [blame] | 27 | extern raw_spinlock_t i8259A_lock; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
David P. Reed | bc0a733 | 2008-02-18 13:58:34 -0500 | [diff] [blame] | 29 | /* the PIC may need a careful delay on some platforms, hence specific calls */ |
| 30 | static inline unsigned char inb_pic(unsigned int port) |
| 31 | { |
| 32 | unsigned char value = inb(port); |
| 33 | |
| 34 | /* |
| 35 | * delay for some accesses to PIC on motherboard or in chipset |
| 36 | * must be at least one microsecond, so be safe here: |
| 37 | */ |
| 38 | udelay(2); |
| 39 | |
| 40 | return value; |
| 41 | } |
| 42 | |
| 43 | static inline void outb_pic(unsigned char value, unsigned int port) |
| 44 | { |
| 45 | outb(value, port); |
| 46 | /* |
| 47 | * delay for some accesses to PIC on motherboard or in chipset |
| 48 | * must be at least one microsecond, so be safe here: |
| 49 | */ |
| 50 | udelay(2); |
| 51 | } |
Alan Cox | 466eed2 | 2008-01-30 13:33:14 +0100 | [diff] [blame] | 52 | |
Pavel Machek | 40bd217 | 2008-05-21 11:44:02 +0200 | [diff] [blame] | 53 | extern struct irq_chip i8259A_chip; |
| 54 | |
Jacob Pan | ef35486 | 2009-11-09 11:24:14 -0800 | [diff] [blame] | 55 | struct legacy_pic { |
| 56 | int nr_legacy_irqs; |
| 57 | struct irq_chip *chip; |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame^] | 58 | void (*mask)(unsigned int irq); |
| 59 | void (*unmask)(unsigned int irq); |
Jacob Pan | ef35486 | 2009-11-09 11:24:14 -0800 | [diff] [blame] | 60 | void (*mask_all)(void); |
| 61 | void (*restore_mask)(void); |
| 62 | void (*init)(int auto_eoi); |
| 63 | int (*irq_pending)(unsigned int irq); |
| 64 | void (*make_irq)(unsigned int irq); |
| 65 | }; |
| 66 | |
| 67 | extern struct legacy_pic *legacy_pic; |
| 68 | extern struct legacy_pic null_legacy_pic; |
| 69 | |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 70 | #endif /* _ASM_X86_I8259_H */ |