Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC |
| 3 | * |
| 4 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
| 5 | * |
| 6 | * based on GPL'ed 2.6 kernel sources |
| 7 | * (c) Marvell International Ltd. |
| 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
| 14 | #include "skeleton.dtsi" |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 15 | #include <dt-bindings/clock/berlin2.h> |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 17 | |
| 18 | / { |
| 19 | model = "Marvell Armada 1500-mini (BG2CD) SoC"; |
| 20 | compatible = "marvell,berlin2cd", "marvell,berlin"; |
| 21 | |
| 22 | cpus { |
| 23 | #address-cells = <1>; |
| 24 | #size-cells = <0>; |
| 25 | |
| 26 | cpu@0 { |
| 27 | compatible = "arm,cortex-a9"; |
| 28 | device_type = "cpu"; |
| 29 | next-level-cache = <&l2>; |
| 30 | reg = <0>; |
| 31 | }; |
| 32 | }; |
| 33 | |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 34 | refclk: oscillator { |
| 35 | compatible = "fixed-clock"; |
| 36 | #clock-cells = <0>; |
| 37 | clock-frequency = <25000000>; |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 38 | }; |
| 39 | |
| 40 | soc { |
| 41 | compatible = "simple-bus"; |
| 42 | #address-cells = <1>; |
| 43 | #size-cells = <1>; |
| 44 | interrupt-parent = <&gic>; |
| 45 | |
| 46 | ranges = <0 0xf7000000 0x1000000>; |
| 47 | |
Jisheng Zhang | d4ce804 | 2014-12-26 16:57:59 +0800 | [diff] [blame] | 48 | pmu { |
| 49 | compatible = "arm,cortex-a9-pmu"; |
| 50 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 51 | }; |
| 52 | |
Sebastian Hesselbarth | 652538c | 2014-05-20 16:48:10 +0200 | [diff] [blame] | 53 | sdhci0: sdhci@ab0000 { |
| 54 | compatible = "mrvl,pxav3-mmc"; |
| 55 | reg = <0xab0000 0x200>; |
| 56 | clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; |
| 57 | clock-names = "io", "core"; |
| 58 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| 59 | status = "disabled"; |
| 60 | }; |
| 61 | |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 62 | l2: l2-cache-controller@ac0000 { |
| 63 | compatible = "arm,pl310-cache"; |
| 64 | reg = <0xac0000 0x1000>; |
| 65 | cache-unified; |
| 66 | cache-level = <2>; |
| 67 | }; |
| 68 | |
| 69 | gic: interrupt-controller@ad1000 { |
| 70 | compatible = "arm,cortex-a9-gic"; |
| 71 | reg = <0xad1000 0x1000>, <0xad0100 0x0100>; |
| 72 | interrupt-controller; |
| 73 | #interrupt-cells = <3>; |
| 74 | }; |
| 75 | |
| 76 | local-timer@ad0600 { |
| 77 | compatible = "arm,cortex-a9-twd-timer"; |
| 78 | reg = <0xad0600 0x20>; |
Jisheng Zhang | 2356d2f | 2014-12-26 16:58:00 +0800 | [diff] [blame] | 79 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 80 | clocks = <&chip CLKID_TWD>; |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 81 | }; |
| 82 | |
Sebastian Hesselbarth | e802b3a | 2014-11-17 14:35:46 +0100 | [diff] [blame] | 83 | usb_phy0: usb-phy@b74000 { |
| 84 | compatible = "marvell,berlin2cd-usb-phy"; |
| 85 | reg = <0xb74000 0x128>; |
| 86 | #phy-cells = <0>; |
Antoine Tenart | 4322572 | 2015-05-16 00:50:40 +0200 | [diff] [blame^] | 87 | resets = <&chip_rst 0x178 23>; |
Sebastian Hesselbarth | e802b3a | 2014-11-17 14:35:46 +0100 | [diff] [blame] | 88 | status = "disabled"; |
| 89 | }; |
| 90 | |
| 91 | usb_phy1: usb-phy@b78000 { |
| 92 | compatible = "marvell,berlin2cd-usb-phy"; |
| 93 | reg = <0xb78000 0x128>; |
| 94 | #phy-cells = <0>; |
Antoine Tenart | 4322572 | 2015-05-16 00:50:40 +0200 | [diff] [blame^] | 95 | resets = <&chip_rst 0x178 24>; |
Sebastian Hesselbarth | e802b3a | 2014-11-17 14:35:46 +0100 | [diff] [blame] | 96 | status = "disabled"; |
| 97 | }; |
| 98 | |
Sebastian Hesselbarth | 631338a | 2014-10-22 20:26:50 +0200 | [diff] [blame] | 99 | eth1: ethernet@b90000 { |
| 100 | compatible = "marvell,pxa168-eth"; |
| 101 | reg = <0xb90000 0x10000>; |
| 102 | clocks = <&chip CLKID_GETH1>; |
| 103 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| 104 | /* set by bootloader */ |
| 105 | local-mac-address = [00 00 00 00 00 00]; |
| 106 | #address-cells = <1>; |
| 107 | #size-cells = <0>; |
| 108 | phy-connection-type = "mii"; |
| 109 | phy-handle = <ðphy1>; |
| 110 | status = "disabled"; |
| 111 | |
| 112 | ethphy1: ethernet-phy@0 { |
| 113 | reg = <0>; |
| 114 | }; |
| 115 | }; |
| 116 | |
| 117 | eth0: ethernet@e50000 { |
| 118 | compatible = "marvell,pxa168-eth"; |
| 119 | reg = <0xe50000 0x10000>; |
| 120 | clocks = <&chip CLKID_GETH0>; |
| 121 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| 122 | /* set by bootloader */ |
| 123 | local-mac-address = [00 00 00 00 00 00]; |
| 124 | #address-cells = <1>; |
| 125 | #size-cells = <0>; |
| 126 | phy-connection-type = "mii"; |
| 127 | phy-handle = <ðphy0>; |
| 128 | status = "disabled"; |
| 129 | |
| 130 | ethphy0: ethernet-phy@0 { |
| 131 | reg = <0>; |
| 132 | }; |
| 133 | }; |
| 134 | |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 135 | apb@e80000 { |
| 136 | compatible = "simple-bus"; |
| 137 | #address-cells = <1>; |
| 138 | #size-cells = <1>; |
| 139 | |
| 140 | ranges = <0 0xe80000 0x10000>; |
| 141 | interrupt-parent = <&aic>; |
| 142 | |
Antoine Tenart | c920a66 | 2014-04-17 10:45:29 +0200 | [diff] [blame] | 143 | gpio0: gpio@0400 { |
| 144 | compatible = "snps,dw-apb-gpio"; |
| 145 | reg = <0x0400 0x400>; |
| 146 | #address-cells = <1>; |
| 147 | #size-cells = <0>; |
| 148 | |
| 149 | porta: gpio-port@0 { |
| 150 | compatible = "snps,dw-apb-gpio-port"; |
| 151 | gpio-controller; |
| 152 | #gpio-cells = <2>; |
| 153 | snps,nr-gpios = <8>; |
| 154 | reg = <0>; |
| 155 | interrupt-controller; |
| 156 | #interrupt-cells = <2>; |
| 157 | interrupts = <0>; |
| 158 | }; |
| 159 | }; |
| 160 | |
| 161 | gpio1: gpio@0800 { |
| 162 | compatible = "snps,dw-apb-gpio"; |
| 163 | reg = <0x0800 0x400>; |
| 164 | #address-cells = <1>; |
| 165 | #size-cells = <0>; |
| 166 | |
| 167 | portb: gpio-port@1 { |
| 168 | compatible = "snps,dw-apb-gpio-port"; |
| 169 | gpio-controller; |
| 170 | #gpio-cells = <2>; |
| 171 | snps,nr-gpios = <8>; |
| 172 | reg = <0>; |
| 173 | interrupt-controller; |
| 174 | #interrupt-cells = <2>; |
| 175 | interrupts = <1>; |
| 176 | }; |
| 177 | }; |
| 178 | |
| 179 | gpio2: gpio@0c00 { |
| 180 | compatible = "snps,dw-apb-gpio"; |
| 181 | reg = <0x0c00 0x400>; |
| 182 | #address-cells = <1>; |
| 183 | #size-cells = <0>; |
| 184 | |
| 185 | portc: gpio-port@2 { |
| 186 | compatible = "snps,dw-apb-gpio-port"; |
| 187 | gpio-controller; |
| 188 | #gpio-cells = <2>; |
| 189 | snps,nr-gpios = <8>; |
| 190 | reg = <0>; |
| 191 | interrupt-controller; |
| 192 | #interrupt-cells = <2>; |
| 193 | interrupts = <2>; |
| 194 | }; |
| 195 | }; |
| 196 | |
| 197 | gpio3: gpio@1000 { |
| 198 | compatible = "snps,dw-apb-gpio"; |
| 199 | reg = <0x1000 0x400>; |
| 200 | #address-cells = <1>; |
| 201 | #size-cells = <0>; |
| 202 | |
| 203 | portd: gpio-port@3 { |
| 204 | compatible = "snps,dw-apb-gpio-port"; |
| 205 | gpio-controller; |
| 206 | #gpio-cells = <2>; |
| 207 | snps,nr-gpios = <8>; |
| 208 | reg = <0>; |
| 209 | interrupt-controller; |
| 210 | #interrupt-cells = <2>; |
| 211 | interrupts = <3>; |
| 212 | }; |
| 213 | }; |
| 214 | |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 215 | timer0: timer@2c00 { |
| 216 | compatible = "snps,dw-apb-timer"; |
| 217 | reg = <0x2c00 0x14>; |
| 218 | interrupts = <8>; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 219 | clocks = <&chip CLKID_CFG>; |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 220 | clock-names = "timer"; |
| 221 | status = "okay"; |
| 222 | }; |
| 223 | |
| 224 | timer1: timer@2c14 { |
| 225 | compatible = "snps,dw-apb-timer"; |
| 226 | reg = <0x2c14 0x14>; |
| 227 | interrupts = <9>; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 228 | clocks = <&chip CLKID_CFG>; |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 229 | clock-names = "timer"; |
| 230 | status = "okay"; |
| 231 | }; |
| 232 | |
| 233 | timer2: timer@2c28 { |
| 234 | compatible = "snps,dw-apb-timer"; |
| 235 | reg = <0x2c28 0x14>; |
| 236 | interrupts = <10>; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 237 | clocks = <&chip CLKID_CFG>; |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 238 | clock-names = "timer"; |
| 239 | status = "disabled"; |
| 240 | }; |
| 241 | |
| 242 | timer3: timer@2c3c { |
| 243 | compatible = "snps,dw-apb-timer"; |
| 244 | reg = <0x2c3c 0x14>; |
| 245 | interrupts = <11>; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 246 | clocks = <&chip CLKID_CFG>; |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 247 | clock-names = "timer"; |
| 248 | status = "disabled"; |
| 249 | }; |
| 250 | |
| 251 | timer4: timer@2c50 { |
| 252 | compatible = "snps,dw-apb-timer"; |
| 253 | reg = <0x2c50 0x14>; |
| 254 | interrupts = <12>; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 255 | clocks = <&chip CLKID_CFG>; |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 256 | clock-names = "timer"; |
| 257 | status = "disabled"; |
| 258 | }; |
| 259 | |
| 260 | timer5: timer@2c64 { |
| 261 | compatible = "snps,dw-apb-timer"; |
| 262 | reg = <0x2c64 0x14>; |
| 263 | interrupts = <13>; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 264 | clocks = <&chip CLKID_CFG>; |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 265 | clock-names = "timer"; |
| 266 | status = "disabled"; |
| 267 | }; |
| 268 | |
| 269 | timer6: timer@2c78 { |
| 270 | compatible = "snps,dw-apb-timer"; |
| 271 | reg = <0x2c78 0x14>; |
| 272 | interrupts = <14>; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 273 | clocks = <&chip CLKID_CFG>; |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 274 | clock-names = "timer"; |
| 275 | status = "disabled"; |
| 276 | }; |
| 277 | |
| 278 | timer7: timer@2c8c { |
| 279 | compatible = "snps,dw-apb-timer"; |
| 280 | reg = <0x2c8c 0x14>; |
| 281 | interrupts = <15>; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 282 | clocks = <&chip CLKID_CFG>; |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 283 | clock-names = "timer"; |
| 284 | status = "disabled"; |
| 285 | }; |
| 286 | |
| 287 | aic: interrupt-controller@3000 { |
| 288 | compatible = "snps,dw-apb-ictl"; |
| 289 | reg = <0x3000 0xc00>; |
| 290 | interrupt-controller; |
| 291 | #interrupt-cells = <1>; |
| 292 | interrupt-parent = <&gic>; |
| 293 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| 294 | }; |
| 295 | }; |
| 296 | |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 297 | chip: chip-control@ea0000 { |
Antoine Tenart | ffcc33a | 2015-05-16 00:30:15 +0200 | [diff] [blame] | 298 | compatible = "marvell,berlin2cd-chip-ctrl", "simple-mfd", "syscon"; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 299 | #clock-cells = <1>; |
| 300 | reg = <0xea0000 0x400>; |
| 301 | clocks = <&refclk>; |
| 302 | clock-names = "refclk"; |
Antoine Tenart | 50cc24f | 2014-05-18 20:15:57 +0200 | [diff] [blame] | 303 | |
| 304 | uart0_pmux: uart0-pmux { |
| 305 | groups = "G6"; |
| 306 | function = "uart0"; |
| 307 | }; |
Antoine Tenart | 4322572 | 2015-05-16 00:50:40 +0200 | [diff] [blame^] | 308 | |
| 309 | chip_rst: reset { |
| 310 | compatible = "marvell,berlin2-reset"; |
| 311 | #reset-cells = <2>; |
| 312 | }; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 313 | }; |
| 314 | |
Sebastian Hesselbarth | e802b3a | 2014-11-17 14:35:46 +0100 | [diff] [blame] | 315 | usb0: usb@ed0000 { |
| 316 | compatible = "chipidea,usb2"; |
| 317 | reg = <0xed0000 0x200>; |
| 318 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 319 | clocks = <&chip CLKID_USB0>; |
| 320 | phys = <&usb_phy0>; |
| 321 | phy-names = "usb-phy"; |
| 322 | status = "disabled"; |
| 323 | }; |
| 324 | |
| 325 | usb1: usb@ee0000 { |
| 326 | compatible = "chipidea,usb2"; |
| 327 | reg = <0xee0000 0x200>; |
| 328 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| 329 | clocks = <&chip CLKID_USB1>; |
| 330 | phys = <&usb_phy1>; |
| 331 | phy-names = "usb-phy"; |
| 332 | status = "disabled"; |
| 333 | }; |
| 334 | |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 335 | apb@fc0000 { |
| 336 | compatible = "simple-bus"; |
| 337 | #address-cells = <1>; |
| 338 | #size-cells = <1>; |
| 339 | |
| 340 | ranges = <0 0xfc0000 0x10000>; |
| 341 | interrupt-parent = <&sic>; |
| 342 | |
Antoine Tenart | c920a66 | 2014-04-17 10:45:29 +0200 | [diff] [blame] | 343 | sm_gpio1: gpio@5000 { |
| 344 | compatible = "snps,dw-apb-gpio"; |
| 345 | reg = <0x5000 0x400>; |
| 346 | #address-cells = <1>; |
| 347 | #size-cells = <0>; |
| 348 | |
| 349 | portf: gpio-port@5 { |
| 350 | compatible = "snps,dw-apb-gpio-port"; |
| 351 | gpio-controller; |
| 352 | #gpio-cells = <2>; |
| 353 | snps,nr-gpios = <8>; |
| 354 | reg = <0>; |
| 355 | }; |
| 356 | }; |
| 357 | |
| 358 | sm_gpio0: gpio@c000 { |
| 359 | compatible = "snps,dw-apb-gpio"; |
| 360 | reg = <0xc000 0x400>; |
| 361 | #address-cells = <1>; |
| 362 | #size-cells = <0>; |
| 363 | |
| 364 | porte: gpio-port@4 { |
| 365 | compatible = "snps,dw-apb-gpio-port"; |
| 366 | gpio-controller; |
| 367 | #gpio-cells = <2>; |
| 368 | snps,nr-gpios = <8>; |
| 369 | reg = <0>; |
| 370 | }; |
| 371 | }; |
| 372 | |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 373 | uart0: serial@9000 { |
| 374 | compatible = "snps,dw-apb-uart"; |
| 375 | reg = <0x9000 0x100>; |
| 376 | reg-shift = <2>; |
| 377 | reg-io-width = <1>; |
| 378 | interrupts = <8>; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 379 | clocks = <&refclk>; |
Antoine Tenart | 50cc24f | 2014-05-18 20:15:57 +0200 | [diff] [blame] | 380 | pinctrl-0 = <&uart0_pmux>; |
| 381 | pinctrl-names = "default"; |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 382 | status = "disabled"; |
| 383 | }; |
| 384 | |
| 385 | uart1: serial@a000 { |
| 386 | compatible = "snps,dw-apb-uart"; |
| 387 | reg = <0xa000 0x100>; |
| 388 | reg-shift = <2>; |
| 389 | reg-io-width = <1>; |
| 390 | interrupts = <9>; |
Sebastian Hesselbarth | 556f4a3 | 2014-05-10 15:22:48 +0200 | [diff] [blame] | 391 | clocks = <&refclk>; |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 392 | status = "disabled"; |
| 393 | }; |
| 394 | |
Antoine Tenart | 50cc24f | 2014-05-18 20:15:57 +0200 | [diff] [blame] | 395 | sysctrl: system-controller@d000 { |
Antoine Tenart | ffcc33a | 2015-05-16 00:30:15 +0200 | [diff] [blame] | 396 | compatible = "marvell,berlin2cd-system-ctrl", "simple-mfd", "syscon"; |
Antoine Tenart | 50cc24f | 2014-05-18 20:15:57 +0200 | [diff] [blame] | 397 | reg = <0xd000 0x100>; |
| 398 | }; |
| 399 | |
Sebastian Hesselbarth | a909211 | 2013-11-05 12:40:22 +0100 | [diff] [blame] | 400 | sic: interrupt-controller@e000 { |
| 401 | compatible = "snps,dw-apb-ictl"; |
| 402 | reg = <0xe000 0x400>; |
| 403 | interrupt-controller; |
| 404 | #interrupt-cells = <1>; |
| 405 | interrupt-parent = <&gic>; |
| 406 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 407 | }; |
| 408 | }; |
| 409 | }; |
| 410 | }; |