Pawel Moll | cca070a | 2011-12-09 18:40:31 +0000 | [diff] [blame] | 1 | /* |
| 2 | * ARM Ltd. Versatile Express |
| 3 | * |
| 4 | * CoreTile Express A9x4 |
| 5 | * Cortex-A9 MPCore (V2P-CA9) |
| 6 | * |
| 7 | * HBI-0191B |
| 8 | */ |
| 9 | |
| 10 | /dts-v1/; |
| 11 | |
| 12 | / { |
| 13 | model = "V2P-CA9"; |
| 14 | arm,hbi = <0x191>; |
Pawel Moll | 842839a | 2012-09-17 16:43:30 +0100 | [diff] [blame] | 15 | arm,vexpress,site = <0xf>; |
Pawel Moll | cca070a | 2011-12-09 18:40:31 +0000 | [diff] [blame] | 16 | compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; |
| 17 | interrupt-parent = <&gic>; |
| 18 | #address-cells = <1>; |
| 19 | #size-cells = <1>; |
| 20 | |
| 21 | chosen { }; |
| 22 | |
| 23 | aliases { |
| 24 | serial0 = &v2m_serial0; |
| 25 | serial1 = &v2m_serial1; |
| 26 | serial2 = &v2m_serial2; |
| 27 | serial3 = &v2m_serial3; |
| 28 | i2c0 = &v2m_i2c_dvi; |
| 29 | i2c1 = &v2m_i2c_pcie; |
| 30 | }; |
| 31 | |
| 32 | cpus { |
| 33 | #address-cells = <1>; |
| 34 | #size-cells = <0>; |
| 35 | |
| 36 | cpu@0 { |
| 37 | device_type = "cpu"; |
| 38 | compatible = "arm,cortex-a9"; |
| 39 | reg = <0>; |
| 40 | next-level-cache = <&L2>; |
| 41 | }; |
| 42 | |
| 43 | cpu@1 { |
| 44 | device_type = "cpu"; |
| 45 | compatible = "arm,cortex-a9"; |
| 46 | reg = <1>; |
| 47 | next-level-cache = <&L2>; |
| 48 | }; |
| 49 | |
| 50 | cpu@2 { |
| 51 | device_type = "cpu"; |
| 52 | compatible = "arm,cortex-a9"; |
| 53 | reg = <2>; |
| 54 | next-level-cache = <&L2>; |
| 55 | }; |
| 56 | |
| 57 | cpu@3 { |
| 58 | device_type = "cpu"; |
| 59 | compatible = "arm,cortex-a9"; |
| 60 | reg = <3>; |
| 61 | next-level-cache = <&L2>; |
| 62 | }; |
| 63 | }; |
| 64 | |
| 65 | memory@60000000 { |
| 66 | device_type = "memory"; |
| 67 | reg = <0x60000000 0x40000000>; |
| 68 | }; |
| 69 | |
| 70 | clcd@10020000 { |
| 71 | compatible = "arm,pl111", "arm,primecell"; |
| 72 | reg = <0x10020000 0x1000>; |
| 73 | interrupts = <0 44 4>; |
Pawel Moll | 842839a | 2012-09-17 16:43:30 +0100 | [diff] [blame] | 74 | clocks = <&oscclk1>, <&oscclk2>; |
| 75 | clock-names = "clcdclk", "apb_pclk"; |
Pawel Moll | cca070a | 2011-12-09 18:40:31 +0000 | [diff] [blame] | 76 | }; |
| 77 | |
| 78 | memory-controller@100e0000 { |
| 79 | compatible = "arm,pl341", "arm,primecell"; |
| 80 | reg = <0x100e0000 0x1000>; |
Pawel Moll | 842839a | 2012-09-17 16:43:30 +0100 | [diff] [blame] | 81 | clocks = <&oscclk2>; |
| 82 | clock-names = "apb_pclk"; |
Pawel Moll | cca070a | 2011-12-09 18:40:31 +0000 | [diff] [blame] | 83 | }; |
| 84 | |
| 85 | memory-controller@100e1000 { |
| 86 | compatible = "arm,pl354", "arm,primecell"; |
| 87 | reg = <0x100e1000 0x1000>; |
| 88 | interrupts = <0 45 4>, |
| 89 | <0 46 4>; |
Pawel Moll | 842839a | 2012-09-17 16:43:30 +0100 | [diff] [blame] | 90 | clocks = <&oscclk2>; |
| 91 | clock-names = "apb_pclk"; |
Pawel Moll | cca070a | 2011-12-09 18:40:31 +0000 | [diff] [blame] | 92 | }; |
| 93 | |
| 94 | timer@100e4000 { |
| 95 | compatible = "arm,sp804", "arm,primecell"; |
| 96 | reg = <0x100e4000 0x1000>; |
| 97 | interrupts = <0 48 4>, |
| 98 | <0 49 4>; |
Pawel Moll | 842839a | 2012-09-17 16:43:30 +0100 | [diff] [blame] | 99 | clocks = <&oscclk2>, <&oscclk2>; |
| 100 | clock-names = "timclk", "apb_pclk"; |
Pawel Moll | cca070a | 2011-12-09 18:40:31 +0000 | [diff] [blame] | 101 | }; |
| 102 | |
| 103 | watchdog@100e5000 { |
| 104 | compatible = "arm,sp805", "arm,primecell"; |
| 105 | reg = <0x100e5000 0x1000>; |
| 106 | interrupts = <0 51 4>; |
Pawel Moll | 842839a | 2012-09-17 16:43:30 +0100 | [diff] [blame] | 107 | clocks = <&oscclk2>, <&oscclk2>; |
| 108 | clock-names = "wdogclk", "apb_pclk"; |
Pawel Moll | cca070a | 2011-12-09 18:40:31 +0000 | [diff] [blame] | 109 | }; |
| 110 | |
| 111 | scu@1e000000 { |
| 112 | compatible = "arm,cortex-a9-scu"; |
| 113 | reg = <0x1e000000 0x58>; |
| 114 | }; |
| 115 | |
| 116 | timer@1e000600 { |
| 117 | compatible = "arm,cortex-a9-twd-timer"; |
| 118 | reg = <0x1e000600 0x20>; |
Pawel Moll | e29b65d | 2012-05-10 17:12:07 +0100 | [diff] [blame] | 119 | interrupts = <1 13 0xf04>; |
| 120 | }; |
| 121 | |
| 122 | watchdog@1e000620 { |
| 123 | compatible = "arm,cortex-a9-twd-wdt"; |
| 124 | reg = <0x1e000620 0x20>; |
| 125 | interrupts = <1 14 0xf04>; |
Pawel Moll | cca070a | 2011-12-09 18:40:31 +0000 | [diff] [blame] | 126 | }; |
| 127 | |
| 128 | gic: interrupt-controller@1e001000 { |
| 129 | compatible = "arm,cortex-a9-gic"; |
| 130 | #interrupt-cells = <3>; |
| 131 | #address-cells = <0>; |
| 132 | interrupt-controller; |
| 133 | reg = <0x1e001000 0x1000>, |
| 134 | <0x1e000100 0x100>; |
| 135 | }; |
| 136 | |
| 137 | L2: cache-controller@1e00a000 { |
| 138 | compatible = "arm,pl310-cache"; |
| 139 | reg = <0x1e00a000 0x1000>; |
| 140 | interrupts = <0 43 4>; |
| 141 | cache-level = <2>; |
| 142 | arm,data-latency = <1 1 1>; |
| 143 | arm,tag-latency = <1 1 1>; |
| 144 | }; |
| 145 | |
| 146 | pmu { |
| 147 | compatible = "arm,cortex-a9-pmu"; |
| 148 | interrupts = <0 60 4>, |
| 149 | <0 61 4>, |
| 150 | <0 62 4>, |
| 151 | <0 63 4>; |
| 152 | }; |
| 153 | |
Pawel Moll | 842839a | 2012-09-17 16:43:30 +0100 | [diff] [blame] | 154 | dcc { |
| 155 | compatible = "arm,vexpress,config-bus"; |
| 156 | arm,vexpress,config-bridge = <&v2m_sysreg>; |
| 157 | |
| 158 | osc@0 { |
| 159 | /* ACLK clock to the AXI master port on the test chip */ |
| 160 | compatible = "arm,vexpress-osc"; |
| 161 | arm,vexpress-sysreg,func = <1 0>; |
| 162 | freq-range = <30000000 50000000>; |
| 163 | #clock-cells = <0>; |
| 164 | clock-output-names = "extsaxiclk"; |
| 165 | }; |
| 166 | |
| 167 | oscclk1: osc@1 { |
| 168 | /* Reference clock for the CLCD */ |
| 169 | compatible = "arm,vexpress-osc"; |
| 170 | arm,vexpress-sysreg,func = <1 1>; |
| 171 | freq-range = <10000000 80000000>; |
| 172 | #clock-cells = <0>; |
| 173 | clock-output-names = "clcdclk"; |
| 174 | }; |
| 175 | |
| 176 | smbclk: oscclk2: osc@2 { |
| 177 | /* Reference clock for the test chip internal PLLs */ |
| 178 | compatible = "arm,vexpress-osc"; |
| 179 | arm,vexpress-sysreg,func = <1 2>; |
| 180 | freq-range = <33000000 100000000>; |
| 181 | #clock-cells = <0>; |
| 182 | clock-output-names = "tcrefclk"; |
| 183 | }; |
| 184 | |
| 185 | volt@0 { |
| 186 | /* Test Chip internal logic voltage */ |
| 187 | compatible = "arm,vexpress-volt"; |
| 188 | arm,vexpress-sysreg,func = <2 0>; |
| 189 | regulator-name = "VD10"; |
| 190 | regulator-always-on; |
| 191 | label = "VD10"; |
| 192 | }; |
| 193 | |
| 194 | volt@1 { |
| 195 | /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ |
| 196 | compatible = "arm,vexpress-volt"; |
| 197 | arm,vexpress-sysreg,func = <2 1>; |
| 198 | regulator-name = "VD10_S2"; |
| 199 | regulator-always-on; |
| 200 | label = "VD10_S2"; |
| 201 | }; |
| 202 | |
| 203 | volt@2 { |
| 204 | /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ |
| 205 | compatible = "arm,vexpress-volt"; |
| 206 | arm,vexpress-sysreg,func = <2 2>; |
| 207 | regulator-name = "VD10_S3"; |
| 208 | regulator-always-on; |
| 209 | label = "VD10_S3"; |
| 210 | }; |
| 211 | |
| 212 | volt@3 { |
| 213 | /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ |
| 214 | compatible = "arm,vexpress-volt"; |
| 215 | arm,vexpress-sysreg,func = <2 3>; |
| 216 | regulator-name = "VCC1V8"; |
| 217 | regulator-always-on; |
| 218 | label = "VCC1V8"; |
| 219 | }; |
| 220 | |
| 221 | volt@4 { |
| 222 | /* DDR2 SDRAM VTT termination voltage */ |
| 223 | compatible = "arm,vexpress-volt"; |
| 224 | arm,vexpress-sysreg,func = <2 4>; |
| 225 | regulator-name = "DDR2VTT"; |
| 226 | regulator-always-on; |
| 227 | label = "DDR2VTT"; |
| 228 | }; |
| 229 | |
| 230 | volt@5 { |
| 231 | /* Local board supply for miscellaneous logic external to the Test Chip */ |
| 232 | arm,vexpress-sysreg,func = <2 5>; |
| 233 | compatible = "arm,vexpress-volt"; |
| 234 | regulator-name = "VCC3V3"; |
| 235 | regulator-always-on; |
| 236 | label = "VCC3V3"; |
| 237 | }; |
| 238 | |
| 239 | amp@0 { |
| 240 | /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ |
| 241 | compatible = "arm,vexpress-amp"; |
| 242 | arm,vexpress-sysreg,func = <3 0>; |
| 243 | label = "VD10_S2"; |
| 244 | }; |
| 245 | |
| 246 | amp@1 { |
| 247 | /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ |
| 248 | compatible = "arm,vexpress-amp"; |
| 249 | arm,vexpress-sysreg,func = <3 1>; |
| 250 | label = "VD10_S3"; |
| 251 | }; |
| 252 | |
| 253 | power@0 { |
| 254 | /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ |
| 255 | compatible = "arm,vexpress-power"; |
| 256 | arm,vexpress-sysreg,func = <12 0>; |
| 257 | label = "PVD10_S2"; |
| 258 | }; |
| 259 | |
| 260 | power@1 { |
| 261 | /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ |
| 262 | compatible = "arm,vexpress-power"; |
| 263 | arm,vexpress-sysreg,func = <12 1>; |
| 264 | label = "PVD10_S3"; |
| 265 | }; |
| 266 | }; |
| 267 | |
Pawel Moll | 433683a | 2012-10-16 15:27:12 +0100 | [diff] [blame^] | 268 | smb { |
| 269 | compatible = "simple-bus"; |
| 270 | |
| 271 | #address-cells = <2>; |
| 272 | #size-cells = <1>; |
Pawel Moll | cca070a | 2011-12-09 18:40:31 +0000 | [diff] [blame] | 273 | ranges = <0 0 0x40000000 0x04000000>, |
| 274 | <1 0 0x44000000 0x04000000>, |
| 275 | <2 0 0x48000000 0x04000000>, |
| 276 | <3 0 0x4c000000 0x04000000>, |
| 277 | <7 0 0x10000000 0x00020000>; |
| 278 | |
Pawel Moll | 433683a | 2012-10-16 15:27:12 +0100 | [diff] [blame^] | 279 | #interrupt-cells = <1>; |
Pawel Moll | cca070a | 2011-12-09 18:40:31 +0000 | [diff] [blame] | 280 | interrupt-map-mask = <0 0 63>; |
| 281 | interrupt-map = <0 0 0 &gic 0 0 4>, |
| 282 | <0 0 1 &gic 0 1 4>, |
| 283 | <0 0 2 &gic 0 2 4>, |
| 284 | <0 0 3 &gic 0 3 4>, |
| 285 | <0 0 4 &gic 0 4 4>, |
| 286 | <0 0 5 &gic 0 5 4>, |
| 287 | <0 0 6 &gic 0 6 4>, |
| 288 | <0 0 7 &gic 0 7 4>, |
| 289 | <0 0 8 &gic 0 8 4>, |
| 290 | <0 0 9 &gic 0 9 4>, |
| 291 | <0 0 10 &gic 0 10 4>, |
| 292 | <0 0 11 &gic 0 11 4>, |
| 293 | <0 0 12 &gic 0 12 4>, |
| 294 | <0 0 13 &gic 0 13 4>, |
| 295 | <0 0 14 &gic 0 14 4>, |
| 296 | <0 0 15 &gic 0 15 4>, |
| 297 | <0 0 16 &gic 0 16 4>, |
| 298 | <0 0 17 &gic 0 17 4>, |
| 299 | <0 0 18 &gic 0 18 4>, |
| 300 | <0 0 19 &gic 0 19 4>, |
| 301 | <0 0 20 &gic 0 20 4>, |
| 302 | <0 0 21 &gic 0 21 4>, |
| 303 | <0 0 22 &gic 0 22 4>, |
| 304 | <0 0 23 &gic 0 23 4>, |
| 305 | <0 0 24 &gic 0 24 4>, |
| 306 | <0 0 25 &gic 0 25 4>, |
| 307 | <0 0 26 &gic 0 26 4>, |
| 308 | <0 0 27 &gic 0 27 4>, |
| 309 | <0 0 28 &gic 0 28 4>, |
| 310 | <0 0 29 &gic 0 29 4>, |
| 311 | <0 0 30 &gic 0 30 4>, |
| 312 | <0 0 31 &gic 0 31 4>, |
| 313 | <0 0 32 &gic 0 32 4>, |
| 314 | <0 0 33 &gic 0 33 4>, |
| 315 | <0 0 34 &gic 0 34 4>, |
| 316 | <0 0 35 &gic 0 35 4>, |
| 317 | <0 0 36 &gic 0 36 4>, |
| 318 | <0 0 37 &gic 0 37 4>, |
| 319 | <0 0 38 &gic 0 38 4>, |
| 320 | <0 0 39 &gic 0 39 4>, |
| 321 | <0 0 40 &gic 0 40 4>, |
| 322 | <0 0 41 &gic 0 41 4>, |
| 323 | <0 0 42 &gic 0 42 4>; |
Pawel Moll | 433683a | 2012-10-16 15:27:12 +0100 | [diff] [blame^] | 324 | |
| 325 | /include/ "vexpress-v2m.dtsi" |
Pawel Moll | cca070a | 2011-12-09 18:40:31 +0000 | [diff] [blame] | 326 | }; |
| 327 | }; |