Vineet Gupta | 41195d2 | 2013-01-18 15:12:23 +0530 | [diff] [blame] | 1 | /* |
| 2 | * ARC700 Simulation-only Extensions for SMP |
| 3 | * |
| 4 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * Vineet Gupta - 2012 : split off arch common and plat specific SMP |
| 11 | * Rajeshwar Ranga - 2007 : Interrupt Distribution Unit API's |
| 12 | */ |
| 13 | |
| 14 | #include <linux/smp.h> |
| 15 | #include <asm/irq.h> |
| 16 | #include <plat/smp.h> |
| 17 | |
| 18 | static char smp_cpuinfo_buf[128]; |
| 19 | |
| 20 | /* |
| 21 | *------------------------------------------------------------------- |
| 22 | * Platform specific callbacks expected by arch SMP code |
| 23 | *------------------------------------------------------------------- |
| 24 | */ |
| 25 | |
| 26 | const char *arc_platform_smp_cpuinfo(void) |
| 27 | { |
| 28 | #define IS_AVAIL1(var, str) ((var) ? str : "") |
| 29 | |
| 30 | struct bcr_mp mp; |
| 31 | |
| 32 | READ_BCR(ARC_REG_MP_BCR, mp); |
| 33 | |
| 34 | sprintf(smp_cpuinfo_buf, "Extn [700-SMP]: v%d, arch(%d) %s %s %s\n", |
| 35 | mp.ver, mp.mp_arch, IS_AVAIL1(mp.scu, "SCU"), |
| 36 | IS_AVAIL1(mp.idu, "IDU"), IS_AVAIL1(mp.sdu, "SDU")); |
| 37 | |
| 38 | return smp_cpuinfo_buf; |
| 39 | } |
| 40 | |
| 41 | /* |
| 42 | * Master kick starting another CPU |
| 43 | */ |
| 44 | void arc_platform_smp_wakeup_cpu(int cpu, unsigned long pc) |
| 45 | { |
| 46 | /* setup the start PC */ |
| 47 | write_aux_reg(ARC_AUX_XTL_REG_PARAM, pc); |
| 48 | |
| 49 | /* Trigger WRITE_PC cmd for this cpu */ |
| 50 | write_aux_reg(ARC_AUX_XTL_REG_CMD, |
| 51 | (ARC_XTL_CMD_WRITE_PC | (cpu << 8))); |
| 52 | |
| 53 | /* Take the cpu out of Halt */ |
| 54 | write_aux_reg(ARC_AUX_XTL_REG_CMD, |
| 55 | (ARC_XTL_CMD_CLEAR_HALT | (cpu << 8))); |
| 56 | |
| 57 | } |
| 58 | |
| 59 | /* |
| 60 | * Any SMP specific init any CPU does when it comes up. |
| 61 | * Here we setup the CPU to enable Inter-Processor-Interrupts |
| 62 | * Called for each CPU |
| 63 | * -Master : init_IRQ() |
| 64 | * -Other(s) : start_kernel_secondary() |
| 65 | */ |
| 66 | void arc_platform_smp_init_cpu(void) |
| 67 | { |
| 68 | int cpu = smp_processor_id(); |
| 69 | |
| 70 | /* Check if CPU is configured for more than 16 interrupts */ |
| 71 | if (NR_IRQS <= 16 || get_hw_config_num_irq() <= 16) |
| 72 | panic("[arcfpga] IRQ system can't support IDU IPI\n"); |
| 73 | |
| 74 | idu_disable(); |
| 75 | |
| 76 | /**************************************************************** |
| 77 | * IDU provides a set of Common IRQs, each of which can be dynamically |
| 78 | * attached to (1|many|all) CPUs. |
| 79 | * The Common IRQs [0-15] are mapped as CPU pvt [16-31] |
| 80 | * |
| 81 | * Here we use a simple 1:1 mapping: |
| 82 | * A CPU 'x' is wired to Common IRQ 'x'. |
| 83 | * So an IDU ASSERT on IRQ 'x' will trigger Interupt on CPU 'x', which |
| 84 | * makes up for our simple IPI plumbing. |
| 85 | * |
| 86 | * TBD: Have a dedicated multicast IRQ for sending IPIs to all CPUs |
| 87 | * w/o having to do one-at-a-time |
| 88 | ******************************************************************/ |
| 89 | |
| 90 | /* |
| 91 | * Claim an IRQ which would trigger IPI on this CPU. |
| 92 | * In IDU parlance it involves setting up a cpu bitmask for the IRQ |
| 93 | * The bitmap here contains only 1 CPU (self). |
| 94 | */ |
| 95 | idu_irq_set_tgtcpu(cpu, 0x1 << cpu); |
| 96 | |
| 97 | /* Set the IRQ destination to use the bitmask above */ |
| 98 | idu_irq_set_mode(cpu, 7, /* XXX: IDU_IRQ_MOD_TCPU_ALLRECP: ISS bug */ |
| 99 | IDU_IRQ_MODE_PULSE_TRIG); |
| 100 | |
| 101 | idu_enable(); |
| 102 | |
| 103 | /* Attach the arch-common IPI ISR to our IDU IRQ */ |
| 104 | smp_ipi_irq_setup(cpu, IDU_INTERRUPT_0 + cpu); |
| 105 | } |
| 106 | |
| 107 | void arc_platform_ipi_send(const struct cpumask *callmap) |
| 108 | { |
| 109 | unsigned int cpu; |
| 110 | |
| 111 | for_each_cpu(cpu, callmap) |
| 112 | idu_irq_assert(cpu); |
| 113 | } |
| 114 | |
| 115 | void arc_platform_ipi_clear(int cpu, int irq) |
| 116 | { |
| 117 | idu_irq_clear(IDU_INTERRUPT_0 + cpu); |
| 118 | } |
| 119 | |
| 120 | /* |
| 121 | *------------------------------------------------------------------- |
| 122 | * Low level Platform IPI Providers |
| 123 | *------------------------------------------------------------------- |
| 124 | */ |
| 125 | |
| 126 | /* Set the Mode for the Common IRQ */ |
| 127 | void idu_irq_set_mode(uint8_t irq, uint8_t dest_mode, uint8_t trig_mode) |
| 128 | { |
| 129 | uint32_t par = IDU_IRQ_MODE_PARAM(dest_mode, trig_mode); |
| 130 | |
| 131 | IDU_SET_PARAM(par); |
| 132 | IDU_SET_COMMAND(irq, IDU_IRQ_WMODE); |
| 133 | } |
| 134 | |
| 135 | /* Set the target cpu Bitmask for Common IRQ */ |
| 136 | void idu_irq_set_tgtcpu(uint8_t irq, uint32_t mask) |
| 137 | { |
| 138 | IDU_SET_PARAM(mask); |
| 139 | IDU_SET_COMMAND(irq, IDU_IRQ_WBITMASK); |
| 140 | } |
| 141 | |
| 142 | /* Get the Interrupt Acknowledged status for IRQ (as CPU Bitmask) */ |
| 143 | bool idu_irq_get_ack(uint8_t irq) |
| 144 | { |
| 145 | uint32_t val; |
| 146 | |
| 147 | IDU_SET_COMMAND(irq, IDU_IRQ_ACK); |
| 148 | val = IDU_GET_PARAM(); |
| 149 | |
| 150 | return val & (1 << irq); |
| 151 | } |
| 152 | |
| 153 | /* |
| 154 | * Get the Interrupt Pending status for IRQ (as CPU Bitmask) |
| 155 | * -Pending means CPU has not yet noticed the IRQ (e.g. disabled) |
| 156 | * -After Interrupt has been taken, the IPI expcitily needs to be |
| 157 | * cleared, to be acknowledged. |
| 158 | */ |
| 159 | bool idu_irq_get_pend(uint8_t irq) |
| 160 | { |
| 161 | uint32_t val; |
| 162 | |
| 163 | IDU_SET_COMMAND(irq, IDU_IRQ_PEND); |
| 164 | val = IDU_GET_PARAM(); |
| 165 | |
| 166 | return val & (1 << irq); |
| 167 | } |