Taniya Das | 988608c | 2016-08-04 22:12:44 +0530 | [diff] [blame] | 1 | QTI Global Distributed Switch Controller (GDSC) Regulator Driver |
| 2 | |
| 3 | The GDSC driver, implemented under the regulator framework, is responsible for |
| 4 | safely collapsing and restoring power to peripheral cores on chipsets like |
| 5 | msm8996 for power savings. |
| 6 | |
| 7 | Required properties: |
| 8 | - compatible: Must be "qcom,gdsc" |
| 9 | - regulator-name: A string used as a descriptive name for regulator outputs |
| 10 | - reg: The address of the GDSCR register |
| 11 | |
| 12 | Optional properties: |
| 13 | - parent-supply: phandle to the parent supply/regulator node |
| 14 | - clock-names: List of string names for core clocks |
| 15 | - qcom,retain-mem: Presence denotes a hardware requirement to leave the |
| 16 | forced core memory retention signals in the core's clock |
| 17 | branch control registers asserted. |
| 18 | - qcom,retain-periph: Presence denotes a hardware requirement to leave the |
| 19 | forced periph memory retention signal in the core's clock |
| 20 | branch control registers asserted. |
| 21 | - qcom,skip-logic-collapse: Presence denotes a requirement to leave power to |
| 22 | the core's logic enabled. |
| 23 | - qcom,support-hw-trigger: Presence denotes a hardware feature to switch |
| 24 | on/off this regulator based on internal HW signals |
| 25 | to save more power. |
| 26 | - qcom,enable-root-clk: Presence denotes that the clocks in the "clocks" |
| 27 | property are required to be enabled before gdsc is |
| 28 | turned on and disabled before turning off gdsc. This |
| 29 | will be used in subsystems where reset is synchronous |
| 30 | and root clk is active without sw being aware of its |
| 31 | state. The clock-name which denotes the root clock |
| 32 | should be named as "core_root_clk". |
| 33 | - qcom,force-enable-root-clk: If set, denotes that the root clock should be |
| 34 | force enabled before turning on the GDSC and then be |
| 35 | immediately force disabled. Likewise for GDSC disable. |
| 36 | This is used in cases where the core root clock needs |
| 37 | to be force-enabled prior to turning on the core. The |
| 38 | clock-name which denotes the root clock should be |
| 39 | "core_root_clk". |
| 40 | - qcom,clk-dis-wait-val: Input value for CLK_DIS_WAIT controls state transition |
| 41 | delay after halting clock in the collapsible core. |
| 42 | - reg-names: Names of the bases for the above "reg" registers. |
| 43 | Ex. "base", "domain-addr", "sw-reset", "hw-ctrl-addr". |
| 44 | - qcom,no-status-check-on-disable: Do not poll the status bit when GDSC |
| 45 | is disabled. |
| 46 | - qcom,disallow-clear: Presence denotes the periph & core memory will not be |
| 47 | cleared, unless the required subsystem does not invoke |
| 48 | the api which will allow clearing the bits. |
| 49 | - qcom,gds-timeout: Maximum time (in usecs) that might be taken by a GDSC |
| 50 | to enable. |
| 51 | - qcom,reset-aon-logic: If present, the GPU DEMET cells need to be reset while |
| 52 | enabling the GX GDSC. |
Odelu Kukatla | 0cb925e | 2019-01-02 18:25:30 +0530 | [diff] [blame] | 53 | - vdd_parent-supply: phandle to the regulator that this GDSC gates. If |
| 54 | present, need to vote for a minimum operational voltage |
| 55 | (LOW_SVS) on the GDSC parent regulator prior to |
| 56 | configuring it. The vote is removed once the GDSC FSM |
| 57 | has latched on to the new state. |
Taniya Das | 988608c | 2016-08-04 22:12:44 +0530 | [diff] [blame] | 58 | - resets: reset specifier pair consisting of phandle for the reset controller |
| 59 | and reset lines used by this controller. These can be |
| 60 | supplied only if we support qcom,skip-logic-collapse. |
| 61 | - reset-names: reset signal name strings sorted in the same order as the resets |
| 62 | property. These can be supplied only if we support |
| 63 | qcom,skip-logic-collapse. |
Deepak Katragadda | 522c803 | 2016-11-11 11:37:10 -0800 | [diff] [blame] | 64 | - qcom,poll-cfg-gdscr: Poll the CFG register of the GDSC to determine if the |
| 65 | GDSC is enabled/disabled. This flag should not be set |
| 66 | in conjunction with "hw-ctrl-addr". |
Vicky Wallace | 209cfbb | 2017-05-16 17:19:38 -0700 | [diff] [blame] | 67 | - qcom,toggle-sw-collapse-in-disable: If set, SW_COLLAPSE bit is toggled |
| 68 | in disable call. |
Amit Nischal | 9acc096 | 2018-06-14 13:30:04 +0530 | [diff] [blame] | 69 | - qcom,en-few-wait-val: Input value for EN_FEW_WAIT controls state transition |
| 70 | delay after receiving ack signal (gds_enf_ack) from the |
| 71 | longest en_few power switch chain. |
| 72 | - qcom,en-rest-wait-val: Input value for EN_REST_WAIT controls state transition |
| 73 | delay after receiving ack signal (gds_enr_ack) from the |
| 74 | longest en_rest power switch chain. |
Naveen Yadav | 255113b | 2020-04-29 22:26:26 +0530 | [diff] [blame] | 75 | - qcom,skip-disable-before-sw-enable: Presence denotes a hardware requirement |
| 76 | to leave the GDSC on that has been |
| 77 | enabled by an entity external to HLOS. |
Taniya Das | 988608c | 2016-08-04 22:12:44 +0530 | [diff] [blame] | 78 | Example: |
| 79 | gdsc_oxili_gx: qcom,gdsc@fd8c4024 { |
| 80 | compatible = "qcom,gdsc"; |
| 81 | regulator-name = "gdsc_oxili_gx"; |
| 82 | parent-supply = <&pm8841_s4>; |
| 83 | reg = <0xfd8c4024 0x4>; |
| 84 | clock-names = "core_clk"; |
| 85 | }; |