Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/regmap.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/mutex.h> |
| 23 | #include <linux/types.h> |
| 24 | #include <linux/hwmon.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/debugfs.h> |
| 27 | #include <linux/spmi.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/of_irq.h> |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 30 | #include <linux/interrupt.h> |
| 31 | #include <linux/completion.h> |
| 32 | #include <linux/hwmon-sysfs.h> |
| 33 | #include <linux/qpnp/qpnp-adc.h> |
| 34 | #include <linux/platform_device.h> |
Siddartha Mohanadoss | 37d9c8a | 2017-01-23 19:21:58 -0800 | [diff] [blame] | 35 | |
| 36 | /* QPNP IADC register definition */ |
| 37 | #define QPNP_IADC_REVISION1 0x0 |
| 38 | #define QPNP_IADC_REVISION2 0x1 |
| 39 | #define QPNP_IADC_REVISION3 0x2 |
| 40 | #define QPNP_IADC_REVISION4 0x3 |
| 41 | #define QPNP_IADC_PERPH_TYPE 0x4 |
| 42 | #define QPNP_IADC_PERH_SUBTYPE 0x5 |
| 43 | |
| 44 | #define QPNP_IADC_SUPPORTED_REVISION2 1 |
| 45 | |
| 46 | #define QPNP_STATUS1 0x8 |
| 47 | #define QPNP_STATUS1_OP_MODE 4 |
| 48 | #define QPNP_STATUS1_MULTI_MEAS_EN BIT(3) |
| 49 | #define QPNP_STATUS1_MEAS_INTERVAL_EN_STS BIT(2) |
| 50 | #define QPNP_STATUS1_REQ_STS BIT(1) |
| 51 | #define QPNP_STATUS1_EOC BIT(0) |
| 52 | #define QPNP_STATUS1_REQ_STS_EOC_MASK 0x3 |
| 53 | #define QPNP_STATUS2 0x9 |
| 54 | #define QPNP_STATUS2_CONV_SEQ_STATE_SHIFT 4 |
| 55 | #define QPNP_STATUS2_FIFO_NOT_EMPTY_FLAG BIT(1) |
| 56 | #define QPNP_STATUS2_CONV_SEQ_TIMEOUT_STS BIT(0) |
| 57 | #define QPNP_CONV_TIMEOUT_ERR 2 |
| 58 | |
| 59 | #define QPNP_IADC_MODE_CTL 0x40 |
| 60 | #define QPNP_OP_MODE_SHIFT 4 |
| 61 | #define QPNP_USE_BMS_DATA BIT(4) |
| 62 | #define QPNP_VADC_SYNCH_EN BIT(2) |
| 63 | #define QPNP_OFFSET_RMV_EN BIT(1) |
| 64 | #define QPNP_ADC_TRIM_EN BIT(0) |
| 65 | #define QPNP_IADC_EN_CTL1 0x46 |
| 66 | #define QPNP_IADC_ADC_EN BIT(7) |
| 67 | #define QPNP_ADC_CH_SEL_CTL 0x48 |
| 68 | #define QPNP_ADC_DIG_PARAM 0x50 |
| 69 | #define QPNP_ADC_CLK_SEL_MASK 0x3 |
| 70 | #define QPNP_ADC_DEC_RATIO_SEL_MASK 0xc |
| 71 | #define QPNP_ADC_DIG_DEC_RATIO_SEL_SHIFT 2 |
| 72 | |
| 73 | #define QPNP_CONV_REQ 0x52 |
| 74 | #define QPNP_CONV_REQ_SET BIT(7) |
| 75 | #define QPNP_CONV_SEQ_CTL 0x54 |
| 76 | #define QPNP_CONV_SEQ_HOLDOFF_SHIFT 4 |
| 77 | #define QPNP_CONV_SEQ_TRIG_CTL 0x55 |
| 78 | #define QPNP_FAST_AVG_CTL 0x5a |
| 79 | |
| 80 | #define QPNP_M0_LOW_THR_LSB 0x5c |
| 81 | #define QPNP_M0_LOW_THR_MSB 0x5d |
| 82 | #define QPNP_M0_HIGH_THR_LSB 0x5e |
| 83 | #define QPNP_M0_HIGH_THR_MSB 0x5f |
| 84 | #define QPNP_M1_LOW_THR_LSB 0x69 |
| 85 | #define QPNP_M1_LOW_THR_MSB 0x6a |
| 86 | #define QPNP_M1_HIGH_THR_LSB 0x6b |
| 87 | #define QPNP_M1_HIGH_THR_MSB 0x6c |
| 88 | |
| 89 | #define QPNP_DATA0 0x60 |
| 90 | #define QPNP_DATA1 0x61 |
| 91 | #define QPNP_CONV_TIMEOUT_ERR 2 |
| 92 | |
| 93 | #define QPNP_IADC_SEC_ACCESS 0xD0 |
| 94 | #define QPNP_IADC_SEC_ACCESS_DATA 0xA5 |
| 95 | #define QPNP_IADC_MSB_OFFSET 0xF2 |
| 96 | #define QPNP_IADC_LSB_OFFSET 0xF3 |
| 97 | #define QPNP_IADC_NOMINAL_RSENSE 0xF4 |
| 98 | #define QPNP_IADC_ATE_GAIN_CALIB_OFFSET 0xF5 |
| 99 | #define QPNP_INT_TEST_VAL 0xE1 |
| 100 | |
| 101 | #define QPNP_IADC_ADC_CH_SEL_CTL 0x48 |
| 102 | #define QPNP_IADC_ADC_CHX_SEL_SHIFT 3 |
| 103 | |
| 104 | #define QPNP_IADC_ADC_DIG_PARAM 0x50 |
| 105 | #define QPNP_IADC_CLK_SEL_SHIFT 1 |
| 106 | #define QPNP_IADC_DEC_RATIO_SEL 3 |
| 107 | |
| 108 | #define QPNP_IADC_CONV_REQUEST 0x52 |
| 109 | #define QPNP_IADC_CONV_REQ BIT(7) |
| 110 | |
| 111 | #define QPNP_IADC_DATA0 0x60 |
| 112 | #define QPNP_IADC_DATA1 0x61 |
| 113 | |
| 114 | #define QPNP_ADC_CONV_TIME_MIN 2000 |
| 115 | #define QPNP_ADC_CONV_TIME_MAX 2100 |
| 116 | #define QPNP_ADC_ERR_COUNT 20 |
| 117 | |
| 118 | #define QPNP_ADC_GAIN_NV 17857 |
| 119 | #define QPNP_OFFSET_CALIBRATION_SHORT_CADC_LEADS_IDEAL 0 |
| 120 | #define QPNP_IADC_INTERNAL_RSENSE_N_OHMS_FACTOR 10000000 |
| 121 | #define QPNP_IADC_NANO_VOLTS_FACTOR 1000000 |
| 122 | #define QPNP_IADC_CALIB_SECONDS 300000 |
| 123 | #define QPNP_IADC_RSENSE_LSB_N_OHMS_PER_BIT 15625 |
| 124 | #define QPNP_IADC_DIE_TEMP_CALIB_OFFSET 5000 |
| 125 | |
| 126 | #define QPNP_RAW_CODE_16_BIT_MSB_MASK 0xff00 |
| 127 | #define QPNP_RAW_CODE_16_BIT_LSB_MASK 0xff |
| 128 | #define QPNP_BIT_SHIFT_8 8 |
| 129 | #define QPNP_RSENSE_MSB_SIGN_CHECK 0x80 |
| 130 | #define QPNP_ADC_COMPLETION_TIMEOUT HZ |
| 131 | #define SMBB_BAT_IF_TRIM_CNST_RDS_MASK 0x7 |
| 132 | #define SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_0 0 |
| 133 | #define SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2 2 |
| 134 | #define QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST 127 |
| 135 | #define QPNP_IADC_RSENSE_DEFAULT_VALUE 7800000 |
| 136 | #define QPNP_IADC_RSENSE_DEFAULT_TYPEB_GF 9000000 |
| 137 | #define QPNP_IADC_RSENSE_DEFAULT_TYPEB_SMIC 9700000 |
| 138 | |
| 139 | struct qpnp_iadc_comp { |
| 140 | bool ext_rsense; |
| 141 | u8 id; |
| 142 | u8 sys_gain; |
| 143 | u8 revision_dig_major; |
| 144 | u8 revision_ana_minor; |
| 145 | }; |
| 146 | |
| 147 | struct qpnp_iadc_chip { |
| 148 | struct device *dev; |
| 149 | struct qpnp_adc_drv *adc; |
| 150 | int32_t rsense; |
| 151 | bool external_rsense; |
| 152 | bool default_internal_rsense; |
| 153 | struct device *iadc_hwmon; |
| 154 | struct list_head list; |
| 155 | int64_t die_temp; |
| 156 | struct delayed_work iadc_work; |
| 157 | bool iadc_mode_sel; |
| 158 | struct qpnp_iadc_comp iadc_comp; |
| 159 | struct qpnp_vadc_chip *vadc_dev; |
| 160 | struct work_struct trigger_completion_work; |
| 161 | bool skip_auto_calibrations; |
| 162 | bool iadc_poll_eoc; |
| 163 | u16 batt_id_trim_cnst_rds; |
| 164 | int rds_trim_default_type; |
| 165 | int max_channels_available; |
| 166 | bool rds_trim_default_check; |
| 167 | int32_t rsense_workaround_value; |
| 168 | struct sensor_device_attribute sens_attr[0]; |
| 169 | }; |
| 170 | |
| 171 | LIST_HEAD(qpnp_iadc_device_list); |
| 172 | |
| 173 | enum qpnp_iadc_rsense_rds_workaround { |
| 174 | QPNP_IADC_RDS_DEFAULT_TYPEA, |
| 175 | QPNP_IADC_RDS_DEFAULT_TYPEB, |
| 176 | QPNP_IADC_RDS_DEFAULT_TYPEC, |
| 177 | }; |
| 178 | |
| 179 | static int32_t qpnp_iadc_read_reg(struct qpnp_iadc_chip *iadc, |
| 180 | uint32_t reg, u8 *data) |
| 181 | { |
| 182 | int rc; |
| 183 | uint val; |
| 184 | |
| 185 | rc = regmap_read(iadc->adc->regmap, (iadc->adc->offset + reg), &val); |
| 186 | if (rc < 0) { |
| 187 | pr_err("qpnp iadc read reg %d failed with %d\n", reg, rc); |
| 188 | return rc; |
| 189 | } |
| 190 | *data = (u8)val; |
| 191 | |
| 192 | return 0; |
| 193 | } |
| 194 | |
| 195 | static int32_t qpnp_iadc_write_reg(struct qpnp_iadc_chip *iadc, |
| 196 | uint32_t reg, u8 data) |
| 197 | { |
| 198 | int rc; |
| 199 | u8 *buf; |
| 200 | |
| 201 | buf = &data; |
| 202 | rc = regmap_write(iadc->adc->regmap, (iadc->adc->offset + reg), *buf); |
| 203 | if (rc < 0) { |
| 204 | pr_err("qpnp iadc write reg %d failed with %d\n", reg, rc); |
| 205 | return rc; |
| 206 | } |
| 207 | |
| 208 | return 0; |
| 209 | } |
| 210 | |
| 211 | static int qpnp_iadc_is_valid(struct qpnp_iadc_chip *iadc) |
| 212 | { |
| 213 | struct qpnp_iadc_chip *iadc_chip = NULL; |
| 214 | |
| 215 | list_for_each_entry(iadc_chip, &qpnp_iadc_device_list, list) |
| 216 | if (iadc == iadc_chip) |
| 217 | return 0; |
| 218 | |
| 219 | return -EINVAL; |
| 220 | } |
| 221 | |
| 222 | static void qpnp_iadc_trigger_completion(struct work_struct *work) |
| 223 | { |
| 224 | struct qpnp_iadc_chip *iadc = container_of(work, |
| 225 | struct qpnp_iadc_chip, trigger_completion_work); |
| 226 | |
| 227 | if (qpnp_iadc_is_valid(iadc) < 0) |
| 228 | return; |
| 229 | |
| 230 | complete(&iadc->adc->adc_rslt_completion); |
| 231 | } |
| 232 | |
| 233 | static irqreturn_t qpnp_iadc_isr(int irq, void *dev_id) |
| 234 | { |
| 235 | struct qpnp_iadc_chip *iadc = dev_id; |
| 236 | |
| 237 | schedule_work(&iadc->trigger_completion_work); |
| 238 | |
| 239 | return IRQ_HANDLED; |
| 240 | } |
| 241 | |
| 242 | static int32_t qpnp_iadc_enable(struct qpnp_iadc_chip *dev, bool state) |
| 243 | { |
| 244 | int rc = 0; |
| 245 | u8 data = 0; |
| 246 | |
| 247 | data = QPNP_IADC_ADC_EN; |
| 248 | if (state) { |
| 249 | rc = qpnp_iadc_write_reg(dev, QPNP_IADC_EN_CTL1, |
| 250 | data); |
| 251 | if (rc < 0) { |
| 252 | pr_err("IADC enable failed\n"); |
| 253 | return rc; |
| 254 | } |
| 255 | } else { |
| 256 | rc = qpnp_iadc_write_reg(dev, QPNP_IADC_EN_CTL1, |
| 257 | (~data & QPNP_IADC_ADC_EN)); |
| 258 | if (rc < 0) { |
| 259 | pr_err("IADC disable failed\n"); |
| 260 | return rc; |
| 261 | } |
| 262 | } |
| 263 | |
| 264 | return 0; |
| 265 | } |
| 266 | |
| 267 | static int32_t qpnp_iadc_status_debug(struct qpnp_iadc_chip *dev) |
| 268 | { |
| 269 | int rc = 0; |
| 270 | u8 mode = 0, status1 = 0, chan = 0, dig = 0, en = 0; |
| 271 | |
| 272 | rc = qpnp_iadc_read_reg(dev, QPNP_IADC_MODE_CTL, &mode); |
| 273 | if (rc < 0) { |
| 274 | pr_err("mode ctl register read failed with %d\n", rc); |
| 275 | return rc; |
| 276 | } |
| 277 | |
| 278 | rc = qpnp_iadc_read_reg(dev, QPNP_ADC_DIG_PARAM, &dig); |
| 279 | if (rc < 0) { |
| 280 | pr_err("digital param read failed with %d\n", rc); |
| 281 | return rc; |
| 282 | } |
| 283 | |
| 284 | rc = qpnp_iadc_read_reg(dev, QPNP_IADC_ADC_CH_SEL_CTL, &chan); |
| 285 | if (rc < 0) { |
| 286 | pr_err("channel read failed with %d\n", rc); |
| 287 | return rc; |
| 288 | } |
| 289 | |
| 290 | rc = qpnp_iadc_read_reg(dev, QPNP_STATUS1, &status1); |
| 291 | if (rc < 0) { |
| 292 | pr_err("status1 read failed with %d\n", rc); |
| 293 | return rc; |
| 294 | } |
| 295 | |
| 296 | rc = qpnp_iadc_read_reg(dev, QPNP_IADC_EN_CTL1, &en); |
| 297 | if (rc < 0) { |
| 298 | pr_err("en read failed with %d\n", rc); |
| 299 | return rc; |
| 300 | } |
| 301 | |
| 302 | pr_debug("EOC not set with status:%x, dig:%x, ch:%x, mode:%x, en:%x\n", |
| 303 | status1, dig, chan, mode, en); |
| 304 | |
| 305 | rc = qpnp_iadc_enable(dev, false); |
| 306 | if (rc < 0) { |
| 307 | pr_err("IADC disable failed with %d\n", rc); |
| 308 | return rc; |
| 309 | } |
| 310 | |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | static int32_t qpnp_iadc_read_conversion_result(struct qpnp_iadc_chip *iadc, |
| 315 | int16_t *data) |
| 316 | { |
| 317 | uint8_t rslt_lsb, rslt_msb; |
| 318 | uint16_t rslt; |
| 319 | int32_t rc; |
| 320 | |
| 321 | rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_DATA0, &rslt_lsb); |
| 322 | if (rc < 0) { |
| 323 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 324 | return rc; |
| 325 | } |
| 326 | |
| 327 | rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_DATA1, &rslt_msb); |
| 328 | if (rc < 0) { |
| 329 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 330 | return rc; |
| 331 | } |
| 332 | |
| 333 | rslt = (rslt_msb << 8) | rslt_lsb; |
| 334 | *data = rslt; |
| 335 | |
| 336 | rc = qpnp_iadc_enable(iadc, false); |
| 337 | if (rc) |
| 338 | return rc; |
| 339 | |
| 340 | return 0; |
| 341 | } |
| 342 | |
| 343 | #define QPNP_IADC_PM8026_2_REV2 4 |
| 344 | #define QPNP_IADC_PM8026_2_REV3 2 |
| 345 | |
| 346 | #define QPNP_COEFF_1 969000 |
| 347 | #define QPNP_COEFF_2 32 |
| 348 | #define QPNP_COEFF_3_TYPEA 1700000 |
| 349 | #define QPNP_COEFF_3_TYPEB 1000000 |
| 350 | #define QPNP_COEFF_4 100 |
| 351 | #define QPNP_COEFF_5 15 |
| 352 | #define QPNP_COEFF_6 100000 |
| 353 | #define QPNP_COEFF_7 21 |
| 354 | #define QPNP_COEFF_8 100000000 |
| 355 | #define QPNP_COEFF_9 38 |
| 356 | #define QPNP_COEFF_10 40 |
| 357 | #define QPNP_COEFF_11 7 |
| 358 | #define QPNP_COEFF_12 11 |
| 359 | #define QPNP_COEFF_13 37 |
| 360 | #define QPNP_COEFF_14 39 |
| 361 | #define QPNP_COEFF_15 9 |
| 362 | #define QPNP_COEFF_16 11 |
| 363 | #define QPNP_COEFF_17 851200 |
| 364 | #define QPNP_COEFF_18 296500 |
| 365 | #define QPNP_COEFF_19 222400 |
| 366 | #define QPNP_COEFF_20 813800 |
| 367 | #define QPNP_COEFF_21 1059100 |
| 368 | #define QPNP_COEFF_22 5000000 |
| 369 | #define QPNP_COEFF_23 3722500 |
| 370 | #define QPNP_COEFF_24 84 |
| 371 | #define QPNP_COEFF_25 33 |
| 372 | #define QPNP_COEFF_26 22 |
| 373 | #define QPNP_COEFF_27 53 |
| 374 | #define QPNP_COEFF_28 48 |
| 375 | |
| 376 | static int32_t qpnp_iadc_comp(int64_t *result, struct qpnp_iadc_chip *iadc, |
| 377 | int64_t die_temp) |
| 378 | { |
| 379 | int64_t temp_var = 0, sys_gain_coeff = 0, old; |
| 380 | int32_t coeff_a = 0, coeff_b = 0; |
| 381 | int version = 0; |
| 382 | |
| 383 | version = qpnp_adc_get_revid_version(iadc->dev); |
| 384 | if (version == -EINVAL) |
| 385 | return 0; |
| 386 | |
| 387 | old = *result; |
| 388 | *result = *result * 1000000; |
| 389 | |
| 390 | if (iadc->iadc_comp.sys_gain > 127) |
| 391 | sys_gain_coeff = -QPNP_COEFF_6 * |
| 392 | (iadc->iadc_comp.sys_gain - 128); |
| 393 | else |
| 394 | sys_gain_coeff = QPNP_COEFF_6 * |
| 395 | iadc->iadc_comp.sys_gain; |
| 396 | |
| 397 | switch (version) { |
| 398 | case QPNP_REV_ID_8941_3_1: |
| 399 | switch (iadc->iadc_comp.id) { |
| 400 | case COMP_ID_GF: |
| 401 | if (!iadc->iadc_comp.ext_rsense) { |
| 402 | /* internal rsense */ |
| 403 | coeff_a = QPNP_COEFF_2; |
| 404 | coeff_b = -QPNP_COEFF_3_TYPEA; |
| 405 | } else { |
| 406 | if (*result < 0) { |
| 407 | /* charge */ |
| 408 | coeff_a = QPNP_COEFF_5; |
| 409 | coeff_b = QPNP_COEFF_6; |
| 410 | } else { |
| 411 | /* discharge */ |
| 412 | coeff_a = -QPNP_COEFF_7; |
| 413 | coeff_b = QPNP_COEFF_6; |
| 414 | } |
| 415 | } |
| 416 | break; |
| 417 | case COMP_ID_TSMC: |
| 418 | default: |
| 419 | if (!iadc->iadc_comp.ext_rsense) { |
| 420 | /* internal rsense */ |
| 421 | coeff_a = QPNP_COEFF_2; |
| 422 | coeff_b = -QPNP_COEFF_3_TYPEB; |
| 423 | } else { |
| 424 | if (*result < 0) { |
| 425 | /* charge */ |
| 426 | coeff_a = QPNP_COEFF_5; |
| 427 | coeff_b = QPNP_COEFF_6; |
| 428 | } else { |
| 429 | /* discharge */ |
| 430 | coeff_a = -QPNP_COEFF_7; |
| 431 | coeff_b = QPNP_COEFF_6; |
| 432 | } |
| 433 | } |
| 434 | break; |
| 435 | } |
| 436 | break; |
| 437 | case QPNP_REV_ID_8026_2_1: |
| 438 | case QPNP_REV_ID_8026_2_2: |
| 439 | /* pm8026 rev 2.1 and 2.2 */ |
| 440 | switch (iadc->iadc_comp.id) { |
| 441 | case COMP_ID_GF: |
| 442 | if (!iadc->iadc_comp.ext_rsense) { |
| 443 | /* internal rsense */ |
| 444 | if (*result < 0) { |
| 445 | /* charge */ |
| 446 | coeff_a = 0; |
| 447 | coeff_b = 0; |
| 448 | } else { |
| 449 | coeff_a = QPNP_COEFF_25; |
| 450 | coeff_b = 0; |
| 451 | } |
| 452 | } else { |
| 453 | if (*result < 0) { |
| 454 | /* charge */ |
| 455 | coeff_a = 0; |
| 456 | coeff_b = 0; |
| 457 | } else { |
| 458 | /* discharge */ |
| 459 | coeff_a = 0; |
| 460 | coeff_b = 0; |
| 461 | } |
| 462 | } |
| 463 | break; |
| 464 | case COMP_ID_TSMC: |
| 465 | default: |
| 466 | if (!iadc->iadc_comp.ext_rsense) { |
| 467 | /* internal rsense */ |
| 468 | if (*result < 0) { |
| 469 | /* charge */ |
| 470 | coeff_a = 0; |
| 471 | coeff_b = 0; |
| 472 | } else { |
| 473 | coeff_a = QPNP_COEFF_26; |
| 474 | coeff_b = 0; |
| 475 | } |
| 476 | } else { |
| 477 | if (*result < 0) { |
| 478 | /* charge */ |
| 479 | coeff_a = 0; |
| 480 | coeff_b = 0; |
| 481 | } else { |
| 482 | /* discharge */ |
| 483 | coeff_a = 0; |
| 484 | coeff_b = 0; |
| 485 | } |
| 486 | } |
| 487 | break; |
| 488 | } |
| 489 | break; |
| 490 | case QPNP_REV_ID_8026_1_0: |
| 491 | /* pm8026 rev 1.0 */ |
| 492 | switch (iadc->iadc_comp.id) { |
| 493 | case COMP_ID_GF: |
| 494 | if (!iadc->iadc_comp.ext_rsense) { |
| 495 | /* internal rsense */ |
| 496 | if (*result < 0) { |
| 497 | /* charge */ |
| 498 | coeff_a = QPNP_COEFF_9; |
| 499 | coeff_b = -QPNP_COEFF_17; |
| 500 | } else { |
| 501 | coeff_a = QPNP_COEFF_10; |
| 502 | coeff_b = QPNP_COEFF_18; |
| 503 | } |
| 504 | } else { |
| 505 | if (*result < 0) { |
| 506 | /* charge */ |
| 507 | coeff_a = -QPNP_COEFF_11; |
| 508 | coeff_b = 0; |
| 509 | } else { |
| 510 | /* discharge */ |
| 511 | coeff_a = -QPNP_COEFF_17; |
| 512 | coeff_b = -QPNP_COEFF_19; |
| 513 | } |
| 514 | } |
| 515 | break; |
| 516 | case COMP_ID_TSMC: |
| 517 | default: |
| 518 | if (!iadc->iadc_comp.ext_rsense) { |
| 519 | /* internal rsense */ |
| 520 | if (*result < 0) { |
| 521 | /* charge */ |
| 522 | coeff_a = QPNP_COEFF_13; |
| 523 | coeff_b = -QPNP_COEFF_20; |
| 524 | } else { |
| 525 | coeff_a = QPNP_COEFF_14; |
| 526 | coeff_b = QPNP_COEFF_21; |
| 527 | } |
| 528 | } else { |
| 529 | if (*result < 0) { |
| 530 | /* charge */ |
| 531 | coeff_a = -QPNP_COEFF_15; |
| 532 | coeff_b = 0; |
| 533 | } else { |
| 534 | /* discharge */ |
| 535 | coeff_a = -QPNP_COEFF_12; |
| 536 | coeff_b = -QPNP_COEFF_19; |
| 537 | } |
| 538 | } |
| 539 | break; |
| 540 | } |
| 541 | break; |
| 542 | case QPNP_REV_ID_8110_1_0: |
| 543 | /* pm8110 rev 1.0 */ |
| 544 | switch (iadc->iadc_comp.id) { |
| 545 | case COMP_ID_GF: |
| 546 | if (!iadc->iadc_comp.ext_rsense) { |
| 547 | /* internal rsense */ |
| 548 | if (*result < 0) { |
| 549 | /* charge */ |
| 550 | coeff_a = QPNP_COEFF_24; |
| 551 | coeff_b = -QPNP_COEFF_22; |
| 552 | } else { |
| 553 | coeff_a = QPNP_COEFF_24; |
| 554 | coeff_b = -QPNP_COEFF_23; |
| 555 | } |
| 556 | } |
| 557 | break; |
| 558 | case COMP_ID_SMIC: |
| 559 | default: |
| 560 | if (!iadc->iadc_comp.ext_rsense) { |
| 561 | /* internal rsense */ |
| 562 | if (*result < 0) { |
| 563 | /* charge */ |
| 564 | coeff_a = QPNP_COEFF_24; |
| 565 | coeff_b = -QPNP_COEFF_22; |
| 566 | } else { |
| 567 | coeff_a = QPNP_COEFF_24; |
| 568 | coeff_b = -QPNP_COEFF_23; |
| 569 | } |
| 570 | } |
| 571 | break; |
| 572 | } |
| 573 | break; |
| 574 | case QPNP_REV_ID_8110_2_0: |
| 575 | die_temp -= 25000; |
| 576 | /* pm8110 rev 2.0 */ |
| 577 | switch (iadc->iadc_comp.id) { |
| 578 | case COMP_ID_GF: |
| 579 | if (!iadc->iadc_comp.ext_rsense) { |
| 580 | /* internal rsense */ |
| 581 | if (*result < 0) { |
| 582 | /* charge */ |
| 583 | coeff_a = 0; |
| 584 | coeff_b = 0; |
| 585 | } else { |
| 586 | coeff_a = QPNP_COEFF_27; |
| 587 | coeff_b = 0; |
| 588 | } |
| 589 | } |
| 590 | break; |
| 591 | case COMP_ID_SMIC: |
| 592 | default: |
| 593 | if (!iadc->iadc_comp.ext_rsense) { |
| 594 | /* internal rsense */ |
| 595 | if (*result < 0) { |
| 596 | /* charge */ |
| 597 | coeff_a = 0; |
| 598 | coeff_b = 0; |
| 599 | } else { |
| 600 | coeff_a = QPNP_COEFF_28; |
| 601 | coeff_b = 0; |
| 602 | } |
| 603 | } |
| 604 | break; |
| 605 | } |
| 606 | break; |
| 607 | default: |
| 608 | case QPNP_REV_ID_8026_2_0: |
| 609 | /* pm8026 rev 1.0 */ |
| 610 | coeff_a = 0; |
| 611 | coeff_b = 0; |
| 612 | break; |
| 613 | } |
| 614 | |
| 615 | temp_var = (coeff_a * die_temp) + coeff_b; |
| 616 | temp_var = div64_s64(temp_var, QPNP_COEFF_4); |
| 617 | temp_var = 1000 * (1000000 - temp_var); |
| 618 | |
| 619 | if (!iadc->iadc_comp.ext_rsense) { |
| 620 | /* internal rsense */ |
| 621 | *result = div64_s64(*result * 1000, temp_var); |
| 622 | } |
| 623 | |
| 624 | if (iadc->iadc_comp.ext_rsense) { |
| 625 | /* external rsense */ |
| 626 | sys_gain_coeff = (1000000 + |
| 627 | div64_s64(sys_gain_coeff, QPNP_COEFF_4)); |
| 628 | temp_var = div64_s64(temp_var * sys_gain_coeff, 1000000); |
| 629 | *result = div64_s64(*result * 1000, temp_var); |
| 630 | } |
| 631 | pr_debug("%lld compensated into %lld, a: %d, b: %d, sys_gain: %lld\n", |
| 632 | old, *result, coeff_a, coeff_b, sys_gain_coeff); |
| 633 | |
| 634 | return 0; |
| 635 | } |
| 636 | |
| 637 | int32_t qpnp_iadc_comp_result(struct qpnp_iadc_chip *iadc, int64_t *result) |
| 638 | { |
| 639 | return qpnp_iadc_comp(result, iadc, iadc->die_temp); |
| 640 | } |
| 641 | EXPORT_SYMBOL(qpnp_iadc_comp_result); |
| 642 | |
| 643 | static int qpnp_iadc_rds_trim_update_check(struct qpnp_iadc_chip *iadc) |
| 644 | { |
| 645 | int rc = 0; |
| 646 | u8 trim2_val = 0; |
| 647 | uint smbb_batt_trm_data = 0; |
| 648 | u8 smbb_batt_trm_cnst_rds = 0; |
| 649 | |
| 650 | if (!iadc->rds_trim_default_check) { |
| 651 | pr_debug("No internal rds trim check needed\n"); |
| 652 | return 0; |
| 653 | } |
| 654 | |
| 655 | rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_NOMINAL_RSENSE, &trim2_val); |
| 656 | if (rc < 0) { |
| 657 | pr_err("qpnp adc trim2_fullscale1 reg read failed %d\n", rc); |
| 658 | return rc; |
| 659 | } |
| 660 | |
| 661 | rc = regmap_read(iadc->adc->regmap, iadc->batt_id_trim_cnst_rds, |
| 662 | &smbb_batt_trm_data); |
| 663 | if (rc < 0) { |
| 664 | pr_err("batt_id trim_cnst rds reg read failed %d\n", rc); |
| 665 | return rc; |
| 666 | } |
| 667 | |
| 668 | smbb_batt_trm_cnst_rds = (u8)smbb_batt_trm_data & |
| 669 | SMBB_BAT_IF_TRIM_CNST_RDS_MASK; |
| 670 | |
| 671 | pr_debug("n_trim:0x%x smb_trm:0x%02x\n", trim2_val, smbb_batt_trm_data); |
| 672 | |
| 673 | if (iadc->rds_trim_default_type == QPNP_IADC_RDS_DEFAULT_TYPEA) { |
| 674 | |
| 675 | if ((smbb_batt_trm_cnst_rds == |
| 676 | SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2) && |
| 677 | (trim2_val == QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST)) { |
| 678 | iadc->rsense_workaround_value = |
| 679 | QPNP_IADC_RSENSE_DEFAULT_VALUE; |
| 680 | iadc->default_internal_rsense = true; |
| 681 | } |
| 682 | } else if (iadc->rds_trim_default_type == |
| 683 | QPNP_IADC_RDS_DEFAULT_TYPEB) { |
| 684 | if ((smbb_batt_trm_cnst_rds >= |
| 685 | SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2) && |
| 686 | (trim2_val == QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST)) { |
| 687 | iadc->rsense_workaround_value = |
| 688 | QPNP_IADC_RSENSE_DEFAULT_VALUE; |
| 689 | iadc->default_internal_rsense = true; |
| 690 | } else if ((smbb_batt_trm_cnst_rds < |
| 691 | SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2) && |
| 692 | (trim2_val == |
| 693 | QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST)) { |
| 694 | if (iadc->iadc_comp.id == COMP_ID_GF) { |
| 695 | iadc->rsense_workaround_value = |
| 696 | QPNP_IADC_RSENSE_DEFAULT_TYPEB_GF; |
| 697 | iadc->default_internal_rsense = true; |
| 698 | } else if (iadc->iadc_comp.id == COMP_ID_SMIC) { |
| 699 | iadc->rsense_workaround_value = |
| 700 | QPNP_IADC_RSENSE_DEFAULT_TYPEB_SMIC; |
| 701 | iadc->default_internal_rsense = true; |
| 702 | } |
| 703 | } |
| 704 | } else if (iadc->rds_trim_default_type == QPNP_IADC_RDS_DEFAULT_TYPEC) { |
| 705 | |
| 706 | if ((smbb_batt_trm_cnst_rds > |
| 707 | SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_0) && |
| 708 | (smbb_batt_trm_cnst_rds <= |
| 709 | SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2) && |
| 710 | (trim2_val == QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST)) { |
| 711 | iadc->rsense_workaround_value = |
| 712 | QPNP_IADC_RSENSE_DEFAULT_VALUE; |
| 713 | iadc->default_internal_rsense = true; |
| 714 | } |
| 715 | } |
| 716 | |
| 717 | return 0; |
| 718 | } |
| 719 | |
| 720 | static int32_t qpnp_iadc_comp_info(struct qpnp_iadc_chip *iadc) |
| 721 | { |
| 722 | int rc = 0; |
| 723 | |
| 724 | rc = qpnp_iadc_read_reg(iadc, QPNP_INT_TEST_VAL, &iadc->iadc_comp.id); |
| 725 | if (rc < 0) { |
| 726 | pr_err("qpnp adc comp id failed with %d\n", rc); |
| 727 | return rc; |
| 728 | } |
| 729 | |
| 730 | rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_REVISION2, |
| 731 | &iadc->iadc_comp.revision_dig_major); |
| 732 | if (rc < 0) { |
| 733 | pr_err("qpnp adc revision2 read failed with %d\n", rc); |
| 734 | return rc; |
| 735 | } |
| 736 | |
| 737 | rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_REVISION3, |
| 738 | &iadc->iadc_comp.revision_ana_minor); |
| 739 | if (rc < 0) { |
| 740 | pr_err("qpnp adc revision3 read failed with %d\n", rc); |
| 741 | return rc; |
| 742 | } |
| 743 | |
| 744 | rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_ATE_GAIN_CALIB_OFFSET, |
| 745 | &iadc->iadc_comp.sys_gain); |
| 746 | if (rc < 0) { |
| 747 | pr_err("full scale read failed with %d\n", rc); |
| 748 | return rc; |
| 749 | } |
| 750 | |
| 751 | if (iadc->external_rsense) |
| 752 | iadc->iadc_comp.ext_rsense = true; |
| 753 | |
| 754 | pr_debug("fab id = %u, revision_dig_major = %u, revision_ana_minor = %u sys gain = %u, external_rsense = %d\n", |
| 755 | iadc->iadc_comp.id, |
| 756 | iadc->iadc_comp.revision_dig_major, |
| 757 | iadc->iadc_comp.revision_ana_minor, |
| 758 | iadc->iadc_comp.sys_gain, |
| 759 | iadc->iadc_comp.ext_rsense); |
| 760 | return rc; |
| 761 | } |
| 762 | |
| 763 | static int32_t qpnp_iadc_configure(struct qpnp_iadc_chip *iadc, |
| 764 | enum qpnp_iadc_channels channel, |
| 765 | uint16_t *raw_code, uint32_t mode_sel) |
| 766 | { |
| 767 | u8 qpnp_iadc_mode_reg = 0, qpnp_iadc_ch_sel_reg = 0; |
| 768 | u8 qpnp_iadc_conv_req = 0, qpnp_iadc_dig_param_reg = 0; |
| 769 | u8 status1 = 0; |
| 770 | uint32_t count = 0; |
| 771 | int32_t rc = 0; |
| 772 | |
| 773 | qpnp_iadc_ch_sel_reg = channel; |
| 774 | |
| 775 | qpnp_iadc_dig_param_reg |= iadc->adc->amux_prop->decimation << |
| 776 | QPNP_IADC_DEC_RATIO_SEL; |
| 777 | if (iadc->iadc_mode_sel) |
| 778 | qpnp_iadc_mode_reg |= (QPNP_ADC_TRIM_EN | QPNP_VADC_SYNCH_EN); |
| 779 | else |
| 780 | qpnp_iadc_mode_reg |= QPNP_ADC_TRIM_EN; |
| 781 | |
| 782 | qpnp_iadc_conv_req = QPNP_IADC_CONV_REQ; |
| 783 | |
| 784 | rc = qpnp_iadc_write_reg(iadc, QPNP_IADC_MODE_CTL, qpnp_iadc_mode_reg); |
| 785 | if (rc) { |
| 786 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 787 | return rc; |
| 788 | } |
| 789 | |
| 790 | rc = qpnp_iadc_write_reg(iadc, QPNP_IADC_ADC_CH_SEL_CTL, |
| 791 | qpnp_iadc_ch_sel_reg); |
| 792 | if (rc) { |
| 793 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 794 | return rc; |
| 795 | } |
| 796 | |
| 797 | rc = qpnp_iadc_write_reg(iadc, QPNP_ADC_DIG_PARAM, |
| 798 | qpnp_iadc_dig_param_reg); |
| 799 | if (rc) { |
| 800 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 801 | return rc; |
| 802 | } |
| 803 | |
| 804 | rc = qpnp_iadc_write_reg(iadc, QPNP_FAST_AVG_CTL, |
| 805 | iadc->adc->amux_prop->fast_avg_setup); |
| 806 | if (rc < 0) { |
| 807 | pr_err("qpnp adc fast averaging configure error\n"); |
| 808 | return rc; |
| 809 | } |
| 810 | |
| 811 | if (!iadc->iadc_poll_eoc) |
| 812 | reinit_completion(&iadc->adc->adc_rslt_completion); |
| 813 | |
| 814 | rc = qpnp_iadc_enable(iadc, true); |
| 815 | if (rc) |
| 816 | return rc; |
| 817 | |
| 818 | rc = qpnp_iadc_write_reg(iadc, QPNP_CONV_REQ, qpnp_iadc_conv_req); |
| 819 | if (rc) { |
| 820 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 821 | return rc; |
| 822 | } |
| 823 | |
| 824 | if (iadc->iadc_poll_eoc) { |
| 825 | while (status1 != QPNP_STATUS1_EOC) { |
| 826 | rc = qpnp_iadc_read_reg(iadc, QPNP_STATUS1, &status1); |
| 827 | if (rc < 0) |
| 828 | return rc; |
| 829 | status1 &= QPNP_STATUS1_REQ_STS_EOC_MASK; |
| 830 | usleep_range(QPNP_ADC_CONV_TIME_MIN, |
| 831 | QPNP_ADC_CONV_TIME_MAX); |
| 832 | count++; |
| 833 | if (count > QPNP_ADC_ERR_COUNT) { |
| 834 | pr_err("retry error exceeded\n"); |
| 835 | rc = qpnp_iadc_status_debug(iadc); |
| 836 | if (rc < 0) |
| 837 | pr_err("IADC status debug failed\n"); |
| 838 | rc = -EINVAL; |
| 839 | return rc; |
| 840 | } |
| 841 | } |
| 842 | } else { |
| 843 | rc = wait_for_completion_timeout( |
| 844 | &iadc->adc->adc_rslt_completion, |
| 845 | QPNP_ADC_COMPLETION_TIMEOUT); |
| 846 | if (!rc) { |
| 847 | rc = qpnp_iadc_read_reg(iadc, QPNP_STATUS1, &status1); |
| 848 | if (rc < 0) |
| 849 | return rc; |
| 850 | status1 &= QPNP_STATUS1_REQ_STS_EOC_MASK; |
| 851 | if (status1 == QPNP_STATUS1_EOC) |
| 852 | pr_debug("End of conversion status set\n"); |
| 853 | else { |
| 854 | rc = qpnp_iadc_status_debug(iadc); |
| 855 | if (rc < 0) { |
| 856 | pr_err("status debug failed %d\n", rc); |
| 857 | return rc; |
| 858 | } |
| 859 | return -EINVAL; |
| 860 | } |
| 861 | } |
| 862 | } |
| 863 | |
| 864 | rc = qpnp_iadc_read_conversion_result(iadc, raw_code); |
| 865 | if (rc) { |
| 866 | pr_err("qpnp adc read adc failed with %d\n", rc); |
| 867 | return rc; |
| 868 | } |
| 869 | |
| 870 | return 0; |
| 871 | } |
| 872 | |
| 873 | #define IADC_CENTER 0xC000 |
| 874 | #define IADC_READING_RESOLUTION_N 542535 |
| 875 | #define IADC_READING_RESOLUTION_D 100000 |
| 876 | static int32_t qpnp_convert_raw_offset_voltage(struct qpnp_iadc_chip *iadc) |
| 877 | { |
| 878 | s64 numerator; |
| 879 | |
| 880 | if ((iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw) == 0) { |
| 881 | pr_err("raw offset errors! raw_gain:0x%x and raw_offset:0x%x\n", |
| 882 | iadc->adc->calib.gain_raw, iadc->adc->calib.offset_raw); |
| 883 | return -EINVAL; |
| 884 | } |
| 885 | |
| 886 | numerator = iadc->adc->calib.offset_raw - IADC_CENTER; |
| 887 | numerator *= IADC_READING_RESOLUTION_N; |
| 888 | iadc->adc->calib.offset_uv = div_s64(numerator, |
| 889 | IADC_READING_RESOLUTION_D); |
| 890 | |
| 891 | numerator = iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw; |
| 892 | numerator *= IADC_READING_RESOLUTION_N; |
| 893 | |
| 894 | iadc->adc->calib.gain_uv = div_s64(numerator, |
| 895 | IADC_READING_RESOLUTION_D); |
| 896 | |
| 897 | pr_debug("gain_uv:%d offset_uv:%d\n", |
| 898 | iadc->adc->calib.gain_uv, iadc->adc->calib.offset_uv); |
| 899 | return 0; |
| 900 | } |
| 901 | |
| 902 | #define IADC_IDEAL_RAW_GAIN 3291 |
| 903 | int32_t qpnp_iadc_calibrate_for_trim(struct qpnp_iadc_chip *iadc, |
| 904 | bool batfet_closed) |
| 905 | { |
| 906 | uint8_t rslt_lsb, rslt_msb; |
| 907 | int32_t rc = 0, version = 0; |
| 908 | uint16_t raw_data; |
| 909 | uint32_t mode_sel = 0; |
| 910 | bool iadc_offset_ch_batfet_check; |
| 911 | |
| 912 | if (qpnp_iadc_is_valid(iadc) < 0) |
| 913 | return -EPROBE_DEFER; |
| 914 | |
| 915 | mutex_lock(&iadc->adc->adc_lock); |
| 916 | |
| 917 | if (iadc->iadc_poll_eoc) { |
| 918 | pr_debug("acquiring iadc eoc wakelock\n"); |
| 919 | pm_stay_awake(iadc->dev); |
| 920 | } |
| 921 | |
| 922 | iadc->adc->amux_prop->decimation = DECIMATION_TYPE1; |
| 923 | iadc->adc->amux_prop->fast_avg_setup = ADC_FAST_AVG_SAMPLE_1; |
| 924 | |
| 925 | rc = qpnp_iadc_configure(iadc, GAIN_CALIBRATION_17P857MV, |
| 926 | &raw_data, mode_sel); |
| 927 | if (rc < 0) { |
| 928 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 929 | goto fail; |
| 930 | } |
| 931 | |
| 932 | iadc->adc->calib.gain_raw = raw_data; |
| 933 | |
| 934 | /* |
| 935 | * there is a features on PM8941 in the BMS where if the batfet is |
| 936 | * opened the BMS reads from INTERNAL_RSENSE (channel 0) actually go to |
| 937 | * OFFSET_CALIBRATION_CSP_CSN (channel 5). Hence if batfet is opened |
| 938 | * we have to calibrate based on OFFSET_CALIBRATION_CSP_CSN even for |
| 939 | * internal rsense. |
| 940 | */ |
| 941 | version = qpnp_adc_get_revid_version(iadc->dev); |
| 942 | if ((version == QPNP_REV_ID_8941_3_1) || |
| 943 | (version == QPNP_REV_ID_8941_3_0) || |
| 944 | (version == QPNP_REV_ID_8941_2_0)) |
| 945 | iadc_offset_ch_batfet_check = true; |
| 946 | else |
| 947 | iadc_offset_ch_batfet_check = false; |
| 948 | |
| 949 | if ((iadc_offset_ch_batfet_check && !batfet_closed) || |
| 950 | (iadc->external_rsense)) { |
| 951 | /* external offset calculation */ |
| 952 | rc = qpnp_iadc_configure(iadc, OFFSET_CALIBRATION_CSP_CSN, |
| 953 | &raw_data, mode_sel); |
| 954 | if (rc < 0) { |
| 955 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 956 | goto fail; |
| 957 | } |
| 958 | } else { |
| 959 | /* internal offset calculation */ |
| 960 | rc = qpnp_iadc_configure(iadc, OFFSET_CALIBRATION_CSP2_CSN2, |
| 961 | &raw_data, mode_sel); |
| 962 | if (rc < 0) { |
| 963 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 964 | goto fail; |
| 965 | } |
| 966 | } |
| 967 | |
| 968 | iadc->adc->calib.offset_raw = raw_data; |
| 969 | if (rc < 0) { |
| 970 | pr_err("qpnp adc offset/gain calculation failed\n"); |
| 971 | goto fail; |
| 972 | } |
| 973 | |
| 974 | if (iadc->iadc_comp.revision_dig_major == QPNP_IADC_PM8026_2_REV2 |
| 975 | && iadc->iadc_comp.revision_ana_minor == |
| 976 | QPNP_IADC_PM8026_2_REV3) |
| 977 | iadc->adc->calib.gain_raw = |
| 978 | iadc->adc->calib.offset_raw + IADC_IDEAL_RAW_GAIN; |
| 979 | |
| 980 | pr_debug("raw gain:0x%x, raw offset:0x%x\n", |
| 981 | iadc->adc->calib.gain_raw, iadc->adc->calib.offset_raw); |
| 982 | |
| 983 | rc = qpnp_convert_raw_offset_voltage(iadc); |
| 984 | if (rc < 0) { |
| 985 | pr_err("qpnp raw_voltage conversion failed\n"); |
| 986 | goto fail; |
| 987 | } |
| 988 | |
| 989 | rslt_msb = (raw_data & QPNP_RAW_CODE_16_BIT_MSB_MASK) >> |
| 990 | QPNP_BIT_SHIFT_8; |
| 991 | rslt_lsb = raw_data & QPNP_RAW_CODE_16_BIT_LSB_MASK; |
| 992 | |
| 993 | pr_debug("trim values:lsb:0x%x and msb:0x%x\n", rslt_lsb, rslt_msb); |
| 994 | |
| 995 | rc = qpnp_iadc_write_reg(iadc, QPNP_IADC_SEC_ACCESS, |
| 996 | QPNP_IADC_SEC_ACCESS_DATA); |
| 997 | if (rc < 0) { |
| 998 | pr_err("qpnp iadc configure error for sec access\n"); |
| 999 | goto fail; |
| 1000 | } |
| 1001 | |
| 1002 | rc = qpnp_iadc_write_reg(iadc, QPNP_IADC_MSB_OFFSET, |
| 1003 | rslt_msb); |
| 1004 | if (rc < 0) { |
| 1005 | pr_err("qpnp iadc configure error for MSB write\n"); |
| 1006 | goto fail; |
| 1007 | } |
| 1008 | |
| 1009 | rc = qpnp_iadc_write_reg(iadc, QPNP_IADC_SEC_ACCESS, |
| 1010 | QPNP_IADC_SEC_ACCESS_DATA); |
| 1011 | if (rc < 0) { |
| 1012 | pr_err("qpnp iadc configure error for sec access\n"); |
| 1013 | goto fail; |
| 1014 | } |
| 1015 | |
| 1016 | rc = qpnp_iadc_write_reg(iadc, QPNP_IADC_LSB_OFFSET, |
| 1017 | rslt_lsb); |
| 1018 | if (rc < 0) { |
| 1019 | pr_err("qpnp iadc configure error for LSB write\n"); |
| 1020 | goto fail; |
| 1021 | } |
| 1022 | fail: |
| 1023 | if (iadc->iadc_poll_eoc) { |
| 1024 | pr_debug("releasing iadc eoc wakelock\n"); |
| 1025 | pm_relax(iadc->dev); |
| 1026 | } |
| 1027 | mutex_unlock(&iadc->adc->adc_lock); |
| 1028 | return rc; |
| 1029 | } |
| 1030 | EXPORT_SYMBOL(qpnp_iadc_calibrate_for_trim); |
| 1031 | |
| 1032 | static void qpnp_iadc_work(struct work_struct *work) |
| 1033 | { |
| 1034 | struct qpnp_iadc_chip *iadc = container_of(work, |
| 1035 | struct qpnp_iadc_chip, iadc_work.work); |
| 1036 | int rc = 0; |
| 1037 | |
| 1038 | if (!iadc->skip_auto_calibrations) { |
| 1039 | rc = qpnp_iadc_calibrate_for_trim(iadc, true); |
| 1040 | if (rc) |
| 1041 | pr_debug("periodic IADC calibration failed\n"); |
| 1042 | } |
| 1043 | |
| 1044 | schedule_delayed_work(&iadc->iadc_work, |
| 1045 | round_jiffies_relative(msecs_to_jiffies |
| 1046 | (QPNP_IADC_CALIB_SECONDS))); |
| 1047 | } |
| 1048 | |
| 1049 | static int32_t qpnp_iadc_version_check(struct qpnp_iadc_chip *iadc) |
| 1050 | { |
| 1051 | uint8_t revision; |
| 1052 | int rc; |
| 1053 | |
| 1054 | rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_REVISION2, &revision); |
| 1055 | if (rc < 0) { |
| 1056 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 1057 | return rc; |
| 1058 | } |
| 1059 | |
| 1060 | if (revision < QPNP_IADC_SUPPORTED_REVISION2) { |
| 1061 | pr_err("IADC Version not supported\n"); |
| 1062 | return -EINVAL; |
| 1063 | } |
| 1064 | |
| 1065 | return 0; |
| 1066 | } |
| 1067 | |
| 1068 | struct qpnp_iadc_chip *qpnp_get_iadc(struct device *dev, const char *name) |
| 1069 | { |
| 1070 | struct qpnp_iadc_chip *iadc; |
| 1071 | struct device_node *node = NULL; |
| 1072 | char prop_name[QPNP_MAX_PROP_NAME_LEN]; |
| 1073 | |
| 1074 | snprintf(prop_name, QPNP_MAX_PROP_NAME_LEN, "qcom,%s-iadc", name); |
| 1075 | |
| 1076 | node = of_parse_phandle(dev->of_node, prop_name, 0); |
| 1077 | if (node == NULL) |
| 1078 | return ERR_PTR(-ENODEV); |
| 1079 | |
| 1080 | list_for_each_entry(iadc, &qpnp_iadc_device_list, list) |
| 1081 | if (iadc->adc->pdev->dev.of_node == node) |
| 1082 | return iadc; |
| 1083 | return ERR_PTR(-EPROBE_DEFER); |
| 1084 | } |
| 1085 | EXPORT_SYMBOL(qpnp_get_iadc); |
| 1086 | |
| 1087 | int32_t qpnp_iadc_get_rsense(struct qpnp_iadc_chip *iadc, int32_t *rsense) |
| 1088 | { |
| 1089 | uint8_t rslt_rsense = 0; |
| 1090 | int32_t rc = 0, sign_bit = 0; |
| 1091 | |
| 1092 | if (qpnp_iadc_is_valid(iadc) < 0) |
| 1093 | return -EPROBE_DEFER; |
| 1094 | |
| 1095 | if (iadc->external_rsense) { |
| 1096 | *rsense = iadc->rsense; |
| 1097 | } else if (iadc->default_internal_rsense) { |
| 1098 | *rsense = iadc->rsense_workaround_value; |
| 1099 | } else { |
| 1100 | |
| 1101 | rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_NOMINAL_RSENSE, |
| 1102 | &rslt_rsense); |
| 1103 | if (rc < 0) { |
| 1104 | pr_err("qpnp adc rsense read failed with %d\n", rc); |
| 1105 | return rc; |
| 1106 | } |
| 1107 | |
| 1108 | pr_debug("rsense:0%x\n", rslt_rsense); |
| 1109 | |
| 1110 | if (rslt_rsense & QPNP_RSENSE_MSB_SIGN_CHECK) |
| 1111 | sign_bit = 1; |
| 1112 | |
| 1113 | rslt_rsense &= ~QPNP_RSENSE_MSB_SIGN_CHECK; |
| 1114 | |
| 1115 | if (sign_bit) |
| 1116 | *rsense = QPNP_IADC_INTERNAL_RSENSE_N_OHMS_FACTOR - |
| 1117 | (rslt_rsense * QPNP_IADC_RSENSE_LSB_N_OHMS_PER_BIT); |
| 1118 | else |
| 1119 | *rsense = QPNP_IADC_INTERNAL_RSENSE_N_OHMS_FACTOR + |
| 1120 | (rslt_rsense * QPNP_IADC_RSENSE_LSB_N_OHMS_PER_BIT); |
| 1121 | } |
| 1122 | pr_debug("rsense value is %d\n", *rsense); |
| 1123 | |
| 1124 | if (*rsense == 0) |
| 1125 | pr_err("incorrect rsens value:%d rslt_rsense:%d\n", |
| 1126 | *rsense, rslt_rsense); |
| 1127 | |
| 1128 | return rc; |
| 1129 | } |
| 1130 | EXPORT_SYMBOL(qpnp_iadc_get_rsense); |
| 1131 | |
| 1132 | static int32_t qpnp_check_pmic_temp(struct qpnp_iadc_chip *iadc) |
| 1133 | { |
| 1134 | struct qpnp_vadc_result result_pmic_therm; |
| 1135 | int64_t die_temp_offset; |
| 1136 | int rc = 0; |
| 1137 | |
| 1138 | rc = qpnp_vadc_read(iadc->vadc_dev, DIE_TEMP, &result_pmic_therm); |
| 1139 | if (rc < 0) |
| 1140 | return rc; |
| 1141 | |
| 1142 | die_temp_offset = result_pmic_therm.physical - |
| 1143 | iadc->die_temp; |
| 1144 | if (die_temp_offset < 0) |
| 1145 | die_temp_offset = -die_temp_offset; |
| 1146 | |
| 1147 | if (die_temp_offset > QPNP_IADC_DIE_TEMP_CALIB_OFFSET) { |
| 1148 | iadc->die_temp = result_pmic_therm.physical; |
| 1149 | if (!iadc->skip_auto_calibrations) { |
| 1150 | rc = qpnp_iadc_calibrate_for_trim(iadc, true); |
| 1151 | if (rc) |
| 1152 | pr_err("IADC calibration failed rc = %d\n", rc); |
| 1153 | } |
| 1154 | } |
| 1155 | |
| 1156 | return rc; |
| 1157 | } |
| 1158 | |
| 1159 | int32_t qpnp_iadc_read(struct qpnp_iadc_chip *iadc, |
| 1160 | enum qpnp_iadc_channels channel, |
| 1161 | struct qpnp_iadc_result *result) |
| 1162 | { |
| 1163 | int32_t rc, rsense_n_ohms, sign = 0, num, mode_sel = 0; |
| 1164 | int32_t rsense_u_ohms = 0; |
| 1165 | int64_t result_current; |
| 1166 | uint16_t raw_data; |
| 1167 | int dt_index = 0; |
| 1168 | |
| 1169 | if (qpnp_iadc_is_valid(iadc) < 0) |
| 1170 | return -EPROBE_DEFER; |
| 1171 | |
| 1172 | if ((iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw) == 0) { |
| 1173 | pr_err("raw offset errors! run iadc calibration again\n"); |
| 1174 | return -EINVAL; |
| 1175 | } |
| 1176 | |
| 1177 | rc = qpnp_check_pmic_temp(iadc); |
| 1178 | if (rc) { |
| 1179 | pr_err("Error checking pmic therm temp\n"); |
| 1180 | return rc; |
| 1181 | } |
| 1182 | |
| 1183 | mutex_lock(&iadc->adc->adc_lock); |
| 1184 | |
| 1185 | while (((enum qpnp_iadc_channels) |
| 1186 | iadc->adc->adc_channels[dt_index].channel_num |
| 1187 | != channel) && (dt_index < iadc->max_channels_available)) |
| 1188 | dt_index++; |
| 1189 | |
| 1190 | if (dt_index >= iadc->max_channels_available) { |
| 1191 | pr_err("not a valid IADC channel\n"); |
| 1192 | rc = -EINVAL; |
| 1193 | goto fail; |
| 1194 | } |
| 1195 | |
| 1196 | iadc->adc->amux_prop->decimation = |
| 1197 | iadc->adc->adc_channels[dt_index].adc_decimation; |
| 1198 | iadc->adc->amux_prop->fast_avg_setup = |
| 1199 | iadc->adc->adc_channels[dt_index].fast_avg_setup; |
| 1200 | |
| 1201 | if (iadc->iadc_poll_eoc) { |
| 1202 | pr_debug("acquiring iadc eoc wakelock\n"); |
| 1203 | pm_stay_awake(iadc->dev); |
| 1204 | } |
| 1205 | |
| 1206 | rc = qpnp_iadc_configure(iadc, channel, &raw_data, mode_sel); |
| 1207 | if (rc < 0) { |
| 1208 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 1209 | goto fail; |
| 1210 | } |
| 1211 | |
| 1212 | rc = qpnp_iadc_get_rsense(iadc, &rsense_n_ohms); |
| 1213 | pr_debug("current raw:0%x and rsense:%d\n", |
| 1214 | raw_data, rsense_n_ohms); |
| 1215 | rsense_u_ohms = rsense_n_ohms/1000; |
| 1216 | num = raw_data - iadc->adc->calib.offset_raw; |
| 1217 | if (num < 0) { |
| 1218 | sign = 1; |
| 1219 | num = -num; |
| 1220 | } |
| 1221 | |
| 1222 | result->result_uv = (num * QPNP_ADC_GAIN_NV)/ |
| 1223 | (iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw); |
| 1224 | result_current = result->result_uv; |
| 1225 | result_current *= QPNP_IADC_NANO_VOLTS_FACTOR; |
| 1226 | /* Intentional fall through. Process the result w/o comp */ |
| 1227 | do_div(result_current, rsense_u_ohms); |
| 1228 | |
| 1229 | if (sign) { |
| 1230 | result->result_uv = -result->result_uv; |
| 1231 | result_current = -result_current; |
| 1232 | } |
| 1233 | result_current *= -1; |
| 1234 | rc = qpnp_iadc_comp_result(iadc, &result_current); |
| 1235 | if (rc < 0) |
| 1236 | pr_err("Error during compensating the IADC\n"); |
| 1237 | rc = 0; |
| 1238 | result_current *= -1; |
| 1239 | |
| 1240 | result->result_ua = (int32_t) result_current; |
| 1241 | fail: |
| 1242 | if (iadc->iadc_poll_eoc) { |
| 1243 | pr_debug("releasing iadc eoc wakelock\n"); |
| 1244 | pm_relax(iadc->dev); |
| 1245 | } |
| 1246 | mutex_unlock(&iadc->adc->adc_lock); |
| 1247 | |
| 1248 | return rc; |
| 1249 | } |
| 1250 | EXPORT_SYMBOL(qpnp_iadc_read); |
| 1251 | |
| 1252 | int32_t qpnp_iadc_get_gain_and_offset(struct qpnp_iadc_chip *iadc, |
| 1253 | struct qpnp_iadc_calib *result) |
| 1254 | { |
| 1255 | int rc; |
| 1256 | |
| 1257 | if (qpnp_iadc_is_valid(iadc) < 0) |
| 1258 | return -EPROBE_DEFER; |
| 1259 | |
| 1260 | rc = qpnp_check_pmic_temp(iadc); |
| 1261 | if (rc) { |
| 1262 | pr_err("Error checking pmic therm temp\n"); |
| 1263 | return rc; |
| 1264 | } |
| 1265 | |
| 1266 | mutex_lock(&iadc->adc->adc_lock); |
| 1267 | result->gain_raw = iadc->adc->calib.gain_raw; |
| 1268 | result->ideal_gain_nv = QPNP_ADC_GAIN_NV; |
| 1269 | result->gain_uv = iadc->adc->calib.gain_uv; |
| 1270 | result->offset_raw = iadc->adc->calib.offset_raw; |
| 1271 | result->ideal_offset_uv = |
| 1272 | QPNP_OFFSET_CALIBRATION_SHORT_CADC_LEADS_IDEAL; |
| 1273 | result->offset_uv = iadc->adc->calib.offset_uv; |
| 1274 | pr_debug("raw gain:0%x, raw offset:0%x\n", |
| 1275 | result->gain_raw, result->offset_raw); |
| 1276 | pr_debug("gain_uv:%d offset_uv:%d\n", |
| 1277 | result->gain_uv, result->offset_uv); |
| 1278 | mutex_unlock(&iadc->adc->adc_lock); |
| 1279 | |
| 1280 | return 0; |
| 1281 | } |
| 1282 | EXPORT_SYMBOL(qpnp_iadc_get_gain_and_offset); |
| 1283 | |
| 1284 | int qpnp_iadc_skip_calibration(struct qpnp_iadc_chip *iadc) |
| 1285 | { |
| 1286 | iadc->skip_auto_calibrations = true; |
| 1287 | return 0; |
| 1288 | } |
| 1289 | EXPORT_SYMBOL(qpnp_iadc_skip_calibration); |
| 1290 | |
| 1291 | int qpnp_iadc_resume_calibration(struct qpnp_iadc_chip *iadc) |
| 1292 | { |
| 1293 | iadc->skip_auto_calibrations = false; |
| 1294 | return 0; |
| 1295 | } |
| 1296 | EXPORT_SYMBOL(qpnp_iadc_resume_calibration); |
| 1297 | |
| 1298 | int32_t qpnp_iadc_vadc_sync_read(struct qpnp_iadc_chip *iadc, |
| 1299 | enum qpnp_iadc_channels i_channel, struct qpnp_iadc_result *i_result, |
| 1300 | enum qpnp_vadc_channels v_channel, struct qpnp_vadc_result *v_result) |
| 1301 | { |
| 1302 | int rc = 0, mode_sel = 0, num = 0, rsense_n_ohms = 0, sign = 0; |
| 1303 | int dt_index = 0; |
| 1304 | uint16_t raw_data; |
| 1305 | int32_t rsense_u_ohms = 0; |
| 1306 | int64_t result_current; |
| 1307 | |
| 1308 | if (qpnp_iadc_is_valid(iadc) < 0) |
| 1309 | return -EPROBE_DEFER; |
| 1310 | |
| 1311 | if ((iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw) == 0) { |
| 1312 | pr_err("raw offset errors! run iadc calibration again\n"); |
| 1313 | return -EINVAL; |
| 1314 | } |
| 1315 | |
| 1316 | mutex_lock(&iadc->adc->adc_lock); |
| 1317 | |
| 1318 | if (iadc->iadc_poll_eoc) { |
| 1319 | pr_debug("acquiring iadc eoc wakelock\n"); |
| 1320 | pm_stay_awake(iadc->dev); |
| 1321 | } |
| 1322 | |
| 1323 | iadc->iadc_mode_sel = true; |
| 1324 | |
| 1325 | rc = qpnp_vadc_iadc_sync_request(iadc->vadc_dev, v_channel); |
| 1326 | if (rc) { |
| 1327 | pr_err("Configuring VADC failed\n"); |
| 1328 | goto fail; |
| 1329 | } |
| 1330 | |
| 1331 | while (((enum qpnp_iadc_channels) |
| 1332 | iadc->adc->adc_channels[dt_index].channel_num |
| 1333 | != i_channel) && (dt_index < iadc->max_channels_available)) |
| 1334 | dt_index++; |
| 1335 | |
| 1336 | if (dt_index >= iadc->max_channels_available) { |
| 1337 | pr_err("not a valid IADC channel\n"); |
| 1338 | rc = -EINVAL; |
| 1339 | goto fail; |
| 1340 | } |
| 1341 | |
| 1342 | iadc->adc->amux_prop->decimation = |
| 1343 | iadc->adc->adc_channels[dt_index].adc_decimation; |
| 1344 | iadc->adc->amux_prop->fast_avg_setup = |
| 1345 | iadc->adc->adc_channels[dt_index].fast_avg_setup; |
| 1346 | |
| 1347 | rc = qpnp_iadc_configure(iadc, i_channel, &raw_data, mode_sel); |
| 1348 | if (rc < 0) { |
| 1349 | pr_err("qpnp adc result read failed with %d\n", rc); |
| 1350 | goto fail_release_vadc; |
| 1351 | } |
| 1352 | |
| 1353 | rc = qpnp_iadc_get_rsense(iadc, &rsense_n_ohms); |
| 1354 | pr_debug("current raw:0%x and rsense:%d\n", |
| 1355 | raw_data, rsense_n_ohms); |
| 1356 | rsense_u_ohms = rsense_n_ohms/1000; |
| 1357 | num = raw_data - iadc->adc->calib.offset_raw; |
| 1358 | if (num < 0) { |
| 1359 | sign = 1; |
| 1360 | num = -num; |
| 1361 | } |
| 1362 | |
| 1363 | i_result->result_uv = (num * QPNP_ADC_GAIN_NV)/ |
| 1364 | (iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw); |
| 1365 | result_current = i_result->result_uv; |
| 1366 | result_current *= QPNP_IADC_NANO_VOLTS_FACTOR; |
| 1367 | /* Intentional fall through. Process the result w/o comp */ |
| 1368 | if (!rsense_u_ohms) { |
| 1369 | pr_err("rsense error=%d\n", rsense_u_ohms); |
| 1370 | goto fail_release_vadc; |
| 1371 | } |
| 1372 | |
| 1373 | do_div(result_current, rsense_u_ohms); |
| 1374 | |
| 1375 | if (sign) { |
| 1376 | i_result->result_uv = -i_result->result_uv; |
| 1377 | result_current = -result_current; |
| 1378 | } |
| 1379 | result_current *= -1; |
| 1380 | rc = qpnp_iadc_comp_result(iadc, &result_current); |
| 1381 | if (rc < 0) |
| 1382 | pr_err("Error during compensating the IADC\n"); |
| 1383 | rc = 0; |
| 1384 | result_current *= -1; |
| 1385 | |
| 1386 | i_result->result_ua = (int32_t) result_current; |
| 1387 | |
| 1388 | fail_release_vadc: |
| 1389 | rc = qpnp_vadc_iadc_sync_complete_request(iadc->vadc_dev, v_channel, |
| 1390 | v_result); |
| 1391 | if (rc) |
| 1392 | pr_err("Releasing VADC failed\n"); |
| 1393 | fail: |
| 1394 | iadc->iadc_mode_sel = false; |
| 1395 | |
| 1396 | if (iadc->iadc_poll_eoc) { |
| 1397 | pr_debug("releasing iadc eoc wakelock\n"); |
| 1398 | pm_relax(iadc->dev); |
| 1399 | } |
| 1400 | mutex_unlock(&iadc->adc->adc_lock); |
| 1401 | |
| 1402 | return rc; |
| 1403 | } |
| 1404 | EXPORT_SYMBOL(qpnp_iadc_vadc_sync_read); |
| 1405 | |
| 1406 | static ssize_t qpnp_iadc_show(struct device *dev, |
| 1407 | struct device_attribute *devattr, char *buf) |
| 1408 | { |
| 1409 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); |
| 1410 | struct qpnp_iadc_chip *iadc = dev_get_drvdata(dev); |
| 1411 | struct qpnp_iadc_result result; |
| 1412 | int rc = -1; |
| 1413 | |
| 1414 | rc = qpnp_iadc_read(iadc, attr->index, &result); |
| 1415 | |
| 1416 | if (rc) |
| 1417 | return 0; |
| 1418 | |
| 1419 | return snprintf(buf, QPNP_ADC_HWMON_NAME_LENGTH, |
| 1420 | "Result:%d\n", result.result_ua); |
| 1421 | } |
| 1422 | |
| 1423 | static struct sensor_device_attribute qpnp_adc_attr = |
| 1424 | SENSOR_ATTR(NULL, 0444, qpnp_iadc_show, NULL, 0); |
| 1425 | |
| 1426 | static int32_t qpnp_iadc_init_hwmon(struct qpnp_iadc_chip *iadc, |
| 1427 | struct platform_device *pdev) |
| 1428 | { |
| 1429 | struct device_node *child; |
| 1430 | struct device_node *node = pdev->dev.of_node; |
| 1431 | int rc = 0, i = 0, channel; |
| 1432 | |
| 1433 | for_each_child_of_node(node, child) { |
| 1434 | channel = iadc->adc->adc_channels[i].channel_num; |
| 1435 | qpnp_adc_attr.index = iadc->adc->adc_channels[i].channel_num; |
| 1436 | qpnp_adc_attr.dev_attr.attr.name = |
| 1437 | iadc->adc->adc_channels[i].name; |
| 1438 | memcpy(&iadc->sens_attr[i], &qpnp_adc_attr, |
| 1439 | sizeof(qpnp_adc_attr)); |
| 1440 | sysfs_attr_init(&iadc->sens_attr[i].dev_attr.attr); |
| 1441 | rc = device_create_file(&pdev->dev, |
| 1442 | &iadc->sens_attr[i].dev_attr); |
| 1443 | if (rc) { |
| 1444 | dev_err(&pdev->dev, |
| 1445 | "device_create_file failed for dev %s\n", |
| 1446 | iadc->adc->adc_channels[i].name); |
| 1447 | goto hwmon_err_sens; |
| 1448 | } |
| 1449 | i++; |
| 1450 | } |
| 1451 | |
| 1452 | return 0; |
| 1453 | hwmon_err_sens: |
| 1454 | pr_err("Init HWMON failed for qpnp_iadc with %d\n", rc); |
| 1455 | return rc; |
| 1456 | } |
| 1457 | |
| 1458 | static int qpnp_iadc_probe(struct platform_device *pdev) |
| 1459 | { |
| 1460 | struct qpnp_iadc_chip *iadc; |
| 1461 | struct qpnp_adc_drv *adc_qpnp; |
| 1462 | struct device_node *node = pdev->dev.of_node; |
| 1463 | struct device_node *child; |
| 1464 | unsigned int base; |
| 1465 | int rc, count_adc_channel_list = 0, i = 0; |
| 1466 | |
| 1467 | for_each_child_of_node(node, child) |
| 1468 | count_adc_channel_list++; |
| 1469 | |
| 1470 | if (!count_adc_channel_list) { |
| 1471 | pr_err("No channel listing\n"); |
| 1472 | return -EINVAL; |
| 1473 | } |
| 1474 | |
| 1475 | iadc = devm_kzalloc(&pdev->dev, sizeof(struct qpnp_iadc_chip) + |
| 1476 | (sizeof(struct sensor_device_attribute) * |
| 1477 | count_adc_channel_list), GFP_KERNEL); |
| 1478 | if (!iadc) { |
| 1479 | dev_err(&pdev->dev, "Unable to allocate memory\n"); |
| 1480 | return -ENOMEM; |
| 1481 | } |
| 1482 | |
| 1483 | adc_qpnp = devm_kzalloc(&pdev->dev, sizeof(struct qpnp_adc_drv), |
| 1484 | GFP_KERNEL); |
| 1485 | if (!adc_qpnp) |
| 1486 | return -ENOMEM; |
| 1487 | |
| 1488 | adc_qpnp->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
| 1489 | if (!adc_qpnp->regmap) { |
| 1490 | dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); |
| 1491 | return -EINVAL; |
| 1492 | } |
| 1493 | |
| 1494 | iadc->dev = &(pdev->dev); |
| 1495 | iadc->adc = adc_qpnp; |
| 1496 | |
| 1497 | rc = qpnp_adc_get_devicetree_data(pdev, iadc->adc); |
| 1498 | if (rc) { |
| 1499 | dev_err(&pdev->dev, "failed to read device tree\n"); |
| 1500 | return rc; |
| 1501 | } |
| 1502 | |
| 1503 | rc = of_property_read_u32(pdev->dev.of_node, "batt-id-trim-cnst-rds", |
| 1504 | &base); |
| 1505 | if (rc < 0) { |
| 1506 | dev_err(&pdev->dev, |
| 1507 | "Couldn't find batt-id-trim-cnst-rds in node = %s rc = %d\n", |
| 1508 | pdev->dev.of_node->full_name, rc); |
| 1509 | return rc; |
| 1510 | } |
| 1511 | iadc->batt_id_trim_cnst_rds = base; |
| 1512 | rc = of_property_read_u32(node, "qcom,use-default-rds-trim", |
| 1513 | &iadc->rds_trim_default_type); |
| 1514 | if (rc) |
| 1515 | pr_debug("No trim workaround needed\n"); |
| 1516 | else { |
| 1517 | pr_debug("Use internal RDS trim workaround\n"); |
| 1518 | iadc->rds_trim_default_check = true; |
| 1519 | } |
| 1520 | |
| 1521 | iadc->vadc_dev = qpnp_get_vadc(&pdev->dev, "iadc"); |
| 1522 | if (IS_ERR(iadc->vadc_dev)) { |
| 1523 | rc = PTR_ERR(iadc->vadc_dev); |
| 1524 | if (rc != -EPROBE_DEFER) |
| 1525 | pr_err("vadc property missing, rc=%d\n", rc); |
| 1526 | return rc; |
| 1527 | } |
| 1528 | |
| 1529 | mutex_init(&iadc->adc->adc_lock); |
| 1530 | |
| 1531 | rc = of_property_read_u32(node, "qcom,rsense", |
| 1532 | &iadc->rsense); |
| 1533 | if (rc) |
| 1534 | pr_debug("Defaulting to internal rsense\n"); |
| 1535 | else { |
| 1536 | pr_debug("Use external rsense\n"); |
| 1537 | iadc->external_rsense = true; |
| 1538 | } |
| 1539 | |
| 1540 | iadc->iadc_poll_eoc = of_property_read_bool(node, |
| 1541 | "qcom,iadc-poll-eoc"); |
| 1542 | if (!iadc->iadc_poll_eoc) { |
| 1543 | rc = devm_request_irq(&pdev->dev, iadc->adc->adc_irq_eoc, |
| 1544 | qpnp_iadc_isr, IRQF_TRIGGER_RISING, |
| 1545 | "qpnp_iadc_interrupt", iadc); |
| 1546 | if (rc) { |
| 1547 | dev_err(&pdev->dev, "failed to request adc irq\n"); |
| 1548 | return rc; |
| 1549 | } |
| 1550 | enable_irq_wake(iadc->adc->adc_irq_eoc); |
| 1551 | } |
| 1552 | |
| 1553 | rc = qpnp_iadc_init_hwmon(iadc, pdev); |
| 1554 | if (rc) { |
| 1555 | dev_err(&pdev->dev, "failed to initialize qpnp hwmon adc\n"); |
| 1556 | return rc; |
| 1557 | } |
| 1558 | iadc->iadc_hwmon = hwmon_device_register(&iadc->adc->pdev->dev); |
| 1559 | |
| 1560 | rc = qpnp_iadc_version_check(iadc); |
| 1561 | if (rc) { |
| 1562 | dev_err(&pdev->dev, "IADC version not supported\n"); |
| 1563 | goto fail; |
| 1564 | } |
| 1565 | |
| 1566 | iadc->max_channels_available = count_adc_channel_list; |
| 1567 | INIT_WORK(&iadc->trigger_completion_work, qpnp_iadc_trigger_completion); |
| 1568 | INIT_DELAYED_WORK(&iadc->iadc_work, qpnp_iadc_work); |
| 1569 | rc = qpnp_iadc_comp_info(iadc); |
| 1570 | if (rc) { |
| 1571 | dev_err(&pdev->dev, "abstracting IADC comp info failed!\n"); |
| 1572 | goto fail; |
| 1573 | } |
| 1574 | |
| 1575 | rc = qpnp_iadc_rds_trim_update_check(iadc); |
| 1576 | if (rc) { |
| 1577 | dev_err(&pdev->dev, "Rds trim update failed!\n"); |
| 1578 | goto fail; |
| 1579 | } |
| 1580 | |
| 1581 | dev_set_drvdata(&pdev->dev, iadc); |
| 1582 | list_add(&iadc->list, &qpnp_iadc_device_list); |
| 1583 | rc = qpnp_iadc_calibrate_for_trim(iadc, true); |
| 1584 | if (rc) |
| 1585 | dev_err(&pdev->dev, "failed to calibrate for USR trim\n"); |
| 1586 | |
| 1587 | if (iadc->iadc_poll_eoc) |
| 1588 | device_init_wakeup(iadc->dev, 1); |
| 1589 | |
| 1590 | schedule_delayed_work(&iadc->iadc_work, |
| 1591 | round_jiffies_relative(msecs_to_jiffies |
| 1592 | (QPNP_IADC_CALIB_SECONDS))); |
| 1593 | return 0; |
| 1594 | fail: |
| 1595 | for_each_child_of_node(node, child) { |
| 1596 | device_remove_file(&pdev->dev, &iadc->sens_attr[i].dev_attr); |
| 1597 | i++; |
| 1598 | } |
| 1599 | hwmon_device_unregister(iadc->iadc_hwmon); |
| 1600 | |
| 1601 | return rc; |
| 1602 | } |
| 1603 | |
| 1604 | static int qpnp_iadc_remove(struct platform_device *pdev) |
| 1605 | { |
| 1606 | struct qpnp_iadc_chip *iadc = dev_get_drvdata(&pdev->dev); |
| 1607 | struct device_node *node = pdev->dev.of_node; |
| 1608 | struct device_node *child; |
| 1609 | int i = 0; |
| 1610 | |
| 1611 | cancel_delayed_work(&iadc->iadc_work); |
| 1612 | for_each_child_of_node(node, child) { |
| 1613 | device_remove_file(&pdev->dev, &iadc->sens_attr[i].dev_attr); |
| 1614 | i++; |
| 1615 | } |
| 1616 | hwmon_device_unregister(iadc->iadc_hwmon); |
| 1617 | if (iadc->iadc_poll_eoc) |
| 1618 | pm_relax(iadc->dev); |
| 1619 | dev_set_drvdata(&pdev->dev, NULL); |
| 1620 | |
| 1621 | return 0; |
| 1622 | } |
| 1623 | |
| 1624 | static const struct of_device_id qpnp_iadc_match_table[] = { |
| 1625 | { .compatible = "qcom,qpnp-iadc", |
| 1626 | }, |
| 1627 | {} |
| 1628 | }; |
| 1629 | |
| 1630 | static struct platform_driver qpnp_iadc_driver = { |
| 1631 | .driver = { |
| 1632 | .name = "qcom,qpnp-iadc", |
| 1633 | .of_match_table = qpnp_iadc_match_table, |
| 1634 | }, |
| 1635 | .probe = qpnp_iadc_probe, |
| 1636 | .remove = qpnp_iadc_remove, |
| 1637 | }; |
| 1638 | |
| 1639 | static int __init qpnp_iadc_init(void) |
| 1640 | { |
| 1641 | return platform_driver_register(&qpnp_iadc_driver); |
| 1642 | } |
| 1643 | module_init(qpnp_iadc_init); |
| 1644 | |
| 1645 | static void __exit qpnp_iadc_exit(void) |
| 1646 | { |
| 1647 | platform_driver_unregister(&qpnp_iadc_driver); |
| 1648 | } |
| 1649 | module_exit(qpnp_iadc_exit); |
| 1650 | |
| 1651 | MODULE_DESCRIPTION("QPNP PMIC current ADC driver"); |
| 1652 | MODULE_LICENSE("GPL v2"); |