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Thomas Gleixnerb8ce3352007-10-12 23:04:07 +02001#ifndef ASM_X86_HPET_H
2#define ASM_X86_HPET_H
3
4#ifdef CONFIG_HPET_TIMER
5
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +02006#define HPET_MMAP_SIZE 1024
7
8#define HPET_ID 0x000
9#define HPET_PERIOD 0x004
10#define HPET_CFG 0x010
11#define HPET_STATUS 0x020
12#define HPET_COUNTER 0x0f0
13#define HPET_T0_CFG 0x100
14#define HPET_T0_CMP 0x108
15#define HPET_T0_ROUTE 0x110
16#define HPET_T1_CFG 0x120
17#define HPET_T1_CMP 0x128
18#define HPET_T1_ROUTE 0x130
19#define HPET_T2_CFG 0x140
20#define HPET_T2_CMP 0x148
21#define HPET_T2_ROUTE 0x150
22
23#define HPET_ID_REV 0x000000ff
24#define HPET_ID_NUMBER 0x00001f00
25#define HPET_ID_64BIT 0x00002000
26#define HPET_ID_LEGSUP 0x00008000
27#define HPET_ID_VENDOR 0xffff0000
28#define HPET_ID_NUMBER_SHIFT 8
29#define HPET_ID_VENDOR_SHIFT 16
30
31#define HPET_ID_VENDOR_8086 0x8086
32
33#define HPET_CFG_ENABLE 0x001
34#define HPET_CFG_LEGACY 0x002
35#define HPET_LEGACY_8254 2
36#define HPET_LEGACY_RTC 8
37
38#define HPET_TN_LEVEL 0x0002
39#define HPET_TN_ENABLE 0x0004
40#define HPET_TN_PERIODIC 0x0008
41#define HPET_TN_PERIODIC_CAP 0x0010
42#define HPET_TN_64BIT_CAP 0x0020
43#define HPET_TN_SETVAL 0x0040
44#define HPET_TN_32BIT 0x0100
45#define HPET_TN_ROUTE 0x3e00
46#define HPET_TN_FSB 0x4000
47#define HPET_TN_FSB_CAP 0x8000
48#define HPET_TN_ROUTE_SHIFT 9
49
50/* Max HPET Period is 10^8 femto sec as in HPET spec */
51#define HPET_MAX_PERIOD 100000000UL
52/*
53 * Min HPET period is 10^5 femto sec just for safety. If it is less than this,
54 * then 32 bit HPET counter wrapsaround in less than 0.5 sec.
55 */
56#define HPET_MIN_PERIOD 100000UL
57
58/* hpet memory map physical address */
59extern unsigned long hpet_address;
Venki Pallipadi59c69f22007-10-12 23:04:23 +020060extern unsigned long force_hpet_address;
Thomas Gleixnerb17530b2007-10-19 20:35:02 +020061extern int hpet_force_user;
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +020062extern int is_hpet_enabled(void);
63extern int hpet_enable(void);
OGAWA Hirofumic86c7fb2007-12-03 17:17:10 +010064extern void hpet_disable(void);
Chris Wright31c435d2007-10-12 23:04:23 +020065extern unsigned long hpet_readl(unsigned long a);
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +020066extern void force_hpet_resume(void);
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +020067
68#ifdef CONFIG_HPET_EMULATE_RTC
69
70#include <linux/interrupt.h>
71
Bernhard Walle1bdbdaa2008-01-30 13:33:28 +010072typedef irqreturn_t (*rtc_irq_handler)(int interrupt, void *cookie);
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +020073extern int hpet_mask_rtc_irq_bit(unsigned long bit_mask);
74extern int hpet_set_rtc_irq_bit(unsigned long bit_mask);
75extern int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
76 unsigned char sec);
77extern int hpet_set_periodic_freq(unsigned long freq);
78extern int hpet_rtc_dropped_irq(void);
79extern int hpet_rtc_timer_init(void);
80extern irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id);
Bernhard Walle1bdbdaa2008-01-30 13:33:28 +010081extern int hpet_register_irq_handler(rtc_irq_handler handler);
82extern void hpet_unregister_irq_handler(rtc_irq_handler handler);
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +020083
84#endif /* CONFIG_HPET_EMULATE_RTC */
85
Ingo Molnardf619e62008-01-30 13:30:02 +010086#else /* CONFIG_HPET_TIMER */
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +020087
88static inline int hpet_enable(void) { return 0; }
Chris Wright31c435d2007-10-12 23:04:23 +020089static inline unsigned long hpet_readl(unsigned long a) { return 0; }
Ingo Molnardf619e62008-01-30 13:30:02 +010090static inline int is_hpet_enabled(void) { return 0; }
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +020091
Ingo Molnardf619e62008-01-30 13:30:02 +010092#endif
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +020093#endif /* ASM_X86_HPET_H */