blob: 65a2d0ba64e226919cb1be572c8d3de578f266b0 [file] [log] [blame]
Anant Golea6286ee2009-05-18 15:19:01 -07001/*
2 * DaVinci Ethernet Medium Access Controller
3 *
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
5 *
6 * Copyright (C) 2009 Texas Instruments.
7 *
8 * ---------------------------------------------------------------------------
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
24 * History:
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
29 * PHY layer usage
30 */
31
32/** Pending Items in this driver:
33 * 1. Use Linux cache infrastcture for DMA'ed memory (dma_xxx functions)
34 */
35
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/sched.h>
39#include <linux/string.h>
40#include <linux/timer.h>
41#include <linux/errno.h>
42#include <linux/in.h>
43#include <linux/ioport.h>
44#include <linux/slab.h>
45#include <linux/mm.h>
46#include <linux/interrupt.h>
47#include <linux/init.h>
48#include <linux/netdevice.h>
49#include <linux/etherdevice.h>
50#include <linux/skbuff.h>
51#include <linux/ethtool.h>
52#include <linux/highmem.h>
53#include <linux/proc_fs.h>
54#include <linux/ctype.h>
55#include <linux/version.h>
56#include <linux/spinlock.h>
57#include <linux/dma-mapping.h>
58#include <linux/clk.h>
59#include <linux/platform_device.h>
60#include <linux/semaphore.h>
61#include <linux/phy.h>
62#include <linux/bitops.h>
63#include <linux/io.h>
64#include <linux/uaccess.h>
65
66#include <asm/irq.h>
67#include <asm/page.h>
68
69#include <mach/emac.h>
70
71static int debug_level;
72module_param(debug_level, int, 0);
73MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
74
75/* Netif debug messages possible */
76#define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
77 NETIF_MSG_PROBE | \
78 NETIF_MSG_LINK | \
79 NETIF_MSG_TIMER | \
80 NETIF_MSG_IFDOWN | \
81 NETIF_MSG_IFUP | \
82 NETIF_MSG_RX_ERR | \
83 NETIF_MSG_TX_ERR | \
84 NETIF_MSG_TX_QUEUED | \
85 NETIF_MSG_INTR | \
86 NETIF_MSG_TX_DONE | \
87 NETIF_MSG_RX_STATUS | \
88 NETIF_MSG_PKTDATA | \
89 NETIF_MSG_HW | \
90 NETIF_MSG_WOL)
91
92/* version info */
93#define EMAC_MAJOR_VERSION 6
94#define EMAC_MINOR_VERSION 1
95#define EMAC_MODULE_VERSION "6.1"
96MODULE_VERSION(EMAC_MODULE_VERSION);
97static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
98
99/* Configuration items */
100#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */
101#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
102#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
103#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
104#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
105#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
106#define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */
107#define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */
108#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
109#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
110#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
111#define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
112
113#define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
114#define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
115
116#define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
117#define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
118#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
119#define EMAC_DEF_TX_CH (0) /* Default 0th channel */
120#define EMAC_DEF_RX_CH (0) /* Default 0th channel */
121#define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */
122#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
123#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
124#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
125
126/* Buffer descriptor parameters */
127#define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
128#define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
129
130/* EMAC register related defines */
131#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
132#define EMAC_NUM_MULTICAST_BITS (64)
133#define EMAC_TEARDOWN_VALUE (0xFFFFFFFC)
134#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
135#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
136#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
137#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
138#define EMAC_INT_MASK_CLEAR (0xFF)
139
140/* RX MBP register bit positions */
141#define EMAC_RXMBP_PASSCRC_MASK BIT(30)
142#define EMAC_RXMBP_QOSEN_MASK BIT(29)
143#define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
144#define EMAC_RXMBP_CMFEN_MASK BIT(24)
145#define EMAC_RXMBP_CSFEN_MASK BIT(23)
146#define EMAC_RXMBP_CEFEN_MASK BIT(22)
147#define EMAC_RXMBP_CAFEN_MASK BIT(21)
148#define EMAC_RXMBP_PROMCH_SHIFT (16)
149#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
150#define EMAC_RXMBP_BROADEN_MASK BIT(13)
151#define EMAC_RXMBP_BROADCH_SHIFT (8)
152#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
153#define EMAC_RXMBP_MULTIEN_MASK BIT(5)
154#define EMAC_RXMBP_MULTICH_SHIFT (0)
155#define EMAC_RXMBP_MULTICH_MASK (0x7)
156#define EMAC_RXMBP_CHMASK (0x7)
157
158/* EMAC register definitions/bit maps used */
159# define EMAC_MBP_RXPROMISC (0x00200000)
160# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
161# define EMAC_MBP_RXBCAST (0x00002000)
162# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
163# define EMAC_MBP_RXMCAST (0x00000020)
164# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
165
166/* EMAC mac_control register */
167#define EMAC_MACCONTROL_TXPTYPE (0x200)
168#define EMAC_MACCONTROL_TXPACEEN (0x40)
169#define EMAC_MACCONTROL_MIIEN (0x20)
170#define EMAC_MACCONTROL_GIGABITEN (0x80)
171#define EMAC_MACCONTROL_GIGABITEN_SHIFT (7)
172#define EMAC_MACCONTROL_FULLDUPLEXEN (0x1)
173#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
174
175/* GIGABIT MODE related bits */
176#define EMAC_DM646X_MACCONTORL_GMIIEN BIT(5)
177#define EMAC_DM646X_MACCONTORL_GIG BIT(7)
178#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
179
180/* EMAC mac_status register */
181#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
182#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
183#define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
184#define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
185#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
186#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
187#define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
188#define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
189
190/* EMAC RX register masks */
191#define EMAC_RX_MAX_LEN_MASK (0xFFFF)
192#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
193
194/* MAC_IN_VECTOR (0x180) register bit fields */
195#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT (0x20000)
196#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT (0x10000)
197#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC (0x0100)
198#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC (0x01)
199
200/** NOTE:: For DM646x the IN_VECTOR has changed */
201#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
202#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
Sriram43c2ed82009-09-24 19:15:18 +0000203#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
204#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
205
Anant Golea6286ee2009-05-18 15:19:01 -0700206
207/* CPPI bit positions */
208#define EMAC_CPPI_SOP_BIT BIT(31)
209#define EMAC_CPPI_EOP_BIT BIT(30)
210#define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
211#define EMAC_CPPI_EOQ_BIT BIT(28)
212#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
213#define EMAC_CPPI_PASS_CRC_BIT BIT(26)
214#define EMAC_RX_BD_BUF_SIZE (0xFFFF)
215#define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
216#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
217
218/* Max hardware defines */
219#define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
220#define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
221
222/* EMAC Peripheral Device Register Memory Layout structure */
223#define EMAC_TXIDVER 0x0
224#define EMAC_TXCONTROL 0x4
225#define EMAC_TXTEARDOWN 0x8
226#define EMAC_RXIDVER 0x10
227#define EMAC_RXCONTROL 0x14
228#define EMAC_RXTEARDOWN 0x18
229#define EMAC_TXINTSTATRAW 0x80
230#define EMAC_TXINTSTATMASKED 0x84
231#define EMAC_TXINTMASKSET 0x88
232#define EMAC_TXINTMASKCLEAR 0x8C
233#define EMAC_MACINVECTOR 0x90
234
235#define EMAC_DM646X_MACEOIVECTOR 0x94
236
237#define EMAC_RXINTSTATRAW 0xA0
238#define EMAC_RXINTSTATMASKED 0xA4
239#define EMAC_RXINTMASKSET 0xA8
240#define EMAC_RXINTMASKCLEAR 0xAC
241#define EMAC_MACINTSTATRAW 0xB0
242#define EMAC_MACINTSTATMASKED 0xB4
243#define EMAC_MACINTMASKSET 0xB8
244#define EMAC_MACINTMASKCLEAR 0xBC
245
246#define EMAC_RXMBPENABLE 0x100
247#define EMAC_RXUNICASTSET 0x104
248#define EMAC_RXUNICASTCLEAR 0x108
249#define EMAC_RXMAXLEN 0x10C
250#define EMAC_RXBUFFEROFFSET 0x110
251#define EMAC_RXFILTERLOWTHRESH 0x114
252
253#define EMAC_MACCONTROL 0x160
254#define EMAC_MACSTATUS 0x164
255#define EMAC_EMCONTROL 0x168
256#define EMAC_FIFOCONTROL 0x16C
257#define EMAC_MACCONFIG 0x170
258#define EMAC_SOFTRESET 0x174
259#define EMAC_MACSRCADDRLO 0x1D0
260#define EMAC_MACSRCADDRHI 0x1D4
261#define EMAC_MACHASH1 0x1D8
262#define EMAC_MACHASH2 0x1DC
263#define EMAC_MACADDRLO 0x500
264#define EMAC_MACADDRHI 0x504
265#define EMAC_MACINDEX 0x508
266
267/* EMAC HDP and Completion registors */
268#define EMAC_TXHDP(ch) (0x600 + (ch * 4))
269#define EMAC_RXHDP(ch) (0x620 + (ch * 4))
270#define EMAC_TXCP(ch) (0x640 + (ch * 4))
271#define EMAC_RXCP(ch) (0x660 + (ch * 4))
272
273/* EMAC statistics registers */
274#define EMAC_RXGOODFRAMES 0x200
275#define EMAC_RXBCASTFRAMES 0x204
276#define EMAC_RXMCASTFRAMES 0x208
277#define EMAC_RXPAUSEFRAMES 0x20C
278#define EMAC_RXCRCERRORS 0x210
279#define EMAC_RXALIGNCODEERRORS 0x214
280#define EMAC_RXOVERSIZED 0x218
281#define EMAC_RXJABBER 0x21C
282#define EMAC_RXUNDERSIZED 0x220
283#define EMAC_RXFRAGMENTS 0x224
284#define EMAC_RXFILTERED 0x228
285#define EMAC_RXQOSFILTERED 0x22C
286#define EMAC_RXOCTETS 0x230
287#define EMAC_TXGOODFRAMES 0x234
288#define EMAC_TXBCASTFRAMES 0x238
289#define EMAC_TXMCASTFRAMES 0x23C
290#define EMAC_TXPAUSEFRAMES 0x240
291#define EMAC_TXDEFERRED 0x244
292#define EMAC_TXCOLLISION 0x248
293#define EMAC_TXSINGLECOLL 0x24C
294#define EMAC_TXMULTICOLL 0x250
295#define EMAC_TXEXCESSIVECOLL 0x254
296#define EMAC_TXLATECOLL 0x258
297#define EMAC_TXUNDERRUN 0x25C
298#define EMAC_TXCARRIERSENSE 0x260
299#define EMAC_TXOCTETS 0x264
300#define EMAC_NETOCTETS 0x280
301#define EMAC_RXSOFOVERRUNS 0x284
302#define EMAC_RXMOFOVERRUNS 0x288
303#define EMAC_RXDMAOVERRUNS 0x28C
304
305/* EMAC DM644x control registers */
306#define EMAC_CTRL_EWCTL (0x4)
307#define EMAC_CTRL_EWINTTCNT (0x8)
308
309/* EMAC MDIO related */
310/* Mask & Control defines */
311#define MDIO_CONTROL_CLKDIV (0xFF)
312#define MDIO_CONTROL_ENABLE BIT(30)
313#define MDIO_USERACCESS_GO BIT(31)
314#define MDIO_USERACCESS_WRITE BIT(30)
315#define MDIO_USERACCESS_READ (0)
316#define MDIO_USERACCESS_REGADR (0x1F << 21)
317#define MDIO_USERACCESS_PHYADR (0x1F << 16)
318#define MDIO_USERACCESS_DATA (0xFFFF)
319#define MDIO_USERPHYSEL_LINKSEL BIT(7)
320#define MDIO_VER_MODID (0xFFFF << 16)
321#define MDIO_VER_REVMAJ (0xFF << 8)
322#define MDIO_VER_REVMIN (0xFF)
323
324#define MDIO_USERACCESS(inst) (0x80 + (inst * 8))
325#define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8))
326#define MDIO_CONTROL (0x04)
327
328/* EMAC DM646X control module registers */
329#define EMAC_DM646X_CMRXINTEN (0x14)
330#define EMAC_DM646X_CMTXINTEN (0x18)
331
332/* EMAC EOI codes for C0 */
333#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
334#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
335
336/** net_buf_obj: EMAC network bufferdata structure
337 *
338 * EMAC network buffer data structure
339 */
340struct emac_netbufobj {
341 void *buf_token;
342 char *data_ptr;
343 int length;
344};
345
346/** net_pkt_obj: EMAC network packet data structure
347 *
348 * EMAC network packet data structure - supports buffer list (for future)
349 */
350struct emac_netpktobj {
351 void *pkt_token; /* data token may hold tx/rx chan id */
352 struct emac_netbufobj *buf_list; /* array of network buffer objects */
353 int num_bufs;
354 int pkt_length;
355};
356
357/** emac_tx_bd: EMAC TX Buffer descriptor data structure
358 *
359 * EMAC TX Buffer descriptor data structure
360 */
361struct emac_tx_bd {
362 int h_next;
363 int buff_ptr;
364 int off_b_len;
365 int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
366 struct emac_tx_bd __iomem *next;
367 void *buf_token;
368};
369
370/** emac_txch: EMAC TX Channel data structure
371 *
372 * EMAC TX Channel data structure
373 */
374struct emac_txch {
375 /* Config related */
376 u32 num_bd;
377 u32 service_max;
378
379 /* CPPI specific */
380 u32 alloc_size;
381 void __iomem *bd_mem;
382 struct emac_tx_bd __iomem *bd_pool_head;
383 struct emac_tx_bd __iomem *active_queue_head;
384 struct emac_tx_bd __iomem *active_queue_tail;
385 struct emac_tx_bd __iomem *last_hw_bdprocessed;
386 u32 queue_active;
387 u32 teardown_pending;
388 u32 *tx_complete;
389
390 /** statistics */
391 u32 proc_count; /* TX: # of times emac_tx_bdproc is called */
392 u32 mis_queued_packets;
393 u32 queue_reinit;
394 u32 end_of_queue_add;
395 u32 out_of_tx_bd;
396 u32 no_active_pkts; /* IRQ when there were no packets to process */
397 u32 active_queue_count;
398};
399
400/** emac_rx_bd: EMAC RX Buffer descriptor data structure
401 *
402 * EMAC RX Buffer descriptor data structure
403 */
404struct emac_rx_bd {
405 int h_next;
406 int buff_ptr;
407 int off_b_len;
408 int mode;
409 struct emac_rx_bd __iomem *next;
410 void *data_ptr;
411 void *buf_token;
412};
413
414/** emac_rxch: EMAC RX Channel data structure
415 *
416 * EMAC RX Channel data structure
417 */
418struct emac_rxch {
419 /* configuration info */
420 u32 num_bd;
421 u32 service_max;
422 u32 buf_size;
423 char mac_addr[6];
424
425 /** CPPI specific */
426 u32 alloc_size;
427 void __iomem *bd_mem;
428 struct emac_rx_bd __iomem *bd_pool_head;
429 struct emac_rx_bd __iomem *active_queue_head;
430 struct emac_rx_bd __iomem *active_queue_tail;
431 u32 queue_active;
432 u32 teardown_pending;
433
434 /* packet and buffer objects */
435 struct emac_netpktobj pkt_queue;
436 struct emac_netbufobj buf_queue;
437
438 /** statistics */
439 u32 proc_count; /* number of times emac_rx_bdproc is called */
440 u32 processed_bd;
441 u32 recycled_bd;
442 u32 out_of_rx_bd;
443 u32 out_of_rx_buffers;
444 u32 queue_reinit;
445 u32 end_of_queue_add;
446 u32 end_of_queue;
447 u32 mis_queued_packets;
448};
449
450/* emac_priv: EMAC private data structure
451 *
452 * EMAC adapter private data structure
453 */
454struct emac_priv {
455 u32 msg_enable;
456 struct net_device *ndev;
457 struct platform_device *pdev;
458 struct napi_struct napi;
459 char mac_addr[6];
460 spinlock_t tx_lock;
461 spinlock_t rx_lock;
462 void __iomem *remap_addr;
463 u32 emac_base_phys;
464 void __iomem *emac_base;
465 void __iomem *ctrl_base;
466 void __iomem *emac_ctrl_ram;
467 u32 ctrl_ram_size;
468 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
469 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
470 u32 link; /* 1=link on, 0=link off */
471 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
472 u32 duplex; /* Link duplex: 0=Half, 1=Full */
473 u32 rx_buf_size;
474 u32 isr_count;
475 u8 rmii_en;
476 u8 version;
477 struct net_device_stats net_dev_stats;
478 u32 mac_hash1;
479 u32 mac_hash2;
480 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
481 u32 rx_addr_type;
482 /* periodic timer required for MDIO polling */
483 struct timer_list periodic_timer;
484 u32 periodic_ticks;
485 u32 timer_active;
486 u32 phy_mask;
487 /* mii_bus,phy members */
488 struct mii_bus *mii_bus;
489 struct phy_device *phydev;
490 spinlock_t lock;
491};
492
493/* clock frequency for EMAC */
494static struct clk *emac_clk;
495static unsigned long emac_bus_frequency;
496static unsigned long mdio_max_freq;
497
498/* EMAC internal utility function */
499static inline u32 emac_virt_to_phys(void __iomem *addr)
500{
501 return (u32 __force) io_v2p(addr);
502}
503
504/* Cache macros - Packet buffers would be from skb pool which is cached */
505#define EMAC_VIRT_NOCACHE(addr) (addr)
506#define EMAC_CACHE_INVALIDATE(addr, size) \
507 dma_cache_maint((void *)addr, size, DMA_FROM_DEVICE)
508#define EMAC_CACHE_WRITEBACK(addr, size) \
509 dma_cache_maint((void *)addr, size, DMA_TO_DEVICE)
510#define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
511 dma_cache_maint((void *)addr, size, DMA_BIDIRECTIONAL)
512
513/* DM644x does not have BD's in cached memory - so no cache functions */
514#define BD_CACHE_INVALIDATE(addr, size)
515#define BD_CACHE_WRITEBACK(addr, size)
516#define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
517
518/* EMAC TX Host Error description strings */
519static char *emac_txhost_errcodes[16] = {
520 "No error", "SOP error", "Ownership bit not set in SOP buffer",
521 "Zero Next Buffer Descriptor Pointer Without EOP",
522 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
523 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
524 "Reserved", "Reserved", "Reserved", "Reserved"
525};
526
527/* EMAC RX Host Error description strings */
528static char *emac_rxhost_errcodes[16] = {
529 "No error", "Reserved", "Ownership bit not set in input buffer",
530 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
531 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
532 "Reserved", "Reserved", "Reserved", "Reserved"
533};
534
535/* Helper macros */
536#define emac_read(reg) ioread32(priv->emac_base + (reg))
537#define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
538
539#define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
540#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
541
542#define emac_mdio_read(reg) ioread32(bus->priv + (reg))
543#define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg)))
544
545/**
546 * emac_dump_regs: Dump important EMAC registers to debug terminal
547 * @priv: The DaVinci EMAC private adapter structure
548 *
549 * Executes ethtool set cmd & sets phy mode
550 *
551 */
552static void emac_dump_regs(struct emac_priv *priv)
553{
554 struct device *emac_dev = &priv->ndev->dev;
555
556 /* Print important registers in EMAC */
557 dev_info(emac_dev, "EMAC Basic registers\n");
558 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
559 emac_ctrl_read(EMAC_CTRL_EWCTL),
560 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
561 dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n",
562 emac_read(EMAC_TXIDVER),
563 ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"),
564 emac_read(EMAC_RXIDVER),
565 ((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled"));
566 dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\
567 "TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW),
568 emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET));
569 dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\
570 "RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW),
571 emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET));
572 dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\
573 "MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW),
574 emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR));
575 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
576 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
577 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
578 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
579 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
580 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
581 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
582 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
583 dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n",
584 emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0)));
585 dev_info(emac_dev, "EMAC Statistics\n");
586 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
587 emac_read(EMAC_RXGOODFRAMES));
588 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
589 emac_read(EMAC_RXBCASTFRAMES));
590 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
591 emac_read(EMAC_RXMCASTFRAMES));
592 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
593 emac_read(EMAC_RXPAUSEFRAMES));
594 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
595 emac_read(EMAC_RXCRCERRORS));
596 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
597 emac_read(EMAC_RXALIGNCODEERRORS));
598 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
599 emac_read(EMAC_RXOVERSIZED));
600 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
601 emac_read(EMAC_RXJABBER));
602 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
603 emac_read(EMAC_RXUNDERSIZED));
604 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
605 emac_read(EMAC_RXFRAGMENTS));
606 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
607 emac_read(EMAC_RXFILTERED));
608 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
609 emac_read(EMAC_RXQOSFILTERED));
610 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
611 emac_read(EMAC_RXOCTETS));
612 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
613 emac_read(EMAC_TXGOODFRAMES));
614 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
615 emac_read(EMAC_TXBCASTFRAMES));
616 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
617 emac_read(EMAC_TXMCASTFRAMES));
618 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
619 emac_read(EMAC_TXPAUSEFRAMES));
620 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
621 emac_read(EMAC_TXDEFERRED));
622 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
623 emac_read(EMAC_TXCOLLISION));
624 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
625 emac_read(EMAC_TXSINGLECOLL));
626 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
627 emac_read(EMAC_TXMULTICOLL));
628 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
629 emac_read(EMAC_TXEXCESSIVECOLL));
630 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
631 emac_read(EMAC_TXLATECOLL));
632 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
633 emac_read(EMAC_TXUNDERRUN));
634 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
635 emac_read(EMAC_TXCARRIERSENSE));
636 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
637 emac_read(EMAC_TXOCTETS));
638 dev_info(emac_dev, "EMAC: net_octets:%d\n",
639 emac_read(EMAC_NETOCTETS));
640 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
641 emac_read(EMAC_RXSOFOVERRUNS));
642 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
643 emac_read(EMAC_RXMOFOVERRUNS));
644 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
645 emac_read(EMAC_RXDMAOVERRUNS));
646}
647
648/*************************************************************************
649 * EMAC MDIO/Phy Functionality
650 *************************************************************************/
651/**
652 * emac_get_drvinfo: Get EMAC driver information
653 * @ndev: The DaVinci EMAC network adapter
654 * @info: ethtool info structure containing name and version
655 *
656 * Returns EMAC driver information (name and version)
657 *
658 */
659static void emac_get_drvinfo(struct net_device *ndev,
660 struct ethtool_drvinfo *info)
661{
662 strcpy(info->driver, emac_version_string);
663 strcpy(info->version, EMAC_MODULE_VERSION);
664}
665
666/**
667 * emac_get_settings: Get EMAC settings
668 * @ndev: The DaVinci EMAC network adapter
669 * @ecmd: ethtool command
670 *
671 * Executes ethool get command
672 *
673 */
674static int emac_get_settings(struct net_device *ndev,
675 struct ethtool_cmd *ecmd)
676{
677 struct emac_priv *priv = netdev_priv(ndev);
678 if (priv->phy_mask)
679 return phy_ethtool_gset(priv->phydev, ecmd);
680 else
681 return -EOPNOTSUPP;
682
683}
684
685/**
686 * emac_set_settings: Set EMAC settings
687 * @ndev: The DaVinci EMAC network adapter
688 * @ecmd: ethtool command
689 *
690 * Executes ethool set command
691 *
692 */
693static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
694{
695 struct emac_priv *priv = netdev_priv(ndev);
696 if (priv->phy_mask)
697 return phy_ethtool_sset(priv->phydev, ecmd);
698 else
699 return -EOPNOTSUPP;
700
701}
702
703/**
704 * ethtool_ops: DaVinci EMAC Ethtool structure
705 *
706 * Ethtool support for EMAC adapter
707 *
708 */
709static const struct ethtool_ops ethtool_ops = {
710 .get_drvinfo = emac_get_drvinfo,
711 .get_settings = emac_get_settings,
712 .set_settings = emac_set_settings,
713 .get_link = ethtool_op_get_link,
714};
715
716/**
717 * emac_update_phystatus: Update Phy status
718 * @priv: The DaVinci EMAC private adapter structure
719 *
720 * Updates phy status and takes action for network queue if required
721 * based upon link status
722 *
723 */
724static void emac_update_phystatus(struct emac_priv *priv)
725{
726 u32 mac_control;
727 u32 new_duplex;
728 u32 cur_duplex;
729 struct net_device *ndev = priv->ndev;
730
731 mac_control = emac_read(EMAC_MACCONTROL);
732 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
733 DUPLEX_FULL : DUPLEX_HALF;
734 if (priv->phy_mask)
735 new_duplex = priv->phydev->duplex;
736 else
737 new_duplex = DUPLEX_FULL;
738
739 /* We get called only if link has changed (speed/duplex/status) */
740 if ((priv->link) && (new_duplex != cur_duplex)) {
741 priv->duplex = new_duplex;
742 if (DUPLEX_FULL == priv->duplex)
743 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
744 else
745 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
746 }
747
748 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
749 mac_control = emac_read(EMAC_MACCONTROL);
750 mac_control |= (EMAC_DM646X_MACCONTORL_GMIIEN |
751 EMAC_DM646X_MACCONTORL_GIG |
752 EMAC_DM646X_MACCONTORL_GIGFORCE);
753 } else {
754 /* Clear the GIG bit and GIGFORCE bit */
755 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
756 EMAC_DM646X_MACCONTORL_GIG);
757
758 if (priv->rmii_en && (priv->speed == SPEED_100))
759 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
760 else
761 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
762 }
763
764 /* Update mac_control if changed */
765 emac_write(EMAC_MACCONTROL, mac_control);
766
767 if (priv->link) {
768 /* link ON */
769 if (!netif_carrier_ok(ndev))
770 netif_carrier_on(ndev);
771 /* reactivate the transmit queue if it is stopped */
772 if (netif_running(ndev) && netif_queue_stopped(ndev))
773 netif_wake_queue(ndev);
774 } else {
775 /* link OFF */
776 if (netif_carrier_ok(ndev))
777 netif_carrier_off(ndev);
778 if (!netif_queue_stopped(ndev))
779 netif_stop_queue(ndev);
780 }
781}
782
783/**
784 * hash_get: Calculate hash value from mac address
785 * @addr: mac address to delete from hash table
786 *
787 * Calculates hash value from mac address
788 *
789 */
790static u32 hash_get(u8 *addr)
791{
792 u32 hash;
793 u8 tmpval;
794 int cnt;
795 hash = 0;
796
797 for (cnt = 0; cnt < 2; cnt++) {
798 tmpval = *addr++;
799 hash ^= (tmpval >> 2) ^ (tmpval << 4);
800 tmpval = *addr++;
801 hash ^= (tmpval >> 4) ^ (tmpval << 2);
802 tmpval = *addr++;
803 hash ^= (tmpval >> 6) ^ (tmpval);
804 }
805
806 return hash & 0x3F;
807}
808
809/**
810 * hash_add: Hash function to add mac addr from hash table
811 * @priv: The DaVinci EMAC private adapter structure
812 * mac_addr: mac address to delete from hash table
813 *
814 * Adds mac address to the internal hash table
815 *
816 */
817static int hash_add(struct emac_priv *priv, u8 *mac_addr)
818{
819 struct device *emac_dev = &priv->ndev->dev;
820 u32 rc = 0;
821 u32 hash_bit;
822 u32 hash_value = hash_get(mac_addr);
823
824 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
825 if (netif_msg_drv(priv)) {
826 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
827 "Hash %08x, should not be greater than %08x",
828 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
829 }
830 return -1;
831 }
832
833 /* set the hash bit only if not previously set */
834 if (priv->multicast_hash_cnt[hash_value] == 0) {
835 rc = 1; /* hash value changed */
836 if (hash_value < 32) {
837 hash_bit = BIT(hash_value);
838 priv->mac_hash1 |= hash_bit;
839 } else {
840 hash_bit = BIT((hash_value - 32));
841 priv->mac_hash2 |= hash_bit;
842 }
843 }
844
845 /* incr counter for num of mcast addr's mapped to "this" hash bit */
846 ++priv->multicast_hash_cnt[hash_value];
847
848 return rc;
849}
850
851/**
852 * hash_del: Hash function to delete mac addr from hash table
853 * @priv: The DaVinci EMAC private adapter structure
854 * mac_addr: mac address to delete from hash table
855 *
856 * Removes mac address from the internal hash table
857 *
858 */
859static int hash_del(struct emac_priv *priv, u8 *mac_addr)
860{
861 u32 hash_value;
862 u32 hash_bit;
863
864 hash_value = hash_get(mac_addr);
865 if (priv->multicast_hash_cnt[hash_value] > 0) {
866 /* dec cntr for num of mcast addr's mapped to this hash bit */
867 --priv->multicast_hash_cnt[hash_value];
868 }
869
870 /* if counter still > 0, at least one multicast address refers
871 * to this hash bit. so return 0 */
872 if (priv->multicast_hash_cnt[hash_value] > 0)
873 return 0;
874
875 if (hash_value < 32) {
876 hash_bit = BIT(hash_value);
877 priv->mac_hash1 &= ~hash_bit;
878 } else {
879 hash_bit = BIT((hash_value - 32));
880 priv->mac_hash2 &= ~hash_bit;
881 }
882
883 /* return 1 to indicate change in mac_hash registers reqd */
884 return 1;
885}
886
887/* EMAC multicast operation */
888#define EMAC_MULTICAST_ADD 0
889#define EMAC_MULTICAST_DEL 1
890#define EMAC_ALL_MULTI_SET 2
891#define EMAC_ALL_MULTI_CLR 3
892
893/**
894 * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
895 * @priv: The DaVinci EMAC private adapter structure
896 * @action: multicast operation to perform
897 * mac_addr: mac address to set
898 *
899 * Set multicast addresses in EMAC adapter - internal function
900 *
901 */
902static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
903{
904 struct device *emac_dev = &priv->ndev->dev;
905 int update = -1;
906
907 switch (action) {
908 case EMAC_MULTICAST_ADD:
909 update = hash_add(priv, mac_addr);
910 break;
911 case EMAC_MULTICAST_DEL:
912 update = hash_del(priv, mac_addr);
913 break;
914 case EMAC_ALL_MULTI_SET:
915 update = 1;
916 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
917 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
918 break;
919 case EMAC_ALL_MULTI_CLR:
920 update = 1;
921 priv->mac_hash1 = 0;
922 priv->mac_hash2 = 0;
923 memset(&(priv->multicast_hash_cnt[0]), 0,
924 sizeof(priv->multicast_hash_cnt[0]) *
925 EMAC_NUM_MULTICAST_BITS);
926 break;
927 default:
928 if (netif_msg_drv(priv))
929 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
930 ": bad operation %d", action);
931 break;
932 }
933
934 /* write to the hardware only if the register status chances */
935 if (update > 0) {
936 emac_write(EMAC_MACHASH1, priv->mac_hash1);
937 emac_write(EMAC_MACHASH2, priv->mac_hash2);
938 }
939}
940
941/**
942 * emac_dev_mcast_set: Set multicast address in the EMAC adapter
943 * @ndev: The DaVinci EMAC network adapter
944 *
945 * Set multicast addresses in EMAC adapter
946 *
947 */
948static void emac_dev_mcast_set(struct net_device *ndev)
949{
950 u32 mbp_enable;
951 struct emac_priv *priv = netdev_priv(ndev);
952
953 mbp_enable = emac_read(EMAC_RXMBPENABLE);
954 if (ndev->flags & IFF_PROMISC) {
955 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
956 mbp_enable |= (EMAC_MBP_RXPROMISC);
957 } else {
958 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
959 if ((ndev->flags & IFF_ALLMULTI) ||
960 (ndev->mc_count > EMAC_DEF_MAX_MULTICAST_ADDRESSES)) {
961 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
962 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
963 }
964 if (ndev->mc_count > 0) {
965 struct dev_mc_list *mc_ptr;
966 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
967 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
968 /* program multicast address list into EMAC hardware */
969 for (mc_ptr = ndev->mc_list; mc_ptr;
970 mc_ptr = mc_ptr->next) {
971 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
972 (u8 *)mc_ptr->dmi_addr);
973 }
974 } else {
975 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
976 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
977 }
978 }
979 /* Set mbp config register */
980 emac_write(EMAC_RXMBPENABLE, mbp_enable);
981}
982
983/*************************************************************************
984 * EMAC Hardware manipulation
985 *************************************************************************/
986
987/**
988 * emac_int_disable: Disable EMAC module interrupt (from adapter)
989 * @priv: The DaVinci EMAC private adapter structure
990 *
991 * Disable EMAC interrupt on the adapter
992 *
993 */
994static void emac_int_disable(struct emac_priv *priv)
995{
996 if (priv->version == EMAC_VERSION_2) {
997 unsigned long flags;
998
999 local_irq_save(flags);
1000
1001 /* Program C0_Int_En to zero to turn off
1002 * interrupts to the CPU */
1003 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
1004 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
1005 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
1006
1007 local_irq_restore(flags);
1008
1009 } else {
1010 /* Set DM644x control registers for interrupt control */
1011 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
1012 }
1013}
1014
1015/**
1016 * emac_int_enable: Enable EMAC module interrupt (from adapter)
1017 * @priv: The DaVinci EMAC private adapter structure
1018 *
1019 * Enable EMAC interrupt on the adapter
1020 *
1021 */
1022static void emac_int_enable(struct emac_priv *priv)
1023{
1024 if (priv->version == EMAC_VERSION_2) {
1025 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
1026 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
1027
1028 /* In addition to turning on interrupt Enable, we need
1029 * ack by writing appropriate values to the EOI
1030 * register */
1031
1032 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
1033
1034 /* ack rxen only then a new pulse will be generated */
1035 emac_write(EMAC_DM646X_MACEOIVECTOR,
1036 EMAC_DM646X_MAC_EOI_C0_RXEN);
1037
1038 /* ack txen- only then a new pulse will be generated */
1039 emac_write(EMAC_DM646X_MACEOIVECTOR,
1040 EMAC_DM646X_MAC_EOI_C0_TXEN);
1041
1042 } else {
1043 /* Set DM644x control registers for interrupt control */
1044 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
1045 }
1046}
1047
1048/**
1049 * emac_irq: EMAC interrupt handler
1050 * @irq: interrupt number
1051 * @dev_id: EMAC network adapter data structure ptr
1052 *
1053 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
1054 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
1055 *
1056 * Returns interrupt handled condition
1057 */
1058static irqreturn_t emac_irq(int irq, void *dev_id)
1059{
1060 struct net_device *ndev = (struct net_device *)dev_id;
1061 struct emac_priv *priv = netdev_priv(ndev);
1062
1063 ++priv->isr_count;
1064 if (likely(netif_running(priv->ndev))) {
1065 emac_int_disable(priv);
1066 napi_schedule(&priv->napi);
1067 } else {
1068 /* we are closing down, so dont process anything */
1069 }
1070 return IRQ_HANDLED;
1071}
1072
1073/** EMAC on-chip buffer descriptor memory
1074 *
1075 * WARNING: Please note that the on chip memory is used for both TX and RX
1076 * buffer descriptor queues and is equally divided between TX and RX desc's
1077 * If the number of TX or RX descriptors change this memory pointers need
1078 * to be adjusted. If external memory is allocated then these pointers can
1079 * pointer to the memory
1080 *
1081 */
1082#define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram)
1083#define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \
1084 (((priv)->ctrl_ram_size) >> 1))
1085
1086/**
1087 * emac_init_txch: TX channel initialization
1088 * @priv: The DaVinci EMAC private adapter structure
1089 * @ch: RX channel number
1090 *
1091 * Called during device init to setup a TX channel (allocate buffer desc
1092 * create free pool and keep ready for transmission
1093 *
1094 * Returns success(0) or mem alloc failures error code
1095 */
1096static int emac_init_txch(struct emac_priv *priv, u32 ch)
1097{
1098 struct device *emac_dev = &priv->ndev->dev;
1099 u32 cnt, bd_size;
1100 void __iomem *mem;
1101 struct emac_tx_bd __iomem *curr_bd;
1102 struct emac_txch *txch = NULL;
1103
1104 txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL);
1105 if (NULL == txch) {
1106 dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed");
1107 return -ENOMEM;
1108 }
1109 priv->txch[ch] = txch;
1110 txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
1111 txch->active_queue_head = NULL;
1112 txch->active_queue_tail = NULL;
1113 txch->queue_active = 0;
1114 txch->teardown_pending = 0;
1115
1116 /* allocate memory for TX CPPI channel on a 4 byte boundry */
1117 txch->tx_complete = kzalloc(txch->service_max * sizeof(u32),
1118 GFP_KERNEL);
1119 if (NULL == txch->tx_complete) {
1120 dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed");
1121 kfree(txch);
1122 return -ENOMEM;
1123 }
1124
1125 /* allocate buffer descriptor pool align every BD on four word
1126 * boundry for future requirements */
1127 bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
1128 txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1129 txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
1130
1131 /* alloc TX BD memory */
1132 txch->bd_mem = EMAC_TX_BD_MEM(priv);
1133 __memzero((void __force *)txch->bd_mem, txch->alloc_size);
1134
1135 /* initialize the BD linked list */
1136 mem = (void __force __iomem *)
1137 (((u32 __force) txch->bd_mem + 0xF) & ~0xF);
1138 txch->bd_pool_head = NULL;
1139 for (cnt = 0; cnt < txch->num_bd; cnt++) {
1140 curr_bd = mem + (cnt * bd_size);
1141 curr_bd->next = txch->bd_pool_head;
1142 txch->bd_pool_head = curr_bd;
1143 }
1144
1145 /* reset statistics counters */
1146 txch->out_of_tx_bd = 0;
1147 txch->no_active_pkts = 0;
1148 txch->active_queue_count = 0;
1149
1150 return 0;
1151}
1152
1153/**
1154 * emac_cleanup_txch: Book-keep function to clean TX channel resources
1155 * @priv: The DaVinci EMAC private adapter structure
1156 * @ch: TX channel number
1157 *
1158 * Called to clean up TX channel resources
1159 *
1160 */
1161static void emac_cleanup_txch(struct emac_priv *priv, u32 ch)
1162{
1163 struct emac_txch *txch = priv->txch[ch];
1164
1165 if (txch) {
1166 if (txch->bd_mem)
1167 txch->bd_mem = NULL;
1168 kfree(txch->tx_complete);
1169 kfree(txch);
1170 priv->txch[ch] = NULL;
1171 }
1172}
1173
1174/**
1175 * emac_net_tx_complete: TX packet completion function
1176 * @priv: The DaVinci EMAC private adapter structure
1177 * @net_data_tokens: packet token - skb pointer
1178 * @num_tokens: number of skb's to free
1179 * @ch: TX channel number
1180 *
1181 * Frees the skb once packet is transmitted
1182 *
1183 */
1184static int emac_net_tx_complete(struct emac_priv *priv,
1185 void **net_data_tokens,
1186 int num_tokens, u32 ch)
1187{
1188 u32 cnt;
1189
1190 if (unlikely(num_tokens && netif_queue_stopped(priv->ndev)))
1191 netif_start_queue(priv->ndev);
1192 for (cnt = 0; cnt < num_tokens; cnt++) {
1193 struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt];
1194 if (skb == NULL)
1195 continue;
1196 priv->net_dev_stats.tx_packets++;
1197 priv->net_dev_stats.tx_bytes += skb->len;
1198 dev_kfree_skb_any(skb);
1199 }
1200 return 0;
1201}
1202
1203/**
1204 * emac_txch_teardown: TX channel teardown
1205 * @priv: The DaVinci EMAC private adapter structure
1206 * @ch: TX channel number
1207 *
1208 * Called to teardown TX channel
1209 *
1210 */
1211static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
1212{
1213 struct device *emac_dev = &priv->ndev->dev;
1214 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1215 struct emac_txch *txch = priv->txch[ch];
1216 struct emac_tx_bd __iomem *curr_bd;
1217
1218 while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1219 EMAC_TEARDOWN_VALUE) {
1220 /* wait till tx teardown complete */
1221 cpu_relax(); /* TODO: check if this helps ... */
1222 --teardown_cnt;
1223 if (0 == teardown_cnt) {
1224 dev_err(emac_dev, "EMAC: TX teardown aborted\n");
1225 break;
1226 }
1227 }
1228 emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
1229
1230 /* process sent packets and return skb's to upper layer */
1231 if (1 == txch->queue_active) {
1232 curr_bd = txch->active_queue_head;
1233 while (curr_bd != NULL) {
1234 emac_net_tx_complete(priv, (void __force *)
1235 &curr_bd->buf_token, 1, ch);
1236 if (curr_bd != txch->active_queue_tail)
1237 curr_bd = curr_bd->next;
1238 else
1239 break;
1240 }
1241 txch->bd_pool_head = txch->active_queue_head;
1242 txch->active_queue_head =
1243 txch->active_queue_tail = NULL;
1244 }
1245}
1246
1247/**
1248 * emac_stop_txch: Stop TX channel operation
1249 * @priv: The DaVinci EMAC private adapter structure
1250 * @ch: TX channel number
1251 *
1252 * Called to stop TX channel operation
1253 *
1254 */
1255static void emac_stop_txch(struct emac_priv *priv, u32 ch)
1256{
1257 struct emac_txch *txch = priv->txch[ch];
1258
1259 if (txch) {
1260 txch->teardown_pending = 1;
1261 emac_write(EMAC_TXTEARDOWN, 0);
1262 emac_txch_teardown(priv, ch);
1263 txch->teardown_pending = 0;
1264 emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
1265 }
1266}
1267
1268/**
1269 * emac_tx_bdproc: TX buffer descriptor (packet) processing
1270 * @priv: The DaVinci EMAC private adapter structure
1271 * @ch: TX channel number to process buffer descriptors for
1272 * @budget: number of packets allowed to process
1273 * @pending: indication to caller that packets are pending to process
1274 *
1275 * Processes TX buffer descriptors after packets are transmitted - checks
1276 * ownership bit on the TX * descriptor and requeues it to free pool & frees
1277 * the SKB buffer. Only "budget" number of packets are processed and
1278 * indication of pending packets provided to the caller
1279 *
1280 * Returns number of packets processed
1281 */
1282static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1283{
1284 struct device *emac_dev = &priv->ndev->dev;
1285 unsigned long flags;
1286 u32 frame_status;
1287 u32 pkts_processed = 0;
1288 u32 tx_complete_cnt = 0;
1289 struct emac_tx_bd __iomem *curr_bd;
1290 struct emac_txch *txch = priv->txch[ch];
1291 u32 *tx_complete_ptr = txch->tx_complete;
1292
1293 if (unlikely(1 == txch->teardown_pending)) {
1294 if (netif_msg_tx_err(priv) && net_ratelimit()) {
1295 dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\
1296 "teardown pending\n");
1297 }
1298 return 0; /* dont handle any pkt completions */
1299 }
1300
1301 ++txch->proc_count;
1302 spin_lock_irqsave(&priv->tx_lock, flags);
1303 curr_bd = txch->active_queue_head;
1304 if (NULL == curr_bd) {
1305 emac_write(EMAC_TXCP(ch),
1306 emac_virt_to_phys(txch->last_hw_bdprocessed));
1307 txch->no_active_pkts++;
1308 spin_unlock_irqrestore(&priv->tx_lock, flags);
1309 return 0;
1310 }
1311 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1312 frame_status = curr_bd->mode;
1313 while ((curr_bd) &&
1314 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1315 (pkts_processed < budget)) {
1316 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd));
1317 txch->active_queue_head = curr_bd->next;
1318 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1319 if (curr_bd->next) { /* misqueued packet */
1320 emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
1321 ++txch->mis_queued_packets;
1322 } else {
1323 txch->queue_active = 0; /* end of queue */
1324 }
1325 }
1326 *tx_complete_ptr = (u32) curr_bd->buf_token;
1327 ++tx_complete_ptr;
1328 ++tx_complete_cnt;
1329 curr_bd->next = txch->bd_pool_head;
1330 txch->bd_pool_head = curr_bd;
1331 --txch->active_queue_count;
1332 pkts_processed++;
1333 txch->last_hw_bdprocessed = curr_bd;
1334 curr_bd = txch->active_queue_head;
1335 if (curr_bd) {
1336 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1337 frame_status = curr_bd->mode;
1338 }
1339 } /* end of pkt processing loop */
1340
1341 emac_net_tx_complete(priv,
1342 (void *)&txch->tx_complete[0],
1343 tx_complete_cnt, ch);
1344 spin_unlock_irqrestore(&priv->tx_lock, flags);
1345 return pkts_processed;
1346}
1347
1348#define EMAC_ERR_TX_OUT_OF_BD -1
1349
1350/**
1351 * emac_send: EMAC Transmit function (internal)
1352 * @priv: The DaVinci EMAC private adapter structure
1353 * @pkt: packet pointer (contains skb ptr)
1354 * @ch: TX channel number
1355 *
1356 * Called by the transmit function to queue the packet in EMAC hardware queue
1357 *
1358 * Returns success(0) or error code (typically out of desc's)
1359 */
1360static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1361{
1362 unsigned long flags;
1363 struct emac_tx_bd __iomem *curr_bd;
1364 struct emac_txch *txch;
1365 struct emac_netbufobj *buf_list;
1366
1367 txch = priv->txch[ch];
1368 buf_list = pkt->buf_list; /* get handle to the buffer array */
1369
1370 /* check packet size and pad if short */
1371 if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
1372 buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
1373 pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
1374 }
1375
1376 spin_lock_irqsave(&priv->tx_lock, flags);
1377 curr_bd = txch->bd_pool_head;
1378 if (curr_bd == NULL) {
1379 txch->out_of_tx_bd++;
1380 spin_unlock_irqrestore(&priv->tx_lock, flags);
1381 return EMAC_ERR_TX_OUT_OF_BD;
1382 }
1383
1384 txch->bd_pool_head = curr_bd->next;
1385 curr_bd->buf_token = buf_list->buf_token;
1386 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1387 curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr);
1388 curr_bd->off_b_len = buf_list->length;
1389 curr_bd->h_next = 0;
1390 curr_bd->next = NULL;
1391 curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
1392 EMAC_CPPI_EOP_BIT | pkt->pkt_length);
1393
1394 /* flush the packet from cache if write back cache is present */
1395 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1396
1397 /* send the packet */
1398 if (txch->active_queue_head == NULL) {
1399 txch->active_queue_head = curr_bd;
1400 txch->active_queue_tail = curr_bd;
1401 if (1 != txch->queue_active) {
1402 emac_write(EMAC_TXHDP(ch),
1403 emac_virt_to_phys(curr_bd));
1404 txch->queue_active = 1;
1405 }
1406 ++txch->queue_reinit;
1407 } else {
1408 register struct emac_tx_bd __iomem *tail_bd;
1409 register u32 frame_status;
1410
1411 tail_bd = txch->active_queue_tail;
1412 tail_bd->next = curr_bd;
1413 txch->active_queue_tail = curr_bd;
1414 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1415 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd);
1416 frame_status = tail_bd->mode;
1417 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1418 emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd));
1419 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1420 tail_bd->mode = frame_status;
1421 ++txch->end_of_queue_add;
1422 }
1423 }
1424 txch->active_queue_count++;
1425 spin_unlock_irqrestore(&priv->tx_lock, flags);
1426 return 0;
1427}
1428
1429/**
1430 * emac_dev_xmit: EMAC Transmit function
1431 * @skb: SKB pointer
1432 * @ndev: The DaVinci EMAC network adapter
1433 *
1434 * Called by the system to transmit a packet - we queue the packet in
1435 * EMAC hardware transmit queue
1436 *
1437 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1438 */
1439static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1440{
1441 struct device *emac_dev = &ndev->dev;
1442 int ret_code;
1443 struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
1444 struct emac_netpktobj tx_packet; /* packet object */
1445 struct emac_priv *priv = netdev_priv(ndev);
1446
1447 /* If no link, return */
1448 if (unlikely(!priv->link)) {
1449 if (netif_msg_tx_err(priv) && net_ratelimit())
1450 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1451 return NETDEV_TX_BUSY;
1452 }
1453
1454 /* Build the buffer and packet objects - Since only single fragment is
1455 * supported, need not set length and token in both packet & object.
1456 * Doing so for completeness sake & to show that this needs to be done
1457 * in multifragment case
1458 */
1459 tx_packet.buf_list = &tx_buf;
1460 tx_packet.num_bufs = 1; /* only single fragment supported */
1461 tx_packet.pkt_length = skb->len;
1462 tx_packet.pkt_token = (void *)skb;
1463 tx_buf.length = skb->len;
1464 tx_buf.buf_token = (void *)skb;
1465 tx_buf.data_ptr = skb->data;
1466 EMAC_CACHE_WRITEBACK((unsigned long)skb->data, skb->len);
1467 ndev->trans_start = jiffies;
1468 ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
1469 if (unlikely(ret_code != 0)) {
1470 if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
1471 if (netif_msg_tx_err(priv) && net_ratelimit())
1472 dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\
1473 " err. Out of TX BD's");
1474 netif_stop_queue(priv->ndev);
1475 }
1476 priv->net_dev_stats.tx_dropped++;
1477 return NETDEV_TX_BUSY;
1478 }
1479
1480 return NETDEV_TX_OK;
1481}
1482
1483/**
1484 * emac_dev_tx_timeout: EMAC Transmit timeout function
1485 * @ndev: The DaVinci EMAC network adapter
1486 *
1487 * Called when system detects that a skb timeout period has expired
1488 * potentially due to a fault in the adapter in not being able to send
1489 * it out on the wire. We teardown the TX channel assuming a hardware
1490 * error and re-initialize the TX channel for hardware operation
1491 *
1492 */
1493static void emac_dev_tx_timeout(struct net_device *ndev)
1494{
1495 struct emac_priv *priv = netdev_priv(ndev);
1496 struct device *emac_dev = &ndev->dev;
1497
1498 if (netif_msg_tx_err(priv))
1499 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1500
1501 priv->net_dev_stats.tx_errors++;
1502 emac_int_disable(priv);
1503 emac_stop_txch(priv, EMAC_DEF_TX_CH);
1504 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
1505 emac_init_txch(priv, EMAC_DEF_TX_CH);
1506 emac_write(EMAC_TXHDP(0), 0);
1507 emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
1508 emac_int_enable(priv);
1509}
1510
1511/**
1512 * emac_net_alloc_rx_buf: Allocate a skb for RX
1513 * @priv: The DaVinci EMAC private adapter structure
1514 * @buf_size: size of SKB data buffer to allocate
1515 * @data_token: data token returned (skb handle for storing in buffer desc)
1516 * @ch: RX channel number
1517 *
1518 * Called during RX channel setup - allocates skb buffer of required size
1519 * and provides the skb handle and allocated buffer data pointer to caller
1520 *
1521 * Returns skb data pointer or 0 on failure to alloc skb
1522 */
1523static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
1524 void **data_token, u32 ch)
1525{
1526 struct net_device *ndev = priv->ndev;
1527 struct device *emac_dev = &ndev->dev;
1528 struct sk_buff *p_skb;
1529
1530 p_skb = dev_alloc_skb(buf_size);
1531 if (unlikely(NULL == p_skb)) {
1532 if (netif_msg_rx_err(priv) && net_ratelimit())
1533 dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb");
1534 return NULL;
1535 }
1536
1537 /* set device pointer in skb and reserve space for extra bytes */
1538 p_skb->dev = ndev;
1539 skb_reserve(p_skb, NET_IP_ALIGN);
1540 *data_token = (void *) p_skb;
1541 EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p_skb->data, buf_size);
1542 return p_skb->data;
1543}
1544
1545/**
1546 * emac_init_rxch: RX channel initialization
1547 * @priv: The DaVinci EMAC private adapter structure
1548 * @ch: RX channel number
1549 * @param: mac address for RX channel
1550 *
1551 * Called during device init to setup a RX channel (allocate buffers and
1552 * buffer descriptors, create queue and keep ready for reception
1553 *
1554 * Returns success(0) or mem alloc failures error code
1555 */
1556static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
1557{
1558 struct device *emac_dev = &priv->ndev->dev;
1559 u32 cnt, bd_size;
1560 void __iomem *mem;
1561 struct emac_rx_bd __iomem *curr_bd;
1562 struct emac_rxch *rxch = NULL;
1563
1564 rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL);
1565 if (NULL == rxch) {
1566 dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed");
1567 return -ENOMEM;
1568 }
1569 priv->rxch[ch] = rxch;
1570 rxch->buf_size = priv->rx_buf_size;
1571 rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
1572 rxch->queue_active = 0;
1573 rxch->teardown_pending = 0;
1574
1575 /* save mac address */
1576 for (cnt = 0; cnt < 6; cnt++)
1577 rxch->mac_addr[cnt] = param[cnt];
1578
1579 /* allocate buffer descriptor pool align every BD on four word
1580 * boundry for future requirements */
1581 bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
1582 rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1583 rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
1584 rxch->bd_mem = EMAC_RX_BD_MEM(priv);
1585 __memzero((void __force *)rxch->bd_mem, rxch->alloc_size);
1586 rxch->pkt_queue.buf_list = &rxch->buf_queue;
1587
1588 /* allocate RX buffer and initialize the BD linked list */
1589 mem = (void __force __iomem *)
1590 (((u32 __force) rxch->bd_mem + 0xF) & ~0xF);
1591 rxch->active_queue_head = NULL;
1592 rxch->active_queue_tail = mem;
1593 for (cnt = 0; cnt < rxch->num_bd; cnt++) {
1594 curr_bd = mem + (cnt * bd_size);
1595 /* for future use the last parameter contains the BD ptr */
1596 curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
1597 rxch->buf_size,
1598 (void __force **)&curr_bd->buf_token,
1599 EMAC_DEF_RX_CH);
1600 if (curr_bd->data_ptr == NULL) {
1601 dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \
1602 "failed for ch %d\n", ch);
1603 kfree(rxch);
1604 return -ENOMEM;
1605 }
1606
1607 /* populate the hardware descriptor */
1608 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head);
1609 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1610 curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr);
1611 curr_bd->off_b_len = rxch->buf_size;
1612 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1613
1614 /* write back to hardware memory */
1615 BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd,
1616 EMAC_BD_LENGTH_FOR_CACHE);
1617 curr_bd->next = rxch->active_queue_head;
1618 rxch->active_queue_head = curr_bd;
1619 }
1620
1621 /* At this point rxCppi->activeQueueHead points to the first
1622 RX BD ready to be given to RX HDP and rxch->active_queue_tail
1623 points to the last RX BD
1624 */
1625 return 0;
1626}
1627
1628/**
1629 * emac_rxch_teardown: RX channel teardown
1630 * @priv: The DaVinci EMAC private adapter structure
1631 * @ch: RX channel number
1632 *
1633 * Called during device stop to teardown RX channel
1634 *
1635 */
1636static void emac_rxch_teardown(struct emac_priv *priv, u32 ch)
1637{
1638 struct device *emac_dev = &priv->ndev->dev;
1639 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1640
1641 while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1642 EMAC_TEARDOWN_VALUE) {
1643 /* wait till tx teardown complete */
1644 cpu_relax(); /* TODO: check if this helps ... */
1645 --teardown_cnt;
1646 if (0 == teardown_cnt) {
1647 dev_err(emac_dev, "EMAC: RX teardown aborted\n");
1648 break;
1649 }
1650 }
1651 emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE);
1652}
1653
1654/**
1655 * emac_stop_rxch: Stop RX channel operation
1656 * @priv: The DaVinci EMAC private adapter structure
1657 * @ch: RX channel number
1658 *
1659 * Called during device stop to stop RX channel operation
1660 *
1661 */
1662static void emac_stop_rxch(struct emac_priv *priv, u32 ch)
1663{
1664 struct emac_rxch *rxch = priv->rxch[ch];
1665
1666 if (rxch) {
1667 rxch->teardown_pending = 1;
1668 emac_write(EMAC_RXTEARDOWN, ch);
1669 /* wait for teardown complete */
1670 emac_rxch_teardown(priv, ch);
1671 rxch->teardown_pending = 0;
1672 emac_write(EMAC_RXINTMASKCLEAR, BIT(ch));
1673 }
1674}
1675
1676/**
1677 * emac_cleanup_rxch: Book-keep function to clean RX channel resources
1678 * @priv: The DaVinci EMAC private adapter structure
1679 * @ch: RX channel number
1680 *
1681 * Called during device stop to clean up RX channel resources
1682 *
1683 */
1684static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
1685{
1686 struct emac_rxch *rxch = priv->rxch[ch];
1687 struct emac_rx_bd __iomem *curr_bd;
1688
1689 if (rxch) {
1690 /* free the receive buffers previously allocated */
1691 curr_bd = rxch->active_queue_head;
1692 while (curr_bd) {
1693 if (curr_bd->buf_token) {
1694 dev_kfree_skb_any((struct sk_buff *)\
1695 curr_bd->buf_token);
1696 }
1697 curr_bd = curr_bd->next;
1698 }
1699 if (rxch->bd_mem)
1700 rxch->bd_mem = NULL;
1701 kfree(rxch);
1702 priv->rxch[ch] = NULL;
1703 }
1704}
1705
1706/**
1707 * emac_set_type0addr: Set EMAC Type0 mac address
1708 * @priv: The DaVinci EMAC private adapter structure
1709 * @ch: RX channel number
1710 * @mac_addr: MAC address to set in device
1711 *
1712 * Called internally to set Type0 mac address of the adapter (Device)
1713 *
1714 * Returns success (0) or appropriate error code (none as of now)
1715 */
1716static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1717{
1718 u32 val;
1719 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1720 emac_write(EMAC_MACSRCADDRLO, val);
1721
1722 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1723 (mac_addr[1] << 8) | (mac_addr[0]));
1724 emac_write(EMAC_MACSRCADDRHI, val);
1725 val = emac_read(EMAC_RXUNICASTSET);
1726 val |= BIT(ch);
1727 emac_write(EMAC_RXUNICASTSET, val);
1728 val = emac_read(EMAC_RXUNICASTCLEAR);
1729 val &= ~BIT(ch);
1730 emac_write(EMAC_RXUNICASTCLEAR, val);
1731}
1732
1733/**
1734 * emac_set_type1addr: Set EMAC Type1 mac address
1735 * @priv: The DaVinci EMAC private adapter structure
1736 * @ch: RX channel number
1737 * @mac_addr: MAC address to set in device
1738 *
1739 * Called internally to set Type1 mac address of the adapter (Device)
1740 *
1741 * Returns success (0) or appropriate error code (none as of now)
1742 */
1743static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1744{
1745 u32 val;
1746 emac_write(EMAC_MACINDEX, ch);
1747 val = ((mac_addr[5] << 8) | mac_addr[4]);
1748 emac_write(EMAC_MACADDRLO, val);
1749 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1750 (mac_addr[1] << 8) | (mac_addr[0]));
1751 emac_write(EMAC_MACADDRHI, val);
1752 emac_set_type0addr(priv, ch, mac_addr);
1753}
1754
1755/**
1756 * emac_set_type2addr: Set EMAC Type2 mac address
1757 * @priv: The DaVinci EMAC private adapter structure
1758 * @ch: RX channel number
1759 * @mac_addr: MAC address to set in device
1760 * @index: index into RX address entries
1761 * @match: match parameter for RX address matching logic
1762 *
1763 * Called internally to set Type2 mac address of the adapter (Device)
1764 *
1765 * Returns success (0) or appropriate error code (none as of now)
1766 */
1767static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1768 char *mac_addr, int index, int match)
1769{
1770 u32 val;
1771 emac_write(EMAC_MACINDEX, index);
1772 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1773 (mac_addr[1] << 8) | (mac_addr[0]));
1774 emac_write(EMAC_MACADDRHI, val);
1775 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1776 (match << 19) | BIT(20));
1777 emac_write(EMAC_MACADDRLO, val);
1778 emac_set_type0addr(priv, ch, mac_addr);
1779}
1780
1781/**
1782 * emac_setmac: Set mac address in the adapter (internal function)
1783 * @priv: The DaVinci EMAC private adapter structure
1784 * @ch: RX channel number
1785 * @mac_addr: MAC address to set in device
1786 *
1787 * Called internally to set the mac address of the adapter (Device)
1788 *
1789 * Returns success (0) or appropriate error code (none as of now)
1790 */
1791static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1792{
1793 struct device *emac_dev = &priv->ndev->dev;
1794
1795 if (priv->rx_addr_type == 0) {
1796 emac_set_type0addr(priv, ch, mac_addr);
1797 } else if (priv->rx_addr_type == 1) {
1798 u32 cnt;
1799 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1800 emac_set_type1addr(priv, ch, mac_addr);
1801 } else if (priv->rx_addr_type == 2) {
1802 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1803 emac_set_type0addr(priv, ch, mac_addr);
1804 } else {
1805 if (netif_msg_drv(priv))
1806 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1807 }
1808}
1809
1810/**
1811 * emac_dev_setmac_addr: Set mac address in the adapter
1812 * @ndev: The DaVinci EMAC network adapter
1813 * @addr: MAC address to set in device
1814 *
1815 * Called by the system to set the mac address of the adapter (Device)
1816 *
1817 * Returns success (0) or appropriate error code (none as of now)
1818 */
1819static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1820{
1821 struct emac_priv *priv = netdev_priv(ndev);
1822 struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH];
1823 struct device *emac_dev = &priv->ndev->dev;
1824 struct sockaddr *sa = addr;
Anant Golea6286ee2009-05-18 15:19:01 -07001825
Pablo Bitton64c81652009-07-07 19:11:10 -07001826 if (!is_valid_ether_addr(sa->sa_data))
1827 return -EINVAL;
1828
Anant Golea6286ee2009-05-18 15:19:01 -07001829 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1830 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
Anant Golea6286ee2009-05-18 15:19:01 -07001831 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
Pablo Bitton64c81652009-07-07 19:11:10 -07001832
1833 /* If the interface is down - rxch is NULL. */
1834 /* MAC address is configured only after the interface is enabled. */
1835 if (netif_running(ndev)) {
1836 memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
1837 emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr);
1838 }
Anant Golea6286ee2009-05-18 15:19:01 -07001839
1840 if (netif_msg_drv(priv))
Chaithrika U S5c726162009-06-03 21:54:29 -07001841 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1842 priv->mac_addr);
Anant Golea6286ee2009-05-18 15:19:01 -07001843
1844 return 0;
1845}
1846
1847/**
1848 * emac_addbd_to_rx_queue: Recycle RX buffer descriptor
1849 * @priv: The DaVinci EMAC private adapter structure
1850 * @ch: RX channel number to process buffer descriptors for
1851 * @curr_bd: current buffer descriptor
1852 * @buffer: buffer pointer for descriptor
1853 * @buf_token: buffer token (stores skb information)
1854 *
1855 * Prepares the recycled buffer descriptor and addes it to hardware
1856 * receive queue - if queue empty this descriptor becomes the head
1857 * else addes the descriptor to end of queue
1858 *
1859 */
1860static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1861 struct emac_rx_bd __iomem *curr_bd,
1862 char *buffer, void *buf_token)
1863{
1864 struct emac_rxch *rxch = priv->rxch[ch];
1865
1866 /* populate the hardware descriptor */
1867 curr_bd->h_next = 0;
1868 /* FIXME buff_ptr = dma_map_single(... buffer ...) */
1869 curr_bd->buff_ptr = virt_to_phys(buffer);
1870 curr_bd->off_b_len = rxch->buf_size;
1871 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1872 curr_bd->next = NULL;
1873 curr_bd->data_ptr = buffer;
1874 curr_bd->buf_token = buf_token;
1875
1876 /* write back */
1877 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1878 if (rxch->active_queue_head == NULL) {
1879 rxch->active_queue_head = curr_bd;
1880 rxch->active_queue_tail = curr_bd;
1881 if (0 != rxch->queue_active) {
1882 emac_write(EMAC_RXHDP(ch),
1883 emac_virt_to_phys(rxch->active_queue_head));
1884 rxch->queue_active = 1;
1885 }
1886 } else {
1887 struct emac_rx_bd __iomem *tail_bd;
1888 u32 frame_status;
1889
1890 tail_bd = rxch->active_queue_tail;
1891 rxch->active_queue_tail = curr_bd;
1892 tail_bd->next = curr_bd;
1893 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1894 tail_bd->h_next = emac_virt_to_phys(curr_bd);
1895 frame_status = tail_bd->mode;
1896 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1897 emac_write(EMAC_RXHDP(ch),
1898 emac_virt_to_phys(curr_bd));
1899 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1900 tail_bd->mode = frame_status;
1901 ++rxch->end_of_queue_add;
1902 }
1903 }
1904 ++rxch->recycled_bd;
1905}
1906
1907/**
1908 * emac_net_rx_cb: Prepares packet and sends to upper layer
1909 * @priv: The DaVinci EMAC private adapter structure
1910 * @net_pkt_list: Network packet list (received packets)
1911 *
1912 * Invalidates packet buffer memory and sends the received packet to upper
1913 * layer
1914 *
1915 * Returns success or appropriate error code (none as of now)
1916 */
1917static int emac_net_rx_cb(struct emac_priv *priv,
1918 struct emac_netpktobj *net_pkt_list)
1919{
1920 struct sk_buff *p_skb;
1921 p_skb = (struct sk_buff *)net_pkt_list->pkt_token;
1922 /* set length of packet */
1923 skb_put(p_skb, net_pkt_list->pkt_length);
1924 EMAC_CACHE_INVALIDATE((unsigned long)p_skb->data, p_skb->len);
1925 p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
Anant Golea6286ee2009-05-18 15:19:01 -07001926 netif_receive_skb(p_skb);
1927 priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length;
1928 priv->net_dev_stats.rx_packets++;
1929 return 0;
1930}
1931
1932/**
1933 * emac_rx_bdproc: RX buffer descriptor (packet) processing
1934 * @priv: The DaVinci EMAC private adapter structure
1935 * @ch: RX channel number to process buffer descriptors for
1936 * @budget: number of packets allowed to process
1937 * @pending: indication to caller that packets are pending to process
1938 *
1939 * Processes RX buffer descriptors - checks ownership bit on the RX buffer
1940 * descriptor, sends the receive packet to upper layer, allocates a new SKB
1941 * and recycles the buffer descriptor (requeues it in hardware RX queue).
1942 * Only "budget" number of packets are processed and indication of pending
1943 * packets provided to the caller.
1944 *
1945 * Returns number of packets processed (and indication of pending packets)
1946 */
1947static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1948{
1949 unsigned long flags;
1950 u32 frame_status;
1951 u32 pkts_processed = 0;
1952 char *new_buffer;
1953 struct emac_rx_bd __iomem *curr_bd;
1954 struct emac_rx_bd __iomem *last_bd;
1955 struct emac_netpktobj *curr_pkt, pkt_obj;
1956 struct emac_netbufobj buf_obj;
1957 struct emac_netbufobj *rx_buf_obj;
1958 void *new_buf_token;
1959 struct emac_rxch *rxch = priv->rxch[ch];
1960
1961 if (unlikely(1 == rxch->teardown_pending))
1962 return 0;
1963 ++rxch->proc_count;
1964 spin_lock_irqsave(&priv->rx_lock, flags);
1965 pkt_obj.buf_list = &buf_obj;
1966 curr_pkt = &pkt_obj;
1967 curr_bd = rxch->active_queue_head;
1968 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1969 frame_status = curr_bd->mode;
1970
1971 while ((curr_bd) &&
1972 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1973 (pkts_processed < budget)) {
1974
1975 new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
1976 &new_buf_token, EMAC_DEF_RX_CH);
1977 if (unlikely(NULL == new_buffer)) {
1978 ++rxch->out_of_rx_buffers;
1979 goto end_emac_rx_bdproc;
1980 }
1981
1982 /* populate received packet data structure */
1983 rx_buf_obj = &curr_pkt->buf_list[0];
1984 rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
1985 rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
1986 rx_buf_obj->buf_token = curr_bd->buf_token;
1987 curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
1988 curr_pkt->num_bufs = 1;
1989 curr_pkt->pkt_length =
1990 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
1991 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd));
1992 ++rxch->processed_bd;
1993 last_bd = curr_bd;
1994 curr_bd = last_bd->next;
1995 rxch->active_queue_head = curr_bd;
1996
1997 /* check if end of RX queue ? */
1998 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1999 if (curr_bd) {
2000 ++rxch->mis_queued_packets;
2001 emac_write(EMAC_RXHDP(ch),
2002 emac_virt_to_phys(curr_bd));
2003 } else {
2004 ++rxch->end_of_queue;
2005 rxch->queue_active = 0;
2006 }
2007 }
2008
2009 /* recycle BD */
2010 emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
2011 new_buf_token);
2012
2013 /* return the packet to the user - BD ptr passed in
2014 * last parameter for potential *future* use */
2015 spin_unlock_irqrestore(&priv->rx_lock, flags);
2016 emac_net_rx_cb(priv, curr_pkt);
2017 spin_lock_irqsave(&priv->rx_lock, flags);
2018 curr_bd = rxch->active_queue_head;
2019 if (curr_bd) {
2020 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2021 frame_status = curr_bd->mode;
2022 }
2023 ++pkts_processed;
2024 }
2025
2026end_emac_rx_bdproc:
2027 spin_unlock_irqrestore(&priv->rx_lock, flags);
2028 return pkts_processed;
2029}
2030
2031/**
2032 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
2033 * @priv: The DaVinci EMAC private adapter structure
2034 *
2035 * Enables EMAC hardware for packet processing - enables PHY, enables RX
2036 * for packet reception and enables device interrupts and then NAPI
2037 *
2038 * Returns success (0) or appropriate error code (none right now)
2039 */
2040static int emac_hw_enable(struct emac_priv *priv)
2041{
2042 u32 ch, val, mbp_enable, mac_control;
2043
2044 /* Soft reset */
2045 emac_write(EMAC_SOFTRESET, 1);
2046 while (emac_read(EMAC_SOFTRESET))
2047 cpu_relax();
2048
2049 /* Disable interrupt & Set pacing for more interrupts initially */
2050 emac_int_disable(priv);
2051
2052 /* Full duplex enable bit set when auto negotiation happens */
2053 mac_control =
2054 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
2055 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
2056 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
2057 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
2058 emac_write(EMAC_MACCONTROL, mac_control);
2059
2060 mbp_enable =
2061 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
2062 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
2063 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
2064 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
2065 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
2066 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
2067 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
2068 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
2069 EMAC_RXMBP_PROMCH_SHIFT) |
2070 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
2071 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
2072 EMAC_RXMBP_BROADCH_SHIFT) |
2073 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
2074 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
2075 EMAC_RXMBP_MULTICH_SHIFT));
2076 emac_write(EMAC_RXMBPENABLE, mbp_enable);
2077 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
2078 EMAC_RX_MAX_LEN_MASK));
2079 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
2080 EMAC_RX_BUFFER_OFFSET_MASK));
2081 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
2082 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
2083 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
2084
2085 val = emac_read(EMAC_TXCONTROL);
2086 val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
2087 emac_write(EMAC_TXCONTROL, val);
2088 val = emac_read(EMAC_RXCONTROL);
2089 val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
2090 emac_write(EMAC_RXCONTROL, val);
2091 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
2092
2093 for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
2094 emac_write(EMAC_TXHDP(ch), 0);
2095 emac_write(EMAC_TXINTMASKSET, BIT(ch));
2096 }
2097 for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
2098 struct emac_rxch *rxch = priv->rxch[ch];
2099 emac_setmac(priv, ch, rxch->mac_addr);
2100 emac_write(EMAC_RXINTMASKSET, BIT(ch));
2101 rxch->queue_active = 1;
2102 emac_write(EMAC_RXHDP(ch),
2103 emac_virt_to_phys(rxch->active_queue_head));
2104 }
2105
2106 /* Enable MII */
2107 val = emac_read(EMAC_MACCONTROL);
2108 val |= (EMAC_MACCONTROL_MIIEN);
2109 emac_write(EMAC_MACCONTROL, val);
2110
2111 /* Enable NAPI and interrupts */
2112 napi_enable(&priv->napi);
2113 emac_int_enable(priv);
2114 return 0;
2115
2116}
2117
2118/**
2119 * emac_poll: EMAC NAPI Poll function
2120 * @ndev: The DaVinci EMAC network adapter
2121 * @budget: Number of receive packets to process (as told by NAPI layer)
2122 *
2123 * NAPI Poll function implemented to process packets as per budget. We check
2124 * the type of interrupt on the device and accordingly call the TX or RX
2125 * packet processing functions. We follow the budget for RX processing and
2126 * also put a cap on number of TX pkts processed through config param. The
2127 * NAPI schedule function is called if more packets pending.
2128 *
2129 * Returns number of packets received (in most cases; else TX pkts - rarely)
2130 */
2131static int emac_poll(struct napi_struct *napi, int budget)
2132{
2133 unsigned int mask;
2134 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
2135 struct net_device *ndev = priv->ndev;
2136 struct device *emac_dev = &ndev->dev;
2137 u32 status = 0;
2138 u32 num_pkts = 0;
2139
2140 if (!netif_running(ndev))
2141 return 0;
2142
2143 /* Check interrupt vectors and call packet processing */
2144 status = emac_read(EMAC_MACINVECTOR);
2145
2146 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
2147
2148 if (priv->version == EMAC_VERSION_2)
2149 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
2150
2151 if (status & mask) {
2152 num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
2153 EMAC_DEF_TX_MAX_SERVICE);
2154 } /* TX processing */
2155
2156 if (num_pkts)
2157 return budget;
2158
2159 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
2160
2161 if (priv->version == EMAC_VERSION_2)
2162 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
2163
2164 if (status & mask) {
2165 num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget);
2166 } /* RX processing */
2167
2168 if (num_pkts < budget) {
2169 napi_complete(napi);
2170 emac_int_enable(priv);
2171 }
2172
Sriram43c2ed82009-09-24 19:15:18 +00002173 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
2174 if (priv->version == EMAC_VERSION_2)
2175 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
2176
2177 if (unlikely(status & mask)) {
Anant Golea6286ee2009-05-18 15:19:01 -07002178 u32 ch, cause;
2179 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
2180 netif_stop_queue(ndev);
2181 napi_disable(&priv->napi);
2182
2183 status = emac_read(EMAC_MACSTATUS);
2184 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
2185 EMAC_MACSTATUS_TXERRCODE_SHIFT);
2186 if (cause) {
2187 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
2188 EMAC_MACSTATUS_TXERRCH_SHIFT);
2189 if (net_ratelimit()) {
2190 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
2191 &emac_txhost_errcodes[cause][0], ch);
2192 }
2193 }
2194 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
2195 EMAC_MACSTATUS_RXERRCODE_SHIFT);
2196 if (cause) {
2197 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
2198 EMAC_MACSTATUS_RXERRCH_SHIFT);
2199 if (netif_msg_hw(priv) && net_ratelimit())
2200 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
2201 &emac_rxhost_errcodes[cause][0], ch);
2202 }
2203 } /* Host error processing */
2204
2205 return num_pkts;
2206}
2207
2208#ifdef CONFIG_NET_POLL_CONTROLLER
2209/**
2210 * emac_poll_controller: EMAC Poll controller function
2211 * @ndev: The DaVinci EMAC network adapter
2212 *
2213 * Polled functionality used by netconsole and others in non interrupt mode
2214 *
2215 */
2216void emac_poll_controller(struct net_device *ndev)
2217{
2218 struct emac_priv *priv = netdev_priv(ndev);
2219
2220 emac_int_disable(priv);
2221 emac_irq(ndev->irq, priv);
2222 emac_int_enable(priv);
2223}
2224#endif
2225
2226/* PHY/MII bus related */
2227
2228/* Wait until mdio is ready for next command */
2229#define MDIO_WAIT_FOR_USER_ACCESS\
2230 while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
2231 MDIO_USERACCESS_GO) != 0)
2232
2233static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg)
2234{
2235 unsigned int phy_data = 0;
2236 unsigned int phy_control;
2237
2238 /* Wait until mdio is ready for next command */
2239 MDIO_WAIT_FOR_USER_ACCESS;
2240
2241 phy_control = (MDIO_USERACCESS_GO |
2242 MDIO_USERACCESS_READ |
2243 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2244 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2245 (phy_data & MDIO_USERACCESS_DATA));
2246 emac_mdio_write(MDIO_USERACCESS(0), phy_control);
2247
2248 /* Wait until mdio is ready for next command */
2249 MDIO_WAIT_FOR_USER_ACCESS;
2250
2251 return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
2252
2253}
2254
2255static int emac_mii_write(struct mii_bus *bus, int phy_id,
2256 int phy_reg, u16 phy_data)
2257{
2258
2259 unsigned int control;
2260
2261 /* until mdio is ready for next command */
2262 MDIO_WAIT_FOR_USER_ACCESS;
2263
2264 control = (MDIO_USERACCESS_GO |
2265 MDIO_USERACCESS_WRITE |
2266 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2267 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2268 (phy_data & MDIO_USERACCESS_DATA));
2269 emac_mdio_write(MDIO_USERACCESS(0), control);
2270
2271 return 0;
2272}
2273
2274static int emac_mii_reset(struct mii_bus *bus)
2275{
2276 unsigned int clk_div;
2277 int mdio_bus_freq = emac_bus_frequency;
2278
2279 if (mdio_max_freq & mdio_bus_freq)
2280 clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
2281 else
2282 clk_div = 0xFF;
2283
2284 clk_div &= MDIO_CONTROL_CLKDIV;
2285
2286 /* Set enable and clock divider in MDIOControl */
2287 emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
2288
2289 return 0;
2290
2291}
2292
2293static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL };
2294
2295/* emac_driver: EMAC MII bus structure */
2296
2297static struct mii_bus *emac_mii;
2298
2299static void emac_adjust_link(struct net_device *ndev)
2300{
2301 struct emac_priv *priv = netdev_priv(ndev);
2302 struct phy_device *phydev = priv->phydev;
2303 unsigned long flags;
2304 int new_state = 0;
2305
2306 spin_lock_irqsave(&priv->lock, flags);
2307
2308 if (phydev->link) {
2309 /* check the mode of operation - full/half duplex */
2310 if (phydev->duplex != priv->duplex) {
2311 new_state = 1;
2312 priv->duplex = phydev->duplex;
2313 }
2314 if (phydev->speed != priv->speed) {
2315 new_state = 1;
2316 priv->speed = phydev->speed;
2317 }
2318 if (!priv->link) {
2319 new_state = 1;
2320 priv->link = 1;
2321 }
2322
2323 } else if (priv->link) {
2324 new_state = 1;
2325 priv->link = 0;
2326 priv->speed = 0;
2327 priv->duplex = ~0;
2328 }
2329 if (new_state) {
2330 emac_update_phystatus(priv);
2331 phy_print_status(priv->phydev);
2332 }
2333
2334 spin_unlock_irqrestore(&priv->lock, flags);
2335}
2336
2337/*************************************************************************
2338 * Linux Driver Model
2339 *************************************************************************/
2340
2341/**
2342 * emac_devioctl: EMAC adapter ioctl
2343 * @ndev: The DaVinci EMAC network adapter
2344 * @ifrq: request parameter
2345 * @cmd: command parameter
2346 *
2347 * EMAC driver ioctl function
2348 *
2349 * Returns success(0) or appropriate error code
2350 */
2351static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
2352{
2353 dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n");
2354
2355 if (!(netif_running(ndev)))
2356 return -EINVAL;
2357
2358 /* TODO: Add phy read and write and private statistics get feature */
2359
2360 return -EOPNOTSUPP;
2361}
2362
2363/**
2364 * emac_dev_open: EMAC device open
2365 * @ndev: The DaVinci EMAC network adapter
2366 *
2367 * Called when system wants to start the interface. We init TX/RX channels
2368 * and enable the hardware for packet reception/transmission and start the
2369 * network queue.
2370 *
2371 * Returns 0 for a successful open, or appropriate error code
2372 */
2373static int emac_dev_open(struct net_device *ndev)
2374{
2375 struct device *emac_dev = &ndev->dev;
2376 u32 rc, cnt, ch;
2377 int phy_addr;
2378 struct resource *res;
2379 int q, m;
2380 int i = 0;
2381 int k = 0;
2382 struct emac_priv *priv = netdev_priv(ndev);
2383
2384 netif_carrier_off(ndev);
2385 for (cnt = 0; cnt <= ETH_ALEN; cnt++)
2386 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
2387
2388 /* Configuration items */
2389 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
2390
2391 /* Clear basic hardware */
2392 for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
2393 emac_write(EMAC_TXHDP(ch), 0);
2394 emac_write(EMAC_RXHDP(ch), 0);
2395 emac_write(EMAC_RXHDP(ch), 0);
2396 emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2397 emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2398 }
2399 priv->mac_hash1 = 0;
2400 priv->mac_hash2 = 0;
2401 emac_write(EMAC_MACHASH1, 0);
2402 emac_write(EMAC_MACHASH2, 0);
2403
2404 /* multi ch not supported - open 1 TX, 1RX ch by default */
2405 rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
2406 if (0 != rc) {
2407 dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed");
2408 return rc;
2409 }
2410 rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
2411 if (0 != rc) {
2412 dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed");
2413 return rc;
2414 }
2415
2416 /* Request IRQ */
2417
2418 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2419 for (i = res->start; i <= res->end; i++) {
2420 if (request_irq(i, emac_irq, IRQF_DISABLED,
2421 ndev->name, ndev))
2422 goto rollback;
2423 }
2424 k++;
2425 }
2426
2427 /* Start/Enable EMAC hardware */
2428 emac_hw_enable(priv);
2429
2430 /* find the first phy */
2431 priv->phydev = NULL;
2432 if (priv->phy_mask) {
2433 emac_mii_reset(priv->mii_bus);
2434 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
2435 if (priv->mii_bus->phy_map[phy_addr]) {
2436 priv->phydev = priv->mii_bus->phy_map[phy_addr];
2437 break;
2438 }
2439 }
2440
2441 if (!priv->phydev) {
2442 printk(KERN_ERR "%s: no PHY found\n", ndev->name);
2443 return -1;
2444 }
2445
2446 priv->phydev = phy_connect(ndev, dev_name(&priv->phydev->dev),
2447 &emac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
2448
2449 if (IS_ERR(priv->phydev)) {
2450 printk(KERN_ERR "%s: Could not attach to PHY\n",
2451 ndev->name);
2452 return PTR_ERR(priv->phydev);
2453 }
2454
2455 priv->link = 0;
2456 priv->speed = 0;
2457 priv->duplex = ~0;
2458
2459 printk(KERN_INFO "%s: attached PHY driver [%s] "
2460 "(mii_bus:phy_addr=%s, id=%x)\n", ndev->name,
2461 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
2462 priv->phydev->phy_id);
2463 } else{
2464 /* No PHY , fix the link, speed and duplex settings */
2465 priv->link = 1;
2466 priv->speed = SPEED_100;
2467 priv->duplex = DUPLEX_FULL;
2468 emac_update_phystatus(priv);
2469 }
2470
2471 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
2472 emac_dump_regs(priv);
2473
2474 if (netif_msg_drv(priv))
2475 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
2476
2477 if (priv->phy_mask)
2478 phy_start(priv->phydev);
2479
2480 return 0;
2481
2482rollback:
2483
2484 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
2485
2486 for (q = k; k >= 0; k--) {
2487 for (m = i; m >= res->start; m--)
2488 free_irq(m, ndev);
2489 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
2490 m = res->end;
2491 }
2492 return -EBUSY;
2493}
2494
2495/**
2496 * emac_dev_stop: EMAC device stop
2497 * @ndev: The DaVinci EMAC network adapter
2498 *
2499 * Called when system wants to stop or down the interface. We stop the network
2500 * queue, disable interrupts and cleanup TX/RX channels.
2501 *
2502 * We return the statistics in net_device_stats structure pulled from emac
2503 */
2504static int emac_dev_stop(struct net_device *ndev)
2505{
2506 struct resource *res;
2507 int i = 0;
2508 int irq_num;
2509 struct emac_priv *priv = netdev_priv(ndev);
2510 struct device *emac_dev = &ndev->dev;
2511
2512 /* inform the upper layers. */
2513 netif_stop_queue(ndev);
2514 napi_disable(&priv->napi);
2515
2516 netif_carrier_off(ndev);
2517 emac_int_disable(priv);
2518 emac_stop_txch(priv, EMAC_DEF_TX_CH);
2519 emac_stop_rxch(priv, EMAC_DEF_RX_CH);
2520 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
2521 emac_cleanup_rxch(priv, EMAC_DEF_RX_CH);
2522 emac_write(EMAC_SOFTRESET, 1);
2523
2524 if (priv->phydev)
2525 phy_disconnect(priv->phydev);
2526
2527 /* Free IRQ */
2528 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
2529 for (irq_num = res->start; irq_num <= res->end; irq_num++)
2530 free_irq(irq_num, priv->ndev);
2531 i++;
2532 }
2533
2534 if (netif_msg_drv(priv))
2535 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
2536
2537 return 0;
2538}
2539
2540/**
2541 * emac_dev_getnetstats: EMAC get statistics function
2542 * @ndev: The DaVinci EMAC network adapter
2543 *
2544 * Called when system wants to get statistics from the device.
2545 *
2546 * We return the statistics in net_device_stats structure pulled from emac
2547 */
2548static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
2549{
2550 struct emac_priv *priv = netdev_priv(ndev);
2551
2552 /* update emac hardware stats and reset the registers*/
2553
2554 priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
2555 emac_write(EMAC_RXMCASTFRAMES, EMAC_ALL_MULTI_REG_VALUE);
2556
2557 priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) +
2558 emac_read(EMAC_TXSINGLECOLL) +
2559 emac_read(EMAC_TXMULTICOLL));
2560 emac_write(EMAC_TXCOLLISION, EMAC_ALL_MULTI_REG_VALUE);
2561 emac_write(EMAC_TXSINGLECOLL, EMAC_ALL_MULTI_REG_VALUE);
2562 emac_write(EMAC_TXMULTICOLL, EMAC_ALL_MULTI_REG_VALUE);
2563
2564 priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
2565 emac_read(EMAC_RXJABBER) +
2566 emac_read(EMAC_RXUNDERSIZED));
2567 emac_write(EMAC_RXOVERSIZED, EMAC_ALL_MULTI_REG_VALUE);
2568 emac_write(EMAC_RXJABBER, EMAC_ALL_MULTI_REG_VALUE);
2569 emac_write(EMAC_RXUNDERSIZED, EMAC_ALL_MULTI_REG_VALUE);
2570
2571 priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
2572 emac_read(EMAC_RXMOFOVERRUNS));
2573 emac_write(EMAC_RXSOFOVERRUNS, EMAC_ALL_MULTI_REG_VALUE);
2574 emac_write(EMAC_RXMOFOVERRUNS, EMAC_ALL_MULTI_REG_VALUE);
2575
2576 priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
2577 emac_write(EMAC_RXDMAOVERRUNS, EMAC_ALL_MULTI_REG_VALUE);
2578
2579 priv->net_dev_stats.tx_carrier_errors +=
2580 emac_read(EMAC_TXCARRIERSENSE);
2581 emac_write(EMAC_TXCARRIERSENSE, EMAC_ALL_MULTI_REG_VALUE);
2582
2583 priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
2584 emac_write(EMAC_TXUNDERRUN, EMAC_ALL_MULTI_REG_VALUE);
2585
2586 return &priv->net_dev_stats;
2587}
2588
2589static const struct net_device_ops emac_netdev_ops = {
2590 .ndo_open = emac_dev_open,
2591 .ndo_stop = emac_dev_stop,
2592 .ndo_start_xmit = emac_dev_xmit,
2593 .ndo_set_multicast_list = emac_dev_mcast_set,
2594 .ndo_set_mac_address = emac_dev_setmac_addr,
2595 .ndo_do_ioctl = emac_devioctl,
2596 .ndo_tx_timeout = emac_dev_tx_timeout,
2597 .ndo_get_stats = emac_dev_getnetstats,
2598#ifdef CONFIG_NET_POLL_CONTROLLER
2599 .ndo_poll_controller = emac_poll_controller,
2600#endif
2601};
2602
2603/**
2604 * davinci_emac_probe: EMAC device probe
2605 * @pdev: The DaVinci EMAC device that we are removing
2606 *
2607 * Called when probing for emac devicesr. We get details of instances and
2608 * resource information from platform init and register a network device
2609 * and allocate resources necessary for driver to perform
2610 */
2611static int __devinit davinci_emac_probe(struct platform_device *pdev)
2612{
2613 int rc = 0;
2614 struct resource *res;
2615 struct net_device *ndev;
2616 struct emac_priv *priv;
2617 unsigned long size;
2618 struct emac_platform_data *pdata;
2619 struct device *emac_dev;
2620
2621 /* obtain emac clock from kernel */
2622 emac_clk = clk_get(&pdev->dev, NULL);
2623 if (IS_ERR(emac_clk)) {
2624 printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n");
2625 return -EBUSY;
2626 }
2627 emac_bus_frequency = clk_get_rate(emac_clk);
2628 /* TODO: Probe PHY here if possible */
2629
2630 ndev = alloc_etherdev(sizeof(struct emac_priv));
2631 if (!ndev) {
2632 printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n");
2633 clk_put(emac_clk);
2634 return -ENOMEM;
2635 }
2636
2637 platform_set_drvdata(pdev, ndev);
2638 priv = netdev_priv(ndev);
2639 priv->pdev = pdev;
2640 priv->ndev = ndev;
2641 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
2642
2643 spin_lock_init(&priv->tx_lock);
2644 spin_lock_init(&priv->rx_lock);
2645 spin_lock_init(&priv->lock);
2646
2647 pdata = pdev->dev.platform_data;
2648 if (!pdata) {
2649 printk(KERN_ERR "DaVinci EMAC: No platfrom data\n");
2650 return -ENODEV;
2651 }
2652
2653 /* MAC addr and PHY mask , RMII enable info from platform_data */
2654 memcpy(priv->mac_addr, pdata->mac_addr, 6);
2655 priv->phy_mask = pdata->phy_mask;
2656 priv->rmii_en = pdata->rmii_en;
2657 priv->version = pdata->version;
2658 emac_dev = &ndev->dev;
2659 /* Get EMAC platform data */
2660 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2661 if (!res) {
2662 dev_err(emac_dev, "DaVinci EMAC: Error getting res\n");
2663 rc = -ENOENT;
2664 goto probe_quit;
2665 }
2666
2667 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
2668 size = res->end - res->start + 1;
2669 if (!request_mem_region(res->start, size, ndev->name)) {
2670 dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() \
2671 for regs\n");
2672 rc = -ENXIO;
2673 goto probe_quit;
2674 }
2675
2676 priv->remap_addr = ioremap(res->start, size);
2677 if (!priv->remap_addr) {
2678 dev_err(emac_dev, "Unable to map IO\n");
2679 rc = -ENOMEM;
2680 release_mem_region(res->start, size);
2681 goto probe_quit;
2682 }
2683 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
2684 ndev->base_addr = (unsigned long)priv->remap_addr;
2685
2686 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
2687 priv->ctrl_ram_size = pdata->ctrl_ram_size;
2688 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2689
2690 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2691 if (!res) {
2692 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n");
2693 rc = -ENOENT;
2694 goto no_irq_res;
2695 }
2696 ndev->irq = res->start;
2697
2698 if (!is_valid_ether_addr(priv->mac_addr)) {
Anant Golea6286ee2009-05-18 15:19:01 -07002699 /* Use random MAC if none passed */
2700 random_ether_addr(priv->mac_addr);
Chaithrika U S5c726162009-06-03 21:54:29 -07002701 printk(KERN_WARNING "%s: using random MAC addr: %pM\n",
2702 __func__, priv->mac_addr);
Anant Golea6286ee2009-05-18 15:19:01 -07002703 }
2704
2705 ndev->netdev_ops = &emac_netdev_ops;
2706 SET_ETHTOOL_OPS(ndev, &ethtool_ops);
2707 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2708
2709 /* register the network device */
2710 SET_NETDEV_DEV(ndev, &pdev->dev);
2711 rc = register_netdev(ndev);
2712 if (rc) {
2713 dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n");
2714 rc = -ENODEV;
2715 goto netdev_reg_err;
2716 }
2717
2718 clk_enable(emac_clk);
2719
2720 /* MII/Phy intialisation, mdio bus registration */
2721 emac_mii = mdiobus_alloc();
2722 if (emac_mii == NULL) {
2723 dev_err(emac_dev, "DaVinci EMAC: Error allocating mii_bus\n");
2724 rc = -ENOMEM;
2725 goto mdio_alloc_err;
2726 }
2727
2728 priv->mii_bus = emac_mii;
2729 emac_mii->name = "emac-mii",
2730 emac_mii->read = emac_mii_read,
2731 emac_mii->write = emac_mii_write,
2732 emac_mii->reset = emac_mii_reset,
2733 emac_mii->irq = mii_irqs,
2734 emac_mii->phy_mask = ~(priv->phy_mask);
2735 emac_mii->parent = &pdev->dev;
2736 emac_mii->priv = priv->remap_addr + pdata->mdio_reg_offset;
2737 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", priv->pdev->id);
2738 mdio_max_freq = pdata->mdio_max_freq;
2739 emac_mii->reset(emac_mii);
2740
2741 /* Register the MII bus */
2742 rc = mdiobus_register(emac_mii);
2743 if (rc)
2744 goto mdiobus_quit;
2745
2746 if (netif_msg_probe(priv)) {
2747 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2748 "(regs: %p, irq: %d)\n",
2749 (void *)priv->emac_base_phys, ndev->irq);
2750 }
2751 return 0;
2752
2753mdiobus_quit:
2754 mdiobus_free(emac_mii);
2755
2756netdev_reg_err:
2757mdio_alloc_err:
2758no_irq_res:
2759 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2760 release_mem_region(res->start, res->end - res->start + 1);
2761 iounmap(priv->remap_addr);
2762
2763probe_quit:
2764 clk_put(emac_clk);
2765 free_netdev(ndev);
2766 return rc;
2767}
2768
2769/**
2770 * davinci_emac_remove: EMAC device remove
2771 * @pdev: The DaVinci EMAC device that we are removing
2772 *
2773 * Called when removing the device driver. We disable clock usage and release
2774 * the resources taken up by the driver and unregister network device
2775 */
2776static int __devexit davinci_emac_remove(struct platform_device *pdev)
2777{
2778 struct resource *res;
2779 struct net_device *ndev = platform_get_drvdata(pdev);
2780 struct emac_priv *priv = netdev_priv(ndev);
2781
2782 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2783
Anant Golea6286ee2009-05-18 15:19:01 -07002784 platform_set_drvdata(pdev, NULL);
2785 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2786 mdiobus_unregister(priv->mii_bus);
2787 mdiobus_free(priv->mii_bus);
2788
2789 release_mem_region(res->start, res->end - res->start + 1);
2790
2791 unregister_netdev(ndev);
2792 free_netdev(ndev);
2793 iounmap(priv->remap_addr);
2794
2795 clk_disable(emac_clk);
2796 clk_put(emac_clk);
2797
2798 return 0;
2799}
2800
2801/**
2802 * davinci_emac_driver: EMAC platform driver structure
2803 *
2804 * We implement only probe and remove functions - suspend/resume and
2805 * others not supported by this module
2806 */
2807static struct platform_driver davinci_emac_driver = {
2808 .driver = {
2809 .name = "davinci_emac",
2810 .owner = THIS_MODULE,
2811 },
2812 .probe = davinci_emac_probe,
2813 .remove = __devexit_p(davinci_emac_remove),
2814};
2815
2816/**
2817 * davinci_emac_init: EMAC driver module init
2818 *
2819 * Called when initializing the driver. We register the driver with
2820 * the platform.
2821 */
2822static int __init davinci_emac_init(void)
2823{
2824 return platform_driver_register(&davinci_emac_driver);
2825}
Rajashekhara, Sudhakar2db95172009-08-19 10:39:55 +00002826late_initcall(davinci_emac_init);
Anant Golea6286ee2009-05-18 15:19:01 -07002827
2828/**
2829 * davinci_emac_exit: EMAC driver module exit
2830 *
2831 * Called when exiting the driver completely. We unregister the driver with
2832 * the platform and exit
2833 */
2834static void __exit davinci_emac_exit(void)
2835{
2836 platform_driver_unregister(&davinci_emac_driver);
2837}
2838module_exit(davinci_emac_exit);
2839
2840MODULE_LICENSE("GPL");
2841MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2842MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2843MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");