Leonid Yegoshin | b0a668f | 2014-12-03 15:47:03 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (c) 2014 Imagination Technologies Ltd. |
| 7 | * Author: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> |
| 8 | * Author: Markos Chandras <markos.chandras@imgtec.com> |
| 9 | * |
| 10 | * MIPS R2 user space instruction emulator for MIPS R6 |
| 11 | * |
| 12 | */ |
| 13 | #include <linux/bug.h> |
| 14 | #include <linux/compiler.h> |
| 15 | #include <linux/debugfs.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/ptrace.h> |
| 20 | #include <linux/seq_file.h> |
| 21 | |
| 22 | #include <asm/asm.h> |
| 23 | #include <asm/branch.h> |
| 24 | #include <asm/break.h> |
| 25 | #include <asm/fpu.h> |
| 26 | #include <asm/fpu_emulator.h> |
| 27 | #include <asm/inst.h> |
| 28 | #include <asm/mips-r2-to-r6-emul.h> |
| 29 | #include <asm/local.h> |
| 30 | #include <asm/ptrace.h> |
| 31 | #include <asm/uaccess.h> |
| 32 | |
| 33 | #ifdef CONFIG_64BIT |
| 34 | #define ADDIU "daddiu " |
| 35 | #define INS "dins " |
| 36 | #define EXT "dext " |
| 37 | #else |
| 38 | #define ADDIU "addiu " |
| 39 | #define INS "ins " |
| 40 | #define EXT "ext " |
| 41 | #endif /* CONFIG_64BIT */ |
| 42 | |
| 43 | #define SB "sb " |
| 44 | #define LB "lb " |
| 45 | #define LL "ll " |
| 46 | #define SC "sc " |
| 47 | |
| 48 | DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2emustats); |
| 49 | DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2bdemustats); |
| 50 | DEFINE_PER_CPU(struct mips_r2br_emulator_stats, mipsr2bremustats); |
| 51 | |
| 52 | extern const unsigned int fpucondbit[8]; |
| 53 | |
| 54 | #define MIPS_R2_EMUL_TOTAL_PASS 10 |
| 55 | |
| 56 | int mipsr2_emulation = 0; |
| 57 | |
| 58 | static int __init mipsr2emu_enable(char *s) |
| 59 | { |
| 60 | mipsr2_emulation = 1; |
| 61 | |
| 62 | pr_info("MIPS R2-to-R6 Emulator Enabled!"); |
| 63 | |
| 64 | return 1; |
| 65 | } |
| 66 | __setup("mipsr2emu", mipsr2emu_enable); |
| 67 | |
| 68 | /** |
| 69 | * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot |
| 70 | * for performance instead of the traditional way of using a stack trampoline |
| 71 | * which is rather slow. |
| 72 | * @regs: Process register set |
| 73 | * @ir: Instruction |
| 74 | */ |
| 75 | static inline int mipsr6_emul(struct pt_regs *regs, u32 ir) |
| 76 | { |
| 77 | switch (MIPSInst_OPCODE(ir)) { |
| 78 | case addiu_op: |
| 79 | if (MIPSInst_RT(ir)) |
| 80 | regs->regs[MIPSInst_RT(ir)] = |
| 81 | (s32)regs->regs[MIPSInst_RS(ir)] + |
| 82 | (s32)MIPSInst_SIMM(ir); |
| 83 | return 0; |
| 84 | case daddiu_op: |
| 85 | if (config_enabled(CONFIG_32BIT)) |
| 86 | break; |
| 87 | |
| 88 | if (MIPSInst_RT(ir)) |
| 89 | regs->regs[MIPSInst_RT(ir)] = |
| 90 | (s64)regs->regs[MIPSInst_RS(ir)] + |
| 91 | (s64)MIPSInst_SIMM(ir); |
| 92 | return 0; |
| 93 | case lwc1_op: |
| 94 | case swc1_op: |
| 95 | case cop1_op: |
| 96 | case cop1x_op: |
| 97 | /* FPU instructions in delay slot */ |
| 98 | return -SIGFPE; |
| 99 | case spec_op: |
| 100 | switch (MIPSInst_FUNC(ir)) { |
| 101 | case or_op: |
| 102 | if (MIPSInst_RD(ir)) |
| 103 | regs->regs[MIPSInst_RD(ir)] = |
| 104 | regs->regs[MIPSInst_RS(ir)] | |
| 105 | regs->regs[MIPSInst_RT(ir)]; |
| 106 | return 0; |
| 107 | case sll_op: |
| 108 | if (MIPSInst_RS(ir)) |
| 109 | break; |
| 110 | |
| 111 | if (MIPSInst_RD(ir)) |
| 112 | regs->regs[MIPSInst_RD(ir)] = |
| 113 | (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) << |
| 114 | MIPSInst_FD(ir)); |
| 115 | return 0; |
| 116 | case srl_op: |
| 117 | if (MIPSInst_RS(ir)) |
| 118 | break; |
| 119 | |
| 120 | if (MIPSInst_RD(ir)) |
| 121 | regs->regs[MIPSInst_RD(ir)] = |
| 122 | (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >> |
| 123 | MIPSInst_FD(ir)); |
| 124 | return 0; |
| 125 | case addu_op: |
| 126 | if (MIPSInst_FD(ir)) |
| 127 | break; |
| 128 | |
| 129 | if (MIPSInst_RD(ir)) |
| 130 | regs->regs[MIPSInst_RD(ir)] = |
| 131 | (s32)((u32)regs->regs[MIPSInst_RS(ir)] + |
| 132 | (u32)regs->regs[MIPSInst_RT(ir)]); |
| 133 | return 0; |
| 134 | case subu_op: |
| 135 | if (MIPSInst_FD(ir)) |
| 136 | break; |
| 137 | |
| 138 | if (MIPSInst_RD(ir)) |
| 139 | regs->regs[MIPSInst_RD(ir)] = |
| 140 | (s32)((u32)regs->regs[MIPSInst_RS(ir)] - |
| 141 | (u32)regs->regs[MIPSInst_RT(ir)]); |
| 142 | return 0; |
| 143 | case dsll_op: |
| 144 | if (config_enabled(CONFIG_32BIT) || MIPSInst_RS(ir)) |
| 145 | break; |
| 146 | |
| 147 | if (MIPSInst_RD(ir)) |
| 148 | regs->regs[MIPSInst_RD(ir)] = |
| 149 | (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) << |
| 150 | MIPSInst_FD(ir)); |
| 151 | return 0; |
| 152 | case dsrl_op: |
| 153 | if (config_enabled(CONFIG_32BIT) || MIPSInst_RS(ir)) |
| 154 | break; |
| 155 | |
| 156 | if (MIPSInst_RD(ir)) |
| 157 | regs->regs[MIPSInst_RD(ir)] = |
| 158 | (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >> |
| 159 | MIPSInst_FD(ir)); |
| 160 | return 0; |
| 161 | case daddu_op: |
| 162 | if (config_enabled(CONFIG_32BIT) || MIPSInst_FD(ir)) |
| 163 | break; |
| 164 | |
| 165 | if (MIPSInst_RD(ir)) |
| 166 | regs->regs[MIPSInst_RD(ir)] = |
| 167 | (u64)regs->regs[MIPSInst_RS(ir)] + |
| 168 | (u64)regs->regs[MIPSInst_RT(ir)]; |
| 169 | return 0; |
| 170 | case dsubu_op: |
| 171 | if (config_enabled(CONFIG_32BIT) || MIPSInst_FD(ir)) |
| 172 | break; |
| 173 | |
| 174 | if (MIPSInst_RD(ir)) |
| 175 | regs->regs[MIPSInst_RD(ir)] = |
| 176 | (s64)((u64)regs->regs[MIPSInst_RS(ir)] - |
| 177 | (u64)regs->regs[MIPSInst_RT(ir)]); |
| 178 | return 0; |
| 179 | } |
| 180 | break; |
| 181 | default: |
| 182 | pr_debug("No fastpath BD emulation for instruction 0x%08x (op: %02x)\n", |
| 183 | ir, MIPSInst_OPCODE(ir)); |
| 184 | } |
| 185 | |
| 186 | return SIGILL; |
| 187 | } |
| 188 | |
| 189 | /** |
Maciej W. Rozycki | 241e9c4 | 2015-04-03 23:24:29 +0100 | [diff] [blame] | 190 | * movf_func - Emulate a MOVF instruction |
Leonid Yegoshin | b0a668f | 2014-12-03 15:47:03 +0000 | [diff] [blame] | 191 | * @regs: Process register set |
| 192 | * @ir: Instruction |
| 193 | * |
| 194 | * Returns 0 since it always succeeds. |
| 195 | */ |
| 196 | static int movf_func(struct pt_regs *regs, u32 ir) |
| 197 | { |
| 198 | u32 csr; |
| 199 | u32 cond; |
| 200 | |
| 201 | csr = current->thread.fpu.fcr31; |
| 202 | cond = fpucondbit[MIPSInst_RT(ir) >> 2]; |
Maciej W. Rozycki | 241e9c4 | 2015-04-03 23:24:29 +0100 | [diff] [blame] | 203 | |
Leonid Yegoshin | b0a668f | 2014-12-03 15:47:03 +0000 | [diff] [blame] | 204 | if (((csr & cond) == 0) && MIPSInst_RD(ir)) |
| 205 | regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; |
Maciej W. Rozycki | 241e9c4 | 2015-04-03 23:24:29 +0100 | [diff] [blame] | 206 | |
Leonid Yegoshin | b0a668f | 2014-12-03 15:47:03 +0000 | [diff] [blame] | 207 | MIPS_R2_STATS(movs); |
Maciej W. Rozycki | 241e9c4 | 2015-04-03 23:24:29 +0100 | [diff] [blame] | 208 | |
Leonid Yegoshin | b0a668f | 2014-12-03 15:47:03 +0000 | [diff] [blame] | 209 | return 0; |
| 210 | } |
| 211 | |
| 212 | /** |
| 213 | * movt_func - Emulate a MOVT instruction |
| 214 | * @regs: Process register set |
| 215 | * @ir: Instruction |
| 216 | * |
| 217 | * Returns 0 since it always succeeds. |
| 218 | */ |
| 219 | static int movt_func(struct pt_regs *regs, u32 ir) |
| 220 | { |
| 221 | u32 csr; |
| 222 | u32 cond; |
| 223 | |
| 224 | csr = current->thread.fpu.fcr31; |
| 225 | cond = fpucondbit[MIPSInst_RT(ir) >> 2]; |
| 226 | |
| 227 | if (((csr & cond) != 0) && MIPSInst_RD(ir)) |
| 228 | regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; |
| 229 | |
| 230 | MIPS_R2_STATS(movs); |
| 231 | |
| 232 | return 0; |
| 233 | } |
| 234 | |
| 235 | /** |
| 236 | * jr_func - Emulate a JR instruction. |
| 237 | * @pt_regs: Process register set |
| 238 | * @ir: Instruction |
| 239 | * |
| 240 | * Returns SIGILL if JR was in delay slot, SIGEMT if we |
| 241 | * can't compute the EPC, SIGSEGV if we can't access the |
| 242 | * userland instruction or 0 on success. |
| 243 | */ |
| 244 | static int jr_func(struct pt_regs *regs, u32 ir) |
| 245 | { |
| 246 | int err; |
| 247 | unsigned long cepc, epc, nepc; |
| 248 | u32 nir; |
| 249 | |
| 250 | if (delay_slot(regs)) |
| 251 | return SIGILL; |
| 252 | |
| 253 | /* EPC after the RI/JR instruction */ |
| 254 | nepc = regs->cp0_epc; |
| 255 | /* Roll back to the reserved R2 JR instruction */ |
| 256 | regs->cp0_epc -= 4; |
| 257 | epc = regs->cp0_epc; |
| 258 | err = __compute_return_epc(regs); |
| 259 | |
| 260 | if (err < 0) |
| 261 | return SIGEMT; |
| 262 | |
| 263 | |
| 264 | /* Computed EPC */ |
| 265 | cepc = regs->cp0_epc; |
| 266 | |
| 267 | /* Get DS instruction */ |
| 268 | err = __get_user(nir, (u32 __user *)nepc); |
| 269 | if (err) |
| 270 | return SIGSEGV; |
| 271 | |
| 272 | MIPS_R2BR_STATS(jrs); |
| 273 | |
| 274 | /* If nir == 0(NOP), then nothing else to do */ |
| 275 | if (nir) { |
| 276 | /* |
| 277 | * Negative err means FPU instruction in BD-slot, |
| 278 | * Zero err means 'BD-slot emulation done' |
| 279 | * For anything else we go back to trampoline emulation. |
| 280 | */ |
| 281 | err = mipsr6_emul(regs, nir); |
| 282 | if (err > 0) { |
| 283 | regs->cp0_epc = nepc; |
| 284 | err = mips_dsemul(regs, nir, cepc); |
| 285 | if (err == SIGILL) |
| 286 | err = SIGEMT; |
| 287 | MIPS_R2_STATS(dsemul); |
| 288 | } |
| 289 | } |
| 290 | |
| 291 | return err; |
| 292 | } |
| 293 | |
| 294 | /** |
| 295 | * movz_func - Emulate a MOVZ instruction |
| 296 | * @regs: Process register set |
| 297 | * @ir: Instruction |
| 298 | * |
| 299 | * Returns 0 since it always succeeds. |
| 300 | */ |
| 301 | static int movz_func(struct pt_regs *regs, u32 ir) |
| 302 | { |
| 303 | if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir)) |
| 304 | regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; |
| 305 | MIPS_R2_STATS(movs); |
| 306 | |
| 307 | return 0; |
| 308 | } |
| 309 | |
| 310 | /** |
| 311 | * movn_func - Emulate a MOVZ instruction |
| 312 | * @regs: Process register set |
| 313 | * @ir: Instruction |
| 314 | * |
| 315 | * Returns 0 since it always succeeds. |
| 316 | */ |
| 317 | static int movn_func(struct pt_regs *regs, u32 ir) |
| 318 | { |
| 319 | if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir)) |
| 320 | regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; |
| 321 | MIPS_R2_STATS(movs); |
| 322 | |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | /** |
| 327 | * mfhi_func - Emulate a MFHI instruction |
| 328 | * @regs: Process register set |
| 329 | * @ir: Instruction |
| 330 | * |
| 331 | * Returns 0 since it always succeeds. |
| 332 | */ |
| 333 | static int mfhi_func(struct pt_regs *regs, u32 ir) |
| 334 | { |
| 335 | if (MIPSInst_RD(ir)) |
| 336 | regs->regs[MIPSInst_RD(ir)] = regs->hi; |
| 337 | |
| 338 | MIPS_R2_STATS(hilo); |
| 339 | |
| 340 | return 0; |
| 341 | } |
| 342 | |
| 343 | /** |
| 344 | * mthi_func - Emulate a MTHI instruction |
| 345 | * @regs: Process register set |
| 346 | * @ir: Instruction |
| 347 | * |
| 348 | * Returns 0 since it always succeeds. |
| 349 | */ |
| 350 | static int mthi_func(struct pt_regs *regs, u32 ir) |
| 351 | { |
| 352 | regs->hi = regs->regs[MIPSInst_RS(ir)]; |
| 353 | |
| 354 | MIPS_R2_STATS(hilo); |
| 355 | |
| 356 | return 0; |
| 357 | } |
| 358 | |
| 359 | /** |
| 360 | * mflo_func - Emulate a MFLO instruction |
| 361 | * @regs: Process register set |
| 362 | * @ir: Instruction |
| 363 | * |
| 364 | * Returns 0 since it always succeeds. |
| 365 | */ |
| 366 | static int mflo_func(struct pt_regs *regs, u32 ir) |
| 367 | { |
| 368 | if (MIPSInst_RD(ir)) |
| 369 | regs->regs[MIPSInst_RD(ir)] = regs->lo; |
| 370 | |
| 371 | MIPS_R2_STATS(hilo); |
| 372 | |
| 373 | return 0; |
| 374 | } |
| 375 | |
| 376 | /** |
| 377 | * mtlo_func - Emulate a MTLO instruction |
| 378 | * @regs: Process register set |
| 379 | * @ir: Instruction |
| 380 | * |
| 381 | * Returns 0 since it always succeeds. |
| 382 | */ |
| 383 | static int mtlo_func(struct pt_regs *regs, u32 ir) |
| 384 | { |
| 385 | regs->lo = regs->regs[MIPSInst_RS(ir)]; |
| 386 | |
| 387 | MIPS_R2_STATS(hilo); |
| 388 | |
| 389 | return 0; |
| 390 | } |
| 391 | |
| 392 | /** |
| 393 | * mult_func - Emulate a MULT instruction |
| 394 | * @regs: Process register set |
| 395 | * @ir: Instruction |
| 396 | * |
| 397 | * Returns 0 since it always succeeds. |
| 398 | */ |
| 399 | static int mult_func(struct pt_regs *regs, u32 ir) |
| 400 | { |
| 401 | s64 res; |
| 402 | s32 rt, rs; |
| 403 | |
| 404 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 405 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 406 | res = (s64)rt * (s64)rs; |
| 407 | |
| 408 | rs = res; |
| 409 | regs->lo = (s64)rs; |
| 410 | rt = res >> 32; |
| 411 | res = (s64)rt; |
| 412 | regs->hi = res; |
| 413 | |
| 414 | MIPS_R2_STATS(muls); |
| 415 | |
| 416 | return 0; |
| 417 | } |
| 418 | |
| 419 | /** |
| 420 | * multu_func - Emulate a MULTU instruction |
| 421 | * @regs: Process register set |
| 422 | * @ir: Instruction |
| 423 | * |
| 424 | * Returns 0 since it always succeeds. |
| 425 | */ |
| 426 | static int multu_func(struct pt_regs *regs, u32 ir) |
| 427 | { |
| 428 | u64 res; |
| 429 | u32 rt, rs; |
| 430 | |
| 431 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 432 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 433 | res = (u64)rt * (u64)rs; |
| 434 | rt = res; |
| 435 | regs->lo = (s64)rt; |
| 436 | regs->hi = (s64)(res >> 32); |
| 437 | |
| 438 | MIPS_R2_STATS(muls); |
| 439 | |
| 440 | return 0; |
| 441 | } |
| 442 | |
| 443 | /** |
| 444 | * div_func - Emulate a DIV instruction |
| 445 | * @regs: Process register set |
| 446 | * @ir: Instruction |
| 447 | * |
| 448 | * Returns 0 since it always succeeds. |
| 449 | */ |
| 450 | static int div_func(struct pt_regs *regs, u32 ir) |
| 451 | { |
| 452 | s32 rt, rs; |
| 453 | |
| 454 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 455 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 456 | |
| 457 | regs->lo = (s64)(rs / rt); |
| 458 | regs->hi = (s64)(rs % rt); |
| 459 | |
| 460 | MIPS_R2_STATS(divs); |
| 461 | |
| 462 | return 0; |
| 463 | } |
| 464 | |
| 465 | /** |
| 466 | * divu_func - Emulate a DIVU instruction |
| 467 | * @regs: Process register set |
| 468 | * @ir: Instruction |
| 469 | * |
| 470 | * Returns 0 since it always succeeds. |
| 471 | */ |
| 472 | static int divu_func(struct pt_regs *regs, u32 ir) |
| 473 | { |
| 474 | u32 rt, rs; |
| 475 | |
| 476 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 477 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 478 | |
| 479 | regs->lo = (s64)(rs / rt); |
| 480 | regs->hi = (s64)(rs % rt); |
| 481 | |
| 482 | MIPS_R2_STATS(divs); |
| 483 | |
| 484 | return 0; |
| 485 | } |
| 486 | |
| 487 | /** |
| 488 | * dmult_func - Emulate a DMULT instruction |
| 489 | * @regs: Process register set |
| 490 | * @ir: Instruction |
| 491 | * |
| 492 | * Returns 0 on success or SIGILL for 32-bit kernels. |
| 493 | */ |
| 494 | static int dmult_func(struct pt_regs *regs, u32 ir) |
| 495 | { |
| 496 | s64 res; |
| 497 | s64 rt, rs; |
| 498 | |
| 499 | if (config_enabled(CONFIG_32BIT)) |
| 500 | return SIGILL; |
| 501 | |
| 502 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 503 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 504 | res = rt * rs; |
| 505 | |
| 506 | regs->lo = res; |
| 507 | __asm__ __volatile__( |
| 508 | "dmuh %0, %1, %2\t\n" |
| 509 | : "=r"(res) |
| 510 | : "r"(rt), "r"(rs)); |
| 511 | |
| 512 | regs->hi = res; |
| 513 | |
| 514 | MIPS_R2_STATS(muls); |
| 515 | |
| 516 | return 0; |
| 517 | } |
| 518 | |
| 519 | /** |
| 520 | * dmultu_func - Emulate a DMULTU instruction |
| 521 | * @regs: Process register set |
| 522 | * @ir: Instruction |
| 523 | * |
| 524 | * Returns 0 on success or SIGILL for 32-bit kernels. |
| 525 | */ |
| 526 | static int dmultu_func(struct pt_regs *regs, u32 ir) |
| 527 | { |
| 528 | u64 res; |
| 529 | u64 rt, rs; |
| 530 | |
| 531 | if (config_enabled(CONFIG_32BIT)) |
| 532 | return SIGILL; |
| 533 | |
| 534 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 535 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 536 | res = rt * rs; |
| 537 | |
| 538 | regs->lo = res; |
| 539 | __asm__ __volatile__( |
| 540 | "dmuhu %0, %1, %2\t\n" |
| 541 | : "=r"(res) |
| 542 | : "r"(rt), "r"(rs)); |
| 543 | |
| 544 | regs->hi = res; |
| 545 | |
| 546 | MIPS_R2_STATS(muls); |
| 547 | |
| 548 | return 0; |
| 549 | } |
| 550 | |
| 551 | /** |
| 552 | * ddiv_func - Emulate a DDIV instruction |
| 553 | * @regs: Process register set |
| 554 | * @ir: Instruction |
| 555 | * |
| 556 | * Returns 0 on success or SIGILL for 32-bit kernels. |
| 557 | */ |
| 558 | static int ddiv_func(struct pt_regs *regs, u32 ir) |
| 559 | { |
| 560 | s64 rt, rs; |
| 561 | |
| 562 | if (config_enabled(CONFIG_32BIT)) |
| 563 | return SIGILL; |
| 564 | |
| 565 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 566 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 567 | |
| 568 | regs->lo = rs / rt; |
| 569 | regs->hi = rs % rt; |
| 570 | |
| 571 | MIPS_R2_STATS(divs); |
| 572 | |
| 573 | return 0; |
| 574 | } |
| 575 | |
| 576 | /** |
| 577 | * ddivu_func - Emulate a DDIVU instruction |
| 578 | * @regs: Process register set |
| 579 | * @ir: Instruction |
| 580 | * |
| 581 | * Returns 0 on success or SIGILL for 32-bit kernels. |
| 582 | */ |
| 583 | static int ddivu_func(struct pt_regs *regs, u32 ir) |
| 584 | { |
| 585 | u64 rt, rs; |
| 586 | |
| 587 | if (config_enabled(CONFIG_32BIT)) |
| 588 | return SIGILL; |
| 589 | |
| 590 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 591 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 592 | |
| 593 | regs->lo = rs / rt; |
| 594 | regs->hi = rs % rt; |
| 595 | |
| 596 | MIPS_R2_STATS(divs); |
| 597 | |
| 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | /* R6 removed instructions for the SPECIAL opcode */ |
| 602 | static struct r2_decoder_table spec_op_table[] = { |
| 603 | { 0xfc1ff83f, 0x00000008, jr_func }, |
| 604 | { 0xfc00ffff, 0x00000018, mult_func }, |
| 605 | { 0xfc00ffff, 0x00000019, multu_func }, |
| 606 | { 0xfc00ffff, 0x0000001c, dmult_func }, |
| 607 | { 0xfc00ffff, 0x0000001d, dmultu_func }, |
| 608 | { 0xffff07ff, 0x00000010, mfhi_func }, |
| 609 | { 0xfc1fffff, 0x00000011, mthi_func }, |
| 610 | { 0xffff07ff, 0x00000012, mflo_func }, |
| 611 | { 0xfc1fffff, 0x00000013, mtlo_func }, |
| 612 | { 0xfc0307ff, 0x00000001, movf_func }, |
| 613 | { 0xfc0307ff, 0x00010001, movt_func }, |
| 614 | { 0xfc0007ff, 0x0000000a, movz_func }, |
| 615 | { 0xfc0007ff, 0x0000000b, movn_func }, |
| 616 | { 0xfc00ffff, 0x0000001a, div_func }, |
| 617 | { 0xfc00ffff, 0x0000001b, divu_func }, |
| 618 | { 0xfc00ffff, 0x0000001e, ddiv_func }, |
| 619 | { 0xfc00ffff, 0x0000001f, ddivu_func }, |
| 620 | {} |
| 621 | }; |
| 622 | |
| 623 | /** |
| 624 | * madd_func - Emulate a MADD instruction |
| 625 | * @regs: Process register set |
| 626 | * @ir: Instruction |
| 627 | * |
| 628 | * Returns 0 since it always succeeds. |
| 629 | */ |
| 630 | static int madd_func(struct pt_regs *regs, u32 ir) |
| 631 | { |
| 632 | s64 res; |
| 633 | s32 rt, rs; |
| 634 | |
| 635 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 636 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 637 | res = (s64)rt * (s64)rs; |
| 638 | rt = regs->hi; |
| 639 | rs = regs->lo; |
| 640 | res += ((((s64)rt) << 32) | (u32)rs); |
| 641 | |
| 642 | rt = res; |
| 643 | regs->lo = (s64)rt; |
| 644 | rs = res >> 32; |
| 645 | regs->hi = (s64)rs; |
| 646 | |
| 647 | MIPS_R2_STATS(dsps); |
| 648 | |
| 649 | return 0; |
| 650 | } |
| 651 | |
| 652 | /** |
| 653 | * maddu_func - Emulate a MADDU instruction |
| 654 | * @regs: Process register set |
| 655 | * @ir: Instruction |
| 656 | * |
| 657 | * Returns 0 since it always succeeds. |
| 658 | */ |
| 659 | static int maddu_func(struct pt_regs *regs, u32 ir) |
| 660 | { |
| 661 | u64 res; |
| 662 | u32 rt, rs; |
| 663 | |
| 664 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 665 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 666 | res = (u64)rt * (u64)rs; |
| 667 | rt = regs->hi; |
| 668 | rs = regs->lo; |
| 669 | res += ((((s64)rt) << 32) | (u32)rs); |
| 670 | |
| 671 | rt = res; |
| 672 | regs->lo = (s64)rt; |
| 673 | rs = res >> 32; |
| 674 | regs->hi = (s64)rs; |
| 675 | |
| 676 | MIPS_R2_STATS(dsps); |
| 677 | |
| 678 | return 0; |
| 679 | } |
| 680 | |
| 681 | /** |
| 682 | * msub_func - Emulate a MSUB instruction |
| 683 | * @regs: Process register set |
| 684 | * @ir: Instruction |
| 685 | * |
| 686 | * Returns 0 since it always succeeds. |
| 687 | */ |
| 688 | static int msub_func(struct pt_regs *regs, u32 ir) |
| 689 | { |
| 690 | s64 res; |
| 691 | s32 rt, rs; |
| 692 | |
| 693 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 694 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 695 | res = (s64)rt * (s64)rs; |
| 696 | rt = regs->hi; |
| 697 | rs = regs->lo; |
| 698 | res = ((((s64)rt) << 32) | (u32)rs) - res; |
| 699 | |
| 700 | rt = res; |
| 701 | regs->lo = (s64)rt; |
| 702 | rs = res >> 32; |
| 703 | regs->hi = (s64)rs; |
| 704 | |
| 705 | MIPS_R2_STATS(dsps); |
| 706 | |
| 707 | return 0; |
| 708 | } |
| 709 | |
| 710 | /** |
| 711 | * msubu_func - Emulate a MSUBU instruction |
| 712 | * @regs: Process register set |
| 713 | * @ir: Instruction |
| 714 | * |
| 715 | * Returns 0 since it always succeeds. |
| 716 | */ |
| 717 | static int msubu_func(struct pt_regs *regs, u32 ir) |
| 718 | { |
| 719 | u64 res; |
| 720 | u32 rt, rs; |
| 721 | |
| 722 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 723 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 724 | res = (u64)rt * (u64)rs; |
| 725 | rt = regs->hi; |
| 726 | rs = regs->lo; |
| 727 | res = ((((s64)rt) << 32) | (u32)rs) - res; |
| 728 | |
| 729 | rt = res; |
| 730 | regs->lo = (s64)rt; |
| 731 | rs = res >> 32; |
| 732 | regs->hi = (s64)rs; |
| 733 | |
| 734 | MIPS_R2_STATS(dsps); |
| 735 | |
| 736 | return 0; |
| 737 | } |
| 738 | |
| 739 | /** |
| 740 | * mul_func - Emulate a MUL instruction |
| 741 | * @regs: Process register set |
| 742 | * @ir: Instruction |
| 743 | * |
| 744 | * Returns 0 since it always succeeds. |
| 745 | */ |
| 746 | static int mul_func(struct pt_regs *regs, u32 ir) |
| 747 | { |
| 748 | s64 res; |
| 749 | s32 rt, rs; |
| 750 | |
| 751 | if (!MIPSInst_RD(ir)) |
| 752 | return 0; |
| 753 | rt = regs->regs[MIPSInst_RT(ir)]; |
| 754 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 755 | res = (s64)rt * (s64)rs; |
| 756 | |
| 757 | rs = res; |
| 758 | regs->regs[MIPSInst_RD(ir)] = (s64)rs; |
| 759 | |
| 760 | MIPS_R2_STATS(muls); |
| 761 | |
| 762 | return 0; |
| 763 | } |
| 764 | |
| 765 | /** |
| 766 | * clz_func - Emulate a CLZ instruction |
| 767 | * @regs: Process register set |
| 768 | * @ir: Instruction |
| 769 | * |
| 770 | * Returns 0 since it always succeeds. |
| 771 | */ |
| 772 | static int clz_func(struct pt_regs *regs, u32 ir) |
| 773 | { |
| 774 | u32 res; |
| 775 | u32 rs; |
| 776 | |
| 777 | if (!MIPSInst_RD(ir)) |
| 778 | return 0; |
| 779 | |
| 780 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 781 | __asm__ __volatile__("clz %0, %1" : "=r"(res) : "r"(rs)); |
| 782 | regs->regs[MIPSInst_RD(ir)] = res; |
| 783 | |
| 784 | MIPS_R2_STATS(bops); |
| 785 | |
| 786 | return 0; |
| 787 | } |
| 788 | |
| 789 | /** |
| 790 | * clo_func - Emulate a CLO instruction |
| 791 | * @regs: Process register set |
| 792 | * @ir: Instruction |
| 793 | * |
| 794 | * Returns 0 since it always succeeds. |
| 795 | */ |
| 796 | |
| 797 | static int clo_func(struct pt_regs *regs, u32 ir) |
| 798 | { |
| 799 | u32 res; |
| 800 | u32 rs; |
| 801 | |
| 802 | if (!MIPSInst_RD(ir)) |
| 803 | return 0; |
| 804 | |
| 805 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 806 | __asm__ __volatile__("clo %0, %1" : "=r"(res) : "r"(rs)); |
| 807 | regs->regs[MIPSInst_RD(ir)] = res; |
| 808 | |
| 809 | MIPS_R2_STATS(bops); |
| 810 | |
| 811 | return 0; |
| 812 | } |
| 813 | |
| 814 | /** |
| 815 | * dclz_func - Emulate a DCLZ instruction |
| 816 | * @regs: Process register set |
| 817 | * @ir: Instruction |
| 818 | * |
| 819 | * Returns 0 since it always succeeds. |
| 820 | */ |
| 821 | static int dclz_func(struct pt_regs *regs, u32 ir) |
| 822 | { |
| 823 | u64 res; |
| 824 | u64 rs; |
| 825 | |
| 826 | if (config_enabled(CONFIG_32BIT)) |
| 827 | return SIGILL; |
| 828 | |
| 829 | if (!MIPSInst_RD(ir)) |
| 830 | return 0; |
| 831 | |
| 832 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 833 | __asm__ __volatile__("dclz %0, %1" : "=r"(res) : "r"(rs)); |
| 834 | regs->regs[MIPSInst_RD(ir)] = res; |
| 835 | |
| 836 | MIPS_R2_STATS(bops); |
| 837 | |
| 838 | return 0; |
| 839 | } |
| 840 | |
| 841 | /** |
| 842 | * dclo_func - Emulate a DCLO instruction |
| 843 | * @regs: Process register set |
| 844 | * @ir: Instruction |
| 845 | * |
| 846 | * Returns 0 since it always succeeds. |
| 847 | */ |
| 848 | static int dclo_func(struct pt_regs *regs, u32 ir) |
| 849 | { |
| 850 | u64 res; |
| 851 | u64 rs; |
| 852 | |
| 853 | if (config_enabled(CONFIG_32BIT)) |
| 854 | return SIGILL; |
| 855 | |
| 856 | if (!MIPSInst_RD(ir)) |
| 857 | return 0; |
| 858 | |
| 859 | rs = regs->regs[MIPSInst_RS(ir)]; |
| 860 | __asm__ __volatile__("dclo %0, %1" : "=r"(res) : "r"(rs)); |
| 861 | regs->regs[MIPSInst_RD(ir)] = res; |
| 862 | |
| 863 | MIPS_R2_STATS(bops); |
| 864 | |
| 865 | return 0; |
| 866 | } |
| 867 | |
| 868 | /* R6 removed instructions for the SPECIAL2 opcode */ |
| 869 | static struct r2_decoder_table spec2_op_table[] = { |
| 870 | { 0xfc00ffff, 0x70000000, madd_func }, |
| 871 | { 0xfc00ffff, 0x70000001, maddu_func }, |
| 872 | { 0xfc0007ff, 0x70000002, mul_func }, |
| 873 | { 0xfc00ffff, 0x70000004, msub_func }, |
| 874 | { 0xfc00ffff, 0x70000005, msubu_func }, |
| 875 | { 0xfc0007ff, 0x70000020, clz_func }, |
| 876 | { 0xfc0007ff, 0x70000021, clo_func }, |
| 877 | { 0xfc0007ff, 0x70000024, dclz_func }, |
| 878 | { 0xfc0007ff, 0x70000025, dclo_func }, |
| 879 | { } |
| 880 | }; |
| 881 | |
| 882 | static inline int mipsr2_find_op_func(struct pt_regs *regs, u32 inst, |
| 883 | struct r2_decoder_table *table) |
| 884 | { |
| 885 | struct r2_decoder_table *p; |
| 886 | int err; |
| 887 | |
| 888 | for (p = table; p->func; p++) { |
| 889 | if ((inst & p->mask) == p->code) { |
| 890 | err = (p->func)(regs, inst); |
| 891 | return err; |
| 892 | } |
| 893 | } |
| 894 | return SIGILL; |
| 895 | } |
| 896 | |
| 897 | /** |
| 898 | * mipsr2_decoder: Decode and emulate a MIPS R2 instruction |
| 899 | * @regs: Process register set |
| 900 | * @inst: Instruction to decode and emulate |
| 901 | */ |
| 902 | int mipsr2_decoder(struct pt_regs *regs, u32 inst) |
| 903 | { |
| 904 | int err = 0; |
| 905 | unsigned long vaddr; |
| 906 | u32 nir; |
| 907 | unsigned long cpc, epc, nepc, r31, res, rs, rt; |
| 908 | |
| 909 | void __user *fault_addr = NULL; |
| 910 | int pass = 0; |
| 911 | |
| 912 | repeat: |
| 913 | r31 = regs->regs[31]; |
| 914 | epc = regs->cp0_epc; |
| 915 | err = compute_return_epc(regs); |
| 916 | if (err < 0) { |
| 917 | BUG(); |
| 918 | return SIGEMT; |
| 919 | } |
| 920 | pr_debug("Emulating the 0x%08x R2 instruction @ 0x%08lx (pass=%d))\n", |
| 921 | inst, epc, pass); |
| 922 | |
| 923 | switch (MIPSInst_OPCODE(inst)) { |
| 924 | case spec_op: |
| 925 | err = mipsr2_find_op_func(regs, inst, spec_op_table); |
| 926 | if (err < 0) { |
| 927 | /* FPU instruction under JR */ |
| 928 | regs->cp0_cause |= CAUSEF_BD; |
| 929 | goto fpu_emul; |
| 930 | } |
| 931 | break; |
| 932 | case spec2_op: |
| 933 | err = mipsr2_find_op_func(regs, inst, spec2_op_table); |
| 934 | break; |
| 935 | case bcond_op: |
| 936 | rt = MIPSInst_RT(inst); |
| 937 | rs = MIPSInst_RS(inst); |
| 938 | switch (rt) { |
| 939 | case tgei_op: |
| 940 | if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst)) |
| 941 | do_trap_or_bp(regs, 0, "TGEI"); |
| 942 | |
| 943 | MIPS_R2_STATS(traps); |
| 944 | |
| 945 | break; |
| 946 | case tgeiu_op: |
| 947 | if (regs->regs[rs] >= MIPSInst_UIMM(inst)) |
| 948 | do_trap_or_bp(regs, 0, "TGEIU"); |
| 949 | |
| 950 | MIPS_R2_STATS(traps); |
| 951 | |
| 952 | break; |
| 953 | case tlti_op: |
| 954 | if ((long)regs->regs[rs] < MIPSInst_SIMM(inst)) |
| 955 | do_trap_or_bp(regs, 0, "TLTI"); |
| 956 | |
| 957 | MIPS_R2_STATS(traps); |
| 958 | |
| 959 | break; |
| 960 | case tltiu_op: |
| 961 | if (regs->regs[rs] < MIPSInst_UIMM(inst)) |
| 962 | do_trap_or_bp(regs, 0, "TLTIU"); |
| 963 | |
| 964 | MIPS_R2_STATS(traps); |
| 965 | |
| 966 | break; |
| 967 | case teqi_op: |
| 968 | if (regs->regs[rs] == MIPSInst_SIMM(inst)) |
| 969 | do_trap_or_bp(regs, 0, "TEQI"); |
| 970 | |
| 971 | MIPS_R2_STATS(traps); |
| 972 | |
| 973 | break; |
| 974 | case tnei_op: |
| 975 | if (regs->regs[rs] != MIPSInst_SIMM(inst)) |
| 976 | do_trap_or_bp(regs, 0, "TNEI"); |
| 977 | |
| 978 | MIPS_R2_STATS(traps); |
| 979 | |
| 980 | break; |
| 981 | case bltzl_op: |
| 982 | case bgezl_op: |
| 983 | case bltzall_op: |
| 984 | case bgezall_op: |
| 985 | if (delay_slot(regs)) { |
| 986 | err = SIGILL; |
| 987 | break; |
| 988 | } |
| 989 | regs->regs[31] = r31; |
| 990 | regs->cp0_epc = epc; |
| 991 | err = __compute_return_epc(regs); |
| 992 | if (err < 0) |
| 993 | return SIGEMT; |
| 994 | if (err != BRANCH_LIKELY_TAKEN) |
| 995 | break; |
| 996 | cpc = regs->cp0_epc; |
| 997 | nepc = epc + 4; |
| 998 | err = __get_user(nir, (u32 __user *)nepc); |
| 999 | if (err) { |
| 1000 | err = SIGSEGV; |
| 1001 | break; |
| 1002 | } |
| 1003 | /* |
| 1004 | * This will probably be optimized away when |
| 1005 | * CONFIG_DEBUG_FS is not enabled |
| 1006 | */ |
| 1007 | switch (rt) { |
| 1008 | case bltzl_op: |
| 1009 | MIPS_R2BR_STATS(bltzl); |
| 1010 | break; |
| 1011 | case bgezl_op: |
| 1012 | MIPS_R2BR_STATS(bgezl); |
| 1013 | break; |
| 1014 | case bltzall_op: |
| 1015 | MIPS_R2BR_STATS(bltzall); |
| 1016 | break; |
| 1017 | case bgezall_op: |
| 1018 | MIPS_R2BR_STATS(bgezall); |
| 1019 | break; |
| 1020 | } |
| 1021 | |
| 1022 | switch (MIPSInst_OPCODE(nir)) { |
| 1023 | case cop1_op: |
| 1024 | case cop1x_op: |
| 1025 | case lwc1_op: |
| 1026 | case swc1_op: |
| 1027 | regs->cp0_cause |= CAUSEF_BD; |
| 1028 | goto fpu_emul; |
| 1029 | } |
| 1030 | if (nir) { |
| 1031 | err = mipsr6_emul(regs, nir); |
| 1032 | if (err > 0) { |
| 1033 | err = mips_dsemul(regs, nir, cpc); |
| 1034 | if (err == SIGILL) |
| 1035 | err = SIGEMT; |
| 1036 | MIPS_R2_STATS(dsemul); |
| 1037 | } |
| 1038 | } |
| 1039 | break; |
| 1040 | case bltzal_op: |
| 1041 | case bgezal_op: |
| 1042 | if (delay_slot(regs)) { |
| 1043 | err = SIGILL; |
| 1044 | break; |
| 1045 | } |
| 1046 | regs->regs[31] = r31; |
| 1047 | regs->cp0_epc = epc; |
| 1048 | err = __compute_return_epc(regs); |
| 1049 | if (err < 0) |
| 1050 | return SIGEMT; |
| 1051 | cpc = regs->cp0_epc; |
| 1052 | nepc = epc + 4; |
| 1053 | err = __get_user(nir, (u32 __user *)nepc); |
| 1054 | if (err) { |
| 1055 | err = SIGSEGV; |
| 1056 | break; |
| 1057 | } |
| 1058 | /* |
| 1059 | * This will probably be optimized away when |
| 1060 | * CONFIG_DEBUG_FS is not enabled |
| 1061 | */ |
| 1062 | switch (rt) { |
| 1063 | case bltzal_op: |
| 1064 | MIPS_R2BR_STATS(bltzal); |
| 1065 | break; |
| 1066 | case bgezal_op: |
| 1067 | MIPS_R2BR_STATS(bgezal); |
| 1068 | break; |
| 1069 | } |
| 1070 | |
| 1071 | switch (MIPSInst_OPCODE(nir)) { |
| 1072 | case cop1_op: |
| 1073 | case cop1x_op: |
| 1074 | case lwc1_op: |
| 1075 | case swc1_op: |
| 1076 | regs->cp0_cause |= CAUSEF_BD; |
| 1077 | goto fpu_emul; |
| 1078 | } |
| 1079 | if (nir) { |
| 1080 | err = mipsr6_emul(regs, nir); |
| 1081 | if (err > 0) { |
| 1082 | err = mips_dsemul(regs, nir, cpc); |
| 1083 | if (err == SIGILL) |
| 1084 | err = SIGEMT; |
| 1085 | MIPS_R2_STATS(dsemul); |
| 1086 | } |
| 1087 | } |
| 1088 | break; |
| 1089 | default: |
| 1090 | regs->regs[31] = r31; |
| 1091 | regs->cp0_epc = epc; |
| 1092 | err = SIGILL; |
| 1093 | break; |
| 1094 | } |
| 1095 | break; |
| 1096 | |
| 1097 | case beql_op: |
| 1098 | case bnel_op: |
| 1099 | case blezl_op: |
| 1100 | case bgtzl_op: |
| 1101 | if (delay_slot(regs)) { |
| 1102 | err = SIGILL; |
| 1103 | break; |
| 1104 | } |
| 1105 | regs->regs[31] = r31; |
| 1106 | regs->cp0_epc = epc; |
| 1107 | err = __compute_return_epc(regs); |
| 1108 | if (err < 0) |
| 1109 | return SIGEMT; |
| 1110 | if (err != BRANCH_LIKELY_TAKEN) |
| 1111 | break; |
| 1112 | cpc = regs->cp0_epc; |
| 1113 | nepc = epc + 4; |
| 1114 | err = __get_user(nir, (u32 __user *)nepc); |
| 1115 | if (err) { |
| 1116 | err = SIGSEGV; |
| 1117 | break; |
| 1118 | } |
| 1119 | /* |
| 1120 | * This will probably be optimized away when |
| 1121 | * CONFIG_DEBUG_FS is not enabled |
| 1122 | */ |
| 1123 | switch (MIPSInst_OPCODE(inst)) { |
| 1124 | case beql_op: |
| 1125 | MIPS_R2BR_STATS(beql); |
| 1126 | break; |
| 1127 | case bnel_op: |
| 1128 | MIPS_R2BR_STATS(bnel); |
| 1129 | break; |
| 1130 | case blezl_op: |
| 1131 | MIPS_R2BR_STATS(blezl); |
| 1132 | break; |
| 1133 | case bgtzl_op: |
| 1134 | MIPS_R2BR_STATS(bgtzl); |
| 1135 | break; |
| 1136 | } |
| 1137 | |
| 1138 | switch (MIPSInst_OPCODE(nir)) { |
| 1139 | case cop1_op: |
| 1140 | case cop1x_op: |
| 1141 | case lwc1_op: |
| 1142 | case swc1_op: |
| 1143 | regs->cp0_cause |= CAUSEF_BD; |
| 1144 | goto fpu_emul; |
| 1145 | } |
| 1146 | if (nir) { |
| 1147 | err = mipsr6_emul(regs, nir); |
| 1148 | if (err > 0) { |
| 1149 | err = mips_dsemul(regs, nir, cpc); |
| 1150 | if (err == SIGILL) |
| 1151 | err = SIGEMT; |
| 1152 | MIPS_R2_STATS(dsemul); |
| 1153 | } |
| 1154 | } |
| 1155 | break; |
| 1156 | case lwc1_op: |
| 1157 | case swc1_op: |
| 1158 | case cop1_op: |
| 1159 | case cop1x_op: |
| 1160 | fpu_emul: |
| 1161 | regs->regs[31] = r31; |
| 1162 | regs->cp0_epc = epc; |
| 1163 | if (!used_math()) { /* First time FPU user. */ |
| 1164 | err = init_fpu(); |
| 1165 | set_used_math(); |
| 1166 | } |
| 1167 | lose_fpu(1); /* Save FPU state for the emulator. */ |
| 1168 | |
| 1169 | err = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, |
| 1170 | &fault_addr); |
| 1171 | |
| 1172 | /* |
Maciej W. Rozycki | 443c440 | 2015-04-03 23:27:10 +0100 | [diff] [blame^] | 1173 | * We can't allow the emulated instruction to leave any of |
| 1174 | * the cause bits set in $fcr31. |
| 1175 | */ |
| 1176 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
| 1177 | |
| 1178 | /* |
Leonid Yegoshin | b0a668f | 2014-12-03 15:47:03 +0000 | [diff] [blame] | 1179 | * this is a tricky issue - lose_fpu() uses LL/SC atomics |
| 1180 | * if FPU is owned and effectively cancels user level LL/SC. |
| 1181 | * So, it could be logical to don't restore FPU ownership here. |
| 1182 | * But the sequence of multiple FPU instructions is much much |
| 1183 | * more often than LL-FPU-SC and I prefer loop here until |
| 1184 | * next scheduler cycle cancels FPU ownership |
| 1185 | */ |
| 1186 | own_fpu(1); /* Restore FPU state. */ |
| 1187 | |
| 1188 | if (err) |
| 1189 | current->thread.cp0_baduaddr = (unsigned long)fault_addr; |
| 1190 | |
| 1191 | MIPS_R2_STATS(fpus); |
| 1192 | |
| 1193 | break; |
| 1194 | |
| 1195 | case lwl_op: |
| 1196 | rt = regs->regs[MIPSInst_RT(inst)]; |
| 1197 | vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); |
| 1198 | if (!access_ok(VERIFY_READ, vaddr, 4)) { |
| 1199 | current->thread.cp0_baduaddr = vaddr; |
| 1200 | err = SIGSEGV; |
| 1201 | break; |
| 1202 | } |
| 1203 | __asm__ __volatile__( |
| 1204 | " .set push\n" |
| 1205 | " .set reorder\n" |
| 1206 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 1207 | "1:" LB "%1, 0(%2)\n" |
| 1208 | INS "%0, %1, 24, 8\n" |
| 1209 | " andi %1, %2, 0x3\n" |
| 1210 | " beq $0, %1, 9f\n" |
| 1211 | ADDIU "%2, %2, -1\n" |
| 1212 | "2:" LB "%1, 0(%2)\n" |
| 1213 | INS "%0, %1, 16, 8\n" |
| 1214 | " andi %1, %2, 0x3\n" |
| 1215 | " beq $0, %1, 9f\n" |
| 1216 | ADDIU "%2, %2, -1\n" |
| 1217 | "3:" LB "%1, 0(%2)\n" |
| 1218 | INS "%0, %1, 8, 8\n" |
| 1219 | " andi %1, %2, 0x3\n" |
| 1220 | " beq $0, %1, 9f\n" |
| 1221 | ADDIU "%2, %2, -1\n" |
| 1222 | "4:" LB "%1, 0(%2)\n" |
| 1223 | INS "%0, %1, 0, 8\n" |
| 1224 | #else /* !CONFIG_CPU_LITTLE_ENDIAN */ |
| 1225 | "1:" LB "%1, 0(%2)\n" |
| 1226 | INS "%0, %1, 24, 8\n" |
| 1227 | ADDIU "%2, %2, 1\n" |
| 1228 | " andi %1, %2, 0x3\n" |
| 1229 | " beq $0, %1, 9f\n" |
| 1230 | "2:" LB "%1, 0(%2)\n" |
| 1231 | INS "%0, %1, 16, 8\n" |
| 1232 | ADDIU "%2, %2, 1\n" |
| 1233 | " andi %1, %2, 0x3\n" |
| 1234 | " beq $0, %1, 9f\n" |
| 1235 | "3:" LB "%1, 0(%2)\n" |
| 1236 | INS "%0, %1, 8, 8\n" |
| 1237 | ADDIU "%2, %2, 1\n" |
| 1238 | " andi %1, %2, 0x3\n" |
| 1239 | " beq $0, %1, 9f\n" |
| 1240 | "4:" LB "%1, 0(%2)\n" |
| 1241 | INS "%0, %1, 0, 8\n" |
| 1242 | #endif /* CONFIG_CPU_LITTLE_ENDIAN */ |
| 1243 | "9: sll %0, %0, 0\n" |
| 1244 | "10:\n" |
| 1245 | " .insn\n" |
| 1246 | " .section .fixup,\"ax\"\n" |
| 1247 | "8: li %3,%4\n" |
| 1248 | " j 10b\n" |
| 1249 | " .previous\n" |
| 1250 | " .section __ex_table,\"a\"\n" |
| 1251 | " .word 1b,8b\n" |
| 1252 | " .word 2b,8b\n" |
| 1253 | " .word 3b,8b\n" |
| 1254 | " .word 4b,8b\n" |
| 1255 | " .previous\n" |
| 1256 | " .set pop\n" |
| 1257 | : "+&r"(rt), "=&r"(rs), |
| 1258 | "+&r"(vaddr), "+&r"(err) |
| 1259 | : "i"(SIGSEGV)); |
| 1260 | |
| 1261 | if (MIPSInst_RT(inst) && !err) |
| 1262 | regs->regs[MIPSInst_RT(inst)] = rt; |
| 1263 | |
| 1264 | MIPS_R2_STATS(loads); |
| 1265 | |
| 1266 | break; |
| 1267 | |
| 1268 | case lwr_op: |
| 1269 | rt = regs->regs[MIPSInst_RT(inst)]; |
| 1270 | vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); |
| 1271 | if (!access_ok(VERIFY_READ, vaddr, 4)) { |
| 1272 | current->thread.cp0_baduaddr = vaddr; |
| 1273 | err = SIGSEGV; |
| 1274 | break; |
| 1275 | } |
| 1276 | __asm__ __volatile__( |
| 1277 | " .set push\n" |
| 1278 | " .set reorder\n" |
| 1279 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 1280 | "1:" LB "%1, 0(%2)\n" |
| 1281 | INS "%0, %1, 0, 8\n" |
| 1282 | ADDIU "%2, %2, 1\n" |
| 1283 | " andi %1, %2, 0x3\n" |
| 1284 | " beq $0, %1, 9f\n" |
| 1285 | "2:" LB "%1, 0(%2)\n" |
| 1286 | INS "%0, %1, 8, 8\n" |
| 1287 | ADDIU "%2, %2, 1\n" |
| 1288 | " andi %1, %2, 0x3\n" |
| 1289 | " beq $0, %1, 9f\n" |
| 1290 | "3:" LB "%1, 0(%2)\n" |
| 1291 | INS "%0, %1, 16, 8\n" |
| 1292 | ADDIU "%2, %2, 1\n" |
| 1293 | " andi %1, %2, 0x3\n" |
| 1294 | " beq $0, %1, 9f\n" |
| 1295 | "4:" LB "%1, 0(%2)\n" |
| 1296 | INS "%0, %1, 24, 8\n" |
| 1297 | " sll %0, %0, 0\n" |
| 1298 | #else /* !CONFIG_CPU_LITTLE_ENDIAN */ |
| 1299 | "1:" LB "%1, 0(%2)\n" |
| 1300 | INS "%0, %1, 0, 8\n" |
| 1301 | " andi %1, %2, 0x3\n" |
| 1302 | " beq $0, %1, 9f\n" |
| 1303 | ADDIU "%2, %2, -1\n" |
| 1304 | "2:" LB "%1, 0(%2)\n" |
| 1305 | INS "%0, %1, 8, 8\n" |
| 1306 | " andi %1, %2, 0x3\n" |
| 1307 | " beq $0, %1, 9f\n" |
| 1308 | ADDIU "%2, %2, -1\n" |
| 1309 | "3:" LB "%1, 0(%2)\n" |
| 1310 | INS "%0, %1, 16, 8\n" |
| 1311 | " andi %1, %2, 0x3\n" |
| 1312 | " beq $0, %1, 9f\n" |
| 1313 | ADDIU "%2, %2, -1\n" |
| 1314 | "4:" LB "%1, 0(%2)\n" |
| 1315 | INS "%0, %1, 24, 8\n" |
| 1316 | " sll %0, %0, 0\n" |
| 1317 | #endif /* CONFIG_CPU_LITTLE_ENDIAN */ |
| 1318 | "9:\n" |
| 1319 | "10:\n" |
| 1320 | " .insn\n" |
| 1321 | " .section .fixup,\"ax\"\n" |
| 1322 | "8: li %3,%4\n" |
| 1323 | " j 10b\n" |
| 1324 | " .previous\n" |
| 1325 | " .section __ex_table,\"a\"\n" |
| 1326 | " .word 1b,8b\n" |
| 1327 | " .word 2b,8b\n" |
| 1328 | " .word 3b,8b\n" |
| 1329 | " .word 4b,8b\n" |
| 1330 | " .previous\n" |
| 1331 | " .set pop\n" |
| 1332 | : "+&r"(rt), "=&r"(rs), |
| 1333 | "+&r"(vaddr), "+&r"(err) |
| 1334 | : "i"(SIGSEGV)); |
| 1335 | if (MIPSInst_RT(inst) && !err) |
| 1336 | regs->regs[MIPSInst_RT(inst)] = rt; |
| 1337 | |
| 1338 | MIPS_R2_STATS(loads); |
| 1339 | |
| 1340 | break; |
| 1341 | |
| 1342 | case swl_op: |
| 1343 | rt = regs->regs[MIPSInst_RT(inst)]; |
| 1344 | vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); |
| 1345 | if (!access_ok(VERIFY_WRITE, vaddr, 4)) { |
| 1346 | current->thread.cp0_baduaddr = vaddr; |
| 1347 | err = SIGSEGV; |
| 1348 | break; |
| 1349 | } |
| 1350 | __asm__ __volatile__( |
| 1351 | " .set push\n" |
| 1352 | " .set reorder\n" |
| 1353 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 1354 | EXT "%1, %0, 24, 8\n" |
| 1355 | "1:" SB "%1, 0(%2)\n" |
| 1356 | " andi %1, %2, 0x3\n" |
| 1357 | " beq $0, %1, 9f\n" |
| 1358 | ADDIU "%2, %2, -1\n" |
| 1359 | EXT "%1, %0, 16, 8\n" |
| 1360 | "2:" SB "%1, 0(%2)\n" |
| 1361 | " andi %1, %2, 0x3\n" |
| 1362 | " beq $0, %1, 9f\n" |
| 1363 | ADDIU "%2, %2, -1\n" |
| 1364 | EXT "%1, %0, 8, 8\n" |
| 1365 | "3:" SB "%1, 0(%2)\n" |
| 1366 | " andi %1, %2, 0x3\n" |
| 1367 | " beq $0, %1, 9f\n" |
| 1368 | ADDIU "%2, %2, -1\n" |
| 1369 | EXT "%1, %0, 0, 8\n" |
| 1370 | "4:" SB "%1, 0(%2)\n" |
| 1371 | #else /* !CONFIG_CPU_LITTLE_ENDIAN */ |
| 1372 | EXT "%1, %0, 24, 8\n" |
| 1373 | "1:" SB "%1, 0(%2)\n" |
| 1374 | ADDIU "%2, %2, 1\n" |
| 1375 | " andi %1, %2, 0x3\n" |
| 1376 | " beq $0, %1, 9f\n" |
| 1377 | EXT "%1, %0, 16, 8\n" |
| 1378 | "2:" SB "%1, 0(%2)\n" |
| 1379 | ADDIU "%2, %2, 1\n" |
| 1380 | " andi %1, %2, 0x3\n" |
| 1381 | " beq $0, %1, 9f\n" |
| 1382 | EXT "%1, %0, 8, 8\n" |
| 1383 | "3:" SB "%1, 0(%2)\n" |
| 1384 | ADDIU "%2, %2, 1\n" |
| 1385 | " andi %1, %2, 0x3\n" |
| 1386 | " beq $0, %1, 9f\n" |
| 1387 | EXT "%1, %0, 0, 8\n" |
| 1388 | "4:" SB "%1, 0(%2)\n" |
| 1389 | #endif /* CONFIG_CPU_LITTLE_ENDIAN */ |
| 1390 | "9:\n" |
| 1391 | " .insn\n" |
| 1392 | " .section .fixup,\"ax\"\n" |
| 1393 | "8: li %3,%4\n" |
| 1394 | " j 9b\n" |
| 1395 | " .previous\n" |
| 1396 | " .section __ex_table,\"a\"\n" |
| 1397 | " .word 1b,8b\n" |
| 1398 | " .word 2b,8b\n" |
| 1399 | " .word 3b,8b\n" |
| 1400 | " .word 4b,8b\n" |
| 1401 | " .previous\n" |
| 1402 | " .set pop\n" |
| 1403 | : "+&r"(rt), "=&r"(rs), |
| 1404 | "+&r"(vaddr), "+&r"(err) |
| 1405 | : "i"(SIGSEGV) |
| 1406 | : "memory"); |
| 1407 | |
| 1408 | MIPS_R2_STATS(stores); |
| 1409 | |
| 1410 | break; |
| 1411 | |
| 1412 | case swr_op: |
| 1413 | rt = regs->regs[MIPSInst_RT(inst)]; |
| 1414 | vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); |
| 1415 | if (!access_ok(VERIFY_WRITE, vaddr, 4)) { |
| 1416 | current->thread.cp0_baduaddr = vaddr; |
| 1417 | err = SIGSEGV; |
| 1418 | break; |
| 1419 | } |
| 1420 | __asm__ __volatile__( |
| 1421 | " .set push\n" |
| 1422 | " .set reorder\n" |
| 1423 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 1424 | EXT "%1, %0, 0, 8\n" |
| 1425 | "1:" SB "%1, 0(%2)\n" |
| 1426 | ADDIU "%2, %2, 1\n" |
| 1427 | " andi %1, %2, 0x3\n" |
| 1428 | " beq $0, %1, 9f\n" |
| 1429 | EXT "%1, %0, 8, 8\n" |
| 1430 | "2:" SB "%1, 0(%2)\n" |
| 1431 | ADDIU "%2, %2, 1\n" |
| 1432 | " andi %1, %2, 0x3\n" |
| 1433 | " beq $0, %1, 9f\n" |
| 1434 | EXT "%1, %0, 16, 8\n" |
| 1435 | "3:" SB "%1, 0(%2)\n" |
| 1436 | ADDIU "%2, %2, 1\n" |
| 1437 | " andi %1, %2, 0x3\n" |
| 1438 | " beq $0, %1, 9f\n" |
| 1439 | EXT "%1, %0, 24, 8\n" |
| 1440 | "4:" SB "%1, 0(%2)\n" |
| 1441 | #else /* !CONFIG_CPU_LITTLE_ENDIAN */ |
| 1442 | EXT "%1, %0, 0, 8\n" |
| 1443 | "1:" SB "%1, 0(%2)\n" |
| 1444 | " andi %1, %2, 0x3\n" |
| 1445 | " beq $0, %1, 9f\n" |
| 1446 | ADDIU "%2, %2, -1\n" |
| 1447 | EXT "%1, %0, 8, 8\n" |
| 1448 | "2:" SB "%1, 0(%2)\n" |
| 1449 | " andi %1, %2, 0x3\n" |
| 1450 | " beq $0, %1, 9f\n" |
| 1451 | ADDIU "%2, %2, -1\n" |
| 1452 | EXT "%1, %0, 16, 8\n" |
| 1453 | "3:" SB "%1, 0(%2)\n" |
| 1454 | " andi %1, %2, 0x3\n" |
| 1455 | " beq $0, %1, 9f\n" |
| 1456 | ADDIU "%2, %2, -1\n" |
| 1457 | EXT "%1, %0, 24, 8\n" |
| 1458 | "4:" SB "%1, 0(%2)\n" |
| 1459 | #endif /* CONFIG_CPU_LITTLE_ENDIAN */ |
| 1460 | "9:\n" |
| 1461 | " .insn\n" |
| 1462 | " .section .fixup,\"ax\"\n" |
| 1463 | "8: li %3,%4\n" |
| 1464 | " j 9b\n" |
| 1465 | " .previous\n" |
| 1466 | " .section __ex_table,\"a\"\n" |
| 1467 | " .word 1b,8b\n" |
| 1468 | " .word 2b,8b\n" |
| 1469 | " .word 3b,8b\n" |
| 1470 | " .word 4b,8b\n" |
| 1471 | " .previous\n" |
| 1472 | " .set pop\n" |
| 1473 | : "+&r"(rt), "=&r"(rs), |
| 1474 | "+&r"(vaddr), "+&r"(err) |
| 1475 | : "i"(SIGSEGV) |
| 1476 | : "memory"); |
| 1477 | |
| 1478 | MIPS_R2_STATS(stores); |
| 1479 | |
| 1480 | break; |
| 1481 | |
| 1482 | case ldl_op: |
| 1483 | if (config_enabled(CONFIG_32BIT)) { |
| 1484 | err = SIGILL; |
| 1485 | break; |
| 1486 | } |
| 1487 | |
| 1488 | rt = regs->regs[MIPSInst_RT(inst)]; |
| 1489 | vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); |
| 1490 | if (!access_ok(VERIFY_READ, vaddr, 8)) { |
| 1491 | current->thread.cp0_baduaddr = vaddr; |
| 1492 | err = SIGSEGV; |
| 1493 | break; |
| 1494 | } |
| 1495 | __asm__ __volatile__( |
| 1496 | " .set push\n" |
| 1497 | " .set reorder\n" |
| 1498 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 1499 | "1: lb %1, 0(%2)\n" |
| 1500 | " dinsu %0, %1, 56, 8\n" |
| 1501 | " andi %1, %2, 0x7\n" |
| 1502 | " beq $0, %1, 9f\n" |
| 1503 | " daddiu %2, %2, -1\n" |
| 1504 | "2: lb %1, 0(%2)\n" |
| 1505 | " dinsu %0, %1, 48, 8\n" |
| 1506 | " andi %1, %2, 0x7\n" |
| 1507 | " beq $0, %1, 9f\n" |
| 1508 | " daddiu %2, %2, -1\n" |
| 1509 | "3: lb %1, 0(%2)\n" |
| 1510 | " dinsu %0, %1, 40, 8\n" |
| 1511 | " andi %1, %2, 0x7\n" |
| 1512 | " beq $0, %1, 9f\n" |
| 1513 | " daddiu %2, %2, -1\n" |
| 1514 | "4: lb %1, 0(%2)\n" |
| 1515 | " dinsu %0, %1, 32, 8\n" |
| 1516 | " andi %1, %2, 0x7\n" |
| 1517 | " beq $0, %1, 9f\n" |
| 1518 | " daddiu %2, %2, -1\n" |
| 1519 | "5: lb %1, 0(%2)\n" |
| 1520 | " dins %0, %1, 24, 8\n" |
| 1521 | " andi %1, %2, 0x7\n" |
| 1522 | " beq $0, %1, 9f\n" |
| 1523 | " daddiu %2, %2, -1\n" |
| 1524 | "6: lb %1, 0(%2)\n" |
| 1525 | " dins %0, %1, 16, 8\n" |
| 1526 | " andi %1, %2, 0x7\n" |
| 1527 | " beq $0, %1, 9f\n" |
| 1528 | " daddiu %2, %2, -1\n" |
| 1529 | "7: lb %1, 0(%2)\n" |
| 1530 | " dins %0, %1, 8, 8\n" |
| 1531 | " andi %1, %2, 0x7\n" |
| 1532 | " beq $0, %1, 9f\n" |
| 1533 | " daddiu %2, %2, -1\n" |
| 1534 | "0: lb %1, 0(%2)\n" |
| 1535 | " dins %0, %1, 0, 8\n" |
| 1536 | #else /* !CONFIG_CPU_LITTLE_ENDIAN */ |
| 1537 | "1: lb %1, 0(%2)\n" |
| 1538 | " dinsu %0, %1, 56, 8\n" |
| 1539 | " daddiu %2, %2, 1\n" |
| 1540 | " andi %1, %2, 0x7\n" |
| 1541 | " beq $0, %1, 9f\n" |
| 1542 | "2: lb %1, 0(%2)\n" |
| 1543 | " dinsu %0, %1, 48, 8\n" |
| 1544 | " daddiu %2, %2, 1\n" |
| 1545 | " andi %1, %2, 0x7\n" |
| 1546 | " beq $0, %1, 9f\n" |
| 1547 | "3: lb %1, 0(%2)\n" |
| 1548 | " dinsu %0, %1, 40, 8\n" |
| 1549 | " daddiu %2, %2, 1\n" |
| 1550 | " andi %1, %2, 0x7\n" |
| 1551 | " beq $0, %1, 9f\n" |
| 1552 | "4: lb %1, 0(%2)\n" |
| 1553 | " dinsu %0, %1, 32, 8\n" |
| 1554 | " daddiu %2, %2, 1\n" |
| 1555 | " andi %1, %2, 0x7\n" |
| 1556 | " beq $0, %1, 9f\n" |
| 1557 | "5: lb %1, 0(%2)\n" |
| 1558 | " dins %0, %1, 24, 8\n" |
| 1559 | " daddiu %2, %2, 1\n" |
| 1560 | " andi %1, %2, 0x7\n" |
| 1561 | " beq $0, %1, 9f\n" |
| 1562 | "6: lb %1, 0(%2)\n" |
| 1563 | " dins %0, %1, 16, 8\n" |
| 1564 | " daddiu %2, %2, 1\n" |
| 1565 | " andi %1, %2, 0x7\n" |
| 1566 | " beq $0, %1, 9f\n" |
| 1567 | "7: lb %1, 0(%2)\n" |
| 1568 | " dins %0, %1, 8, 8\n" |
| 1569 | " daddiu %2, %2, 1\n" |
| 1570 | " andi %1, %2, 0x7\n" |
| 1571 | " beq $0, %1, 9f\n" |
| 1572 | "0: lb %1, 0(%2)\n" |
| 1573 | " dins %0, %1, 0, 8\n" |
| 1574 | #endif /* CONFIG_CPU_LITTLE_ENDIAN */ |
| 1575 | "9:\n" |
| 1576 | " .insn\n" |
| 1577 | " .section .fixup,\"ax\"\n" |
| 1578 | "8: li %3,%4\n" |
| 1579 | " j 9b\n" |
| 1580 | " .previous\n" |
| 1581 | " .section __ex_table,\"a\"\n" |
| 1582 | " .word 1b,8b\n" |
| 1583 | " .word 2b,8b\n" |
| 1584 | " .word 3b,8b\n" |
| 1585 | " .word 4b,8b\n" |
| 1586 | " .word 5b,8b\n" |
| 1587 | " .word 6b,8b\n" |
| 1588 | " .word 7b,8b\n" |
| 1589 | " .word 0b,8b\n" |
| 1590 | " .previous\n" |
| 1591 | " .set pop\n" |
| 1592 | : "+&r"(rt), "=&r"(rs), |
| 1593 | "+&r"(vaddr), "+&r"(err) |
| 1594 | : "i"(SIGSEGV)); |
| 1595 | if (MIPSInst_RT(inst) && !err) |
| 1596 | regs->regs[MIPSInst_RT(inst)] = rt; |
| 1597 | |
| 1598 | MIPS_R2_STATS(loads); |
| 1599 | break; |
| 1600 | |
| 1601 | case ldr_op: |
| 1602 | if (config_enabled(CONFIG_32BIT)) { |
| 1603 | err = SIGILL; |
| 1604 | break; |
| 1605 | } |
| 1606 | |
| 1607 | rt = regs->regs[MIPSInst_RT(inst)]; |
| 1608 | vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); |
| 1609 | if (!access_ok(VERIFY_READ, vaddr, 8)) { |
| 1610 | current->thread.cp0_baduaddr = vaddr; |
| 1611 | err = SIGSEGV; |
| 1612 | break; |
| 1613 | } |
| 1614 | __asm__ __volatile__( |
| 1615 | " .set push\n" |
| 1616 | " .set reorder\n" |
| 1617 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 1618 | "1: lb %1, 0(%2)\n" |
| 1619 | " dins %0, %1, 0, 8\n" |
| 1620 | " daddiu %2, %2, 1\n" |
| 1621 | " andi %1, %2, 0x7\n" |
| 1622 | " beq $0, %1, 9f\n" |
| 1623 | "2: lb %1, 0(%2)\n" |
| 1624 | " dins %0, %1, 8, 8\n" |
| 1625 | " daddiu %2, %2, 1\n" |
| 1626 | " andi %1, %2, 0x7\n" |
| 1627 | " beq $0, %1, 9f\n" |
| 1628 | "3: lb %1, 0(%2)\n" |
| 1629 | " dins %0, %1, 16, 8\n" |
| 1630 | " daddiu %2, %2, 1\n" |
| 1631 | " andi %1, %2, 0x7\n" |
| 1632 | " beq $0, %1, 9f\n" |
| 1633 | "4: lb %1, 0(%2)\n" |
| 1634 | " dins %0, %1, 24, 8\n" |
| 1635 | " daddiu %2, %2, 1\n" |
| 1636 | " andi %1, %2, 0x7\n" |
| 1637 | " beq $0, %1, 9f\n" |
| 1638 | "5: lb %1, 0(%2)\n" |
| 1639 | " dinsu %0, %1, 32, 8\n" |
| 1640 | " daddiu %2, %2, 1\n" |
| 1641 | " andi %1, %2, 0x7\n" |
| 1642 | " beq $0, %1, 9f\n" |
| 1643 | "6: lb %1, 0(%2)\n" |
| 1644 | " dinsu %0, %1, 40, 8\n" |
| 1645 | " daddiu %2, %2, 1\n" |
| 1646 | " andi %1, %2, 0x7\n" |
| 1647 | " beq $0, %1, 9f\n" |
| 1648 | "7: lb %1, 0(%2)\n" |
| 1649 | " dinsu %0, %1, 48, 8\n" |
| 1650 | " daddiu %2, %2, 1\n" |
| 1651 | " andi %1, %2, 0x7\n" |
| 1652 | " beq $0, %1, 9f\n" |
| 1653 | "0: lb %1, 0(%2)\n" |
| 1654 | " dinsu %0, %1, 56, 8\n" |
| 1655 | #else /* !CONFIG_CPU_LITTLE_ENDIAN */ |
| 1656 | "1: lb %1, 0(%2)\n" |
| 1657 | " dins %0, %1, 0, 8\n" |
| 1658 | " andi %1, %2, 0x7\n" |
| 1659 | " beq $0, %1, 9f\n" |
| 1660 | " daddiu %2, %2, -1\n" |
| 1661 | "2: lb %1, 0(%2)\n" |
| 1662 | " dins %0, %1, 8, 8\n" |
| 1663 | " andi %1, %2, 0x7\n" |
| 1664 | " beq $0, %1, 9f\n" |
| 1665 | " daddiu %2, %2, -1\n" |
| 1666 | "3: lb %1, 0(%2)\n" |
| 1667 | " dins %0, %1, 16, 8\n" |
| 1668 | " andi %1, %2, 0x7\n" |
| 1669 | " beq $0, %1, 9f\n" |
| 1670 | " daddiu %2, %2, -1\n" |
| 1671 | "4: lb %1, 0(%2)\n" |
| 1672 | " dins %0, %1, 24, 8\n" |
| 1673 | " andi %1, %2, 0x7\n" |
| 1674 | " beq $0, %1, 9f\n" |
| 1675 | " daddiu %2, %2, -1\n" |
| 1676 | "5: lb %1, 0(%2)\n" |
| 1677 | " dinsu %0, %1, 32, 8\n" |
| 1678 | " andi %1, %2, 0x7\n" |
| 1679 | " beq $0, %1, 9f\n" |
| 1680 | " daddiu %2, %2, -1\n" |
| 1681 | "6: lb %1, 0(%2)\n" |
| 1682 | " dinsu %0, %1, 40, 8\n" |
| 1683 | " andi %1, %2, 0x7\n" |
| 1684 | " beq $0, %1, 9f\n" |
| 1685 | " daddiu %2, %2, -1\n" |
| 1686 | "7: lb %1, 0(%2)\n" |
| 1687 | " dinsu %0, %1, 48, 8\n" |
| 1688 | " andi %1, %2, 0x7\n" |
| 1689 | " beq $0, %1, 9f\n" |
| 1690 | " daddiu %2, %2, -1\n" |
| 1691 | "0: lb %1, 0(%2)\n" |
| 1692 | " dinsu %0, %1, 56, 8\n" |
| 1693 | #endif /* CONFIG_CPU_LITTLE_ENDIAN */ |
| 1694 | "9:\n" |
| 1695 | " .insn\n" |
| 1696 | " .section .fixup,\"ax\"\n" |
| 1697 | "8: li %3,%4\n" |
| 1698 | " j 9b\n" |
| 1699 | " .previous\n" |
| 1700 | " .section __ex_table,\"a\"\n" |
| 1701 | " .word 1b,8b\n" |
| 1702 | " .word 2b,8b\n" |
| 1703 | " .word 3b,8b\n" |
| 1704 | " .word 4b,8b\n" |
| 1705 | " .word 5b,8b\n" |
| 1706 | " .word 6b,8b\n" |
| 1707 | " .word 7b,8b\n" |
| 1708 | " .word 0b,8b\n" |
| 1709 | " .previous\n" |
| 1710 | " .set pop\n" |
| 1711 | : "+&r"(rt), "=&r"(rs), |
| 1712 | "+&r"(vaddr), "+&r"(err) |
| 1713 | : "i"(SIGSEGV)); |
| 1714 | if (MIPSInst_RT(inst) && !err) |
| 1715 | regs->regs[MIPSInst_RT(inst)] = rt; |
| 1716 | |
| 1717 | MIPS_R2_STATS(loads); |
| 1718 | break; |
| 1719 | |
| 1720 | case sdl_op: |
| 1721 | if (config_enabled(CONFIG_32BIT)) { |
| 1722 | err = SIGILL; |
| 1723 | break; |
| 1724 | } |
| 1725 | |
| 1726 | rt = regs->regs[MIPSInst_RT(inst)]; |
| 1727 | vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); |
| 1728 | if (!access_ok(VERIFY_WRITE, vaddr, 8)) { |
| 1729 | current->thread.cp0_baduaddr = vaddr; |
| 1730 | err = SIGSEGV; |
| 1731 | break; |
| 1732 | } |
| 1733 | __asm__ __volatile__( |
| 1734 | " .set push\n" |
| 1735 | " .set reorder\n" |
| 1736 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 1737 | " dextu %1, %0, 56, 8\n" |
| 1738 | "1: sb %1, 0(%2)\n" |
| 1739 | " andi %1, %2, 0x7\n" |
| 1740 | " beq $0, %1, 9f\n" |
| 1741 | " daddiu %2, %2, -1\n" |
| 1742 | " dextu %1, %0, 48, 8\n" |
| 1743 | "2: sb %1, 0(%2)\n" |
| 1744 | " andi %1, %2, 0x7\n" |
| 1745 | " beq $0, %1, 9f\n" |
| 1746 | " daddiu %2, %2, -1\n" |
| 1747 | " dextu %1, %0, 40, 8\n" |
| 1748 | "3: sb %1, 0(%2)\n" |
| 1749 | " andi %1, %2, 0x7\n" |
| 1750 | " beq $0, %1, 9f\n" |
| 1751 | " daddiu %2, %2, -1\n" |
| 1752 | " dextu %1, %0, 32, 8\n" |
| 1753 | "4: sb %1, 0(%2)\n" |
| 1754 | " andi %1, %2, 0x7\n" |
| 1755 | " beq $0, %1, 9f\n" |
| 1756 | " daddiu %2, %2, -1\n" |
| 1757 | " dext %1, %0, 24, 8\n" |
| 1758 | "5: sb %1, 0(%2)\n" |
| 1759 | " andi %1, %2, 0x7\n" |
| 1760 | " beq $0, %1, 9f\n" |
| 1761 | " daddiu %2, %2, -1\n" |
| 1762 | " dext %1, %0, 16, 8\n" |
| 1763 | "6: sb %1, 0(%2)\n" |
| 1764 | " andi %1, %2, 0x7\n" |
| 1765 | " beq $0, %1, 9f\n" |
| 1766 | " daddiu %2, %2, -1\n" |
| 1767 | " dext %1, %0, 8, 8\n" |
| 1768 | "7: sb %1, 0(%2)\n" |
| 1769 | " andi %1, %2, 0x7\n" |
| 1770 | " beq $0, %1, 9f\n" |
| 1771 | " daddiu %2, %2, -1\n" |
| 1772 | " dext %1, %0, 0, 8\n" |
| 1773 | "0: sb %1, 0(%2)\n" |
| 1774 | #else /* !CONFIG_CPU_LITTLE_ENDIAN */ |
| 1775 | " dextu %1, %0, 56, 8\n" |
| 1776 | "1: sb %1, 0(%2)\n" |
| 1777 | " daddiu %2, %2, 1\n" |
| 1778 | " andi %1, %2, 0x7\n" |
| 1779 | " beq $0, %1, 9f\n" |
| 1780 | " dextu %1, %0, 48, 8\n" |
| 1781 | "2: sb %1, 0(%2)\n" |
| 1782 | " daddiu %2, %2, 1\n" |
| 1783 | " andi %1, %2, 0x7\n" |
| 1784 | " beq $0, %1, 9f\n" |
| 1785 | " dextu %1, %0, 40, 8\n" |
| 1786 | "3: sb %1, 0(%2)\n" |
| 1787 | " daddiu %2, %2, 1\n" |
| 1788 | " andi %1, %2, 0x7\n" |
| 1789 | " beq $0, %1, 9f\n" |
| 1790 | " dextu %1, %0, 32, 8\n" |
| 1791 | "4: sb %1, 0(%2)\n" |
| 1792 | " daddiu %2, %2, 1\n" |
| 1793 | " andi %1, %2, 0x7\n" |
| 1794 | " beq $0, %1, 9f\n" |
| 1795 | " dext %1, %0, 24, 8\n" |
| 1796 | "5: sb %1, 0(%2)\n" |
| 1797 | " daddiu %2, %2, 1\n" |
| 1798 | " andi %1, %2, 0x7\n" |
| 1799 | " beq $0, %1, 9f\n" |
| 1800 | " dext %1, %0, 16, 8\n" |
| 1801 | "6: sb %1, 0(%2)\n" |
| 1802 | " daddiu %2, %2, 1\n" |
| 1803 | " andi %1, %2, 0x7\n" |
| 1804 | " beq $0, %1, 9f\n" |
| 1805 | " dext %1, %0, 8, 8\n" |
| 1806 | "7: sb %1, 0(%2)\n" |
| 1807 | " daddiu %2, %2, 1\n" |
| 1808 | " andi %1, %2, 0x7\n" |
| 1809 | " beq $0, %1, 9f\n" |
| 1810 | " dext %1, %0, 0, 8\n" |
| 1811 | "0: sb %1, 0(%2)\n" |
| 1812 | #endif /* CONFIG_CPU_LITTLE_ENDIAN */ |
| 1813 | "9:\n" |
| 1814 | " .insn\n" |
| 1815 | " .section .fixup,\"ax\"\n" |
| 1816 | "8: li %3,%4\n" |
| 1817 | " j 9b\n" |
| 1818 | " .previous\n" |
| 1819 | " .section __ex_table,\"a\"\n" |
| 1820 | " .word 1b,8b\n" |
| 1821 | " .word 2b,8b\n" |
| 1822 | " .word 3b,8b\n" |
| 1823 | " .word 4b,8b\n" |
| 1824 | " .word 5b,8b\n" |
| 1825 | " .word 6b,8b\n" |
| 1826 | " .word 7b,8b\n" |
| 1827 | " .word 0b,8b\n" |
| 1828 | " .previous\n" |
| 1829 | " .set pop\n" |
| 1830 | : "+&r"(rt), "=&r"(rs), |
| 1831 | "+&r"(vaddr), "+&r"(err) |
| 1832 | : "i"(SIGSEGV) |
| 1833 | : "memory"); |
| 1834 | |
| 1835 | MIPS_R2_STATS(stores); |
| 1836 | break; |
| 1837 | |
| 1838 | case sdr_op: |
| 1839 | if (config_enabled(CONFIG_32BIT)) { |
| 1840 | err = SIGILL; |
| 1841 | break; |
| 1842 | } |
| 1843 | |
| 1844 | rt = regs->regs[MIPSInst_RT(inst)]; |
| 1845 | vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); |
| 1846 | if (!access_ok(VERIFY_WRITE, vaddr, 8)) { |
| 1847 | current->thread.cp0_baduaddr = vaddr; |
| 1848 | err = SIGSEGV; |
| 1849 | break; |
| 1850 | } |
| 1851 | __asm__ __volatile__( |
| 1852 | " .set push\n" |
| 1853 | " .set reorder\n" |
| 1854 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 1855 | " dext %1, %0, 0, 8\n" |
| 1856 | "1: sb %1, 0(%2)\n" |
| 1857 | " daddiu %2, %2, 1\n" |
| 1858 | " andi %1, %2, 0x7\n" |
| 1859 | " beq $0, %1, 9f\n" |
| 1860 | " dext %1, %0, 8, 8\n" |
| 1861 | "2: sb %1, 0(%2)\n" |
| 1862 | " daddiu %2, %2, 1\n" |
| 1863 | " andi %1, %2, 0x7\n" |
| 1864 | " beq $0, %1, 9f\n" |
| 1865 | " dext %1, %0, 16, 8\n" |
| 1866 | "3: sb %1, 0(%2)\n" |
| 1867 | " daddiu %2, %2, 1\n" |
| 1868 | " andi %1, %2, 0x7\n" |
| 1869 | " beq $0, %1, 9f\n" |
| 1870 | " dext %1, %0, 24, 8\n" |
| 1871 | "4: sb %1, 0(%2)\n" |
| 1872 | " daddiu %2, %2, 1\n" |
| 1873 | " andi %1, %2, 0x7\n" |
| 1874 | " beq $0, %1, 9f\n" |
| 1875 | " dextu %1, %0, 32, 8\n" |
| 1876 | "5: sb %1, 0(%2)\n" |
| 1877 | " daddiu %2, %2, 1\n" |
| 1878 | " andi %1, %2, 0x7\n" |
| 1879 | " beq $0, %1, 9f\n" |
| 1880 | " dextu %1, %0, 40, 8\n" |
| 1881 | "6: sb %1, 0(%2)\n" |
| 1882 | " daddiu %2, %2, 1\n" |
| 1883 | " andi %1, %2, 0x7\n" |
| 1884 | " beq $0, %1, 9f\n" |
| 1885 | " dextu %1, %0, 48, 8\n" |
| 1886 | "7: sb %1, 0(%2)\n" |
| 1887 | " daddiu %2, %2, 1\n" |
| 1888 | " andi %1, %2, 0x7\n" |
| 1889 | " beq $0, %1, 9f\n" |
| 1890 | " dextu %1, %0, 56, 8\n" |
| 1891 | "0: sb %1, 0(%2)\n" |
| 1892 | #else /* !CONFIG_CPU_LITTLE_ENDIAN */ |
| 1893 | " dext %1, %0, 0, 8\n" |
| 1894 | "1: sb %1, 0(%2)\n" |
| 1895 | " andi %1, %2, 0x7\n" |
| 1896 | " beq $0, %1, 9f\n" |
| 1897 | " daddiu %2, %2, -1\n" |
| 1898 | " dext %1, %0, 8, 8\n" |
| 1899 | "2: sb %1, 0(%2)\n" |
| 1900 | " andi %1, %2, 0x7\n" |
| 1901 | " beq $0, %1, 9f\n" |
| 1902 | " daddiu %2, %2, -1\n" |
| 1903 | " dext %1, %0, 16, 8\n" |
| 1904 | "3: sb %1, 0(%2)\n" |
| 1905 | " andi %1, %2, 0x7\n" |
| 1906 | " beq $0, %1, 9f\n" |
| 1907 | " daddiu %2, %2, -1\n" |
| 1908 | " dext %1, %0, 24, 8\n" |
| 1909 | "4: sb %1, 0(%2)\n" |
| 1910 | " andi %1, %2, 0x7\n" |
| 1911 | " beq $0, %1, 9f\n" |
| 1912 | " daddiu %2, %2, -1\n" |
| 1913 | " dextu %1, %0, 32, 8\n" |
| 1914 | "5: sb %1, 0(%2)\n" |
| 1915 | " andi %1, %2, 0x7\n" |
| 1916 | " beq $0, %1, 9f\n" |
| 1917 | " daddiu %2, %2, -1\n" |
| 1918 | " dextu %1, %0, 40, 8\n" |
| 1919 | "6: sb %1, 0(%2)\n" |
| 1920 | " andi %1, %2, 0x7\n" |
| 1921 | " beq $0, %1, 9f\n" |
| 1922 | " daddiu %2, %2, -1\n" |
| 1923 | " dextu %1, %0, 48, 8\n" |
| 1924 | "7: sb %1, 0(%2)\n" |
| 1925 | " andi %1, %2, 0x7\n" |
| 1926 | " beq $0, %1, 9f\n" |
| 1927 | " daddiu %2, %2, -1\n" |
| 1928 | " dextu %1, %0, 56, 8\n" |
| 1929 | "0: sb %1, 0(%2)\n" |
| 1930 | #endif /* CONFIG_CPU_LITTLE_ENDIAN */ |
| 1931 | "9:\n" |
| 1932 | " .insn\n" |
| 1933 | " .section .fixup,\"ax\"\n" |
| 1934 | "8: li %3,%4\n" |
| 1935 | " j 9b\n" |
| 1936 | " .previous\n" |
| 1937 | " .section __ex_table,\"a\"\n" |
| 1938 | " .word 1b,8b\n" |
| 1939 | " .word 2b,8b\n" |
| 1940 | " .word 3b,8b\n" |
| 1941 | " .word 4b,8b\n" |
| 1942 | " .word 5b,8b\n" |
| 1943 | " .word 6b,8b\n" |
| 1944 | " .word 7b,8b\n" |
| 1945 | " .word 0b,8b\n" |
| 1946 | " .previous\n" |
| 1947 | " .set pop\n" |
| 1948 | : "+&r"(rt), "=&r"(rs), |
| 1949 | "+&r"(vaddr), "+&r"(err) |
| 1950 | : "i"(SIGSEGV) |
| 1951 | : "memory"); |
| 1952 | |
| 1953 | MIPS_R2_STATS(stores); |
| 1954 | |
| 1955 | break; |
| 1956 | case ll_op: |
| 1957 | vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); |
| 1958 | if (vaddr & 0x3) { |
| 1959 | current->thread.cp0_baduaddr = vaddr; |
| 1960 | err = SIGBUS; |
| 1961 | break; |
| 1962 | } |
| 1963 | if (!access_ok(VERIFY_READ, vaddr, 4)) { |
| 1964 | current->thread.cp0_baduaddr = vaddr; |
| 1965 | err = SIGBUS; |
| 1966 | break; |
| 1967 | } |
| 1968 | |
| 1969 | if (!cpu_has_rw_llb) { |
| 1970 | /* |
| 1971 | * An LL/SC block can't be safely emulated without |
| 1972 | * a Config5/LLB availability. So it's probably time to |
| 1973 | * kill our process before things get any worse. This is |
| 1974 | * because Config5/LLB allows us to use ERETNC so that |
| 1975 | * the LLAddr/LLB bit is not cleared when we return from |
| 1976 | * an exception. MIPS R2 LL/SC instructions trap with an |
| 1977 | * RI exception so once we emulate them here, we return |
| 1978 | * back to userland with ERETNC. That preserves the |
| 1979 | * LLAddr/LLB so the subsequent SC instruction will |
| 1980 | * succeed preserving the atomic semantics of the LL/SC |
| 1981 | * block. Without that, there is no safe way to emulate |
| 1982 | * an LL/SC block in MIPSR2 userland. |
| 1983 | */ |
| 1984 | pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); |
| 1985 | err = SIGKILL; |
| 1986 | break; |
| 1987 | } |
| 1988 | |
| 1989 | __asm__ __volatile__( |
| 1990 | "1:\n" |
| 1991 | "ll %0, 0(%2)\n" |
| 1992 | "2:\n" |
| 1993 | ".insn\n" |
| 1994 | ".section .fixup,\"ax\"\n" |
| 1995 | "3:\n" |
| 1996 | "li %1, %3\n" |
| 1997 | "j 2b\n" |
| 1998 | ".previous\n" |
| 1999 | ".section __ex_table,\"a\"\n" |
| 2000 | ".word 1b, 3b\n" |
| 2001 | ".previous\n" |
| 2002 | : "=&r"(res), "+&r"(err) |
| 2003 | : "r"(vaddr), "i"(SIGSEGV) |
| 2004 | : "memory"); |
| 2005 | |
| 2006 | if (MIPSInst_RT(inst) && !err) |
| 2007 | regs->regs[MIPSInst_RT(inst)] = res; |
| 2008 | MIPS_R2_STATS(llsc); |
| 2009 | |
| 2010 | break; |
| 2011 | |
| 2012 | case sc_op: |
| 2013 | vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); |
| 2014 | if (vaddr & 0x3) { |
| 2015 | current->thread.cp0_baduaddr = vaddr; |
| 2016 | err = SIGBUS; |
| 2017 | break; |
| 2018 | } |
| 2019 | if (!access_ok(VERIFY_WRITE, vaddr, 4)) { |
| 2020 | current->thread.cp0_baduaddr = vaddr; |
| 2021 | err = SIGBUS; |
| 2022 | break; |
| 2023 | } |
| 2024 | |
| 2025 | if (!cpu_has_rw_llb) { |
| 2026 | /* |
| 2027 | * An LL/SC block can't be safely emulated without |
| 2028 | * a Config5/LLB availability. So it's probably time to |
| 2029 | * kill our process before things get any worse. This is |
| 2030 | * because Config5/LLB allows us to use ERETNC so that |
| 2031 | * the LLAddr/LLB bit is not cleared when we return from |
| 2032 | * an exception. MIPS R2 LL/SC instructions trap with an |
| 2033 | * RI exception so once we emulate them here, we return |
| 2034 | * back to userland with ERETNC. That preserves the |
| 2035 | * LLAddr/LLB so the subsequent SC instruction will |
| 2036 | * succeed preserving the atomic semantics of the LL/SC |
| 2037 | * block. Without that, there is no safe way to emulate |
| 2038 | * an LL/SC block in MIPSR2 userland. |
| 2039 | */ |
| 2040 | pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); |
| 2041 | err = SIGKILL; |
| 2042 | break; |
| 2043 | } |
| 2044 | |
| 2045 | res = regs->regs[MIPSInst_RT(inst)]; |
| 2046 | |
| 2047 | __asm__ __volatile__( |
| 2048 | "1:\n" |
| 2049 | "sc %0, 0(%2)\n" |
| 2050 | "2:\n" |
| 2051 | ".insn\n" |
| 2052 | ".section .fixup,\"ax\"\n" |
| 2053 | "3:\n" |
| 2054 | "li %1, %3\n" |
| 2055 | "j 2b\n" |
| 2056 | ".previous\n" |
| 2057 | ".section __ex_table,\"a\"\n" |
| 2058 | ".word 1b, 3b\n" |
| 2059 | ".previous\n" |
| 2060 | : "+&r"(res), "+&r"(err) |
| 2061 | : "r"(vaddr), "i"(SIGSEGV)); |
| 2062 | |
| 2063 | if (MIPSInst_RT(inst) && !err) |
| 2064 | regs->regs[MIPSInst_RT(inst)] = res; |
| 2065 | |
| 2066 | MIPS_R2_STATS(llsc); |
| 2067 | |
| 2068 | break; |
| 2069 | |
| 2070 | case lld_op: |
| 2071 | if (config_enabled(CONFIG_32BIT)) { |
| 2072 | err = SIGILL; |
| 2073 | break; |
| 2074 | } |
| 2075 | |
| 2076 | vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); |
| 2077 | if (vaddr & 0x7) { |
| 2078 | current->thread.cp0_baduaddr = vaddr; |
| 2079 | err = SIGBUS; |
| 2080 | break; |
| 2081 | } |
| 2082 | if (!access_ok(VERIFY_READ, vaddr, 8)) { |
| 2083 | current->thread.cp0_baduaddr = vaddr; |
| 2084 | err = SIGBUS; |
| 2085 | break; |
| 2086 | } |
| 2087 | |
| 2088 | if (!cpu_has_rw_llb) { |
| 2089 | /* |
| 2090 | * An LL/SC block can't be safely emulated without |
| 2091 | * a Config5/LLB availability. So it's probably time to |
| 2092 | * kill our process before things get any worse. This is |
| 2093 | * because Config5/LLB allows us to use ERETNC so that |
| 2094 | * the LLAddr/LLB bit is not cleared when we return from |
| 2095 | * an exception. MIPS R2 LL/SC instructions trap with an |
| 2096 | * RI exception so once we emulate them here, we return |
| 2097 | * back to userland with ERETNC. That preserves the |
| 2098 | * LLAddr/LLB so the subsequent SC instruction will |
| 2099 | * succeed preserving the atomic semantics of the LL/SC |
| 2100 | * block. Without that, there is no safe way to emulate |
| 2101 | * an LL/SC block in MIPSR2 userland. |
| 2102 | */ |
| 2103 | pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); |
| 2104 | err = SIGKILL; |
| 2105 | break; |
| 2106 | } |
| 2107 | |
| 2108 | __asm__ __volatile__( |
| 2109 | "1:\n" |
| 2110 | "lld %0, 0(%2)\n" |
| 2111 | "2:\n" |
| 2112 | ".insn\n" |
| 2113 | ".section .fixup,\"ax\"\n" |
| 2114 | "3:\n" |
| 2115 | "li %1, %3\n" |
| 2116 | "j 2b\n" |
| 2117 | ".previous\n" |
| 2118 | ".section __ex_table,\"a\"\n" |
| 2119 | ".word 1b, 3b\n" |
| 2120 | ".previous\n" |
| 2121 | : "=&r"(res), "+&r"(err) |
| 2122 | : "r"(vaddr), "i"(SIGSEGV) |
| 2123 | : "memory"); |
| 2124 | if (MIPSInst_RT(inst) && !err) |
| 2125 | regs->regs[MIPSInst_RT(inst)] = res; |
| 2126 | |
| 2127 | MIPS_R2_STATS(llsc); |
| 2128 | |
| 2129 | break; |
| 2130 | |
| 2131 | case scd_op: |
| 2132 | if (config_enabled(CONFIG_32BIT)) { |
| 2133 | err = SIGILL; |
| 2134 | break; |
| 2135 | } |
| 2136 | |
| 2137 | vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); |
| 2138 | if (vaddr & 0x7) { |
| 2139 | current->thread.cp0_baduaddr = vaddr; |
| 2140 | err = SIGBUS; |
| 2141 | break; |
| 2142 | } |
| 2143 | if (!access_ok(VERIFY_WRITE, vaddr, 8)) { |
| 2144 | current->thread.cp0_baduaddr = vaddr; |
| 2145 | err = SIGBUS; |
| 2146 | break; |
| 2147 | } |
| 2148 | |
| 2149 | if (!cpu_has_rw_llb) { |
| 2150 | /* |
| 2151 | * An LL/SC block can't be safely emulated without |
| 2152 | * a Config5/LLB availability. So it's probably time to |
| 2153 | * kill our process before things get any worse. This is |
| 2154 | * because Config5/LLB allows us to use ERETNC so that |
| 2155 | * the LLAddr/LLB bit is not cleared when we return from |
| 2156 | * an exception. MIPS R2 LL/SC instructions trap with an |
| 2157 | * RI exception so once we emulate them here, we return |
| 2158 | * back to userland with ERETNC. That preserves the |
| 2159 | * LLAddr/LLB so the subsequent SC instruction will |
| 2160 | * succeed preserving the atomic semantics of the LL/SC |
| 2161 | * block. Without that, there is no safe way to emulate |
| 2162 | * an LL/SC block in MIPSR2 userland. |
| 2163 | */ |
| 2164 | pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); |
| 2165 | err = SIGKILL; |
| 2166 | break; |
| 2167 | } |
| 2168 | |
| 2169 | res = regs->regs[MIPSInst_RT(inst)]; |
| 2170 | |
| 2171 | __asm__ __volatile__( |
| 2172 | "1:\n" |
| 2173 | "scd %0, 0(%2)\n" |
| 2174 | "2:\n" |
| 2175 | ".insn\n" |
| 2176 | ".section .fixup,\"ax\"\n" |
| 2177 | "3:\n" |
| 2178 | "li %1, %3\n" |
| 2179 | "j 2b\n" |
| 2180 | ".previous\n" |
| 2181 | ".section __ex_table,\"a\"\n" |
| 2182 | ".word 1b, 3b\n" |
| 2183 | ".previous\n" |
| 2184 | : "+&r"(res), "+&r"(err) |
| 2185 | : "r"(vaddr), "i"(SIGSEGV)); |
| 2186 | |
| 2187 | if (MIPSInst_RT(inst) && !err) |
| 2188 | regs->regs[MIPSInst_RT(inst)] = res; |
| 2189 | |
| 2190 | MIPS_R2_STATS(llsc); |
| 2191 | |
| 2192 | break; |
| 2193 | case pref_op: |
| 2194 | /* skip it */ |
| 2195 | break; |
| 2196 | default: |
| 2197 | err = SIGILL; |
| 2198 | } |
| 2199 | |
| 2200 | /* |
| 2201 | * Lets not return to userland just yet. It's constly and |
| 2202 | * it's likely we have more R2 instructions to emulate |
| 2203 | */ |
| 2204 | if (!err && (pass++ < MIPS_R2_EMUL_TOTAL_PASS)) { |
| 2205 | regs->cp0_cause &= ~CAUSEF_BD; |
| 2206 | err = get_user(inst, (u32 __user *)regs->cp0_epc); |
| 2207 | if (!err) |
| 2208 | goto repeat; |
| 2209 | |
| 2210 | if (err < 0) |
| 2211 | err = SIGSEGV; |
| 2212 | } |
| 2213 | |
| 2214 | if (err && (err != SIGEMT)) { |
| 2215 | regs->regs[31] = r31; |
| 2216 | regs->cp0_epc = epc; |
| 2217 | } |
| 2218 | |
| 2219 | /* Likely a MIPS R6 compatible instruction */ |
| 2220 | if (pass && (err == SIGILL)) |
| 2221 | err = 0; |
| 2222 | |
| 2223 | return err; |
| 2224 | } |
| 2225 | |
| 2226 | #ifdef CONFIG_DEBUG_FS |
| 2227 | |
| 2228 | static int mipsr2_stats_show(struct seq_file *s, void *unused) |
| 2229 | { |
| 2230 | |
| 2231 | seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n"); |
| 2232 | seq_printf(s, "movs\t\t%ld\t%ld\n", |
| 2233 | (unsigned long)__this_cpu_read(mipsr2emustats.movs), |
| 2234 | (unsigned long)__this_cpu_read(mipsr2bdemustats.movs)); |
| 2235 | seq_printf(s, "hilo\t\t%ld\t%ld\n", |
| 2236 | (unsigned long)__this_cpu_read(mipsr2emustats.hilo), |
| 2237 | (unsigned long)__this_cpu_read(mipsr2bdemustats.hilo)); |
| 2238 | seq_printf(s, "muls\t\t%ld\t%ld\n", |
| 2239 | (unsigned long)__this_cpu_read(mipsr2emustats.muls), |
| 2240 | (unsigned long)__this_cpu_read(mipsr2bdemustats.muls)); |
| 2241 | seq_printf(s, "divs\t\t%ld\t%ld\n", |
| 2242 | (unsigned long)__this_cpu_read(mipsr2emustats.divs), |
| 2243 | (unsigned long)__this_cpu_read(mipsr2bdemustats.divs)); |
| 2244 | seq_printf(s, "dsps\t\t%ld\t%ld\n", |
| 2245 | (unsigned long)__this_cpu_read(mipsr2emustats.dsps), |
| 2246 | (unsigned long)__this_cpu_read(mipsr2bdemustats.dsps)); |
| 2247 | seq_printf(s, "bops\t\t%ld\t%ld\n", |
| 2248 | (unsigned long)__this_cpu_read(mipsr2emustats.bops), |
| 2249 | (unsigned long)__this_cpu_read(mipsr2bdemustats.bops)); |
| 2250 | seq_printf(s, "traps\t\t%ld\t%ld\n", |
| 2251 | (unsigned long)__this_cpu_read(mipsr2emustats.traps), |
| 2252 | (unsigned long)__this_cpu_read(mipsr2bdemustats.traps)); |
| 2253 | seq_printf(s, "fpus\t\t%ld\t%ld\n", |
| 2254 | (unsigned long)__this_cpu_read(mipsr2emustats.fpus), |
| 2255 | (unsigned long)__this_cpu_read(mipsr2bdemustats.fpus)); |
| 2256 | seq_printf(s, "loads\t\t%ld\t%ld\n", |
| 2257 | (unsigned long)__this_cpu_read(mipsr2emustats.loads), |
| 2258 | (unsigned long)__this_cpu_read(mipsr2bdemustats.loads)); |
| 2259 | seq_printf(s, "stores\t\t%ld\t%ld\n", |
| 2260 | (unsigned long)__this_cpu_read(mipsr2emustats.stores), |
| 2261 | (unsigned long)__this_cpu_read(mipsr2bdemustats.stores)); |
| 2262 | seq_printf(s, "llsc\t\t%ld\t%ld\n", |
| 2263 | (unsigned long)__this_cpu_read(mipsr2emustats.llsc), |
| 2264 | (unsigned long)__this_cpu_read(mipsr2bdemustats.llsc)); |
| 2265 | seq_printf(s, "dsemul\t\t%ld\t%ld\n", |
| 2266 | (unsigned long)__this_cpu_read(mipsr2emustats.dsemul), |
| 2267 | (unsigned long)__this_cpu_read(mipsr2bdemustats.dsemul)); |
| 2268 | seq_printf(s, "jr\t\t%ld\n", |
| 2269 | (unsigned long)__this_cpu_read(mipsr2bremustats.jrs)); |
| 2270 | seq_printf(s, "bltzl\t\t%ld\n", |
| 2271 | (unsigned long)__this_cpu_read(mipsr2bremustats.bltzl)); |
| 2272 | seq_printf(s, "bgezl\t\t%ld\n", |
| 2273 | (unsigned long)__this_cpu_read(mipsr2bremustats.bgezl)); |
| 2274 | seq_printf(s, "bltzll\t\t%ld\n", |
| 2275 | (unsigned long)__this_cpu_read(mipsr2bremustats.bltzll)); |
| 2276 | seq_printf(s, "bgezll\t\t%ld\n", |
| 2277 | (unsigned long)__this_cpu_read(mipsr2bremustats.bgezll)); |
| 2278 | seq_printf(s, "bltzal\t\t%ld\n", |
| 2279 | (unsigned long)__this_cpu_read(mipsr2bremustats.bltzal)); |
| 2280 | seq_printf(s, "bgezal\t\t%ld\n", |
| 2281 | (unsigned long)__this_cpu_read(mipsr2bremustats.bgezal)); |
| 2282 | seq_printf(s, "beql\t\t%ld\n", |
| 2283 | (unsigned long)__this_cpu_read(mipsr2bremustats.beql)); |
| 2284 | seq_printf(s, "bnel\t\t%ld\n", |
| 2285 | (unsigned long)__this_cpu_read(mipsr2bremustats.bnel)); |
| 2286 | seq_printf(s, "blezl\t\t%ld\n", |
| 2287 | (unsigned long)__this_cpu_read(mipsr2bremustats.blezl)); |
| 2288 | seq_printf(s, "bgtzl\t\t%ld\n", |
| 2289 | (unsigned long)__this_cpu_read(mipsr2bremustats.bgtzl)); |
| 2290 | |
| 2291 | return 0; |
| 2292 | } |
| 2293 | |
| 2294 | static int mipsr2_stats_clear_show(struct seq_file *s, void *unused) |
| 2295 | { |
| 2296 | mipsr2_stats_show(s, unused); |
| 2297 | |
| 2298 | __this_cpu_write((mipsr2emustats).movs, 0); |
| 2299 | __this_cpu_write((mipsr2bdemustats).movs, 0); |
| 2300 | __this_cpu_write((mipsr2emustats).hilo, 0); |
| 2301 | __this_cpu_write((mipsr2bdemustats).hilo, 0); |
| 2302 | __this_cpu_write((mipsr2emustats).muls, 0); |
| 2303 | __this_cpu_write((mipsr2bdemustats).muls, 0); |
| 2304 | __this_cpu_write((mipsr2emustats).divs, 0); |
| 2305 | __this_cpu_write((mipsr2bdemustats).divs, 0); |
| 2306 | __this_cpu_write((mipsr2emustats).dsps, 0); |
| 2307 | __this_cpu_write((mipsr2bdemustats).dsps, 0); |
| 2308 | __this_cpu_write((mipsr2emustats).bops, 0); |
| 2309 | __this_cpu_write((mipsr2bdemustats).bops, 0); |
| 2310 | __this_cpu_write((mipsr2emustats).traps, 0); |
| 2311 | __this_cpu_write((mipsr2bdemustats).traps, 0); |
| 2312 | __this_cpu_write((mipsr2emustats).fpus, 0); |
| 2313 | __this_cpu_write((mipsr2bdemustats).fpus, 0); |
| 2314 | __this_cpu_write((mipsr2emustats).loads, 0); |
| 2315 | __this_cpu_write((mipsr2bdemustats).loads, 0); |
| 2316 | __this_cpu_write((mipsr2emustats).stores, 0); |
| 2317 | __this_cpu_write((mipsr2bdemustats).stores, 0); |
| 2318 | __this_cpu_write((mipsr2emustats).llsc, 0); |
| 2319 | __this_cpu_write((mipsr2bdemustats).llsc, 0); |
| 2320 | __this_cpu_write((mipsr2emustats).dsemul, 0); |
| 2321 | __this_cpu_write((mipsr2bdemustats).dsemul, 0); |
| 2322 | __this_cpu_write((mipsr2bremustats).jrs, 0); |
| 2323 | __this_cpu_write((mipsr2bremustats).bltzl, 0); |
| 2324 | __this_cpu_write((mipsr2bremustats).bgezl, 0); |
| 2325 | __this_cpu_write((mipsr2bremustats).bltzll, 0); |
| 2326 | __this_cpu_write((mipsr2bremustats).bgezll, 0); |
| 2327 | __this_cpu_write((mipsr2bremustats).bltzal, 0); |
| 2328 | __this_cpu_write((mipsr2bremustats).bgezal, 0); |
| 2329 | __this_cpu_write((mipsr2bremustats).beql, 0); |
| 2330 | __this_cpu_write((mipsr2bremustats).bnel, 0); |
| 2331 | __this_cpu_write((mipsr2bremustats).blezl, 0); |
| 2332 | __this_cpu_write((mipsr2bremustats).bgtzl, 0); |
| 2333 | |
| 2334 | return 0; |
| 2335 | } |
| 2336 | |
| 2337 | static int mipsr2_stats_open(struct inode *inode, struct file *file) |
| 2338 | { |
| 2339 | return single_open(file, mipsr2_stats_show, inode->i_private); |
| 2340 | } |
| 2341 | |
| 2342 | static int mipsr2_stats_clear_open(struct inode *inode, struct file *file) |
| 2343 | { |
| 2344 | return single_open(file, mipsr2_stats_clear_show, inode->i_private); |
| 2345 | } |
| 2346 | |
| 2347 | static const struct file_operations mipsr2_emul_fops = { |
| 2348 | .open = mipsr2_stats_open, |
| 2349 | .read = seq_read, |
| 2350 | .llseek = seq_lseek, |
| 2351 | .release = single_release, |
| 2352 | }; |
| 2353 | |
| 2354 | static const struct file_operations mipsr2_clear_fops = { |
| 2355 | .open = mipsr2_stats_clear_open, |
| 2356 | .read = seq_read, |
| 2357 | .llseek = seq_lseek, |
| 2358 | .release = single_release, |
| 2359 | }; |
| 2360 | |
| 2361 | |
| 2362 | static int __init mipsr2_init_debugfs(void) |
| 2363 | { |
| 2364 | extern struct dentry *mips_debugfs_dir; |
| 2365 | struct dentry *mipsr2_emul; |
| 2366 | |
| 2367 | if (!mips_debugfs_dir) |
| 2368 | return -ENODEV; |
| 2369 | |
| 2370 | mipsr2_emul = debugfs_create_file("r2_emul_stats", S_IRUGO, |
| 2371 | mips_debugfs_dir, NULL, |
| 2372 | &mipsr2_emul_fops); |
| 2373 | if (!mipsr2_emul) |
| 2374 | return -ENOMEM; |
| 2375 | |
| 2376 | mipsr2_emul = debugfs_create_file("r2_emul_stats_clear", S_IRUGO, |
| 2377 | mips_debugfs_dir, NULL, |
| 2378 | &mipsr2_clear_fops); |
| 2379 | if (!mipsr2_emul) |
| 2380 | return -ENOMEM; |
| 2381 | |
| 2382 | return 0; |
| 2383 | } |
| 2384 | |
| 2385 | device_initcall(mipsr2_init_debugfs); |
| 2386 | |
| 2387 | #endif /* CONFIG_DEBUG_FS */ |