Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 1 | /* |
Joseph Lo | 291fde3 | 2013-02-28 21:32:10 +0000 | [diff] [blame] | 2 | * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved. |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <linux/kernel.h> |
Joseph Lo | 0337c3e | 2013-04-03 19:31:28 +0800 | [diff] [blame] | 19 | #include <linux/clk.h> |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 20 | #include <linux/io.h> |
| 21 | #include <linux/of.h> |
Joseph Lo | 291fde3 | 2013-02-28 21:32:10 +0000 | [diff] [blame] | 22 | #include <linux/of_address.h> |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 23 | |
Joseph Lo | 3f1be81 | 2013-07-03 17:50:41 +0800 | [diff] [blame] | 24 | #include "flowctrl.h" |
Joseph Lo | c8c2e60 | 2013-04-03 19:31:47 +0800 | [diff] [blame] | 25 | #include "fuse.h" |
| 26 | #include "pm.h" |
Joseph Lo | 4b51ccb | 2013-04-03 19:31:46 +0800 | [diff] [blame] | 27 | #include "pmc.h" |
Joseph Lo | c8c2e60 | 2013-04-03 19:31:47 +0800 | [diff] [blame] | 28 | #include "sleep.h" |
| 29 | |
Joseph Lo | 444f9a80 | 2013-08-12 17:40:01 +0800 | [diff] [blame^] | 30 | #define TEGRA_POWER_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */ |
| 31 | #define TEGRA_POWER_SYSCLK_OE (1 << 11) /* system clock enable */ |
Joseph Lo | c8c2e60 | 2013-04-03 19:31:47 +0800 | [diff] [blame] | 32 | #define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ |
| 33 | #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ |
| 34 | #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ |
Joseph Lo | 4b51ccb | 2013-04-03 19:31:46 +0800 | [diff] [blame] | 35 | |
Joseph Lo | c141753 | 2013-02-28 21:32:11 +0000 | [diff] [blame] | 36 | #define PMC_CTRL 0x0 |
| 37 | #define PMC_CTRL_INTR_LOW (1 << 17) |
| 38 | #define PMC_PWRGATE_TOGGLE 0x30 |
| 39 | #define PMC_PWRGATE_TOGGLE_START (1 << 8) |
| 40 | #define PMC_REMOVE_CLAMPING 0x34 |
| 41 | #define PMC_PWRGATE_STATUS 0x38 |
| 42 | |
Joseph Lo | 0337c3e | 2013-04-03 19:31:28 +0800 | [diff] [blame] | 43 | #define PMC_CPUPWRGOOD_TIMER 0xc8 |
| 44 | #define PMC_CPUPWROFF_TIMER 0xcc |
| 45 | |
Joseph Lo | c141753 | 2013-02-28 21:32:11 +0000 | [diff] [blame] | 46 | #define TEGRA_POWERGATE_PCIE 3 |
| 47 | #define TEGRA_POWERGATE_VDEC 4 |
| 48 | #define TEGRA_POWERGATE_CPU1 9 |
| 49 | #define TEGRA_POWERGATE_CPU2 10 |
| 50 | #define TEGRA_POWERGATE_CPU3 11 |
| 51 | |
| 52 | static u8 tegra_cpu_domains[] = { |
| 53 | 0xFF, /* not available for CPU0 */ |
| 54 | TEGRA_POWERGATE_CPU1, |
| 55 | TEGRA_POWERGATE_CPU2, |
| 56 | TEGRA_POWERGATE_CPU3, |
| 57 | }; |
| 58 | static DEFINE_SPINLOCK(tegra_powergate_lock); |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 59 | |
Joseph Lo | 291fde3 | 2013-02-28 21:32:10 +0000 | [diff] [blame] | 60 | static void __iomem *tegra_pmc_base; |
| 61 | static bool tegra_pmc_invert_interrupt; |
Joseph Lo | 0337c3e | 2013-04-03 19:31:28 +0800 | [diff] [blame] | 62 | static struct clk *tegra_pclk; |
Joseph Lo | 291fde3 | 2013-02-28 21:32:10 +0000 | [diff] [blame] | 63 | |
Joseph Lo | 4b51ccb | 2013-04-03 19:31:46 +0800 | [diff] [blame] | 64 | struct pmc_pm_data { |
| 65 | u32 cpu_good_time; /* CPU power good time in uS */ |
| 66 | u32 cpu_off_time; /* CPU power off time in uS */ |
| 67 | u32 core_osc_time; /* Core power good osc time in uS */ |
| 68 | u32 core_pmu_time; /* Core power good pmu time in uS */ |
| 69 | u32 core_off_time; /* Core power off time in uS */ |
| 70 | bool corereq_high; /* Core power request active-high */ |
| 71 | bool sysclkreq_high; /* System clock request active-high */ |
| 72 | bool combined_req; /* Combined pwr req for CPU & Core */ |
| 73 | bool cpu_pwr_good_en; /* CPU power good signal is enabled */ |
| 74 | u32 lp0_vec_phy_addr; /* The phy addr of LP0 warm boot code */ |
| 75 | u32 lp0_vec_size; /* The size of LP0 warm boot code */ |
| 76 | enum tegra_suspend_mode suspend_mode; |
| 77 | }; |
| 78 | static struct pmc_pm_data pmc_pm_data; |
| 79 | |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 80 | static inline u32 tegra_pmc_readl(u32 reg) |
| 81 | { |
Joseph Lo | 291fde3 | 2013-02-28 21:32:10 +0000 | [diff] [blame] | 82 | return readl(tegra_pmc_base + reg); |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 83 | } |
| 84 | |
| 85 | static inline void tegra_pmc_writel(u32 val, u32 reg) |
| 86 | { |
Joseph Lo | 291fde3 | 2013-02-28 21:32:10 +0000 | [diff] [blame] | 87 | writel(val, tegra_pmc_base + reg); |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 88 | } |
| 89 | |
Joseph Lo | c141753 | 2013-02-28 21:32:11 +0000 | [diff] [blame] | 90 | static int tegra_pmc_get_cpu_powerdomain_id(int cpuid) |
| 91 | { |
| 92 | if (cpuid <= 0 || cpuid >= num_possible_cpus()) |
| 93 | return -EINVAL; |
| 94 | return tegra_cpu_domains[cpuid]; |
| 95 | } |
| 96 | |
| 97 | static bool tegra_pmc_powergate_is_powered(int id) |
| 98 | { |
| 99 | return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1; |
| 100 | } |
| 101 | |
| 102 | static int tegra_pmc_powergate_set(int id, bool new_state) |
| 103 | { |
| 104 | bool old_state; |
| 105 | unsigned long flags; |
| 106 | |
| 107 | spin_lock_irqsave(&tegra_powergate_lock, flags); |
| 108 | |
| 109 | old_state = tegra_pmc_powergate_is_powered(id); |
| 110 | WARN_ON(old_state == new_state); |
| 111 | |
| 112 | tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE); |
| 113 | |
| 114 | spin_unlock_irqrestore(&tegra_powergate_lock, flags); |
| 115 | |
| 116 | return 0; |
| 117 | } |
| 118 | |
| 119 | static int tegra_pmc_powergate_remove_clamping(int id) |
| 120 | { |
| 121 | u32 mask; |
| 122 | |
| 123 | /* |
| 124 | * Tegra has a bug where PCIE and VDE clamping masks are |
| 125 | * swapped relatively to the partition ids. |
| 126 | */ |
| 127 | if (id == TEGRA_POWERGATE_VDEC) |
| 128 | mask = (1 << TEGRA_POWERGATE_PCIE); |
| 129 | else if (id == TEGRA_POWERGATE_PCIE) |
| 130 | mask = (1 << TEGRA_POWERGATE_VDEC); |
| 131 | else |
| 132 | mask = (1 << id); |
| 133 | |
| 134 | tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING); |
| 135 | |
| 136 | return 0; |
| 137 | } |
| 138 | |
| 139 | bool tegra_pmc_cpu_is_powered(int cpuid) |
| 140 | { |
| 141 | int id; |
| 142 | |
| 143 | id = tegra_pmc_get_cpu_powerdomain_id(cpuid); |
| 144 | if (id < 0) |
| 145 | return false; |
| 146 | return tegra_pmc_powergate_is_powered(id); |
| 147 | } |
| 148 | |
| 149 | int tegra_pmc_cpu_power_on(int cpuid) |
| 150 | { |
| 151 | int id; |
| 152 | |
| 153 | id = tegra_pmc_get_cpu_powerdomain_id(cpuid); |
| 154 | if (id < 0) |
| 155 | return id; |
| 156 | return tegra_pmc_powergate_set(id, true); |
| 157 | } |
| 158 | |
| 159 | int tegra_pmc_cpu_remove_clamping(int cpuid) |
| 160 | { |
| 161 | int id; |
| 162 | |
| 163 | id = tegra_pmc_get_cpu_powerdomain_id(cpuid); |
| 164 | if (id < 0) |
| 165 | return id; |
| 166 | return tegra_pmc_powergate_remove_clamping(id); |
| 167 | } |
| 168 | |
Joseph Lo | 0337c3e | 2013-04-03 19:31:28 +0800 | [diff] [blame] | 169 | #ifdef CONFIG_PM_SLEEP |
Joseph Lo | c8c2e60 | 2013-04-03 19:31:47 +0800 | [diff] [blame] | 170 | static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate) |
Joseph Lo | 0337c3e | 2013-04-03 19:31:28 +0800 | [diff] [blame] | 171 | { |
| 172 | unsigned long long ticks; |
| 173 | unsigned long long pclk; |
Joseph Lo | 0337c3e | 2013-04-03 19:31:28 +0800 | [diff] [blame] | 174 | static unsigned long tegra_last_pclk; |
| 175 | |
Joseph Lo | 0337c3e | 2013-04-03 19:31:28 +0800 | [diff] [blame] | 176 | if (WARN_ON_ONCE(rate <= 0)) |
| 177 | pclk = 100000000; |
| 178 | else |
| 179 | pclk = rate; |
| 180 | |
| 181 | if ((rate != tegra_last_pclk)) { |
| 182 | ticks = (us_on * pclk) + 999999ull; |
| 183 | do_div(ticks, 1000000); |
| 184 | tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER); |
| 185 | |
| 186 | ticks = (us_off * pclk) + 999999ull; |
| 187 | do_div(ticks, 1000000); |
| 188 | tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER); |
| 189 | wmb(); |
| 190 | } |
| 191 | tegra_last_pclk = pclk; |
| 192 | } |
Joseph Lo | c8c2e60 | 2013-04-03 19:31:47 +0800 | [diff] [blame] | 193 | |
| 194 | enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) |
| 195 | { |
| 196 | return pmc_pm_data.suspend_mode; |
| 197 | } |
| 198 | |
| 199 | void tegra_pmc_pm_set(enum tegra_suspend_mode mode) |
| 200 | { |
Joseph Lo | 3f1be81 | 2013-07-03 17:50:41 +0800 | [diff] [blame] | 201 | u32 reg, csr_reg; |
Joseph Lo | c8c2e60 | 2013-04-03 19:31:47 +0800 | [diff] [blame] | 202 | unsigned long rate = 0; |
| 203 | |
| 204 | reg = tegra_pmc_readl(PMC_CTRL); |
| 205 | reg |= TEGRA_POWER_CPU_PWRREQ_OE; |
| 206 | reg &= ~TEGRA_POWER_EFFECT_LP0; |
| 207 | |
Joseph Lo | 3f1be81 | 2013-07-03 17:50:41 +0800 | [diff] [blame] | 208 | switch (tegra_chip_id) { |
| 209 | case TEGRA20: |
| 210 | case TEGRA30: |
| 211 | break; |
| 212 | default: |
| 213 | /* Turn off CRAIL */ |
| 214 | csr_reg = flowctrl_read_cpu_csr(0); |
| 215 | csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK; |
| 216 | csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL; |
| 217 | flowctrl_write_cpu_csr(0, csr_reg); |
| 218 | break; |
| 219 | } |
| 220 | |
Joseph Lo | c8c2e60 | 2013-04-03 19:31:47 +0800 | [diff] [blame] | 221 | switch (mode) { |
| 222 | case TEGRA_SUSPEND_LP2: |
| 223 | rate = clk_get_rate(tegra_pclk); |
| 224 | break; |
| 225 | default: |
| 226 | break; |
| 227 | } |
| 228 | |
| 229 | set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time, |
| 230 | rate); |
| 231 | |
| 232 | tegra_pmc_writel(reg, PMC_CTRL); |
| 233 | } |
| 234 | |
| 235 | void tegra_pmc_suspend_init(void) |
| 236 | { |
| 237 | u32 reg; |
| 238 | |
| 239 | /* Always enable CPU power request */ |
| 240 | reg = tegra_pmc_readl(PMC_CTRL); |
| 241 | reg |= TEGRA_POWER_CPU_PWRREQ_OE; |
| 242 | tegra_pmc_writel(reg, PMC_CTRL); |
Joseph Lo | 444f9a80 | 2013-08-12 17:40:01 +0800 | [diff] [blame^] | 243 | |
| 244 | reg = tegra_pmc_readl(PMC_CTRL); |
| 245 | |
| 246 | if (!pmc_pm_data.sysclkreq_high) |
| 247 | reg |= TEGRA_POWER_SYSCLK_POLARITY; |
| 248 | else |
| 249 | reg &= ~TEGRA_POWER_SYSCLK_POLARITY; |
| 250 | |
| 251 | /* configure the output polarity while the request is tristated */ |
| 252 | tegra_pmc_writel(reg, PMC_CTRL); |
| 253 | |
| 254 | /* now enable the request */ |
| 255 | reg |= TEGRA_POWER_SYSCLK_OE; |
| 256 | tegra_pmc_writel(reg, PMC_CTRL); |
Joseph Lo | c8c2e60 | 2013-04-03 19:31:47 +0800 | [diff] [blame] | 257 | } |
Joseph Lo | 0337c3e | 2013-04-03 19:31:28 +0800 | [diff] [blame] | 258 | #endif |
| 259 | |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 260 | static const struct of_device_id matches[] __initconst = { |
Joseph Lo | 88c4aba | 2013-02-26 16:27:42 +0000 | [diff] [blame] | 261 | { .compatible = "nvidia,tegra114-pmc" }, |
| 262 | { .compatible = "nvidia,tegra30-pmc" }, |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 263 | { .compatible = "nvidia,tegra20-pmc" }, |
| 264 | { } |
| 265 | }; |
Joseph Lo | 291fde3 | 2013-02-28 21:32:10 +0000 | [diff] [blame] | 266 | |
Stephen Warren | 1d54e08 | 2013-06-21 16:39:07 -0600 | [diff] [blame] | 267 | static void __init tegra_pmc_parse_dt(void) |
Joseph Lo | 291fde3 | 2013-02-28 21:32:10 +0000 | [diff] [blame] | 268 | { |
| 269 | struct device_node *np; |
Joseph Lo | 4b51ccb | 2013-04-03 19:31:46 +0800 | [diff] [blame] | 270 | u32 prop; |
| 271 | enum tegra_suspend_mode suspend_mode; |
| 272 | u32 core_good_time[2] = {0, 0}; |
| 273 | u32 lp0_vec[2] = {0, 0}; |
Joseph Lo | 291fde3 | 2013-02-28 21:32:10 +0000 | [diff] [blame] | 274 | |
| 275 | np = of_find_matching_node(NULL, matches); |
| 276 | BUG_ON(!np); |
| 277 | |
| 278 | tegra_pmc_base = of_iomap(np, 0); |
| 279 | |
| 280 | tegra_pmc_invert_interrupt = of_property_read_bool(np, |
| 281 | "nvidia,invert-interrupt"); |
Joseph Lo | 0337c3e | 2013-04-03 19:31:28 +0800 | [diff] [blame] | 282 | tegra_pclk = of_clk_get_by_name(np, "pclk"); |
| 283 | WARN_ON(IS_ERR(tegra_pclk)); |
Joseph Lo | 4b51ccb | 2013-04-03 19:31:46 +0800 | [diff] [blame] | 284 | |
| 285 | /* Grabbing the power management configurations */ |
| 286 | if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) { |
| 287 | suspend_mode = TEGRA_SUSPEND_NONE; |
| 288 | } else { |
| 289 | switch (prop) { |
| 290 | case 0: |
| 291 | suspend_mode = TEGRA_SUSPEND_LP0; |
| 292 | break; |
| 293 | case 1: |
| 294 | suspend_mode = TEGRA_SUSPEND_LP1; |
| 295 | break; |
| 296 | case 2: |
| 297 | suspend_mode = TEGRA_SUSPEND_LP2; |
| 298 | break; |
| 299 | default: |
| 300 | suspend_mode = TEGRA_SUSPEND_NONE; |
| 301 | break; |
| 302 | } |
| 303 | } |
Joseph Lo | c8c2e60 | 2013-04-03 19:31:47 +0800 | [diff] [blame] | 304 | suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode); |
Joseph Lo | 4b51ccb | 2013-04-03 19:31:46 +0800 | [diff] [blame] | 305 | |
| 306 | if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop)) |
| 307 | suspend_mode = TEGRA_SUSPEND_NONE; |
| 308 | pmc_pm_data.cpu_good_time = prop; |
| 309 | |
| 310 | if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop)) |
| 311 | suspend_mode = TEGRA_SUSPEND_NONE; |
| 312 | pmc_pm_data.cpu_off_time = prop; |
| 313 | |
| 314 | if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", |
| 315 | core_good_time, ARRAY_SIZE(core_good_time))) |
| 316 | suspend_mode = TEGRA_SUSPEND_NONE; |
| 317 | pmc_pm_data.core_osc_time = core_good_time[0]; |
| 318 | pmc_pm_data.core_pmu_time = core_good_time[1]; |
| 319 | |
| 320 | if (of_property_read_u32(np, "nvidia,core-pwr-off-time", |
| 321 | &prop)) |
| 322 | suspend_mode = TEGRA_SUSPEND_NONE; |
| 323 | pmc_pm_data.core_off_time = prop; |
| 324 | |
| 325 | pmc_pm_data.corereq_high = of_property_read_bool(np, |
| 326 | "nvidia,core-power-req-active-high"); |
| 327 | |
| 328 | pmc_pm_data.sysclkreq_high = of_property_read_bool(np, |
| 329 | "nvidia,sys-clock-req-active-high"); |
| 330 | |
| 331 | pmc_pm_data.combined_req = of_property_read_bool(np, |
| 332 | "nvidia,combined-power-req"); |
| 333 | |
| 334 | pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np, |
| 335 | "nvidia,cpu-pwr-good-en"); |
| 336 | |
| 337 | if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec, |
| 338 | ARRAY_SIZE(lp0_vec))) |
| 339 | if (suspend_mode == TEGRA_SUSPEND_LP0) |
| 340 | suspend_mode = TEGRA_SUSPEND_LP1; |
| 341 | |
| 342 | pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0]; |
| 343 | pmc_pm_data.lp0_vec_size = lp0_vec[1]; |
| 344 | |
| 345 | pmc_pm_data.suspend_mode = suspend_mode; |
Joseph Lo | 291fde3 | 2013-02-28 21:32:10 +0000 | [diff] [blame] | 346 | } |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 347 | |
| 348 | void __init tegra_pmc_init(void) |
| 349 | { |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 350 | u32 val; |
| 351 | |
Joseph Lo | 291fde3 | 2013-02-28 21:32:10 +0000 | [diff] [blame] | 352 | tegra_pmc_parse_dt(); |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 353 | |
| 354 | val = tegra_pmc_readl(PMC_CTRL); |
Joseph Lo | 291fde3 | 2013-02-28 21:32:10 +0000 | [diff] [blame] | 355 | if (tegra_pmc_invert_interrupt) |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 356 | val |= PMC_CTRL_INTR_LOW; |
| 357 | else |
| 358 | val &= ~PMC_CTRL_INTR_LOW; |
| 359 | tegra_pmc_writel(val, PMC_CTRL); |
| 360 | } |