Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 1 | /* |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 2 | * GPIOs on MPC512x/8349/8572/8610 and compatible |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/spinlock.h> |
| 14 | #include <linux/io.h> |
| 15 | #include <linux/of.h> |
| 16 | #include <linux/of_gpio.h> |
Rob Herring | 5af5073 | 2013-09-17 14:28:33 -0500 | [diff] [blame] | 17 | #include <linux/of_irq.h> |
Ricardo Ribalda Delgado | 98686d9a5 | 2015-01-18 12:39:32 +0100 | [diff] [blame] | 18 | #include <linux/of_platform.h> |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 19 | #include <linux/gpio.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 20 | #include <linux/slab.h> |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 21 | #include <linux/irq.h> |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 22 | |
| 23 | #define MPC8XXX_GPIO_PINS 32 |
| 24 | |
| 25 | #define GPIO_DIR 0x00 |
| 26 | #define GPIO_ODR 0x04 |
| 27 | #define GPIO_DAT 0x08 |
| 28 | #define GPIO_IER 0x0c |
| 29 | #define GPIO_IMR 0x10 |
| 30 | #define GPIO_ICR 0x14 |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 31 | #define GPIO_ICR2 0x18 |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 32 | |
| 33 | struct mpc8xxx_gpio_chip { |
| 34 | struct of_mm_gpio_chip mm_gc; |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 35 | raw_spinlock_t lock; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 36 | |
| 37 | /* |
| 38 | * shadowed data register to be able to clear/set output pins in |
| 39 | * open drain mode safely |
| 40 | */ |
| 41 | u32 data; |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 42 | struct irq_domain *irq; |
Ricardo Ribalda Delgado | 257e107 | 2015-01-18 12:39:33 +0100 | [diff] [blame] | 43 | unsigned int irqn; |
Uwe Kleine-König | 01a04dd | 2012-05-21 21:57:39 +0200 | [diff] [blame] | 44 | const void *of_dev_id_data; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 45 | }; |
| 46 | |
| 47 | static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) |
| 48 | { |
| 49 | return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); |
| 50 | } |
| 51 | |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 52 | static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm) |
| 53 | { |
Guenter Roeck | 7817998 | 2016-01-07 08:25:24 -0800 | [diff] [blame] | 54 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = |
| 55 | container_of(mm, struct mpc8xxx_gpio_chip, mm_gc); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 56 | |
| 57 | mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT); |
| 58 | } |
| 59 | |
Felix Radensky | c1a676d | 2009-08-12 08:57:39 +0300 | [diff] [blame] | 60 | /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs |
| 61 | * defined as output cannot be determined by reading GPDAT register, |
| 62 | * so we use shadow data register instead. The status of input pins |
| 63 | * is determined by reading GPDAT register. |
| 64 | */ |
| 65 | static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
| 66 | { |
| 67 | u32 val; |
| 68 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
Linus Walleij | 709d71a | 2015-12-07 10:34:28 +0100 | [diff] [blame] | 69 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); |
Liu Gang | 1aeef30 | 2013-11-22 16:12:40 +0800 | [diff] [blame] | 70 | u32 out_mask, out_shadow; |
Felix Radensky | c1a676d | 2009-08-12 08:57:39 +0300 | [diff] [blame] | 71 | |
Liu Gang | 1aeef30 | 2013-11-22 16:12:40 +0800 | [diff] [blame] | 72 | out_mask = in_be32(mm->regs + GPIO_DIR); |
Felix Radensky | c1a676d | 2009-08-12 08:57:39 +0300 | [diff] [blame] | 73 | |
Liu Gang | 1aeef30 | 2013-11-22 16:12:40 +0800 | [diff] [blame] | 74 | val = in_be32(mm->regs + GPIO_DAT) & ~out_mask; |
| 75 | out_shadow = mpc8xxx_gc->data & out_mask; |
| 76 | |
Linus Walleij | c759174 | 2015-12-21 11:20:56 +0100 | [diff] [blame] | 77 | return !!((val | out_shadow) & mpc8xxx_gpio2mask(gpio)); |
Felix Radensky | c1a676d | 2009-08-12 08:57:39 +0300 | [diff] [blame] | 78 | } |
| 79 | |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 80 | static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
| 81 | { |
| 82 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 83 | |
| 84 | return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); |
| 85 | } |
| 86 | |
| 87 | static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
| 88 | { |
| 89 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
Linus Walleij | 709d71a | 2015-12-07 10:34:28 +0100 | [diff] [blame] | 90 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 91 | unsigned long flags; |
| 92 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 93 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 94 | |
| 95 | if (val) |
| 96 | mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio); |
| 97 | else |
| 98 | mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); |
| 99 | |
| 100 | out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); |
| 101 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 102 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 103 | } |
| 104 | |
Rojhalat Ibrahim | e5db3b3 | 2014-11-04 17:12:09 +0100 | [diff] [blame] | 105 | static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc, |
| 106 | unsigned long *mask, unsigned long *bits) |
| 107 | { |
| 108 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
Linus Walleij | 709d71a | 2015-12-07 10:34:28 +0100 | [diff] [blame] | 109 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); |
Rojhalat Ibrahim | e5db3b3 | 2014-11-04 17:12:09 +0100 | [diff] [blame] | 110 | unsigned long flags; |
| 111 | int i; |
| 112 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 113 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
Rojhalat Ibrahim | e5db3b3 | 2014-11-04 17:12:09 +0100 | [diff] [blame] | 114 | |
| 115 | for (i = 0; i < gc->ngpio; i++) { |
| 116 | if (*mask == 0) |
| 117 | break; |
| 118 | if (__test_and_clear_bit(i, mask)) { |
| 119 | if (test_bit(i, bits)) |
| 120 | mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i); |
| 121 | else |
| 122 | mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i); |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); |
| 127 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 128 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
Rojhalat Ibrahim | e5db3b3 | 2014-11-04 17:12:09 +0100 | [diff] [blame] | 129 | } |
| 130 | |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 131 | static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
| 132 | { |
| 133 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
Linus Walleij | 709d71a | 2015-12-07 10:34:28 +0100 | [diff] [blame] | 134 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 135 | unsigned long flags; |
| 136 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 137 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 138 | |
| 139 | clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); |
| 140 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 141 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 142 | |
| 143 | return 0; |
| 144 | } |
| 145 | |
| 146 | static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
| 147 | { |
| 148 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
Linus Walleij | 709d71a | 2015-12-07 10:34:28 +0100 | [diff] [blame] | 149 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 150 | unsigned long flags; |
| 151 | |
| 152 | mpc8xxx_gpio_set(gc, gpio, val); |
| 153 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 154 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 155 | |
| 156 | setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); |
| 157 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 158 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 159 | |
| 160 | return 0; |
| 161 | } |
| 162 | |
Wolfram Sang | 28538df | 2011-12-13 10:12:48 +0100 | [diff] [blame] | 163 | static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
| 164 | { |
| 165 | /* GPIO 28..31 are input only on MPC5121 */ |
| 166 | if (gpio >= 28) |
| 167 | return -EINVAL; |
| 168 | |
| 169 | return mpc8xxx_gpio_dir_out(gc, gpio, val); |
| 170 | } |
| 171 | |
Uwe Kleine-König | 0ba69e0 | 2015-07-16 21:08:23 +0200 | [diff] [blame] | 172 | static int mpc5125_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
| 173 | { |
| 174 | /* GPIO 0..3 are input only on MPC5125 */ |
| 175 | if (gpio <= 3) |
| 176 | return -EINVAL; |
| 177 | |
| 178 | return mpc8xxx_gpio_dir_out(gc, gpio, val); |
| 179 | } |
| 180 | |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 181 | static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
| 182 | { |
Linus Walleij | 709d71a | 2015-12-07 10:34:28 +0100 | [diff] [blame] | 183 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 184 | |
| 185 | if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) |
| 186 | return irq_create_mapping(mpc8xxx_gc->irq, offset); |
| 187 | else |
| 188 | return -ENXIO; |
| 189 | } |
| 190 | |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 191 | static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc) |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 192 | { |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 193 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); |
Felix Radensky | cfadd83 | 2011-10-11 10:24:21 +0200 | [diff] [blame] | 194 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 195 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 196 | unsigned int mask; |
| 197 | |
| 198 | mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); |
| 199 | if (mask) |
| 200 | generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, |
| 201 | 32 - ffs(mask))); |
Thomas Gleixner | d6de85e | 2012-05-03 12:22:06 +0200 | [diff] [blame] | 202 | if (chip->irq_eoi) |
| 203 | chip->irq_eoi(&desc->irq_data); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 204 | } |
| 205 | |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 206 | static void mpc8xxx_irq_unmask(struct irq_data *d) |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 207 | { |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 208 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 209 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 210 | unsigned long flags; |
| 211 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 212 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 213 | |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 214 | setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 215 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 216 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 217 | } |
| 218 | |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 219 | static void mpc8xxx_irq_mask(struct irq_data *d) |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 220 | { |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 221 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 222 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 223 | unsigned long flags; |
| 224 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 225 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 226 | |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 227 | clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 228 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 229 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 230 | } |
| 231 | |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 232 | static void mpc8xxx_irq_ack(struct irq_data *d) |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 233 | { |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 234 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 235 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 236 | |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 237 | out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 238 | } |
| 239 | |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 240 | static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 241 | { |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 242 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 243 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 244 | unsigned long flags; |
| 245 | |
| 246 | switch (flow_type) { |
| 247 | case IRQ_TYPE_EDGE_FALLING: |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 248 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 249 | setbits32(mm->regs + GPIO_ICR, |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 250 | mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 251 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 252 | break; |
| 253 | |
| 254 | case IRQ_TYPE_EDGE_BOTH: |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 255 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 256 | clrbits32(mm->regs + GPIO_ICR, |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 257 | mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 258 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 259 | break; |
| 260 | |
| 261 | default: |
| 262 | return -EINVAL; |
| 263 | } |
| 264 | |
| 265 | return 0; |
| 266 | } |
| 267 | |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 268 | static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 269 | { |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 270 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 271 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 272 | unsigned long gpio = irqd_to_hwirq(d); |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 273 | void __iomem *reg; |
| 274 | unsigned int shift; |
| 275 | unsigned long flags; |
| 276 | |
| 277 | if (gpio < 16) { |
| 278 | reg = mm->regs + GPIO_ICR; |
| 279 | shift = (15 - gpio) * 2; |
| 280 | } else { |
| 281 | reg = mm->regs + GPIO_ICR2; |
| 282 | shift = (15 - (gpio % 16)) * 2; |
| 283 | } |
| 284 | |
| 285 | switch (flow_type) { |
| 286 | case IRQ_TYPE_EDGE_FALLING: |
| 287 | case IRQ_TYPE_LEVEL_LOW: |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 288 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 289 | clrsetbits_be32(reg, 3 << shift, 2 << shift); |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 290 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 291 | break; |
| 292 | |
| 293 | case IRQ_TYPE_EDGE_RISING: |
| 294 | case IRQ_TYPE_LEVEL_HIGH: |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 295 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 296 | clrsetbits_be32(reg, 3 << shift, 1 << shift); |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 297 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 298 | break; |
| 299 | |
| 300 | case IRQ_TYPE_EDGE_BOTH: |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 301 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 302 | clrbits32(reg, 3 << shift); |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 303 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 304 | break; |
| 305 | |
| 306 | default: |
| 307 | return -EINVAL; |
| 308 | } |
| 309 | |
| 310 | return 0; |
| 311 | } |
| 312 | |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 313 | static struct irq_chip mpc8xxx_irq_chip = { |
| 314 | .name = "mpc8xxx-gpio", |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 315 | .irq_unmask = mpc8xxx_irq_unmask, |
| 316 | .irq_mask = mpc8xxx_irq_mask, |
| 317 | .irq_ack = mpc8xxx_irq_ack, |
Uwe Kleine-König | 82e39b0 | 2015-07-16 21:08:22 +0200 | [diff] [blame] | 318 | /* this might get overwritten in mpc8xxx_probe() */ |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 319 | .irq_set_type = mpc8xxx_irq_set_type, |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 320 | }; |
| 321 | |
Linus Walleij | 5ba17ae | 2013-10-11 19:37:30 +0200 | [diff] [blame] | 322 | static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq, |
| 323 | irq_hw_number_t hwirq) |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 324 | { |
Linus Walleij | 5ba17ae | 2013-10-11 19:37:30 +0200 | [diff] [blame] | 325 | irq_set_chip_data(irq, h->host_data); |
| 326 | irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 327 | |
| 328 | return 0; |
| 329 | } |
| 330 | |
Krzysztof Kozlowski | 0b354dc | 2015-04-27 21:54:07 +0900 | [diff] [blame] | 331 | static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = { |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 332 | .map = mpc8xxx_gpio_irq_map, |
Grant Likely | ff8c3ab | 2012-01-24 17:09:13 -0700 | [diff] [blame] | 333 | .xlate = irq_domain_xlate_twocell, |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 334 | }; |
| 335 | |
Uwe Kleine-König | 82e39b0 | 2015-07-16 21:08:22 +0200 | [diff] [blame] | 336 | struct mpc8xxx_gpio_devtype { |
| 337 | int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int); |
| 338 | int (*gpio_get)(struct gpio_chip *, unsigned int); |
| 339 | int (*irq_set_type)(struct irq_data *, unsigned int); |
| 340 | }; |
| 341 | |
| 342 | static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = { |
| 343 | .gpio_dir_out = mpc5121_gpio_dir_out, |
| 344 | .irq_set_type = mpc512x_irq_set_type, |
| 345 | }; |
| 346 | |
Uwe Kleine-König | 0ba69e0 | 2015-07-16 21:08:23 +0200 | [diff] [blame] | 347 | static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = { |
| 348 | .gpio_dir_out = mpc5125_gpio_dir_out, |
| 349 | .irq_set_type = mpc512x_irq_set_type, |
| 350 | }; |
| 351 | |
Uwe Kleine-König | 82e39b0 | 2015-07-16 21:08:22 +0200 | [diff] [blame] | 352 | static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = { |
| 353 | .gpio_get = mpc8572_gpio_get, |
| 354 | }; |
| 355 | |
| 356 | static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = { |
| 357 | .gpio_dir_out = mpc8xxx_gpio_dir_out, |
| 358 | .gpio_get = mpc8xxx_gpio_get, |
| 359 | .irq_set_type = mpc8xxx_irq_set_type, |
| 360 | }; |
| 361 | |
Uwe Kleine-König | 4183afe | 2015-07-16 21:08:21 +0200 | [diff] [blame] | 362 | static const struct of_device_id mpc8xxx_gpio_ids[] = { |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 363 | { .compatible = "fsl,mpc8349-gpio", }, |
Uwe Kleine-König | 82e39b0 | 2015-07-16 21:08:22 +0200 | [diff] [blame] | 364 | { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, }, |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 365 | { .compatible = "fsl,mpc8610-gpio", }, |
Uwe Kleine-König | 82e39b0 | 2015-07-16 21:08:22 +0200 | [diff] [blame] | 366 | { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, }, |
Uwe Kleine-König | 0ba69e0 | 2015-07-16 21:08:23 +0200 | [diff] [blame] | 367 | { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, }, |
Kumar Gala | 15a5148 | 2011-10-22 16:20:42 -0500 | [diff] [blame] | 368 | { .compatible = "fsl,pq3-gpio", }, |
Anatolij Gustschin | d1dcfbb | 2011-01-08 16:51:16 +0100 | [diff] [blame] | 369 | { .compatible = "fsl,qoriq-gpio", }, |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 370 | {} |
| 371 | }; |
| 372 | |
Ricardo Ribalda Delgado | 98686d9a5 | 2015-01-18 12:39:32 +0100 | [diff] [blame] | 373 | static int mpc8xxx_probe(struct platform_device *pdev) |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 374 | { |
Ricardo Ribalda Delgado | 98686d9a5 | 2015-01-18 12:39:32 +0100 | [diff] [blame] | 375 | struct device_node *np = pdev->dev.of_node; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 376 | struct mpc8xxx_gpio_chip *mpc8xxx_gc; |
| 377 | struct of_mm_gpio_chip *mm_gc; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 378 | struct gpio_chip *gc; |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 379 | const struct of_device_id *id; |
Uwe Kleine-König | 82e39b0 | 2015-07-16 21:08:22 +0200 | [diff] [blame] | 380 | const struct mpc8xxx_gpio_devtype *devtype = |
| 381 | of_device_get_match_data(&pdev->dev); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 382 | int ret; |
| 383 | |
Ricardo Ribalda Delgado | 98686d9a5 | 2015-01-18 12:39:32 +0100 | [diff] [blame] | 384 | mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); |
| 385 | if (!mpc8xxx_gc) |
| 386 | return -ENOMEM; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 387 | |
Ricardo Ribalda Delgado | 257e107 | 2015-01-18 12:39:33 +0100 | [diff] [blame] | 388 | platform_set_drvdata(pdev, mpc8xxx_gc); |
| 389 | |
Alexander Stein | 5059361 | 2015-07-21 15:54:30 +0200 | [diff] [blame] | 390 | raw_spin_lock_init(&mpc8xxx_gc->lock); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 391 | |
| 392 | mm_gc = &mpc8xxx_gc->mm_gc; |
Anton Vorontsov | a19e3da | 2010-06-08 07:48:16 -0600 | [diff] [blame] | 393 | gc = &mm_gc->gc; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 394 | |
| 395 | mm_gc->save_regs = mpc8xxx_gpio_save_regs; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 396 | gc->ngpio = MPC8XXX_GPIO_PINS; |
| 397 | gc->direction_input = mpc8xxx_gpio_dir_in; |
Uwe Kleine-König | 82e39b0 | 2015-07-16 21:08:22 +0200 | [diff] [blame] | 398 | |
| 399 | if (!devtype) |
| 400 | devtype = &mpc8xxx_gpio_devtype_default; |
| 401 | |
| 402 | /* |
| 403 | * It's assumed that only a single type of gpio controller is available |
| 404 | * on the current machine, so overwriting global data is fine. |
| 405 | */ |
| 406 | mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; |
| 407 | |
| 408 | gc->direction_output = devtype->gpio_dir_out ?: mpc8xxx_gpio_dir_out; |
| 409 | gc->get = devtype->gpio_get ?: mpc8xxx_gpio_get; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 410 | gc->set = mpc8xxx_gpio_set; |
Rojhalat Ibrahim | e5db3b3 | 2014-11-04 17:12:09 +0100 | [diff] [blame] | 411 | gc->set_multiple = mpc8xxx_gpio_set_multiple; |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 412 | gc->to_irq = mpc8xxx_gpio_to_irq; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 413 | |
Linus Walleij | 709d71a | 2015-12-07 10:34:28 +0100 | [diff] [blame] | 414 | ret = of_mm_gpiochip_add_data(np, mm_gc, mpc8xxx_gc); |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 415 | if (ret) |
Ricardo Ribalda Delgado | 98686d9a5 | 2015-01-18 12:39:32 +0100 | [diff] [blame] | 416 | return ret; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 417 | |
Ricardo Ribalda Delgado | 257e107 | 2015-01-18 12:39:33 +0100 | [diff] [blame] | 418 | mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0); |
| 419 | if (mpc8xxx_gc->irqn == NO_IRQ) |
Ricardo Ribalda Delgado | 98686d9a5 | 2015-01-18 12:39:32 +0100 | [diff] [blame] | 420 | return 0; |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 421 | |
Grant Likely | a8db8cf | 2012-02-14 14:06:54 -0700 | [diff] [blame] | 422 | mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, |
| 423 | &mpc8xxx_gpio_irq_ops, mpc8xxx_gc); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 424 | if (!mpc8xxx_gc->irq) |
Ricardo Ribalda Delgado | 98686d9a5 | 2015-01-18 12:39:32 +0100 | [diff] [blame] | 425 | return 0; |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 426 | |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 427 | id = of_match_node(mpc8xxx_gpio_ids, np); |
| 428 | if (id) |
| 429 | mpc8xxx_gc->of_dev_id_data = id->data; |
| 430 | |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 431 | /* ack and mask all irqs */ |
| 432 | out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); |
| 433 | out_be32(mm_gc->regs + GPIO_IMR, 0); |
| 434 | |
Thomas Gleixner | 0537981 | 2015-06-21 21:10:46 +0200 | [diff] [blame] | 435 | irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, |
| 436 | mpc8xxx_gpio_irq_cascade, mpc8xxx_gc); |
Ricardo Ribalda Delgado | 257e107 | 2015-01-18 12:39:33 +0100 | [diff] [blame] | 437 | |
| 438 | return 0; |
| 439 | } |
| 440 | |
| 441 | static int mpc8xxx_remove(struct platform_device *pdev) |
| 442 | { |
| 443 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev); |
| 444 | |
| 445 | if (mpc8xxx_gc->irq) { |
Thomas Gleixner | 0537981 | 2015-06-21 21:10:46 +0200 | [diff] [blame] | 446 | irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); |
Ricardo Ribalda Delgado | 257e107 | 2015-01-18 12:39:33 +0100 | [diff] [blame] | 447 | irq_domain_remove(mpc8xxx_gc->irq); |
| 448 | } |
| 449 | |
| 450 | of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 451 | |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 452 | return 0; |
| 453 | } |
Ricardo Ribalda Delgado | 98686d9a5 | 2015-01-18 12:39:32 +0100 | [diff] [blame] | 454 | |
| 455 | static struct platform_driver mpc8xxx_plat_driver = { |
| 456 | .probe = mpc8xxx_probe, |
Ricardo Ribalda Delgado | 257e107 | 2015-01-18 12:39:33 +0100 | [diff] [blame] | 457 | .remove = mpc8xxx_remove, |
Ricardo Ribalda Delgado | 98686d9a5 | 2015-01-18 12:39:32 +0100 | [diff] [blame] | 458 | .driver = { |
| 459 | .name = "gpio-mpc8xxx", |
| 460 | .of_match_table = mpc8xxx_gpio_ids, |
| 461 | }, |
| 462 | }; |
| 463 | |
| 464 | static int __init mpc8xxx_init(void) |
| 465 | { |
| 466 | return platform_driver_register(&mpc8xxx_plat_driver); |
| 467 | } |
| 468 | |
| 469 | arch_initcall(mpc8xxx_init); |