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gerrit-public.fairphone.software / kernel / msm-4.9 / 44659021d2b3cc90e6e23a16f0d4c2ca624fb9f6 / . / arch / arm / boot / dts / imx6qdl-sabreauto.dtsi
blob: 33e9bff9b076bece76fb45d0f34051d75f6b0873 [file] [log] [blame]
Shawn Guo082d33d2013-04-02 13:15:16 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/ {
14 memory {
15 reg = <0x10000000 0x80000000>;
16 };
Nicolin Chen1169cf12013-12-16 18:37:48 +0800[diff] [blame]17
18 sound-spdif {
19 compatible = "fsl,imx-audio-spdif",
20 "fsl,imx-sabreauto-spdif";
21 model = "imx-spdif";
22 spdif-controller = <&spdif>;
23 spdif-in;
24 };
Fabio Estevamc0f16622014-01-14 20:51:27 -0200[diff] [blame]25
26 backlight {
27 compatible = "pwm-backlight";
28 pwms = <&pwm3 0 5000000>;
29 brightness-levels = <0 4 8 16 32 64 128 255>;
30 default-brightness-level = <7>;
31 status = "okay";
32 };
Shawn Guo082d33d2013-04-02 13:15:16 +0800[diff] [blame]33};
34
Huang Shijiefaacc292013-05-09 11:29:03 +0800[diff] [blame]35&ecspi1 {
36 fsl,spi-num-chipselects = <1>;
37 cs-gpios = <&gpio3 19 0>;
38 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800[diff] [blame]39 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
Huang Shijiefaacc292013-05-09 11:29:03 +0800[diff] [blame]40 status = "disabled"; /* pin conflict with WEIM NOR */
41
42 flash: m25p80@0 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 compatible = "st,m25p32";
46 spi-max-frequency = <20000000>;
47 reg = <0>;
48 };
49};
50
Shawn Guo082d33d2013-04-02 13:15:16 +0800[diff] [blame]51&fec {
52 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800[diff] [blame]53 pinctrl-0 = <&pinctrl_enet>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800[diff] [blame]54 phy-mode = "rgmii";
Troy Kiskybc20a5d2013-12-20 11:47:12 -0700[diff] [blame]55 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
56 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800[diff] [blame]57 status = "okay";
58};
59
Huang Shijie82726932013-05-07 15:39:20 +0800[diff] [blame]60&gpmi {
61 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800[diff] [blame]62 pinctrl-0 = <&pinctrl_gpmi_nand>;
Huang Shijie82726932013-05-07 15:39:20 +0800[diff] [blame]63 status = "okay";
64};
65
Fabio Estevam44659022014-02-06 09:05:19 -0200[diff] [blame^]66&i2c2 {
67 clock-frequency = <100000>;
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_i2c2>;
70 status = "okay";
71
72 pmic: pfuze100@08 {
73 compatible = "fsl,pfuze100";
74 reg = <0x08>;
75
76 regulators {
77 sw1a_reg: sw1ab {
78 regulator-min-microvolt = <300000>;
79 regulator-max-microvolt = <1875000>;
80 regulator-boot-on;
81 regulator-always-on;
82 regulator-ramp-delay = <6250>;
83 };
84
85 sw1c_reg: sw1c {
86 regulator-min-microvolt = <300000>;
87 regulator-max-microvolt = <1875000>;
88 regulator-boot-on;
89 regulator-always-on;
90 regulator-ramp-delay = <6250>;
91 };
92
93 sw2_reg: sw2 {
94 regulator-min-microvolt = <800000>;
95 regulator-max-microvolt = <3300000>;
96 regulator-boot-on;
97 regulator-always-on;
98 };
99
100 sw3a_reg: sw3a {
101 regulator-min-microvolt = <400000>;
102 regulator-max-microvolt = <1975000>;
103 regulator-boot-on;
104 regulator-always-on;
105 };
106
107 sw3b_reg: sw3b {
108 regulator-min-microvolt = <400000>;
109 regulator-max-microvolt = <1975000>;
110 regulator-boot-on;
111 regulator-always-on;
112 };
113
114 sw4_reg: sw4 {
115 regulator-min-microvolt = <800000>;
116 regulator-max-microvolt = <3300000>;
117 };
118
119 swbst_reg: swbst {
120 regulator-min-microvolt = <5000000>;
121 regulator-max-microvolt = <5150000>;
122 };
123
124 snvs_reg: vsnvs {
125 regulator-min-microvolt = <1000000>;
126 regulator-max-microvolt = <3000000>;
127 regulator-boot-on;
128 regulator-always-on;
129 };
130
131 vref_reg: vrefddr {
132 regulator-boot-on;
133 regulator-always-on;
134 };
135
136 vgen1_reg: vgen1 {
137 regulator-min-microvolt = <800000>;
138 regulator-max-microvolt = <1550000>;
139 };
140
141 vgen2_reg: vgen2 {
142 regulator-min-microvolt = <800000>;
143 regulator-max-microvolt = <1550000>;
144 };
145
146 vgen3_reg: vgen3 {
147 regulator-min-microvolt = <1800000>;
148 regulator-max-microvolt = <3300000>;
149 };
150
151 vgen4_reg: vgen4 {
152 regulator-min-microvolt = <1800000>;
153 regulator-max-microvolt = <3300000>;
154 regulator-always-on;
155 };
156
157 vgen5_reg: vgen5 {
158 regulator-min-microvolt = <1800000>;
159 regulator-max-microvolt = <3300000>;
160 regulator-always-on;
161 };
162
163 vgen6_reg: vgen6 {
164 regulator-min-microvolt = <1800000>;
165 regulator-max-microvolt = <3300000>;
166 regulator-always-on;
167 };
168 };
169 };
170};
171
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]172&iomuxc {
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_hog>;
175
Shawn Guo817c27a2013-10-23 15:36:09 +0800[diff] [blame]176 imx6qdl-sabreauto {
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]177 pinctrl_hog: hoggrp {
178 fsl,pins = <
179 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
180 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
Dong Aisheng93e2ca02013-09-13 19:11:38 +0800[diff] [blame]181 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]182 >;
183 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]184
Shawn Guo817c27a2013-10-23 15:36:09 +0800[diff] [blame]185 pinctrl_ecspi1: ecspi1grp {
186 fsl,pins = <
187 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
188 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
189 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
190 >;
191 };
192
193 pinctrl_ecspi1_cs: ecspi1cs {
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]194 fsl,pins = <
195 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
196 >;
197 };
Shawn Guo817c27a2013-10-23 15:36:09 +0800[diff] [blame]198
199 pinctrl_enet: enetgrp {
200 fsl,pins = <
201 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
202 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
203 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
204 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
205 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
206 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
207 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
208 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
209 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
210 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
211 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
212 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
213 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
214 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
215 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
Troy Kiskybc20a5d2013-12-20 11:47:12 -0700[diff] [blame]216 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
Shawn Guo817c27a2013-10-23 15:36:09 +0800[diff] [blame]217 >;
218 };
219
220 pinctrl_gpmi_nand: gpminandgrp {
221 fsl,pins = <
222 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
223 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
224 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
225 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
226 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
227 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
228 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
229 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
230 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
231 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
232 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
233 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
234 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
235 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
236 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
237 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
238 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
239 >;
240 };
241
Fabio Estevam44659022014-02-06 09:05:19 -0200[diff] [blame^]242 pinctrl_i2c2: i2c2grp {
243 fsl,pins = <
244 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
245 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
246 >;
247 };
248
Fabio Estevamc0f16622014-01-14 20:51:27 -0200[diff] [blame]249 pinctrl_pwm3: pwm1grp {
250 fsl,pins = <
251 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
252 >;
253 };
254
Nicolin Chen1169cf12013-12-16 18:37:48 +0800[diff] [blame]255 pinctrl_spdif: spdifgrp {
256 fsl,pins = <
257 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
258 >;
259 };
260
Shawn Guo817c27a2013-10-23 15:36:09 +0800[diff] [blame]261 pinctrl_uart4: uart4grp {
262 fsl,pins = <
263 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
264 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
265 >;
266 };
267
268 pinctrl_usdhc3: usdhc3grp {
269 fsl,pins = <
270 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
271 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
272 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
273 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
274 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
275 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
276 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
277 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
278 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
279 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
280 >;
281 };
282
283 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
284 fsl,pins = <
285 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
286 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
287 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
288 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
289 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
290 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
291 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
292 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
293 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
294 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
295 >;
296 };
297
298 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
299 fsl,pins = <
300 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
301 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
302 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
303 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
304 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
305 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
306 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
307 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
308 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
309 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
310 >;
311 };
312
313 pinctrl_weim_cs0: weimcs0grp {
314 fsl,pins = <
315 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
316 >;
317 };
318
319 pinctrl_weim_nor: weimnorgrp {
320 fsl,pins = <
321 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
322 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
323 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
324 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
325 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
326 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
327 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
328 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
329 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
330 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
331 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
332 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
333 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
334 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
335 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
336 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
337 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
338 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
339 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
340 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
341 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
342 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
343 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
344 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
345 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
346 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
347 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
348 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
349 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
350 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
351 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
352 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
353 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
354 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
355 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
356 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
357 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
358 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
359 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
360 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
361 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
362 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
363 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
364 >;
365 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]366 };
367};
368
Fabio Estevamc0f16622014-01-14 20:51:27 -0200[diff] [blame]369&ldb {
370 status = "okay";
371
372 lvds-channel@0 {
373 fsl,data-mapping = "spwg";
374 fsl,data-width = <18>;
375 status = "okay";
376
377 display-timings {
378 native-mode = <&timing0>;
379 timing0: hsd100pxn1 {
380 clock-frequency = <65000000>;
381 hactive = <1024>;
382 vactive = <768>;
383 hback-porch = <220>;
384 hfront-porch = <40>;
385 vback-porch = <21>;
386 vfront-porch = <7>;
387 hsync-len = <60>;
388 vsync-len = <10>;
389 };
390 };
391 };
392};
393
394&pwm3 {
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_pwm3>;
397 status = "okay";
398};
399
Nicolin Chen1169cf12013-12-16 18:37:48 +0800[diff] [blame]400&spdif {
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_spdif>;
403 status = "okay";
404};
405
Shawn Guo082d33d2013-04-02 13:15:16 +0800[diff] [blame]406&uart4 {
407 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800[diff] [blame]408 pinctrl-0 = <&pinctrl_uart4>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800[diff] [blame]409 status = "okay";
410};
411
412&usdhc3 {
Dong Aisheng93e2ca02013-09-13 19:11:38 +0800[diff] [blame]413 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guo817c27a2013-10-23 15:36:09 +0800[diff] [blame]414 pinctrl-0 = <&pinctrl_usdhc3>;
415 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
416 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800[diff] [blame]417 cd-gpios = <&gpio6 15 0>;
418 wp-gpios = <&gpio1 13 0>;
419 status = "okay";
420};
Huang Shijie50fe0e92013-05-28 14:20:12 +0800[diff] [blame]421
422&weim {
423 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800[diff] [blame]424 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
Huang Shijie50fe0e92013-05-28 14:20:12 +0800[diff] [blame]425 #address-cells = <2>;
426 #size-cells = <1>;
427 ranges = <0 0 0x08000000 0x08000000>;
428 status = "disabled"; /* pin conflict with SPI NOR */
429
430 nor@0,0 {
431 compatible = "cfi-flash";
432 reg = <0 0 0x02000000>;
433 #address-cells = <1>;
434 #size-cells = <1>;
435 bank-width = <2>;
436 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
437 0x0000c000 0x1404a38e 0x00000000>;
438 };
439};