Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* sun4c_irq.c |
| 2 | * arch/sparc/kernel/sun4c_irq.c: |
| 3 | * |
| 4 | * djhr: Hacked out of irq.c into a CPU dependent version. |
| 5 | * |
| 6 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) |
| 7 | * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx) |
| 8 | * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com) |
| 9 | * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk) |
| 10 | */ |
| 11 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | #include <linux/errno.h> |
| 13 | #include <linux/linkage.h> |
| 14 | #include <linux/kernel_stat.h> |
| 15 | #include <linux/signal.h> |
| 16 | #include <linux/sched.h> |
| 17 | #include <linux/ptrace.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/slab.h> |
| 20 | #include <linux/init.h> |
David S. Miller | 454eeb2 | 2008-08-27 04:05:35 -0700 | [diff] [blame^] | 21 | #include <linux/of.h> |
| 22 | #include <linux/of_device.h> |
Al Viro | 32231a6 | 2007-07-21 19:18:57 -0700 | [diff] [blame] | 23 | #include "irq.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | |
| 25 | #include <asm/ptrace.h> |
| 26 | #include <asm/processor.h> |
| 27 | #include <asm/system.h> |
| 28 | #include <asm/psr.h> |
| 29 | #include <asm/vaddrs.h> |
| 30 | #include <asm/timer.h> |
| 31 | #include <asm/openprom.h> |
| 32 | #include <asm/oplib.h> |
| 33 | #include <asm/traps.h> |
| 34 | #include <asm/irq.h> |
| 35 | #include <asm/io.h> |
| 36 | #include <asm/sun4paddr.h> |
| 37 | #include <asm/idprom.h> |
| 38 | #include <asm/machines.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
| 40 | #if 0 |
| 41 | static struct resource sun4c_timer_eb = { "sun4c_timer" }; |
| 42 | static struct resource sun4c_intr_eb = { "sun4c_intr" }; |
| 43 | #endif |
| 44 | |
Al Viro | 32231a6 | 2007-07-21 19:18:57 -0700 | [diff] [blame] | 45 | /* |
| 46 | * Bit field defines for the interrupt registers on various |
| 47 | * Sparc machines. |
| 48 | */ |
| 49 | |
| 50 | /* The sun4c interrupt register. */ |
| 51 | #define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */ |
| 52 | #define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */ |
| 53 | #define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */ |
| 54 | #define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */ |
| 55 | #define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */ |
| 56 | #define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */ |
| 57 | #define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */ |
| 58 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | /* Pointer to the interrupt enable byte |
| 60 | * |
| 61 | * Dave Redman (djhr@tadpole.co.uk) |
| 62 | * What you may not be aware of is that entry.S requires this variable. |
| 63 | * |
| 64 | * --- linux_trap_nmi_sun4c -- |
| 65 | * |
| 66 | * so don't go making it static, like I tried. sigh. |
| 67 | */ |
| 68 | unsigned char *interrupt_enable = NULL; |
| 69 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | static void sun4c_disable_irq(unsigned int irq_nr) |
| 71 | { |
| 72 | unsigned long flags; |
| 73 | unsigned char current_mask, new_mask; |
| 74 | |
| 75 | local_irq_save(flags); |
| 76 | irq_nr &= (NR_IRQS - 1); |
| 77 | current_mask = *interrupt_enable; |
| 78 | switch(irq_nr) { |
| 79 | case 1: |
| 80 | new_mask = ((current_mask) & (~(SUN4C_INT_E1))); |
| 81 | break; |
| 82 | case 8: |
| 83 | new_mask = ((current_mask) & (~(SUN4C_INT_E8))); |
| 84 | break; |
| 85 | case 10: |
| 86 | new_mask = ((current_mask) & (~(SUN4C_INT_E10))); |
| 87 | break; |
| 88 | case 14: |
| 89 | new_mask = ((current_mask) & (~(SUN4C_INT_E14))); |
| 90 | break; |
| 91 | default: |
| 92 | local_irq_restore(flags); |
| 93 | return; |
| 94 | } |
| 95 | *interrupt_enable = new_mask; |
| 96 | local_irq_restore(flags); |
| 97 | } |
| 98 | |
| 99 | static void sun4c_enable_irq(unsigned int irq_nr) |
| 100 | { |
| 101 | unsigned long flags; |
| 102 | unsigned char current_mask, new_mask; |
| 103 | |
| 104 | local_irq_save(flags); |
| 105 | irq_nr &= (NR_IRQS - 1); |
| 106 | current_mask = *interrupt_enable; |
| 107 | switch(irq_nr) { |
| 108 | case 1: |
| 109 | new_mask = ((current_mask) | SUN4C_INT_E1); |
| 110 | break; |
| 111 | case 8: |
| 112 | new_mask = ((current_mask) | SUN4C_INT_E8); |
| 113 | break; |
| 114 | case 10: |
| 115 | new_mask = ((current_mask) | SUN4C_INT_E10); |
| 116 | break; |
| 117 | case 14: |
| 118 | new_mask = ((current_mask) | SUN4C_INT_E14); |
| 119 | break; |
| 120 | default: |
| 121 | local_irq_restore(flags); |
| 122 | return; |
| 123 | } |
| 124 | *interrupt_enable = new_mask; |
| 125 | local_irq_restore(flags); |
| 126 | } |
| 127 | |
| 128 | #define TIMER_IRQ 10 /* Also at level 14, but we ignore that one. */ |
| 129 | #define PROFILE_IRQ 14 /* Level14 ticker.. used by OBP for polling */ |
| 130 | |
| 131 | volatile struct sun4c_timer_info *sun4c_timers; |
| 132 | |
| 133 | #ifdef CONFIG_SUN4 |
| 134 | /* This is an ugly hack to work around the |
| 135 | current timer code, and make it work with |
| 136 | the sun4/260 intersil |
| 137 | */ |
| 138 | volatile struct sun4c_timer_info sun4_timer; |
| 139 | #endif |
| 140 | |
| 141 | static void sun4c_clear_clock_irq(void) |
| 142 | { |
| 143 | volatile unsigned int clear_intr; |
| 144 | #ifdef CONFIG_SUN4 |
| 145 | if (idprom->id_machtype == (SM_SUN4 | SM_4_260)) |
| 146 | clear_intr = sun4_timer.timer_limit10; |
| 147 | else |
| 148 | #endif |
| 149 | clear_intr = sun4c_timers->timer_limit10; |
| 150 | } |
| 151 | |
| 152 | static void sun4c_clear_profile_irq(int cpu) |
| 153 | { |
| 154 | /* Errm.. not sure how to do this.. */ |
| 155 | } |
| 156 | |
| 157 | static void sun4c_load_profile_irq(int cpu, unsigned int limit) |
| 158 | { |
| 159 | /* Errm.. not sure how to do this.. */ |
| 160 | } |
| 161 | |
David Howells | 40220c1 | 2006-10-09 12:19:47 +0100 | [diff] [blame] | 162 | static void __init sun4c_init_timers(irq_handler_t counter_fn) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | { |
| 164 | int irq; |
| 165 | |
| 166 | /* Map the Timer chip, this is implemented in hardware inside |
| 167 | * the cache chip on the sun4c. |
| 168 | */ |
| 169 | #ifdef CONFIG_SUN4 |
| 170 | if (idprom->id_machtype == (SM_SUN4 | SM_4_260)) |
| 171 | sun4c_timers = &sun4_timer; |
| 172 | else |
| 173 | #endif |
| 174 | sun4c_timers = ioremap(SUN_TIMER_PHYSADDR, |
| 175 | sizeof(struct sun4c_timer_info)); |
| 176 | |
| 177 | /* Have the level 10 timer tick at 100HZ. We don't touch the |
| 178 | * level 14 timer limit since we are letting the prom handle |
| 179 | * them until we have a real console driver so L1-A works. |
| 180 | */ |
| 181 | sun4c_timers->timer_limit10 = (((1000000/HZ) + 1) << 10); |
| 182 | master_l10_counter = &sun4c_timers->cur_count10; |
| 183 | master_l10_limit = &sun4c_timers->timer_limit10; |
| 184 | |
| 185 | irq = request_irq(TIMER_IRQ, |
| 186 | counter_fn, |
Thomas Gleixner | 6741320 | 2006-07-01 19:29:26 -0700 | [diff] [blame] | 187 | (IRQF_DISABLED | SA_STATIC_ALLOC), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | "timer", NULL); |
| 189 | if (irq) { |
| 190 | prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ); |
| 191 | prom_halt(); |
| 192 | } |
| 193 | |
| 194 | #if 0 |
| 195 | /* This does not work on 4/330 */ |
| 196 | sun4c_enable_irq(10); |
| 197 | #endif |
| 198 | claim_ticker14(NULL, PROFILE_IRQ, 0); |
| 199 | } |
| 200 | |
| 201 | #ifdef CONFIG_SMP |
| 202 | static void sun4c_nop(void) {} |
| 203 | #endif |
| 204 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | void __init sun4c_init_IRQ(void) |
| 206 | { |
| 207 | struct linux_prom_registers int_regs[2]; |
| 208 | int ie_node; |
| 209 | |
| 210 | if (ARCH_SUN4) { |
| 211 | interrupt_enable = (char *) |
| 212 | ioremap(sun4_ie_physaddr, PAGE_SIZE); |
| 213 | } else { |
| 214 | struct resource phyres; |
| 215 | |
| 216 | ie_node = prom_searchsiblings (prom_getchild(prom_root_node), |
| 217 | "interrupt-enable"); |
| 218 | if(ie_node == 0) |
| 219 | panic("Cannot find /interrupt-enable node"); |
| 220 | |
| 221 | /* Depending on the "address" property is bad news... */ |
| 222 | interrupt_enable = NULL; |
| 223 | if (prom_getproperty(ie_node, "reg", (char *) int_regs, |
| 224 | sizeof(int_regs)) != -1) { |
| 225 | memset(&phyres, 0, sizeof(struct resource)); |
| 226 | phyres.flags = int_regs[0].which_io; |
| 227 | phyres.start = int_regs[0].phys_addr; |
David S. Miller | 454eeb2 | 2008-08-27 04:05:35 -0700 | [diff] [blame^] | 228 | interrupt_enable = (char *) of_ioremap(&phyres, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | int_regs[0].reg_size, "sun4c_intr"); |
| 230 | } |
| 231 | } |
| 232 | if (!interrupt_enable) |
| 233 | panic("Cannot map interrupt_enable"); |
| 234 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM); |
| 236 | BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM); |
| 237 | BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM); |
| 238 | BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM); |
| 239 | BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM); |
| 240 | BTFIXUPSET_CALL(clear_profile_irq, sun4c_clear_profile_irq, BTFIXUPCALL_NOP); |
| 241 | BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | sparc_init_timers = sun4c_init_timers; |
| 243 | #ifdef CONFIG_SMP |
| 244 | BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP); |
| 245 | BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP); |
| 246 | BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP); |
| 247 | #endif |
| 248 | *interrupt_enable = (SUN4C_INT_ENABLE); |
| 249 | /* Cannot enable interrupts until OBP ticker is disabled. */ |
| 250 | } |