Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Blackfin core register bit & address definitions |
| 3 | * |
| 4 | * Copyright 2005-2008 Analog Devices Inc. |
| 5 | * |
| 6 | * Licensed under the ADI BSD license or GPL-2 (or later). |
| 7 | */ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 8 | |
| 9 | #ifndef _DEF_LPBLACKFIN_H |
| 10 | #define _DEF_LPBLACKFIN_H |
| 11 | |
Bryan Wu | 639f657 | 2008-08-27 10:51:02 +0800 | [diff] [blame] | 12 | #include <mach/anomaly.h> |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 13 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 14 | #define MK_BMSK_(x) (1<<x) |
Mike Frysinger | 3630ac3 | 2009-11-17 04:26:22 +0000 | [diff] [blame] | 15 | #define BFIN_DEPOSIT(mask, x) (((x) << __ffs(mask)) & (mask)) |
| 16 | #define BFIN_EXTRACT(mask, x) (((x) & (mask)) >> __ffs(mask)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 17 | |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 18 | #ifndef __ASSEMBLY__ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 19 | |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 20 | #include <linux/types.h> |
Roy Huang | 75ed405 | 2007-06-14 12:54:44 +0800 | [diff] [blame] | 21 | |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 22 | #if ANOMALY_05000198 |
| 23 | # define NOP_PAD_ANOMALY_05000198 "nop;" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 24 | #else |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 25 | # define NOP_PAD_ANOMALY_05000198 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 26 | #endif |
| 27 | |
Mike Frysinger | 69e1d8a | 2009-12-25 21:06:06 +0000 | [diff] [blame] | 28 | #define _bfin_readX(addr, size, asm_size, asm_ext) ({ \ |
| 29 | u32 __v; \ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 30 | __asm__ __volatile__( \ |
| 31 | NOP_PAD_ANOMALY_05000198 \ |
Mike Frysinger | 69e1d8a | 2009-12-25 21:06:06 +0000 | [diff] [blame] | 32 | "%0 = " #asm_size "[%1]" #asm_ext ";" \ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 33 | : "=d" (__v) \ |
| 34 | : "a" (addr) \ |
| 35 | ); \ |
| 36 | __v; }) |
Mike Frysinger | 69e1d8a | 2009-12-25 21:06:06 +0000 | [diff] [blame] | 37 | #define _bfin_writeX(addr, val, size, asm_size) \ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 38 | __asm__ __volatile__( \ |
| 39 | NOP_PAD_ANOMALY_05000198 \ |
Mike Frysinger | 69e1d8a | 2009-12-25 21:06:06 +0000 | [diff] [blame] | 40 | #asm_size "[%0] = %1;" \ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 41 | : \ |
Mike Frysinger | 69e1d8a | 2009-12-25 21:06:06 +0000 | [diff] [blame] | 42 | : "a" (addr), "d" ((u##size)(val)) \ |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 43 | : "memory" \ |
| 44 | ) |
| 45 | |
Mike Frysinger | 69e1d8a | 2009-12-25 21:06:06 +0000 | [diff] [blame] | 46 | #define bfin_read8(addr) _bfin_readX(addr, 8, b, (z)) |
| 47 | #define bfin_read16(addr) _bfin_readX(addr, 16, w, (z)) |
| 48 | #define bfin_read32(addr) _bfin_readX(addr, 32, , ) |
| 49 | #define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b) |
| 50 | #define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w) |
| 51 | #define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, ) |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 52 | |
Mike Frysinger | f2521ce | 2009-12-26 15:25:56 +0000 | [diff] [blame] | 53 | #define bfin_read(addr) \ |
| 54 | ({ \ |
| 55 | sizeof(*(addr)) == 1 ? bfin_read8(addr) : \ |
| 56 | sizeof(*(addr)) == 2 ? bfin_read16(addr) : \ |
| 57 | sizeof(*(addr)) == 4 ? bfin_read32(addr) : \ |
| 58 | ({ BUG(); 0; }); \ |
| 59 | }) |
| 60 | #define bfin_write(addr, val) \ |
| 61 | ({ \ |
| 62 | switch (sizeof(*(addr))) { \ |
| 63 | case 1: bfin_write8(addr, val); break; \ |
| 64 | case 2: bfin_write16(addr, val); break; \ |
| 65 | case 4: bfin_write32(addr, val); break; \ |
| 66 | default: BUG(); \ |
| 67 | } \ |
| 68 | }) |
| 69 | |
Mike Frysinger | 1aafd90 | 2007-07-25 11:19:14 +0800 | [diff] [blame] | 70 | #endif /* __ASSEMBLY__ */ |
| 71 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 72 | /************************************************** |
| 73 | * System Register Bits |
| 74 | **************************************************/ |
| 75 | |
| 76 | /************************************************** |
| 77 | * ASTAT register |
| 78 | **************************************************/ |
| 79 | |
| 80 | /* definitions of ASTAT bit positions*/ |
| 81 | |
| 82 | /*Result of last ALU0 or shifter operation is zero*/ |
| 83 | #define ASTAT_AZ_P 0x00000000 |
| 84 | /*Result of last ALU0 or shifter operation is negative*/ |
| 85 | #define ASTAT_AN_P 0x00000001 |
| 86 | /*Condition Code, used for holding comparison results*/ |
| 87 | #define ASTAT_CC_P 0x00000005 |
| 88 | /*Quotient Bit*/ |
| 89 | #define ASTAT_AQ_P 0x00000006 |
| 90 | /*Rounding mode, set for biased, clear for unbiased*/ |
| 91 | #define ASTAT_RND_MOD_P 0x00000008 |
| 92 | /*Result of last ALU0 operation generated a carry*/ |
| 93 | #define ASTAT_AC0_P 0x0000000C |
| 94 | /*Result of last ALU0 operation generated a carry*/ |
| 95 | #define ASTAT_AC0_COPY_P 0x00000002 |
| 96 | /*Result of last ALU1 operation generated a carry*/ |
| 97 | #define ASTAT_AC1_P 0x0000000D |
| 98 | /*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/ |
| 99 | #define ASTAT_AV0_P 0x00000010 |
| 100 | /*Sticky version of ASTAT_AV0 */ |
| 101 | #define ASTAT_AV0S_P 0x00000011 |
| 102 | /*Result of last MAC1 operation overflowed, sticky for MAC*/ |
| 103 | #define ASTAT_AV1_P 0x00000012 |
| 104 | /*Sticky version of ASTAT_AV1 */ |
| 105 | #define ASTAT_AV1S_P 0x00000013 |
| 106 | /*Result of last ALU0 or MAC0 operation overflowed*/ |
| 107 | #define ASTAT_V_P 0x00000018 |
| 108 | /*Result of last ALU0 or MAC0 operation overflowed*/ |
| 109 | #define ASTAT_V_COPY_P 0x00000003 |
| 110 | /*Sticky version of ASTAT_V*/ |
| 111 | #define ASTAT_VS_P 0x00000019 |
| 112 | |
| 113 | /* Masks */ |
| 114 | |
| 115 | /*Result of last ALU0 or shifter operation is zero*/ |
| 116 | #define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) |
| 117 | /*Result of last ALU0 or shifter operation is negative*/ |
| 118 | #define ASTAT_AN MK_BMSK_(ASTAT_AN_P) |
| 119 | /*Result of last ALU0 operation generated a carry*/ |
| 120 | #define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) |
| 121 | /*Result of last ALU0 operation generated a carry*/ |
| 122 | #define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) |
| 123 | /*Result of last ALU0 operation generated a carry*/ |
| 124 | #define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) |
| 125 | /*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/ |
| 126 | #define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) |
| 127 | /*Result of last MAC1 operation overflowed, sticky for MAC*/ |
| 128 | #define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) |
| 129 | /*Condition Code, used for holding comparison results*/ |
| 130 | #define ASTAT_CC MK_BMSK_(ASTAT_CC_P) |
| 131 | /*Quotient Bit*/ |
| 132 | #define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) |
| 133 | /*Rounding mode, set for biased, clear for unbiased*/ |
| 134 | #define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) |
| 135 | /*Overflow Bit*/ |
| 136 | #define ASTAT_V MK_BMSK_(ASTAT_V_P) |
| 137 | /*Overflow Bit*/ |
| 138 | #define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) |
| 139 | |
| 140 | /************************************************** |
| 141 | * SEQSTAT register |
| 142 | **************************************************/ |
| 143 | |
| 144 | /* Bit Positions */ |
| 145 | #define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */ |
| 146 | #define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */ |
| 147 | #define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */ |
| 148 | #define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */ |
| 149 | #define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */ |
| 150 | #define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */ |
| 151 | #define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, |
| 152 | * set by IDLE instruction. |
| 153 | */ |
| 154 | #define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last |
| 155 | * reset was a software reset |
| 156 | * (=1) |
| 157 | */ |
| 158 | #define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */ |
| 159 | #define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */ |
| 160 | #define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */ |
| 161 | #define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */ |
| 162 | #define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */ |
| 163 | /* Masks */ |
| 164 | /* Exception cause */ |
| 165 | #define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \ |
| 166 | MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \ |
| 167 | MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \ |
| 168 | MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \ |
| 169 | MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \ |
| 170 | MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \ |
| 171 | 0) |
| 172 | |
| 173 | /* Indicates whether the last reset was a software reset (=1) */ |
| 174 | #define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P)) |
| 175 | |
| 176 | /* Last hw error cause */ |
| 177 | #define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \ |
| 178 | MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \ |
| 179 | MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \ |
| 180 | MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \ |
| 181 | MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \ |
| 182 | 0) |
| 183 | |
| 184 | /* Translate bits to something useful */ |
| 185 | |
| 186 | /* Last hw error cause */ |
| 187 | #define SEQSTAT_HWERRCAUSE_SHIFT (14) |
| 188 | #define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT) |
| 189 | #define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT) |
| 190 | #define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT) |
| 191 | #define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT) |
| 192 | |
| 193 | /************************************************** |
| 194 | * SYSCFG register |
| 195 | **************************************************/ |
| 196 | |
| 197 | /* Bit Positions */ |
| 198 | #define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when |
| 199 | * set it forces an exception |
| 200 | * for each instruction executed |
| 201 | */ |
| 202 | #define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */ |
| 203 | #define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */ |
| 204 | |
| 205 | /* Masks */ |
| 206 | |
| 207 | /* Supervisor single step, when set it forces an exception for each |
| 208 | *instruction executed |
| 209 | */ |
| 210 | #define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P ) |
| 211 | /* Enable cycle counter (=1) */ |
| 212 | #define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P ) |
| 213 | /* Self Nesting Interrupt Enable */ |
| 214 | #define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P) |
| 215 | /* Backward-compatibility for typos in prior releases */ |
| 216 | #define SYSCFG_SSSSTEP SYSCFG_SSSTEP |
| 217 | #define SYSCFG_CCCEN SYSCFG_CCEN |
| 218 | |
| 219 | /**************************************************** |
| 220 | * Core MMR Register Map |
| 221 | ****************************************************/ |
| 222 | |
| 223 | /* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */ |
| 224 | |
| 225 | #define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */ |
| 226 | #define DMEM_CONTROL 0xFFE00004 /* Data memory control */ |
| 227 | #define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside |
| 228 | * Buffer Status |
| 229 | */ |
| 230 | #define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */ |
| 231 | #define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside |
| 232 | * Buffer Fault Address |
| 233 | */ |
| 234 | #define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside |
| 235 | * Buffer 0 |
| 236 | */ |
| 237 | #define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside |
| 238 | * Buffer 1 |
| 239 | */ |
| 240 | #define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside |
| 241 | * Buffer 2 |
| 242 | */ |
| 243 | #define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection |
| 244 | * Lookaside Buffer 3 |
| 245 | */ |
| 246 | #define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection |
| 247 | * Lookaside Buffer 4 |
| 248 | */ |
| 249 | #define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection |
| 250 | * Lookaside Buffer 5 |
| 251 | */ |
| 252 | #define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection |
| 253 | * Lookaside Buffer 6 |
| 254 | */ |
| 255 | #define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection |
| 256 | * Lookaside Buffer 7 |
| 257 | */ |
| 258 | #define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection |
| 259 | * Lookaside Buffer 8 |
| 260 | */ |
| 261 | #define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection |
| 262 | * Lookaside Buffer 9 |
| 263 | */ |
| 264 | #define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection |
| 265 | * Lookaside Buffer 10 |
| 266 | */ |
| 267 | #define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection |
| 268 | * Lookaside Buffer 11 |
| 269 | */ |
| 270 | #define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection |
| 271 | * Lookaside Buffer 12 |
| 272 | */ |
| 273 | #define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection |
| 274 | * Lookaside Buffer 13 |
| 275 | */ |
| 276 | #define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection |
| 277 | * Lookaside Buffer 14 |
| 278 | */ |
| 279 | #define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection |
| 280 | * Lookaside Buffer 15 |
| 281 | */ |
| 282 | #define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ |
| 283 | #define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ |
| 284 | #define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ |
| 285 | #define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ |
| 286 | #define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ |
| 287 | #define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ |
| 288 | #define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ |
| 289 | #define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ |
| 290 | #define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ |
| 291 | #define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ |
| 292 | #define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ |
| 293 | #define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ |
| 294 | #define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ |
| 295 | #define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ |
| 296 | #define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ |
| 297 | #define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ |
| 298 | #define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */ |
| 299 | |
| 300 | #define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ |
| 301 | #define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ |
| 302 | #define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ |
| 303 | |
| 304 | /* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */ |
| 305 | |
| 306 | #define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ |
| 307 | #define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */ |
| 308 | #define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */ |
| 309 | #define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */ |
| 310 | #define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */ |
| 311 | #define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability |
| 312 | * Protection Lookaside Buffer 0 |
| 313 | */ |
| 314 | #define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability |
| 315 | * Protection Lookaside Buffer 1 |
| 316 | */ |
| 317 | #define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability |
| 318 | * Protection Lookaside Buffer 2 |
| 319 | */ |
| 320 | #define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability |
| 321 | * Protection Lookaside Buffer 3 |
| 322 | */ |
| 323 | #define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability |
| 324 | * Protection Lookaside Buffer 4 |
| 325 | */ |
| 326 | #define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability |
| 327 | * Protection Lookaside Buffer 5 |
| 328 | */ |
| 329 | #define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability |
| 330 | * Protection Lookaside Buffer 6 |
| 331 | */ |
| 332 | #define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability |
| 333 | * Protection Lookaside Buffer 7 |
| 334 | */ |
| 335 | #define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability |
| 336 | * Protection Lookaside Buffer 8 |
| 337 | */ |
| 338 | #define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability |
| 339 | * Protection Lookaside Buffer 9 |
| 340 | */ |
| 341 | #define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability |
| 342 | * Protection Lookaside Buffer 10 |
| 343 | */ |
| 344 | #define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability |
| 345 | * Protection Lookaside Buffer 11 |
| 346 | */ |
| 347 | #define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability |
| 348 | * Protection Lookaside Buffer 12 |
| 349 | */ |
| 350 | #define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability |
| 351 | * Protection Lookaside Buffer 13 |
| 352 | */ |
| 353 | #define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability |
| 354 | * Protection Lookaside Buffer 14 |
| 355 | */ |
| 356 | #define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability |
| 357 | * Protection Lookaside Buffer 15 |
| 358 | */ |
| 359 | #define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ |
| 360 | #define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ |
| 361 | #define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ |
| 362 | #define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ |
| 363 | #define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ |
| 364 | #define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ |
| 365 | #define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ |
| 366 | #define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ |
| 367 | #define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ |
| 368 | #define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ |
| 369 | #define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ |
| 370 | #define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ |
| 371 | #define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ |
| 372 | #define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ |
| 373 | #define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ |
| 374 | #define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ |
| 375 | #define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ |
| 376 | #define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ |
| 377 | #define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ |
| 378 | |
| 379 | /* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */ |
| 380 | |
| 381 | #define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ |
| 382 | #define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ |
| 383 | #define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ |
| 384 | #define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ |
| 385 | #define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ |
| 386 | #define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ |
| 387 | #define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ |
| 388 | #define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ |
| 389 | #define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ |
| 390 | #define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ |
| 391 | #define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ |
| 392 | #define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ |
| 393 | #define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ |
| 394 | #define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ |
| 395 | #define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ |
| 396 | #define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ |
Mike Frysinger | ada0917 | 2010-07-28 19:50:47 +0000 | [diff] [blame] | 397 | #define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 398 | #define IMASK 0xFFE02104 /* Interrupt Mask Register */ |
| 399 | #define IPEND 0xFFE02108 /* Interrupt Pending Register */ |
| 400 | #define ILAT 0xFFE0210C /* Interrupt Latch Register */ |
| 401 | #define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */ |
| 402 | |
| 403 | /* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */ |
| 404 | |
| 405 | #define TCNTL 0xFFE03000 /* Core Timer Control Register */ |
| 406 | #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ |
| 407 | #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ |
| 408 | #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ |
| 409 | |
| 410 | /* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */ |
| 411 | #define DSPID 0xFFE05000 /* DSP Processor ID Register for |
| 412 | * MP implementations |
| 413 | */ |
| 414 | |
| 415 | #define DBGSTAT 0xFFE05008 /* Debug Status Register */ |
| 416 | |
| 417 | /* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */ |
| 418 | |
| 419 | #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ |
| 420 | #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ |
| 421 | #define TBUF 0xFFE06100 /* Trace Buffer */ |
| 422 | |
| 423 | /* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */ |
| 424 | |
| 425 | /* Watchpoint Instruction Address Control Register */ |
| 426 | #define WPIACTL 0xFFE07000 |
| 427 | /* Watchpoint Instruction Address Register 0 */ |
| 428 | #define WPIA0 0xFFE07040 |
| 429 | /* Watchpoint Instruction Address Register 1 */ |
| 430 | #define WPIA1 0xFFE07044 |
| 431 | /* Watchpoint Instruction Address Register 2 */ |
| 432 | #define WPIA2 0xFFE07048 |
| 433 | /* Watchpoint Instruction Address Register 3 */ |
| 434 | #define WPIA3 0xFFE0704C |
| 435 | /* Watchpoint Instruction Address Register 4 */ |
| 436 | #define WPIA4 0xFFE07050 |
| 437 | /* Watchpoint Instruction Address Register 5 */ |
| 438 | #define WPIA5 0xFFE07054 |
| 439 | /* Watchpoint Instruction Address Count Register 0 */ |
| 440 | #define WPIACNT0 0xFFE07080 |
| 441 | /* Watchpoint Instruction Address Count Register 1 */ |
| 442 | #define WPIACNT1 0xFFE07084 |
| 443 | /* Watchpoint Instruction Address Count Register 2 */ |
| 444 | #define WPIACNT2 0xFFE07088 |
| 445 | /* Watchpoint Instruction Address Count Register 3 */ |
| 446 | #define WPIACNT3 0xFFE0708C |
| 447 | /* Watchpoint Instruction Address Count Register 4 */ |
| 448 | #define WPIACNT4 0xFFE07090 |
| 449 | /* Watchpoint Instruction Address Count Register 5 */ |
| 450 | #define WPIACNT5 0xFFE07094 |
| 451 | /* Watchpoint Data Address Control Register */ |
| 452 | #define WPDACTL 0xFFE07100 |
| 453 | /* Watchpoint Data Address Register 0 */ |
| 454 | #define WPDA0 0xFFE07140 |
| 455 | /* Watchpoint Data Address Register 1 */ |
| 456 | #define WPDA1 0xFFE07144 |
| 457 | /* Watchpoint Data Address Count Value Register 0 */ |
| 458 | #define WPDACNT0 0xFFE07180 |
| 459 | /* Watchpoint Data Address Count Value Register 1 */ |
| 460 | #define WPDACNT1 0xFFE07184 |
| 461 | /* Watchpoint Status Register */ |
| 462 | #define WPSTAT 0xFFE07200 |
| 463 | |
| 464 | /* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */ |
| 465 | |
| 466 | /* Performance Monitor Control Register */ |
| 467 | #define PFCTL 0xFFE08000 |
| 468 | /* Performance Monitor Counter Register 0 */ |
| 469 | #define PFCNTR0 0xFFE08100 |
| 470 | /* Performance Monitor Counter Register 1 */ |
| 471 | #define PFCNTR1 0xFFE08104 |
| 472 | |
| 473 | /**************************************************** |
| 474 | * Core MMR Register Bits |
| 475 | ****************************************************/ |
| 476 | |
| 477 | /************************************************** |
| 478 | * EVT registers (ILAT, IMASK, and IPEND). |
| 479 | **************************************************/ |
| 480 | |
| 481 | /* Bit Positions */ |
| 482 | #define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */ |
| 483 | #define EVT_RST_P 0x00000001 /* Reset interrupt bit position */ |
| 484 | #define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */ |
| 485 | #define EVT_EVX_P 0x00000003 /* Exception bit position */ |
| 486 | #define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */ |
| 487 | #define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */ |
| 488 | #define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */ |
| 489 | #define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */ |
| 490 | #define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */ |
| 491 | #define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */ |
| 492 | #define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */ |
| 493 | #define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */ |
| 494 | #define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */ |
| 495 | #define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */ |
| 496 | #define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */ |
| 497 | #define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */ |
| 498 | |
| 499 | /* Masks */ |
| 500 | #define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */ |
| 501 | #define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */ |
| 502 | #define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */ |
| 503 | #define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */ |
| 504 | #define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */ |
| 505 | #define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */ |
| 506 | #define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */ |
| 507 | #define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */ |
| 508 | #define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */ |
| 509 | #define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */ |
| 510 | #define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */ |
| 511 | #define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */ |
| 512 | #define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */ |
| 513 | #define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */ |
| 514 | #define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */ |
| 515 | #define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */ |
| 516 | |
| 517 | /************************************************** |
| 518 | * DMEM_CONTROL Register |
| 519 | **************************************************/ |
| 520 | /* Bit Positions */ |
| 521 | #define ENDM_P 0x00 /* (doesn't really exist) Enable |
| 522 | *Data Memory L1 |
| 523 | */ |
| 524 | #define DMCTL_ENDM_P ENDM_P /* "" (older define) */ |
| 525 | |
| 526 | #define ENDCPLB_P 0x01 /* Enable DCPLBS */ |
| 527 | #define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */ |
| 528 | #define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */ |
| 529 | #define DMCTL_DMC0_P DMC0_P /* "" (older define) */ |
| 530 | #define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */ |
| 531 | #define DMCTL_DMC1_P DMC1_P /* "" (older define) */ |
| 532 | #define DCBS_P 0x04 /* L1 Data Cache Bank Select */ |
| 533 | #define PORT_PREF0_P 0x12 /* DAG0 Port Preference */ |
| 534 | #define PORT_PREF1_P 0x13 /* DAG1 Port Preference */ |
| 535 | |
| 536 | /* Masks */ |
| 537 | #define ENDM 0x00000001 /* (doesn't really exist) Enable |
| 538 | * Data Memory L1 |
| 539 | */ |
| 540 | #define ENDCPLB 0x00000002 /* Enable DCPLB */ |
| 541 | #define ASRAM_BSRAM 0x00000000 |
| 542 | #define ACACHE_BSRAM 0x00000008 |
| 543 | #define ACACHE_BCACHE 0x0000000C |
| 544 | #define DCBS 0x00000010 /* L1 Data Cache Bank Select */ |
| 545 | #define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ |
| 546 | #define PORT_PREF1 0x00002000 /* DAG1 Port Preference */ |
| 547 | |
| 548 | /* IMEM_CONTROL Register */ |
| 549 | /* Bit Positions */ |
| 550 | #define ENIM_P 0x00 /* Enable L1 Code Memory */ |
| 551 | #define IMCTL_ENIM_P 0x00 /* "" (older define) */ |
| 552 | #define ENICPLB_P 0x01 /* Enable ICPLB */ |
| 553 | #define IMCTL_ENICPLB_P 0x01 /* "" (older define) */ |
| 554 | #define IMC_P 0x02 /* Enable */ |
| 555 | #define IMCTL_IMC_P 0x02 /* Configure L1 code memory as |
| 556 | * cache (0=SRAM) |
| 557 | */ |
| 558 | #define ILOC0_P 0x03 /* Lock Way 0 */ |
| 559 | #define ILOC1_P 0x04 /* Lock Way 1 */ |
| 560 | #define ILOC2_P 0x05 /* Lock Way 2 */ |
| 561 | #define ILOC3_P 0x06 /* Lock Way 3 */ |
| 562 | #define LRUPRIORST_P 0x0D /* Least Recently Used Replacement |
| 563 | * Priority |
| 564 | */ |
| 565 | /* Masks */ |
| 566 | #define ENIM 0x00000001 /* Enable L1 Code Memory */ |
| 567 | #define ENICPLB 0x00000002 /* Enable ICPLB */ |
| 568 | #define IMC 0x00000004 /* Configure L1 code memory as |
| 569 | * cache (0=SRAM) |
| 570 | */ |
| 571 | #define ILOC0 0x00000008 /* Lock Way 0 */ |
| 572 | #define ILOC1 0x00000010 /* Lock Way 1 */ |
| 573 | #define ILOC2 0x00000020 /* Lock Way 2 */ |
| 574 | #define ILOC3 0x00000040 /* Lock Way 3 */ |
| 575 | #define LRUPRIORST 0x00002000 /* Least Recently Used Replacement |
| 576 | * Priority |
| 577 | */ |
| 578 | |
| 579 | /* TCNTL Masks */ |
| 580 | #define TMPWR 0x00000001 /* Timer Low Power Control, |
| 581 | * 0=low power mode, 1=active state |
| 582 | */ |
| 583 | #define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */ |
| 584 | #define TAUTORLD 0x00000004 /* Timer auto reload */ |
| 585 | #define TINT 0x00000008 /* Timer generated interrupt 0=no |
| 586 | * interrupt has been generated, |
| 587 | * 1=interrupt has been generated |
| 588 | * (sticky) |
| 589 | */ |
| 590 | |
| 591 | /* DCPLB_DATA and ICPLB_DATA Registers */ |
| 592 | /* Bit Positions */ |
| 593 | #define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ |
| 594 | #define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry |
| 595 | * locked |
| 596 | */ |
| 597 | #define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access |
| 598 | * allowed (user mode) |
| 599 | */ |
| 600 | /* Masks */ |
| 601 | #define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ |
| 602 | #define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry |
| 603 | * locked |
| 604 | */ |
| 605 | #define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access |
| 606 | * allowed (user mode) |
| 607 | */ |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 608 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 609 | #define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ |
| 610 | #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ |
| 611 | #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ |
| 612 | #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ |
| 613 | #define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not |
| 614 | * mapped to L1 |
| 615 | */ |
| 616 | #define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high |
| 617 | * priority port |
| 618 | */ |
| 619 | #define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable |
| 620 | * in L1 |
| 621 | */ |
| 622 | /* ICPLB_DATA only */ |
| 623 | #define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, |
| 624 | * 1=priority for non-replacement |
| 625 | */ |
| 626 | /* DCPLB_DATA only */ |
| 627 | #define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write |
| 628 | * access allowed (user mode) |
| 629 | */ |
| 630 | #define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write |
| 631 | * access allowed (supervisor mode) |
| 632 | */ |
| 633 | #define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ |
| 634 | #define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on |
| 635 | * write-through writes, |
| 636 | * 1= allocate cache lines on |
| 637 | * write-through writes. |
| 638 | */ |
| 639 | #define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ |
| 640 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 641 | #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR |
| 642 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 643 | /* TBUFCTL Masks */ |
| 644 | #define TBUFPWR 0x0001 |
| 645 | #define TBUFEN 0x0002 |
| 646 | #define TBUFOVF 0x0004 |
| 647 | #define TBUFCMPLP_SINGLE 0x0008 |
| 648 | #define TBUFCMPLP_DOUBLE 0x0010 |
| 649 | #define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE) |
| 650 | |
| 651 | /* TBUFSTAT Masks */ |
| 652 | #define TBUFCNT 0x001F |
| 653 | |
| 654 | /* ITEST_COMMAND and DTEST_COMMAND Registers */ |
| 655 | /* Masks */ |
| 656 | #define TEST_READ 0x00000000 /* Read Access */ |
| 657 | #define TEST_WRITE 0x00000002 /* Write Access */ |
| 658 | #define TEST_TAG 0x00000000 /* Access TAG */ |
| 659 | #define TEST_DATA 0x00000004 /* Access DATA */ |
| 660 | #define TEST_DW0 0x00000000 /* Select Double Word 0 */ |
| 661 | #define TEST_DW1 0x00000008 /* Select Double Word 1 */ |
| 662 | #define TEST_DW2 0x00000010 /* Select Double Word 2 */ |
| 663 | #define TEST_DW3 0x00000018 /* Select Double Word 3 */ |
| 664 | #define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */ |
| 665 | #define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */ |
| 666 | #define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */ |
| 667 | #define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */ |
| 668 | #define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */ |
| 669 | #define TEST_WAY0 0x00000000 /* Access Way0 */ |
| 670 | #define TEST_WAY1 0x04000000 /* Access Way1 */ |
| 671 | /* ITEST_COMMAND only */ |
| 672 | #define TEST_WAY2 0x08000000 /* Access Way2 */ |
| 673 | #define TEST_WAY3 0x0C000000 /* Access Way3 */ |
| 674 | /* DTEST_COMMAND only */ |
| 675 | #define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ |
| 676 | #define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ |
| 677 | |
| 678 | #endif /* _DEF_LPBLACKFIN_H */ |