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Maxime Ripard4790ecf2013-07-17 10:07:10 +02001/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
Emilio Lópeze751cce2013-11-16 15:17:29 -030019 aliases {
20 ethernet0 = &emac;
21 };
22
Maxime Ripard4790ecf2013-07-17 10:07:10 +020023 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu@0 {
28 compatible = "arm,cortex-a7";
29 device_type = "cpu";
30 reg = <0>;
31 };
32
33 cpu@1 {
34 compatible = "arm,cortex-a7";
35 device_type = "cpu";
36 reg = <1>;
37 };
38 };
39
40 memory {
41 reg = <0x40000000 0x80000000>;
42 };
43
44 clocks {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 osc24M: osc24M@01c20050 {
50 #clock-cells = <0>;
Maxime Ripardde7dc932013-07-25 21:12:52 +020051 compatible = "allwinner,sun4i-osc-clk";
52 reg = <0x01c20050 0x4>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +020053 clock-frequency = <24000000>;
54 };
55
Chen-Yu Tsai673fac72014-01-01 10:30:47 +080056 osc32k: clk@0 {
Maxime Ripard4790ecf2013-07-17 10:07:10 +020057 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <32768>;
Chen-Yu Tsai673fac72014-01-01 10:30:47 +080060 clock-output-names = "osc32k";
Maxime Ripard4790ecf2013-07-17 10:07:10 +020061 };
Maxime Ripardde7dc932013-07-25 21:12:52 +020062
63 pll1: pll1@01c20000 {
64 #clock-cells = <0>;
65 compatible = "allwinner,sun4i-pll1-clk";
66 reg = <0x01c20000 0x4>;
67 clocks = <&osc24M>;
68 };
69
Emilio Lópezec5589f2013-12-23 00:32:35 -030070 pll4: pll4@01c20018 {
Maxime Ripardde7dc932013-07-25 21:12:52 +020071 #clock-cells = <0>;
Emilio Lópezec5589f2013-12-23 00:32:35 -030072 compatible = "allwinner,sun4i-pll1-clk";
73 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>;
75 };
76
Emilio Lópezc3e5e662013-12-23 00:32:38 -030077 pll5: pll5@01c20020 {
78 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk";
80 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other";
83 };
84
85 pll6: pll6@01c20028 {
86 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk";
88 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6";
Maxime Ripardde7dc932013-07-25 21:12:52 +020091 };
92
93 cpu: cpu@01c20054 {
94 #clock-cells = <0>;
95 compatible = "allwinner,sun4i-cpu-clk";
96 reg = <0x01c20054 0x4>;
Emilio Lópezc3e5e662013-12-23 00:32:38 -030097 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
Maxime Ripardde7dc932013-07-25 21:12:52 +020098 };
99
100 axi: axi@01c20054 {
101 #clock-cells = <0>;
102 compatible = "allwinner,sun4i-axi-clk";
103 reg = <0x01c20054 0x4>;
104 clocks = <&cpu>;
105 };
106
107 ahb: ahb@01c20054 {
108 #clock-cells = <0>;
109 compatible = "allwinner,sun4i-ahb-clk";
110 reg = <0x01c20054 0x4>;
111 clocks = <&axi>;
112 };
113
114 ahb_gates: ahb_gates@01c20060 {
115 #clock-cells = <1>;
116 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
117 reg = <0x01c20060 0x8>;
118 clocks = <&ahb>;
119 clock-output-names = "ahb_usb0", "ahb_ehci0",
120 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
121 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
122 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
123 "ahb_nand", "ahb_sdram", "ahb_ace",
124 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
125 "ahb_spi2", "ahb_spi3", "ahb_sata",
126 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
127 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
128 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
129 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
130 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
131 "ahb_mali";
132 };
133
134 apb0: apb0@01c20054 {
135 #clock-cells = <0>;
136 compatible = "allwinner,sun4i-apb0-clk";
137 reg = <0x01c20054 0x4>;
138 clocks = <&ahb>;
139 };
140
141 apb0_gates: apb0_gates@01c20068 {
142 #clock-cells = <1>;
143 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
144 reg = <0x01c20068 0x4>;
145 clocks = <&apb0>;
146 clock-output-names = "apb0_codec", "apb0_spdif",
147 "apb0_ac97", "apb0_iis0", "apb0_iis1",
148 "apb0_pio", "apb0_ir0", "apb0_ir1",
149 "apb0_iis2", "apb0_keypad";
150 };
151
152 apb1_mux: apb1_mux@01c20058 {
153 #clock-cells = <0>;
154 compatible = "allwinner,sun4i-apb1-mux-clk";
155 reg = <0x01c20058 0x4>;
Emilio Lópezc3e5e662013-12-23 00:32:38 -0300156 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
Maxime Ripardde7dc932013-07-25 21:12:52 +0200157 };
158
159 apb1: apb1@01c20058 {
160 #clock-cells = <0>;
161 compatible = "allwinner,sun4i-apb1-clk";
162 reg = <0x01c20058 0x4>;
163 clocks = <&apb1_mux>;
164 };
165
166 apb1_gates: apb1_gates@01c2006c {
167 #clock-cells = <1>;
168 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
169 reg = <0x01c2006c 0x4>;
170 clocks = <&apb1>;
171 clock-output-names = "apb1_i2c0", "apb1_i2c1",
172 "apb1_i2c2", "apb1_i2c3", "apb1_can",
173 "apb1_scr", "apb1_ps20", "apb1_ps21",
174 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
175 "apb1_uart2", "apb1_uart3", "apb1_uart4",
176 "apb1_uart5", "apb1_uart6", "apb1_uart7";
177 };
Emilio López1c92b952013-12-23 00:32:43 -0300178
179 nand_clk: clk@01c20080 {
180 #clock-cells = <0>;
181 compatible = "allwinner,sun4i-mod0-clk";
182 reg = <0x01c20080 0x4>;
183 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
184 clock-output-names = "nand";
185 };
186
187 ms_clk: clk@01c20084 {
188 #clock-cells = <0>;
189 compatible = "allwinner,sun4i-mod0-clk";
190 reg = <0x01c20084 0x4>;
191 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
192 clock-output-names = "ms";
193 };
194
195 mmc0_clk: clk@01c20088 {
196 #clock-cells = <0>;
197 compatible = "allwinner,sun4i-mod0-clk";
198 reg = <0x01c20088 0x4>;
199 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
200 clock-output-names = "mmc0";
201 };
202
203 mmc1_clk: clk@01c2008c {
204 #clock-cells = <0>;
205 compatible = "allwinner,sun4i-mod0-clk";
206 reg = <0x01c2008c 0x4>;
207 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
208 clock-output-names = "mmc1";
209 };
210
211 mmc2_clk: clk@01c20090 {
212 #clock-cells = <0>;
213 compatible = "allwinner,sun4i-mod0-clk";
214 reg = <0x01c20090 0x4>;
215 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
216 clock-output-names = "mmc2";
217 };
218
219 mmc3_clk: clk@01c20094 {
220 #clock-cells = <0>;
221 compatible = "allwinner,sun4i-mod0-clk";
222 reg = <0x01c20094 0x4>;
223 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
224 clock-output-names = "mmc3";
225 };
226
227 ts_clk: clk@01c20098 {
228 #clock-cells = <0>;
229 compatible = "allwinner,sun4i-mod0-clk";
230 reg = <0x01c20098 0x4>;
231 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
232 clock-output-names = "ts";
233 };
234
235 ss_clk: clk@01c2009c {
236 #clock-cells = <0>;
237 compatible = "allwinner,sun4i-mod0-clk";
238 reg = <0x01c2009c 0x4>;
239 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
240 clock-output-names = "ss";
241 };
242
243 spi0_clk: clk@01c200a0 {
244 #clock-cells = <0>;
245 compatible = "allwinner,sun4i-mod0-clk";
246 reg = <0x01c200a0 0x4>;
247 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
248 clock-output-names = "spi0";
249 };
250
251 spi1_clk: clk@01c200a4 {
252 #clock-cells = <0>;
253 compatible = "allwinner,sun4i-mod0-clk";
254 reg = <0x01c200a4 0x4>;
255 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
256 clock-output-names = "spi1";
257 };
258
259 spi2_clk: clk@01c200a8 {
260 #clock-cells = <0>;
261 compatible = "allwinner,sun4i-mod0-clk";
262 reg = <0x01c200a8 0x4>;
263 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
264 clock-output-names = "spi2";
265 };
266
267 pata_clk: clk@01c200ac {
268 #clock-cells = <0>;
269 compatible = "allwinner,sun4i-mod0-clk";
270 reg = <0x01c200ac 0x4>;
271 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
272 clock-output-names = "pata";
273 };
274
275 ir0_clk: clk@01c200b0 {
276 #clock-cells = <0>;
277 compatible = "allwinner,sun4i-mod0-clk";
278 reg = <0x01c200b0 0x4>;
279 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
280 clock-output-names = "ir0";
281 };
282
283 ir1_clk: clk@01c200b4 {
284 #clock-cells = <0>;
285 compatible = "allwinner,sun4i-mod0-clk";
286 reg = <0x01c200b4 0x4>;
287 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
288 clock-output-names = "ir1";
289 };
290
291 spi3_clk: clk@01c200d4 {
292 #clock-cells = <0>;
293 compatible = "allwinner,sun4i-mod0-clk";
294 reg = <0x01c200d4 0x4>;
295 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
296 clock-output-names = "spi3";
297 };
Emilio López118c07a2013-12-23 00:32:44 -0300298
299 mbus_clk: clk@01c2015c {
300 #clock-cells = <0>;
301 compatible = "allwinner,sun4i-mod0-clk";
302 reg = <0x01c2015c 0x4>;
303 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
304 clock-output-names = "mbus";
305 };
Chen-Yu Tsai0aff0372014-01-01 10:30:48 +0800306
307 /*
308 * Dummy clock used by output clocks
309 */
310 osc24M_32k: clk@1 {
311 #clock-cells = <0>;
312 compatible = "fixed-factor-clock";
313 clock-div = <750>;
314 clock-mult = <1>;
315 clocks = <&osc24M>;
316 clock-output-names = "osc24M_32k";
317 };
318
319 clk_out_a: clk@01c201f0 {
320 #clock-cells = <0>;
321 compatible = "allwinner,sun7i-a20-out-clk";
322 reg = <0x01c201f0 0x4>;
323 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
324 clock-output-names = "clk_out_a";
325 };
326
327 clk_out_b: clk@01c201f4 {
328 #clock-cells = <0>;
329 compatible = "allwinner,sun7i-a20-out-clk";
330 reg = <0x01c201f4 0x4>;
331 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
332 clock-output-names = "clk_out_b";
333 };
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200334 };
335
336 soc@01c00000 {
337 compatible = "simple-bus";
338 #address-cells = <1>;
339 #size-cells = <1>;
340 ranges;
341
Maxime Ripard2e804d02013-09-11 11:10:06 +0200342 emac: ethernet@01c0b000 {
Maxime Ripard1c70e092014-02-02 14:49:13 +0100343 compatible = "allwinner,sun4i-a10-emac";
Maxime Ripard2e804d02013-09-11 11:10:06 +0200344 reg = <0x01c0b000 0x1000>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100345 interrupts = <0 55 4>;
Maxime Ripard2e804d02013-09-11 11:10:06 +0200346 clocks = <&ahb_gates 17>;
347 status = "disabled";
348 };
349
350 mdio@01c0b080 {
Maxime Ripard1c70e092014-02-02 14:49:13 +0100351 compatible = "allwinner,sun4i-a10-mdio";
Maxime Ripard2e804d02013-09-11 11:10:06 +0200352 reg = <0x01c0b080 0x14>;
353 status = "disabled";
354 #address-cells = <1>;
355 #size-cells = <0>;
356 };
357
Maxime Ripard17eac032013-07-24 23:46:11 +0200358 pio: pinctrl@01c20800 {
359 compatible = "allwinner,sun7i-a20-pinctrl";
360 reg = <0x01c20800 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100361 interrupts = <0 28 4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +0200362 clocks = <&apb0_gates 5>;
Maxime Ripard17eac032013-07-24 23:46:11 +0200363 gpio-controller;
364 interrupt-controller;
365 #address-cells = <1>;
366 #size-cells = <0>;
367 #gpio-cells = <3>;
Maxime Ripard9f229ba2013-07-25 00:09:47 +0200368
369 uart0_pins_a: uart0@0 {
370 allwinner,pins = "PB22", "PB23";
371 allwinner,function = "uart0";
372 allwinner,drive = <0>;
373 allwinner,pull = <0>;
374 };
375
376 uart6_pins_a: uart6@0 {
377 allwinner,pins = "PI12", "PI13";
378 allwinner,function = "uart6";
379 allwinner,drive = <0>;
380 allwinner,pull = <0>;
381 };
382
383 uart7_pins_a: uart7@0 {
384 allwinner,pins = "PI20", "PI21";
385 allwinner,function = "uart7";
386 allwinner,drive = <0>;
387 allwinner,pull = <0>;
388 };
Maxime Ripard756084c2013-09-11 11:10:07 +0200389
Maxime Riparde5496a32013-08-31 23:08:49 +0200390 i2c0_pins_a: i2c0@0 {
391 allwinner,pins = "PB0", "PB1";
392 allwinner,function = "i2c0";
393 allwinner,drive = <0>;
394 allwinner,pull = <0>;
395 };
396
397 i2c1_pins_a: i2c1@0 {
398 allwinner,pins = "PB18", "PB19";
399 allwinner,function = "i2c1";
400 allwinner,drive = <0>;
401 allwinner,pull = <0>;
402 };
403
404 i2c2_pins_a: i2c2@0 {
405 allwinner,pins = "PB20", "PB21";
406 allwinner,function = "i2c2";
407 allwinner,drive = <0>;
408 allwinner,pull = <0>;
409 };
410
Maxime Ripard756084c2013-09-11 11:10:07 +0200411 emac_pins_a: emac0@0 {
412 allwinner,pins = "PA0", "PA1", "PA2",
413 "PA3", "PA4", "PA5", "PA6",
414 "PA7", "PA8", "PA9", "PA10",
415 "PA11", "PA12", "PA13", "PA14",
416 "PA15", "PA16";
417 allwinner,function = "emac";
418 allwinner,drive = <0>;
419 allwinner,pull = <0>;
420 };
Chen-Yu Tsaif2e07592014-01-01 10:30:50 +0800421
422 clk_out_a_pins_a: clk_out_a@0 {
423 allwinner,pins = "PI12";
424 allwinner,function = "clk_out_a";
425 allwinner,drive = <0>;
426 allwinner,pull = <0>;
427 };
428
429 clk_out_b_pins_a: clk_out_b@0 {
430 allwinner,pins = "PI13";
431 allwinner,function = "clk_out_b";
432 allwinner,drive = <0>;
433 allwinner,pull = <0>;
434 };
Maxime Ripard17eac032013-07-24 23:46:11 +0200435 };
436
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200437 timer@01c20c00 {
438 compatible = "allwinner,sun4i-timer";
439 reg = <0x01c20c00 0x90>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100440 interrupts = <0 22 4>,
441 <0 23 4>,
442 <0 24 4>,
443 <0 25 4>,
444 <0 67 4>,
445 <0 68 4>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200446 clocks = <&osc24M>;
447 };
448
449 wdt: watchdog@01c20c90 {
450 compatible = "allwinner,sun4i-wdt";
451 reg = <0x01c20c90 0x10>;
452 };
453
Carlo Caioneb5d905c2013-10-16 20:30:26 +0200454 rtc: rtc@01c20d00 {
455 compatible = "allwinner,sun7i-a20-rtc";
456 reg = <0x01c20d00 0x20>;
457 interrupts = <0 24 1>;
458 };
459
Oliver Schinagl2bad9692013-09-03 12:33:28 +0200460 sid: eeprom@01c23800 {
461 compatible = "allwinner,sun7i-a20-sid";
462 reg = <0x01c23800 0x200>;
463 };
464
Hans de Goede00f7ed82013-12-31 17:20:52 +0100465 rtp: rtp@01c25000 {
466 compatible = "allwinner,sun4i-ts";
467 reg = <0x01c25000 0x100>;
468 interrupts = <0 29 4>;
469 };
470
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200471 uart0: serial@01c28000 {
472 compatible = "snps,dw-apb-uart";
473 reg = <0x01c28000 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100474 interrupts = <0 1 4>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200475 reg-shift = <2>;
476 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +0200477 clocks = <&apb1_gates 16>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200478 status = "disabled";
479 };
480
481 uart1: serial@01c28400 {
482 compatible = "snps,dw-apb-uart";
483 reg = <0x01c28400 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100484 interrupts = <0 2 4>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200485 reg-shift = <2>;
486 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +0200487 clocks = <&apb1_gates 17>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200488 status = "disabled";
489 };
490
491 uart2: serial@01c28800 {
492 compatible = "snps,dw-apb-uart";
493 reg = <0x01c28800 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100494 interrupts = <0 3 4>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200495 reg-shift = <2>;
496 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +0200497 clocks = <&apb1_gates 18>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200498 status = "disabled";
499 };
500
501 uart3: serial@01c28c00 {
502 compatible = "snps,dw-apb-uart";
503 reg = <0x01c28c00 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100504 interrupts = <0 4 4>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200505 reg-shift = <2>;
506 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +0200507 clocks = <&apb1_gates 19>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200508 status = "disabled";
509 };
510
511 uart4: serial@01c29000 {
512 compatible = "snps,dw-apb-uart";
513 reg = <0x01c29000 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100514 interrupts = <0 17 4>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200515 reg-shift = <2>;
516 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +0200517 clocks = <&apb1_gates 20>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200518 status = "disabled";
519 };
520
521 uart5: serial@01c29400 {
522 compatible = "snps,dw-apb-uart";
523 reg = <0x01c29400 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100524 interrupts = <0 18 4>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200525 reg-shift = <2>;
526 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +0200527 clocks = <&apb1_gates 21>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200528 status = "disabled";
529 };
530
531 uart6: serial@01c29800 {
532 compatible = "snps,dw-apb-uart";
533 reg = <0x01c29800 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100534 interrupts = <0 19 4>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200535 reg-shift = <2>;
536 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +0200537 clocks = <&apb1_gates 22>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200538 status = "disabled";
539 };
540
541 uart7: serial@01c29c00 {
542 compatible = "snps,dw-apb-uart";
543 reg = <0x01c29c00 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100544 interrupts = <0 20 4>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200545 reg-shift = <2>;
546 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +0200547 clocks = <&apb1_gates 23>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200548 status = "disabled";
549 };
550
Maxime Ripard428abbb2013-08-31 23:07:24 +0200551 i2c0: i2c@01c2ac00 {
552 compatible = "allwinner,sun4i-i2c";
553 reg = <0x01c2ac00 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100554 interrupts = <0 7 4>;
Maxime Ripard428abbb2013-08-31 23:07:24 +0200555 clocks = <&apb1_gates 0>;
556 clock-frequency = <100000>;
557 status = "disabled";
558 };
559
560 i2c1: i2c@01c2b000 {
561 compatible = "allwinner,sun4i-i2c";
562 reg = <0x01c2b000 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100563 interrupts = <0 8 4>;
Maxime Ripard428abbb2013-08-31 23:07:24 +0200564 clocks = <&apb1_gates 1>;
565 clock-frequency = <100000>;
566 status = "disabled";
567 };
568
569 i2c2: i2c@01c2b400 {
570 compatible = "allwinner,sun4i-i2c";
571 reg = <0x01c2b400 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100572 interrupts = <0 9 4>;
Maxime Ripard428abbb2013-08-31 23:07:24 +0200573 clocks = <&apb1_gates 2>;
574 clock-frequency = <100000>;
575 status = "disabled";
576 };
577
578 i2c3: i2c@01c2b800 {
579 compatible = "allwinner,sun4i-i2c";
580 reg = <0x01c2b800 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100581 interrupts = <0 88 4>;
Maxime Ripard428abbb2013-08-31 23:07:24 +0200582 clocks = <&apb1_gates 3>;
583 clock-frequency = <100000>;
584 status = "disabled";
585 };
586
587 i2c4: i2c@01c2bc00 {
588 compatible = "allwinner,sun4i-i2c";
589 reg = <0x01c2bc00 0x400>;
Maxime Ripard378d0ae2013-12-10 19:37:21 +0100590 interrupts = <0 89 4>;
Maxime Ripard428abbb2013-08-31 23:07:24 +0200591 clocks = <&apb1_gates 15>;
592 clock-frequency = <100000>;
593 status = "disabled";
594 };
595
Maxime Ripard31f8ad32013-11-07 12:01:48 +0100596 hstimer@01c60000 {
597 compatible = "allwinner,sun7i-a20-hstimer";
598 reg = <0x01c60000 0x1000>;
599 interrupts = <0 81 1>,
600 <0 82 1>,
601 <0 83 1>,
602 <0 84 1>;
603 clocks = <&ahb_gates 28>;
604 };
605
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200606 gic: interrupt-controller@01c81000 {
607 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
608 reg = <0x01c81000 0x1000>,
609 <0x01c82000 0x1000>,
610 <0x01c84000 0x2000>,
611 <0x01c86000 0x2000>;
612 interrupt-controller;
613 #interrupt-cells = <3>;
614 interrupts = <1 9 0xf04>;
615 };
616 };
617};