Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 1 | /* fuc microcode for nvc0 PGRAPH/GPC |
| 2 | * |
| 3 | * Copyright 2011 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Ben Skeggs |
| 24 | */ |
| 25 | |
| 26 | /* To build: |
| 27 | * m4 nvc0_grgpc.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_grgpc.fuc.h |
| 28 | */ |
| 29 | |
| 30 | /* TODO |
| 31 | * - bracket certain functions with scratch writes, useful for debugging |
| 32 | * - watchdog timer around ctx operations |
| 33 | */ |
| 34 | |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 35 | .section #nvc0_grgpc_data |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 36 | include(`nvc0_graph.fuc') |
| 37 | gpc_id: .b32 0 |
| 38 | gpc_mmio_list_head: .b32 0 |
| 39 | gpc_mmio_list_tail: .b32 0 |
| 40 | |
| 41 | tpc_count: .b32 0 |
| 42 | tpc_mask: .b32 0 |
| 43 | tpc_mmio_list_head: .b32 0 |
| 44 | tpc_mmio_list_tail: .b32 0 |
| 45 | |
| 46 | cmd_queue: queue_init |
| 47 | |
| 48 | // chipset descriptions |
| 49 | chipsets: |
| 50 | .b8 0xc0 0 0 0 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 51 | .b16 #nvc0_gpc_mmio_head |
| 52 | .b16 #nvc0_gpc_mmio_tail |
| 53 | .b16 #nvc0_tpc_mmio_head |
| 54 | .b16 #nvc0_tpc_mmio_tail |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 55 | .b8 0xc1 0 0 0 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 56 | .b16 #nvc0_gpc_mmio_head |
| 57 | .b16 #nvc1_gpc_mmio_tail |
| 58 | .b16 #nvc0_tpc_mmio_head |
| 59 | .b16 #nvc1_tpc_mmio_tail |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 60 | .b8 0xc3 0 0 0 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 61 | .b16 #nvc0_gpc_mmio_head |
| 62 | .b16 #nvc0_gpc_mmio_tail |
| 63 | .b16 #nvc0_tpc_mmio_head |
| 64 | .b16 #nvc3_tpc_mmio_tail |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 65 | .b8 0xc4 0 0 0 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 66 | .b16 #nvc0_gpc_mmio_head |
| 67 | .b16 #nvc0_gpc_mmio_tail |
| 68 | .b16 #nvc0_tpc_mmio_head |
| 69 | .b16 #nvc3_tpc_mmio_tail |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 70 | .b8 0xc8 0 0 0 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 71 | .b16 #nvc0_gpc_mmio_head |
| 72 | .b16 #nvc0_gpc_mmio_tail |
| 73 | .b16 #nvc0_tpc_mmio_head |
| 74 | .b16 #nvc0_tpc_mmio_tail |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 75 | .b8 0xce 0 0 0 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 76 | .b16 #nvc0_gpc_mmio_head |
| 77 | .b16 #nvc0_gpc_mmio_tail |
| 78 | .b16 #nvc0_tpc_mmio_head |
| 79 | .b16 #nvc3_tpc_mmio_tail |
Ben Skeggs | 3c23a7b | 2011-06-24 11:14:00 +1000 | [diff] [blame] | 80 | .b8 0xcf 0 0 0 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 81 | .b16 #nvc0_gpc_mmio_head |
| 82 | .b16 #nvc0_gpc_mmio_tail |
| 83 | .b16 #nvc0_tpc_mmio_head |
| 84 | .b16 #nvcf_tpc_mmio_tail |
Ben Skeggs | 0678409 | 2011-07-11 15:57:54 +1000 | [diff] [blame] | 85 | .b8 0xd9 0 0 0 |
| 86 | .b16 #nvd9_gpc_mmio_head |
| 87 | .b16 #nvd9_gpc_mmio_tail |
| 88 | .b16 #nvd9_tpc_mmio_head |
| 89 | .b16 #nvd9_tpc_mmio_tail |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 90 | .b8 0 0 0 0 |
| 91 | |
| 92 | // GPC mmio lists |
| 93 | nvc0_gpc_mmio_head: |
| 94 | mmctx_data(0x000380, 1) |
| 95 | mmctx_data(0x000400, 6) |
| 96 | mmctx_data(0x000450, 9) |
| 97 | mmctx_data(0x000600, 1) |
| 98 | mmctx_data(0x000684, 1) |
| 99 | mmctx_data(0x000700, 5) |
| 100 | mmctx_data(0x000800, 1) |
| 101 | mmctx_data(0x000808, 3) |
| 102 | mmctx_data(0x000828, 1) |
| 103 | mmctx_data(0x000830, 1) |
| 104 | mmctx_data(0x0008d8, 1) |
| 105 | mmctx_data(0x0008e0, 1) |
| 106 | mmctx_data(0x0008e8, 6) |
| 107 | mmctx_data(0x00091c, 1) |
| 108 | mmctx_data(0x000924, 3) |
| 109 | mmctx_data(0x000b00, 1) |
| 110 | mmctx_data(0x000b08, 6) |
| 111 | mmctx_data(0x000bb8, 1) |
| 112 | mmctx_data(0x000c08, 1) |
| 113 | mmctx_data(0x000c10, 8) |
| 114 | mmctx_data(0x000c80, 1) |
| 115 | mmctx_data(0x000c8c, 1) |
| 116 | mmctx_data(0x001000, 3) |
| 117 | mmctx_data(0x001014, 1) |
| 118 | nvc0_gpc_mmio_tail: |
| 119 | mmctx_data(0x000c6c, 1); |
| 120 | nvc1_gpc_mmio_tail: |
| 121 | |
Ben Skeggs | 0678409 | 2011-07-11 15:57:54 +1000 | [diff] [blame] | 122 | nvd9_gpc_mmio_head: |
| 123 | mmctx_data(0x000380, 1) |
| 124 | mmctx_data(0x000400, 2) |
| 125 | mmctx_data(0x00040c, 3) |
| 126 | mmctx_data(0x000450, 9) |
| 127 | mmctx_data(0x000600, 1) |
| 128 | mmctx_data(0x000684, 1) |
| 129 | mmctx_data(0x000700, 5) |
| 130 | mmctx_data(0x000800, 1) |
| 131 | mmctx_data(0x000808, 3) |
| 132 | mmctx_data(0x000828, 1) |
| 133 | mmctx_data(0x000830, 1) |
| 134 | mmctx_data(0x0008d8, 1) |
| 135 | mmctx_data(0x0008e0, 1) |
| 136 | mmctx_data(0x0008e8, 6) |
| 137 | mmctx_data(0x00091c, 1) |
| 138 | mmctx_data(0x000924, 3) |
| 139 | mmctx_data(0x000b00, 1) |
| 140 | mmctx_data(0x000b08, 6) |
| 141 | mmctx_data(0x000bb8, 1) |
| 142 | mmctx_data(0x000c08, 1) |
| 143 | mmctx_data(0x000c10, 8) |
| 144 | mmctx_data(0x000c6c, 1) |
| 145 | mmctx_data(0x000c80, 1) |
| 146 | mmctx_data(0x000c8c, 1) |
| 147 | mmctx_data(0x001000, 3) |
| 148 | mmctx_data(0x001014, 1) |
| 149 | nvd9_gpc_mmio_tail: |
| 150 | |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 151 | // TPC mmio lists |
| 152 | nvc0_tpc_mmio_head: |
| 153 | mmctx_data(0x000018, 1) |
| 154 | mmctx_data(0x00003c, 1) |
| 155 | mmctx_data(0x000048, 1) |
| 156 | mmctx_data(0x000064, 1) |
| 157 | mmctx_data(0x000088, 1) |
| 158 | mmctx_data(0x000200, 6) |
| 159 | mmctx_data(0x00021c, 2) |
| 160 | mmctx_data(0x000300, 6) |
| 161 | mmctx_data(0x0003d0, 1) |
| 162 | mmctx_data(0x0003e0, 2) |
| 163 | mmctx_data(0x000400, 3) |
| 164 | mmctx_data(0x000420, 1) |
| 165 | mmctx_data(0x0004b0, 1) |
| 166 | mmctx_data(0x0004e8, 1) |
| 167 | mmctx_data(0x0004f4, 1) |
| 168 | mmctx_data(0x000520, 2) |
| 169 | mmctx_data(0x000604, 4) |
| 170 | mmctx_data(0x000644, 20) |
| 171 | mmctx_data(0x000698, 1) |
| 172 | mmctx_data(0x000750, 2) |
| 173 | nvc0_tpc_mmio_tail: |
| 174 | mmctx_data(0x000758, 1) |
| 175 | mmctx_data(0x0002c4, 1) |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 176 | mmctx_data(0x0006e0, 1) |
Ben Skeggs | 3c23a7b | 2011-06-24 11:14:00 +1000 | [diff] [blame] | 177 | nvcf_tpc_mmio_tail: |
| 178 | mmctx_data(0x0004bc, 1) |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 179 | nvc3_tpc_mmio_tail: |
| 180 | mmctx_data(0x000544, 1) |
| 181 | nvc1_tpc_mmio_tail: |
| 182 | |
Ben Skeggs | 0678409 | 2011-07-11 15:57:54 +1000 | [diff] [blame] | 183 | nvd9_tpc_mmio_head: |
| 184 | mmctx_data(0x000018, 1) |
| 185 | mmctx_data(0x00003c, 1) |
| 186 | mmctx_data(0x000048, 1) |
| 187 | mmctx_data(0x000064, 1) |
| 188 | mmctx_data(0x000088, 1) |
| 189 | mmctx_data(0x000200, 6) |
| 190 | mmctx_data(0x00021c, 2) |
| 191 | mmctx_data(0x0002c4, 1) |
| 192 | mmctx_data(0x000300, 6) |
| 193 | mmctx_data(0x0003d0, 1) |
| 194 | mmctx_data(0x0003e0, 2) |
| 195 | mmctx_data(0x000400, 3) |
| 196 | mmctx_data(0x000420, 3) |
| 197 | mmctx_data(0x0004b0, 1) |
| 198 | mmctx_data(0x0004e8, 1) |
| 199 | mmctx_data(0x0004f4, 1) |
| 200 | mmctx_data(0x000520, 2) |
| 201 | mmctx_data(0x000544, 1) |
| 202 | mmctx_data(0x000604, 4) |
| 203 | mmctx_data(0x000644, 20) |
| 204 | mmctx_data(0x000698, 1) |
| 205 | mmctx_data(0x0006e0, 1) |
| 206 | mmctx_data(0x000750, 3) |
| 207 | nvd9_tpc_mmio_tail: |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 208 | |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 209 | .section #nvc0_grgpc_code |
| 210 | bra #init |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 211 | define(`include_code') |
| 212 | include(`nvc0_graph.fuc') |
| 213 | |
| 214 | // reports an exception to the host |
| 215 | // |
| 216 | // In: $r15 error code (see nvc0_graph.fuc) |
| 217 | // |
| 218 | error: |
| 219 | push $r14 |
| 220 | mov $r14 -0x67ec // 0x9814 |
| 221 | sethi $r14 0x400000 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 222 | call #nv_wr32 // HUB_CTXCTL_CC_SCRATCH[5] = error code |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 223 | add b32 $r14 0x41c |
| 224 | mov $r15 1 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 225 | call #nv_wr32 // HUB_CTXCTL_INTR_UP_SET |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 226 | pop $r14 |
| 227 | ret |
| 228 | |
| 229 | // GPC fuc initialisation, executed by triggering ucode start, will |
| 230 | // fall through to main loop after completion. |
| 231 | // |
| 232 | // Input: |
| 233 | // CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh) |
| 234 | // CC_SCRATCH[1]: context base |
| 235 | // |
| 236 | // Output: |
| 237 | // CC_SCRATCH[0]: |
| 238 | // 31:31: set to signal completion |
| 239 | // CC_SCRATCH[1]: |
| 240 | // 31:0: GPC context size |
| 241 | // |
| 242 | init: |
| 243 | clear b32 $r0 |
| 244 | mov $sp $r0 |
| 245 | |
| 246 | // enable fifo access |
| 247 | mov $r1 0x1200 |
| 248 | mov $r2 2 |
| 249 | iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE |
| 250 | |
| 251 | // setup i0 handler, and route all interrupts to it |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 252 | mov $r1 #ih |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 253 | mov $iv0 $r1 |
| 254 | mov $r1 0x400 |
| 255 | iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH |
| 256 | |
| 257 | // enable fifo interrupt |
| 258 | mov $r2 4 |
| 259 | iowr I[$r1 + 0x000] $r2 // INTR_EN_SET |
| 260 | |
| 261 | // enable interrupts |
| 262 | bset $flags ie0 |
| 263 | |
| 264 | // figure out which GPC we are, and how many TPCs we have |
| 265 | mov $r1 0x608 |
| 266 | shl b32 $r1 6 |
| 267 | iord $r2 I[$r1 + 0x000] // UNITS |
| 268 | mov $r3 1 |
| 269 | and $r2 0x1f |
| 270 | shl b32 $r3 $r2 |
| 271 | sub b32 $r3 1 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 272 | st b32 D[$r0 + #tpc_count] $r2 |
| 273 | st b32 D[$r0 + #tpc_mask] $r3 |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 274 | add b32 $r1 0x400 |
| 275 | iord $r2 I[$r1 + 0x000] // MYINDEX |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 276 | st b32 D[$r0 + #gpc_id] $r2 |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 277 | |
| 278 | // find context data for this chipset |
| 279 | mov $r2 0x800 |
| 280 | shl b32 $r2 6 |
| 281 | iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0] |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 282 | mov $r1 #chipsets - 12 |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 283 | init_find_chipset: |
| 284 | add b32 $r1 12 |
| 285 | ld b32 $r3 D[$r1 + 0x00] |
| 286 | cmpu b32 $r3 $r2 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 287 | bra e #init_context |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 288 | cmpu b32 $r3 0 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 289 | bra ne #init_find_chipset |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 290 | // unknown chipset |
| 291 | ret |
| 292 | |
| 293 | // initialise context base, and size tracking |
| 294 | init_context: |
| 295 | mov $r2 0x800 |
| 296 | shl b32 $r2 6 |
| 297 | iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base |
| 298 | clear b32 $r3 // track GPC context size here |
| 299 | |
| 300 | // set mmctx base addresses now so we don't have to do it later, |
| 301 | // they don't currently ever change |
| 302 | mov $r4 0x700 |
| 303 | shl b32 $r4 6 |
| 304 | shr b32 $r5 $r2 8 |
| 305 | iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE |
| 306 | iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE |
| 307 | |
| 308 | // calculate GPC mmio context size, store the chipset-specific |
| 309 | // mmio list pointers somewhere we can get at them later without |
| 310 | // re-parsing the chipset list |
| 311 | clear b32 $r14 |
| 312 | clear b32 $r15 |
| 313 | ld b16 $r14 D[$r1 + 4] |
| 314 | ld b16 $r15 D[$r1 + 6] |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 315 | st b16 D[$r0 + #gpc_mmio_list_head] $r14 |
| 316 | st b16 D[$r0 + #gpc_mmio_list_tail] $r15 |
| 317 | call #mmctx_size |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 318 | add b32 $r2 $r15 |
| 319 | add b32 $r3 $r15 |
| 320 | |
| 321 | // calculate per-TPC mmio context size, store the list pointers |
| 322 | ld b16 $r14 D[$r1 + 8] |
| 323 | ld b16 $r15 D[$r1 + 10] |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 324 | st b16 D[$r0 + #tpc_mmio_list_head] $r14 |
| 325 | st b16 D[$r0 + #tpc_mmio_list_tail] $r15 |
| 326 | call #mmctx_size |
| 327 | ld b32 $r14 D[$r0 + #tpc_count] |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 328 | mulu $r14 $r15 |
| 329 | add b32 $r2 $r14 |
| 330 | add b32 $r3 $r14 |
| 331 | |
| 332 | // round up base/size to 256 byte boundary (for strand SWBASE) |
| 333 | add b32 $r4 0x1300 |
| 334 | shr b32 $r3 2 |
| 335 | iowr I[$r4 + 0x000] $r3 // MMCTX_LOAD_COUNT, wtf for?!? |
| 336 | shr b32 $r2 8 |
| 337 | shr b32 $r3 6 |
| 338 | add b32 $r2 1 |
| 339 | add b32 $r3 1 |
| 340 | shl b32 $r2 8 |
| 341 | shl b32 $r3 8 |
| 342 | |
| 343 | // calculate size of strand context data |
| 344 | mov b32 $r15 $r2 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 345 | call #strand_ctx_init |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 346 | add b32 $r3 $r15 |
| 347 | |
| 348 | // save context size, and tell HUB we're done |
| 349 | mov $r1 0x800 |
| 350 | shl b32 $r1 6 |
| 351 | iowr I[$r1 + 0x100] $r3 // CC_SCRATCH[1] = context size |
| 352 | add b32 $r1 0x800 |
| 353 | clear b32 $r2 |
| 354 | bset $r2 31 |
| 355 | iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000 |
| 356 | |
| 357 | // Main program loop, very simple, sleeps until woken up by the interrupt |
| 358 | // handler, pulls a command from the queue and executes its handler |
| 359 | // |
| 360 | main: |
| 361 | bset $flags $p0 |
| 362 | sleep $p0 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 363 | mov $r13 #cmd_queue |
| 364 | call #queue_get |
| 365 | bra $p1 #main |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 366 | |
| 367 | // 0x0000-0x0003 are all context transfers |
| 368 | cmpu b32 $r14 0x04 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 369 | bra nc #main_not_ctx_xfer |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 370 | // fetch $flags and mask off $p1/$p2 |
| 371 | mov $r1 $flags |
| 372 | mov $r2 0x0006 |
| 373 | not b32 $r2 |
| 374 | and $r1 $r2 |
| 375 | // set $p1/$p2 according to transfer type |
| 376 | shl b32 $r14 1 |
| 377 | or $r1 $r14 |
| 378 | mov $flags $r1 |
| 379 | // transfer context data |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 380 | call #ctx_xfer |
| 381 | bra #main |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 382 | |
| 383 | main_not_ctx_xfer: |
| 384 | shl b32 $r15 $r14 16 |
| 385 | or $r15 E_BAD_COMMAND |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 386 | call #error |
| 387 | bra #main |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 388 | |
| 389 | // interrupt handler |
| 390 | ih: |
| 391 | push $r8 |
| 392 | mov $r8 $flags |
| 393 | push $r8 |
| 394 | push $r9 |
| 395 | push $r10 |
| 396 | push $r11 |
| 397 | push $r13 |
| 398 | push $r14 |
| 399 | push $r15 |
| 400 | |
| 401 | // incoming fifo command? |
| 402 | iord $r10 I[$r0 + 0x200] // INTR |
| 403 | and $r11 $r10 0x00000004 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 404 | bra e #ih_no_fifo |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 405 | // queue incoming fifo command for later processing |
| 406 | mov $r11 0x1900 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 407 | mov $r13 #cmd_queue |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 408 | iord $r14 I[$r11 + 0x100] // FIFO_CMD |
| 409 | iord $r15 I[$r11 + 0x000] // FIFO_DATA |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 410 | call #queue_put |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 411 | add b32 $r11 0x400 |
| 412 | mov $r14 1 |
| 413 | iowr I[$r11 + 0x000] $r14 // FIFO_ACK |
| 414 | |
| 415 | // ack, and wake up main() |
| 416 | ih_no_fifo: |
| 417 | iowr I[$r0 + 0x100] $r10 // INTR_ACK |
| 418 | |
| 419 | pop $r15 |
| 420 | pop $r14 |
| 421 | pop $r13 |
| 422 | pop $r11 |
| 423 | pop $r10 |
| 424 | pop $r9 |
| 425 | pop $r8 |
| 426 | mov $flags $r8 |
| 427 | pop $r8 |
| 428 | bclr $flags $p0 |
| 429 | iret |
| 430 | |
| 431 | // Set this GPC's bit in HUB_BAR, used to signal completion of various |
| 432 | // activities to the HUB fuc |
| 433 | // |
| 434 | hub_barrier_done: |
| 435 | mov $r15 1 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 436 | ld b32 $r14 D[$r0 + #gpc_id] |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 437 | shl b32 $r15 $r14 |
| 438 | mov $r14 -0x6be8 // 0x409418 - HUB_BAR_SET |
| 439 | sethi $r14 0x400000 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 440 | call #nv_wr32 |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 441 | ret |
| 442 | |
| 443 | // Disables various things, waits a bit, and re-enables them.. |
| 444 | // |
| 445 | // Not sure how exactly this helps, perhaps "ENABLE" is not such a |
| 446 | // good description for the bits we turn off? Anyways, without this, |
| 447 | // funny things happen. |
| 448 | // |
| 449 | ctx_redswitch: |
| 450 | mov $r14 0x614 |
| 451 | shl b32 $r14 6 |
| 452 | mov $r15 0x020 |
| 453 | iowr I[$r14] $r15 // GPC_RED_SWITCH = POWER |
| 454 | mov $r15 8 |
| 455 | ctx_redswitch_delay: |
| 456 | sub b32 $r15 1 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 457 | bra ne #ctx_redswitch_delay |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 458 | mov $r15 0xa20 |
| 459 | iowr I[$r14] $r15 // GPC_RED_SWITCH = UNK11, ENABLE, POWER |
| 460 | ret |
| 461 | |
| 462 | // Transfer GPC context data between GPU and storage area |
| 463 | // |
| 464 | // In: $r15 context base address |
| 465 | // $p1 clear on save, set on load |
| 466 | // $p2 set if opposite direction done/will be done, so: |
| 467 | // on save it means: "a load will follow this save" |
| 468 | // on load it means: "a save preceeded this load" |
| 469 | // |
| 470 | ctx_xfer: |
| 471 | // set context base address |
| 472 | mov $r1 0xa04 |
| 473 | shl b32 $r1 6 |
| 474 | iowr I[$r1 + 0x000] $r15// MEM_BASE |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 475 | bra not $p1 #ctx_xfer_not_load |
| 476 | call #ctx_redswitch |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 477 | ctx_xfer_not_load: |
| 478 | |
| 479 | // strands |
| 480 | mov $r1 0x4afc |
| 481 | sethi $r1 0x20000 |
| 482 | mov $r2 0xc |
| 483 | iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 484 | call #strand_wait |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 485 | mov $r2 0x47fc |
| 486 | sethi $r2 0x20000 |
| 487 | iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00 |
| 488 | xbit $r2 $flags $p1 |
| 489 | add b32 $r2 3 |
| 490 | iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD) |
| 491 | |
| 492 | // mmio context |
| 493 | xbit $r10 $flags $p1 // direction |
| 494 | or $r10 2 // first |
| 495 | mov $r11 0x0000 |
| 496 | sethi $r11 0x500000 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 497 | ld b32 $r12 D[$r0 + #gpc_id] |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 498 | shl b32 $r12 15 |
| 499 | add b32 $r11 $r12 // base = NV_PGRAPH_GPCn |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 500 | ld b32 $r12 D[$r0 + #gpc_mmio_list_head] |
| 501 | ld b32 $r13 D[$r0 + #gpc_mmio_list_tail] |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 502 | mov $r14 0 // not multi |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 503 | call #mmctx_xfer |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 504 | |
| 505 | // per-TPC mmio context |
| 506 | xbit $r10 $flags $p1 // direction |
| 507 | or $r10 4 // last |
| 508 | mov $r11 0x4000 |
| 509 | sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 510 | ld b32 $r12 D[$r0 + #gpc_id] |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 511 | shl b32 $r12 15 |
| 512 | add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 513 | ld b32 $r12 D[$r0 + #tpc_mmio_list_head] |
| 514 | ld b32 $r13 D[$r0 + #tpc_mmio_list_tail] |
| 515 | ld b32 $r15 D[$r0 + #tpc_mask] |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 516 | mov $r14 0x800 // stride = 0x800 |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 517 | call #mmctx_xfer |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 518 | |
| 519 | // wait for strands to finish |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 520 | call #strand_wait |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 521 | |
| 522 | // if load, or a save without a load following, do some |
| 523 | // unknown stuff that's done after finishing a block of |
| 524 | // strand commands |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 525 | bra $p1 #ctx_xfer_post |
| 526 | bra not $p2 #ctx_xfer_done |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 527 | ctx_xfer_post: |
| 528 | mov $r1 0x4afc |
| 529 | sethi $r1 0x20000 |
| 530 | mov $r2 0xd |
| 531 | iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0d |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 532 | call #strand_wait |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 533 | |
| 534 | // mark completion in HUB's barrier |
| 535 | ctx_xfer_done: |
Ben Skeggs | be7f261 | 2011-10-28 12:06:42 +1000 | [diff] [blame] | 536 | call #hub_barrier_done |
Ben Skeggs | 0411de8 | 2011-05-25 18:32:44 +1000 | [diff] [blame] | 537 | ret |
| 538 | |
| 539 | .align 256 |