blob: 39614a47af1e301755f0cb94d25aa630079afcfb [file] [log] [blame]
nibble.maxd32f9ff2014-10-08 04:31:10 -03001/*
2 * SMI PCIe driver for DVBSky cards.
3 *
4 * Copyright (C) 2014 Max nibble <nibble.max@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include "smipcie.h"
18#include "m88ds3103.h"
19#include "m88ts2022.h"
nibble.max5eedd8d2014-11-04 11:45:58 -030020#include "m88rs6000t.h"
nibble.maxd32f9ff2014-10-08 04:31:10 -030021
22DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
23
24static int smi_hw_init(struct smi_dev *dev)
25{
26 u32 port_mux, port_ctrl, int_stat;
27
28 /* set port mux.*/
29 port_mux = smi_read(MUX_MODE_CTRL);
30 port_mux &= ~(rbPaMSMask);
31 port_mux |= rbPaMSDtvNoGpio;
32 port_mux &= ~(rbPbMSMask);
33 port_mux |= rbPbMSDtvNoGpio;
34 port_mux &= ~(0x0f0000);
35 port_mux |= 0x50000;
36 smi_write(MUX_MODE_CTRL, port_mux);
37
38 /* set DTV register.*/
39 /* Port A */
40 port_ctrl = smi_read(VIDEO_CTRL_STATUS_A);
41 port_ctrl &= ~0x01;
42 smi_write(VIDEO_CTRL_STATUS_A, port_ctrl);
43 port_ctrl = smi_read(MPEG2_CTRL_A);
44 port_ctrl &= ~0x40;
45 port_ctrl |= 0x80;
46 smi_write(MPEG2_CTRL_A, port_ctrl);
47 /* Port B */
48 port_ctrl = smi_read(VIDEO_CTRL_STATUS_B);
49 port_ctrl &= ~0x01;
50 smi_write(VIDEO_CTRL_STATUS_B, port_ctrl);
51 port_ctrl = smi_read(MPEG2_CTRL_B);
52 port_ctrl &= ~0x40;
53 port_ctrl |= 0x80;
54 smi_write(MPEG2_CTRL_B, port_ctrl);
55
56 /* disable and clear interrupt.*/
57 smi_write(MSI_INT_ENA_CLR, ALL_INT);
58 int_stat = smi_read(MSI_INT_STATUS);
59 smi_write(MSI_INT_STATUS_CLR, int_stat);
60
61 /* reset demod.*/
62 smi_clear(PERIPHERAL_CTRL, 0x0303);
63 msleep(50);
64 smi_set(PERIPHERAL_CTRL, 0x0101);
65 return 0;
66}
67
68/* i2c bit bus.*/
69static void smi_i2c_cfg(struct smi_dev *dev, u32 sw_ctl)
70{
71 u32 dwCtrl;
72
73 dwCtrl = smi_read(sw_ctl);
74 dwCtrl &= ~0x18; /* disable output.*/
75 dwCtrl |= 0x21; /* reset and software mode.*/
76 dwCtrl &= ~0xff00;
77 dwCtrl |= 0x6400;
78 smi_write(sw_ctl, dwCtrl);
79 msleep(20);
80 dwCtrl = smi_read(sw_ctl);
81 dwCtrl &= ~0x20;
82 smi_write(sw_ctl, dwCtrl);
83}
84
85static void smi_i2c_setsda(struct smi_dev *dev, int state, u32 sw_ctl)
86{
87 if (state) {
88 /* set as input.*/
89 smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
90 } else {
91 smi_clear(sw_ctl, SW_I2C_MSK_DAT_OUT);
92 /* set as output.*/
93 smi_set(sw_ctl, SW_I2C_MSK_DAT_EN);
94 }
95}
96
97static void smi_i2c_setscl(void *data, int state, u32 sw_ctl)
98{
99 struct smi_dev *dev = data;
100
101 if (state) {
102 /* set as input.*/
103 smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
104 } else {
105 smi_clear(sw_ctl, SW_I2C_MSK_CLK_OUT);
106 /* set as output.*/
107 smi_set(sw_ctl, SW_I2C_MSK_CLK_EN);
108 }
109}
110
111static int smi_i2c_getsda(void *data, u32 sw_ctl)
112{
113 struct smi_dev *dev = data;
114 /* set as input.*/
115 smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
116 udelay(1);
117 return (smi_read(sw_ctl) & SW_I2C_MSK_DAT_IN) ? 1 : 0;
118}
119
120static int smi_i2c_getscl(void *data, u32 sw_ctl)
121{
122 struct smi_dev *dev = data;
123 /* set as input.*/
124 smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
125 udelay(1);
126 return (smi_read(sw_ctl) & SW_I2C_MSK_CLK_IN) ? 1 : 0;
127}
128/* i2c 0.*/
129static void smi_i2c0_setsda(void *data, int state)
130{
131 struct smi_dev *dev = data;
132
133 smi_i2c_setsda(dev, state, I2C_A_SW_CTL);
134}
135
136static void smi_i2c0_setscl(void *data, int state)
137{
138 struct smi_dev *dev = data;
139
140 smi_i2c_setscl(dev, state, I2C_A_SW_CTL);
141}
142
143static int smi_i2c0_getsda(void *data)
144{
145 struct smi_dev *dev = data;
146
147 return smi_i2c_getsda(dev, I2C_A_SW_CTL);
148}
149
150static int smi_i2c0_getscl(void *data)
151{
152 struct smi_dev *dev = data;
153
154 return smi_i2c_getscl(dev, I2C_A_SW_CTL);
155}
156/* i2c 1.*/
157static void smi_i2c1_setsda(void *data, int state)
158{
159 struct smi_dev *dev = data;
160
161 smi_i2c_setsda(dev, state, I2C_B_SW_CTL);
162}
163
164static void smi_i2c1_setscl(void *data, int state)
165{
166 struct smi_dev *dev = data;
167
168 smi_i2c_setscl(dev, state, I2C_B_SW_CTL);
169}
170
171static int smi_i2c1_getsda(void *data)
172{
173 struct smi_dev *dev = data;
174
175 return smi_i2c_getsda(dev, I2C_B_SW_CTL);
176}
177
178static int smi_i2c1_getscl(void *data)
179{
180 struct smi_dev *dev = data;
181
182 return smi_i2c_getscl(dev, I2C_B_SW_CTL);
183}
184
185static int smi_i2c_init(struct smi_dev *dev)
186{
187 int ret;
188
189 /* i2c bus 0 */
190 smi_i2c_cfg(dev, I2C_A_SW_CTL);
191 i2c_set_adapdata(&dev->i2c_bus[0], dev);
192 strcpy(dev->i2c_bus[0].name, "SMI-I2C0");
193 dev->i2c_bus[0].owner = THIS_MODULE;
194 dev->i2c_bus[0].dev.parent = &dev->pci_dev->dev;
195 dev->i2c_bus[0].algo_data = &dev->i2c_bit[0];
196 dev->i2c_bit[0].data = dev;
197 dev->i2c_bit[0].setsda = smi_i2c0_setsda;
198 dev->i2c_bit[0].setscl = smi_i2c0_setscl;
199 dev->i2c_bit[0].getsda = smi_i2c0_getsda;
200 dev->i2c_bit[0].getscl = smi_i2c0_getscl;
201 dev->i2c_bit[0].udelay = 12;
202 dev->i2c_bit[0].timeout = 10;
203 /* Raise SCL and SDA */
204 smi_i2c0_setsda(dev, 1);
205 smi_i2c0_setscl(dev, 1);
206
207 ret = i2c_bit_add_bus(&dev->i2c_bus[0]);
208 if (ret < 0)
209 return ret;
210
211 /* i2c bus 1 */
212 smi_i2c_cfg(dev, I2C_B_SW_CTL);
213 i2c_set_adapdata(&dev->i2c_bus[1], dev);
214 strcpy(dev->i2c_bus[1].name, "SMI-I2C1");
215 dev->i2c_bus[1].owner = THIS_MODULE;
216 dev->i2c_bus[1].dev.parent = &dev->pci_dev->dev;
217 dev->i2c_bus[1].algo_data = &dev->i2c_bit[1];
218 dev->i2c_bit[1].data = dev;
219 dev->i2c_bit[1].setsda = smi_i2c1_setsda;
220 dev->i2c_bit[1].setscl = smi_i2c1_setscl;
221 dev->i2c_bit[1].getsda = smi_i2c1_getsda;
222 dev->i2c_bit[1].getscl = smi_i2c1_getscl;
223 dev->i2c_bit[1].udelay = 12;
224 dev->i2c_bit[1].timeout = 10;
225 /* Raise SCL and SDA */
226 smi_i2c1_setsda(dev, 1);
227 smi_i2c1_setscl(dev, 1);
228
229 ret = i2c_bit_add_bus(&dev->i2c_bus[1]);
230 if (ret < 0)
231 i2c_del_adapter(&dev->i2c_bus[0]);
232
233 return ret;
234}
235
236static void smi_i2c_exit(struct smi_dev *dev)
237{
238 i2c_del_adapter(&dev->i2c_bus[0]);
239 i2c_del_adapter(&dev->i2c_bus[1]);
240}
241
242static int smi_read_eeprom(struct i2c_adapter *i2c, u16 reg, u8 *data, u16 size)
243{
244 int ret;
245 u8 b0[2] = { (reg >> 8) & 0xff, reg & 0xff };
246
247 struct i2c_msg msg[] = {
248 { .addr = 0x50, .flags = 0,
249 .buf = b0, .len = 2 },
250 { .addr = 0x50, .flags = I2C_M_RD,
251 .buf = data, .len = size }
252 };
253
254 ret = i2c_transfer(i2c, msg, 2);
255
256 if (ret != 2) {
257 dev_err(&i2c->dev, "%s: reg=0x%x (error=%d)\n",
258 __func__, reg, ret);
259 return ret;
260 }
261 return ret;
262}
263
264/* ts port interrupt operations */
265static void smi_port_disableInterrupt(struct smi_port *port)
266{
267 struct smi_dev *dev = port->dev;
268
269 smi_write(MSI_INT_ENA_CLR,
270 (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
271}
272
273static void smi_port_enableInterrupt(struct smi_port *port)
274{
275 struct smi_dev *dev = port->dev;
276
277 smi_write(MSI_INT_ENA_SET,
278 (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
279}
280
281static void smi_port_clearInterrupt(struct smi_port *port)
282{
283 struct smi_dev *dev = port->dev;
284
285 smi_write(MSI_INT_STATUS_CLR,
286 (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
287}
288
289/* tasklet handler: DMA data to dmx.*/
290static void smi_dma_xfer(unsigned long data)
291{
292 struct smi_port *port = (struct smi_port *) data;
293 struct smi_dev *dev = port->dev;
294 u32 intr_status, finishedData, dmaManagement;
295 u8 dmaChan0State, dmaChan1State;
296
297 intr_status = port->_int_status;
298 dmaManagement = smi_read(port->DMA_MANAGEMENT);
299 dmaChan0State = (u8)((dmaManagement & 0x00000030) >> 4);
300 dmaChan1State = (u8)((dmaManagement & 0x00300000) >> 20);
301
302 /* CH-0 DMA interrupt.*/
303 if ((intr_status & port->_dmaInterruptCH0) && (dmaChan0State == 0x01)) {
304 dev_dbg(&dev->pci_dev->dev,
305 "Port[%d]-DMA CH0 engine complete successful !\n",
306 port->idx);
307 finishedData = smi_read(port->DMA_CHAN0_TRANS_STATE);
308 finishedData &= 0x003FFFFF;
309 /* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
310 * indicate dma total transfer length and
311 * zero of [21:0] indicate dma total transfer length
312 * equal to 0x400000 (4MB)*/
313 if (finishedData == 0)
314 finishedData = 0x00400000;
315 if (finishedData != SMI_TS_DMA_BUF_SIZE) {
316 dev_dbg(&dev->pci_dev->dev,
317 "DMA CH0 engine complete length mismatched, finish data=%d !\n",
318 finishedData);
319 }
320 dvb_dmx_swfilter_packets(&port->demux,
321 port->cpu_addr[0], (finishedData / 188));
322 /*dvb_dmx_swfilter(&port->demux,
323 port->cpu_addr[0], finishedData);*/
324 }
325 /* CH-1 DMA interrupt.*/
326 if ((intr_status & port->_dmaInterruptCH1) && (dmaChan1State == 0x01)) {
327 dev_dbg(&dev->pci_dev->dev,
328 "Port[%d]-DMA CH1 engine complete successful !\n",
329 port->idx);
330 finishedData = smi_read(port->DMA_CHAN1_TRANS_STATE);
331 finishedData &= 0x003FFFFF;
332 /* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
333 * indicate dma total transfer length and
334 * zero of [21:0] indicate dma total transfer length
335 * equal to 0x400000 (4MB)*/
336 if (finishedData == 0)
337 finishedData = 0x00400000;
338 if (finishedData != SMI_TS_DMA_BUF_SIZE) {
339 dev_dbg(&dev->pci_dev->dev,
340 "DMA CH1 engine complete length mismatched, finish data=%d !\n",
341 finishedData);
342 }
343 dvb_dmx_swfilter_packets(&port->demux,
344 port->cpu_addr[1], (finishedData / 188));
345 /*dvb_dmx_swfilter(&port->demux,
346 port->cpu_addr[1], finishedData);*/
347 }
348 /* restart DMA.*/
349 if (intr_status & port->_dmaInterruptCH0)
350 dmaManagement |= 0x00000002;
351 if (intr_status & port->_dmaInterruptCH1)
352 dmaManagement |= 0x00020000;
353 smi_write(port->DMA_MANAGEMENT, dmaManagement);
354 /* Re-enable interrupts */
355 smi_port_enableInterrupt(port);
356}
357
358static void smi_port_dma_free(struct smi_port *port)
359{
360 if (port->cpu_addr[0]) {
361 pci_free_consistent(port->dev->pci_dev, SMI_TS_DMA_BUF_SIZE,
362 port->cpu_addr[0], port->dma_addr[0]);
363 port->cpu_addr[0] = NULL;
364 }
365 if (port->cpu_addr[1]) {
366 pci_free_consistent(port->dev->pci_dev, SMI_TS_DMA_BUF_SIZE,
367 port->cpu_addr[1], port->dma_addr[1]);
368 port->cpu_addr[1] = NULL;
369 }
370}
371
372static int smi_port_init(struct smi_port *port, int dmaChanUsed)
373{
374 dev_dbg(&port->dev->pci_dev->dev,
375 "%s, port %d, dmaused %d\n", __func__, port->idx, dmaChanUsed);
376 port->enable = 0;
377 if (port->idx == 0) {
378 /* Port A */
379 port->_dmaInterruptCH0 = dmaChanUsed & 0x01;
380 port->_dmaInterruptCH1 = dmaChanUsed & 0x02;
381
382 port->DMA_CHAN0_ADDR_LOW = DMA_PORTA_CHAN0_ADDR_LOW;
383 port->DMA_CHAN0_ADDR_HI = DMA_PORTA_CHAN0_ADDR_HI;
384 port->DMA_CHAN0_TRANS_STATE = DMA_PORTA_CHAN0_TRANS_STATE;
385 port->DMA_CHAN0_CONTROL = DMA_PORTA_CHAN0_CONTROL;
386 port->DMA_CHAN1_ADDR_LOW = DMA_PORTA_CHAN1_ADDR_LOW;
387 port->DMA_CHAN1_ADDR_HI = DMA_PORTA_CHAN1_ADDR_HI;
388 port->DMA_CHAN1_TRANS_STATE = DMA_PORTA_CHAN1_TRANS_STATE;
389 port->DMA_CHAN1_CONTROL = DMA_PORTA_CHAN1_CONTROL;
390 port->DMA_MANAGEMENT = DMA_PORTA_MANAGEMENT;
391 } else {
392 /* Port B */
393 port->_dmaInterruptCH0 = (dmaChanUsed << 2) & 0x04;
394 port->_dmaInterruptCH1 = (dmaChanUsed << 2) & 0x08;
395
396 port->DMA_CHAN0_ADDR_LOW = DMA_PORTB_CHAN0_ADDR_LOW;
397 port->DMA_CHAN0_ADDR_HI = DMA_PORTB_CHAN0_ADDR_HI;
398 port->DMA_CHAN0_TRANS_STATE = DMA_PORTB_CHAN0_TRANS_STATE;
399 port->DMA_CHAN0_CONTROL = DMA_PORTB_CHAN0_CONTROL;
400 port->DMA_CHAN1_ADDR_LOW = DMA_PORTB_CHAN1_ADDR_LOW;
401 port->DMA_CHAN1_ADDR_HI = DMA_PORTB_CHAN1_ADDR_HI;
402 port->DMA_CHAN1_TRANS_STATE = DMA_PORTB_CHAN1_TRANS_STATE;
403 port->DMA_CHAN1_CONTROL = DMA_PORTB_CHAN1_CONTROL;
404 port->DMA_MANAGEMENT = DMA_PORTB_MANAGEMENT;
405 }
406
407 if (port->_dmaInterruptCH0) {
408 port->cpu_addr[0] = pci_alloc_consistent(port->dev->pci_dev,
409 SMI_TS_DMA_BUF_SIZE,
410 &port->dma_addr[0]);
411 if (!port->cpu_addr[0]) {
412 dev_err(&port->dev->pci_dev->dev,
413 "Port[%d] DMA CH0 memory allocation failed!\n",
414 port->idx);
415 goto err;
416 }
417 }
418
419 if (port->_dmaInterruptCH1) {
420 port->cpu_addr[1] = pci_alloc_consistent(port->dev->pci_dev,
421 SMI_TS_DMA_BUF_SIZE,
422 &port->dma_addr[1]);
423 if (!port->cpu_addr[1]) {
424 dev_err(&port->dev->pci_dev->dev,
425 "Port[%d] DMA CH1 memory allocation failed!\n",
426 port->idx);
427 goto err;
428 }
429 }
430
431 smi_port_disableInterrupt(port);
432 tasklet_init(&port->tasklet, smi_dma_xfer, (unsigned long)port);
433 tasklet_disable(&port->tasklet);
434 port->enable = 1;
435 return 0;
436err:
437 smi_port_dma_free(port);
438 return -ENOMEM;
439}
440
441static void smi_port_exit(struct smi_port *port)
442{
443 smi_port_disableInterrupt(port);
444 tasklet_kill(&port->tasklet);
445 smi_port_dma_free(port);
446 port->enable = 0;
447}
448
449static void smi_port_irq(struct smi_port *port, u32 int_status)
450{
451 u32 port_req_irq = port->_dmaInterruptCH0 | port->_dmaInterruptCH1;
452
453 if (int_status & port_req_irq) {
454 smi_port_disableInterrupt(port);
455 port->_int_status = int_status;
456 smi_port_clearInterrupt(port);
457 tasklet_schedule(&port->tasklet);
458 }
459}
460
461static irqreturn_t smi_irq_handler(int irq, void *dev_id)
462{
463 struct smi_dev *dev = dev_id;
464 struct smi_port *port0 = &dev->ts_port[0];
465 struct smi_port *port1 = &dev->ts_port[1];
466
467 u32 intr_status = smi_read(MSI_INT_STATUS);
468
469 /* ts0 interrupt.*/
470 if (dev->info->ts_0)
471 smi_port_irq(port0, intr_status);
472
473 /* ts1 interrupt.*/
474 if (dev->info->ts_1)
475 smi_port_irq(port1, intr_status);
476
477 return IRQ_HANDLED;
478}
479
Nibble Max344e2e52014-11-08 08:35:08 -0300480static struct i2c_client *smi_add_i2c_client(struct i2c_adapter *adapter,
481 struct i2c_board_info *info)
482{
483 struct i2c_client *client;
484
485 request_module(info->type);
486 client = i2c_new_device(adapter, info);
487 if (client == NULL || client->dev.driver == NULL)
488 goto err_add_i2c_client;
489
490 if (!try_module_get(client->dev.driver->owner)) {
491 i2c_unregister_device(client);
492 goto err_add_i2c_client;
493 }
494 return client;
495
496err_add_i2c_client:
497 client = NULL;
498 return client;
499}
500
501static void smi_del_i2c_client(struct i2c_client *client)
502{
503 module_put(client->dev.driver->owner);
504 i2c_unregister_device(client);
505}
506
nibble.maxd32f9ff2014-10-08 04:31:10 -0300507static const struct m88ds3103_config smi_dvbsky_m88ds3103_cfg = {
508 .i2c_addr = 0x68,
509 .clock = 27000000,
510 .i2c_wr_max = 33,
511 .clock_out = 0,
512 .ts_mode = M88DS3103_TS_PARALLEL,
513 .ts_clk = 16000,
514 .ts_clk_pol = 1,
515 .agc = 0x99,
516 .lnb_hv_pol = 0,
517 .lnb_en_pol = 1,
518};
519
520static int smi_dvbsky_m88ds3103_fe_attach(struct smi_port *port)
521{
522 int ret = 0;
523 struct smi_dev *dev = port->dev;
524 struct i2c_adapter *i2c;
525 /* tuner I2C module */
526 struct i2c_adapter *tuner_i2c_adapter;
527 struct i2c_client *tuner_client;
528 struct i2c_board_info tuner_info;
529 struct m88ts2022_config m88ts2022_config = {
Mauro Carvalho Chehab23222872014-11-03 18:13:33 -0200530 .clock = 27000000,
531 };
nibble.maxd32f9ff2014-10-08 04:31:10 -0300532 memset(&tuner_info, 0, sizeof(struct i2c_board_info));
533 i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
534
535 /* attach demod */
536 port->fe = dvb_attach(m88ds3103_attach,
537 &smi_dvbsky_m88ds3103_cfg, i2c, &tuner_i2c_adapter);
538 if (!port->fe) {
539 ret = -ENODEV;
540 return ret;
541 }
542 /* attach tuner */
543 m88ts2022_config.fe = port->fe;
544 strlcpy(tuner_info.type, "m88ts2022", I2C_NAME_SIZE);
545 tuner_info.addr = 0x60;
546 tuner_info.platform_data = &m88ts2022_config;
Nibble Max344e2e52014-11-08 08:35:08 -0300547 tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
548 if (!tuner_client) {
nibble.maxd32f9ff2014-10-08 04:31:10 -0300549 ret = -ENODEV;
550 goto err_tuner_i2c_device;
551 }
552
nibble.maxd32f9ff2014-10-08 04:31:10 -0300553 /* delegate signal strength measurement to tuner */
554 port->fe->ops.read_signal_strength =
555 port->fe->ops.tuner_ops.get_rf_strength;
556
557 port->i2c_client_tuner = tuner_client;
558 return ret;
559
nibble.maxd32f9ff2014-10-08 04:31:10 -0300560err_tuner_i2c_device:
561 dvb_frontend_detach(port->fe);
562 return ret;
563}
564
nibble.max5eedd8d2014-11-04 11:45:58 -0300565static const struct m88ds3103_config smi_dvbsky_m88rs6000_cfg = {
566 .i2c_addr = 0x69,
567 .clock = 27000000,
568 .i2c_wr_max = 33,
569 .ts_mode = M88DS3103_TS_PARALLEL,
570 .ts_clk = 16000,
571 .ts_clk_pol = 1,
572 .agc = 0x99,
573 .lnb_hv_pol = 0,
574 .lnb_en_pol = 1,
575};
576
577static int smi_dvbsky_m88rs6000_fe_attach(struct smi_port *port)
578{
579 int ret = 0;
580 struct smi_dev *dev = port->dev;
581 struct i2c_adapter *i2c;
582 /* tuner I2C module */
583 struct i2c_adapter *tuner_i2c_adapter;
584 struct i2c_client *tuner_client;
585 struct i2c_board_info tuner_info;
586 struct m88rs6000t_config m88rs6000t_config;
587
588 memset(&tuner_info, 0, sizeof(struct i2c_board_info));
589 i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
590
591 /* attach demod */
592 port->fe = dvb_attach(m88ds3103_attach,
593 &smi_dvbsky_m88rs6000_cfg, i2c, &tuner_i2c_adapter);
594 if (!port->fe) {
595 ret = -ENODEV;
596 return ret;
597 }
598 /* attach tuner */
599 m88rs6000t_config.fe = port->fe;
600 strlcpy(tuner_info.type, "m88rs6000t", I2C_NAME_SIZE);
601 tuner_info.addr = 0x21;
602 tuner_info.platform_data = &m88rs6000t_config;
Nibble Max344e2e52014-11-08 08:35:08 -0300603 tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
604 if (!tuner_client) {
nibble.max5eedd8d2014-11-04 11:45:58 -0300605 ret = -ENODEV;
606 goto err_tuner_i2c_device;
607 }
608
nibble.max5eedd8d2014-11-04 11:45:58 -0300609 /* delegate signal strength measurement to tuner */
610 port->fe->ops.read_signal_strength =
611 port->fe->ops.tuner_ops.get_rf_strength;
612
613 port->i2c_client_tuner = tuner_client;
614 return ret;
615
nibble.max5eedd8d2014-11-04 11:45:58 -0300616err_tuner_i2c_device:
617 dvb_frontend_detach(port->fe);
618 return ret;
619}
620
nibble.maxd32f9ff2014-10-08 04:31:10 -0300621static int smi_fe_init(struct smi_port *port)
622{
623 int ret = 0;
624 struct smi_dev *dev = port->dev;
625 struct dvb_adapter *adap = &port->dvb_adapter;
626 u8 mac_ee[16];
627
628 dev_dbg(&port->dev->pci_dev->dev,
629 "%s: port %d, fe_type = %d\n",
630 __func__, port->idx, port->fe_type);
631 switch (port->fe_type) {
632 case DVBSKY_FE_M88DS3103:
633 ret = smi_dvbsky_m88ds3103_fe_attach(port);
634 break;
nibble.max5eedd8d2014-11-04 11:45:58 -0300635 case DVBSKY_FE_M88RS6000:
636 ret = smi_dvbsky_m88rs6000_fe_attach(port);
637 break;
nibble.maxd32f9ff2014-10-08 04:31:10 -0300638 }
639 if (ret < 0)
640 return ret;
641
642 /* register dvb frontend */
643 ret = dvb_register_frontend(adap, port->fe);
644 if (ret < 0) {
Nibble Max344e2e52014-11-08 08:35:08 -0300645 if (port->i2c_client_tuner)
646 smi_del_i2c_client(port->i2c_client_tuner);
647 if (port->i2c_client_demod)
648 smi_del_i2c_client(port->i2c_client_demod);
nibble.maxd32f9ff2014-10-08 04:31:10 -0300649 dvb_frontend_detach(port->fe);
650 return ret;
651 }
652 /* init MAC.*/
653 ret = smi_read_eeprom(&dev->i2c_bus[0], 0xc0, mac_ee, 16);
654 dev_info(&port->dev->pci_dev->dev,
655 "DVBSky SMI PCIe MAC= %pM\n", mac_ee + (port->idx)*8);
656 memcpy(adap->proposed_mac, mac_ee + (port->idx)*8, 6);
657 return ret;
658}
659
660static void smi_fe_exit(struct smi_port *port)
661{
nibble.maxd32f9ff2014-10-08 04:31:10 -0300662 dvb_unregister_frontend(port->fe);
Nibble Max344e2e52014-11-08 08:35:08 -0300663 /* remove I2C demod and tuner */
664 if (port->i2c_client_tuner)
665 smi_del_i2c_client(port->i2c_client_tuner);
666 if (port->i2c_client_demod)
667 smi_del_i2c_client(port->i2c_client_demod);
nibble.maxd32f9ff2014-10-08 04:31:10 -0300668 dvb_frontend_detach(port->fe);
669}
670
671static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
672 int (*start_feed)(struct dvb_demux_feed *),
673 int (*stop_feed)(struct dvb_demux_feed *),
674 void *priv)
675{
676 dvbdemux->priv = priv;
677
678 dvbdemux->filternum = 256;
679 dvbdemux->feednum = 256;
680 dvbdemux->start_feed = start_feed;
681 dvbdemux->stop_feed = stop_feed;
682 dvbdemux->write_to_decoder = NULL;
683 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
684 DMX_SECTION_FILTERING |
685 DMX_MEMORY_BASED_FILTERING);
686 return dvb_dmx_init(dvbdemux);
687}
688
689static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
690 struct dvb_demux *dvbdemux,
691 struct dmx_frontend *hw_frontend,
692 struct dmx_frontend *mem_frontend,
693 struct dvb_adapter *dvb_adapter)
694{
695 int ret;
696
697 dmxdev->filternum = 256;
698 dmxdev->demux = &dvbdemux->dmx;
699 dmxdev->capabilities = 0;
700 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
701 if (ret < 0)
702 return ret;
703
704 hw_frontend->source = DMX_FRONTEND_0;
705 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
706 mem_frontend->source = DMX_MEMORY_FE;
707 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
708 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
709}
710
711static u32 smi_config_DMA(struct smi_port *port)
712{
713 struct smi_dev *dev = port->dev;
714 u32 totalLength = 0, dmaMemPtrLow, dmaMemPtrHi, dmaCtlReg;
715 u8 chanLatencyTimer = 0, dmaChanEnable = 1, dmaTransStart = 1;
716 u32 dmaManagement = 0, tlpTransUnit = DMA_TRANS_UNIT_188;
717 u8 tlpTc = 0, tlpTd = 1, tlpEp = 0, tlpAttr = 0;
718 u64 mem;
719
720 dmaManagement = smi_read(port->DMA_MANAGEMENT);
Mauro Carvalho Chehab23222872014-11-03 18:13:33 -0200721 /* Setup Channel-0 */
nibble.maxd32f9ff2014-10-08 04:31:10 -0300722 if (port->_dmaInterruptCH0) {
723 totalLength = SMI_TS_DMA_BUF_SIZE;
724 mem = port->dma_addr[0];
725 dmaMemPtrLow = mem & 0xffffffff;
726 dmaMemPtrHi = mem >> 32;
727 dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
728 | (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
729 dmaManagement |= dmaChanEnable | (dmaTransStart << 1)
730 | (chanLatencyTimer << 8);
731 /* write DMA register, start DMA engine */
732 smi_write(port->DMA_CHAN0_ADDR_LOW, dmaMemPtrLow);
733 smi_write(port->DMA_CHAN0_ADDR_HI, dmaMemPtrHi);
734 smi_write(port->DMA_CHAN0_CONTROL, dmaCtlReg);
735 }
736 /* Setup Channel-1 */
737 if (port->_dmaInterruptCH1) {
738 totalLength = SMI_TS_DMA_BUF_SIZE;
739 mem = port->dma_addr[1];
740 dmaMemPtrLow = mem & 0xffffffff;
741 dmaMemPtrHi = mem >> 32;
742 dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
743 | (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
744 dmaManagement |= (dmaChanEnable << 16) | (dmaTransStart << 17)
745 | (chanLatencyTimer << 24);
746 /* write DMA register, start DMA engine */
747 smi_write(port->DMA_CHAN1_ADDR_LOW, dmaMemPtrLow);
748 smi_write(port->DMA_CHAN1_ADDR_HI, dmaMemPtrHi);
749 smi_write(port->DMA_CHAN1_CONTROL, dmaCtlReg);
750 }
751 return dmaManagement;
752}
753
754static int smi_start_feed(struct dvb_demux_feed *dvbdmxfeed)
755{
756 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
757 struct smi_port *port = dvbdmx->priv;
758 struct smi_dev *dev = port->dev;
759 u32 dmaManagement;
760
761 if (port->users++ == 0) {
762 dmaManagement = smi_config_DMA(port);
763 smi_port_clearInterrupt(port);
764 smi_port_enableInterrupt(port);
765 smi_write(port->DMA_MANAGEMENT, dmaManagement);
766 tasklet_enable(&port->tasklet);
767 }
768 return port->users;
769}
770
771static int smi_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
772{
773 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
774 struct smi_port *port = dvbdmx->priv;
775 struct smi_dev *dev = port->dev;
776
777 if (--port->users)
778 return port->users;
779
780 tasklet_disable(&port->tasklet);
781 smi_port_disableInterrupt(port);
782 smi_clear(port->DMA_MANAGEMENT, 0x30003);
783 return 0;
784}
785
786static int smi_dvb_init(struct smi_port *port)
787{
788 int ret;
789 struct dvb_adapter *adap = &port->dvb_adapter;
790 struct dvb_demux *dvbdemux = &port->demux;
791
792 dev_dbg(&port->dev->pci_dev->dev,
793 "%s, port %d\n", __func__, port->idx);
794
795 ret = dvb_register_adapter(adap, "SMI_DVB", THIS_MODULE,
796 &port->dev->pci_dev->dev,
797 adapter_nr);
798 if (ret < 0) {
799 dev_err(&port->dev->pci_dev->dev, "Fail to register DVB adapter.\n");
800 return ret;
801 }
802 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
803 smi_start_feed,
804 smi_stop_feed, port);
805 if (ret < 0)
806 goto err_del_dvb_register_adapter;
807
808 ret = my_dvb_dmxdev_ts_card_init(&port->dmxdev, &port->demux,
809 &port->hw_frontend,
810 &port->mem_frontend, adap);
811 if (ret < 0)
812 goto err_del_dvb_dmx;
813
814 ret = dvb_net_init(adap, &port->dvbnet, port->dmxdev.demux);
815 if (ret < 0)
816 goto err_del_dvb_dmxdev;
817 return 0;
818err_del_dvb_dmxdev:
819 dvbdemux->dmx.close(&dvbdemux->dmx);
820 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
821 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
822 dvb_dmxdev_release(&port->dmxdev);
823err_del_dvb_dmx:
824 dvb_dmx_release(&port->demux);
825err_del_dvb_register_adapter:
826 dvb_unregister_adapter(&port->dvb_adapter);
827 return ret;
828}
829
830static void smi_dvb_exit(struct smi_port *port)
831{
832 struct dvb_demux *dvbdemux = &port->demux;
833
834 dvb_net_release(&port->dvbnet);
835
836 dvbdemux->dmx.close(&dvbdemux->dmx);
837 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
838 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
839 dvb_dmxdev_release(&port->dmxdev);
840 dvb_dmx_release(&port->demux);
841
842 dvb_unregister_adapter(&port->dvb_adapter);
843}
844
845static int smi_port_attach(struct smi_dev *dev,
846 struct smi_port *port, int index)
847{
848 int ret, dmachs;
849
850 port->dev = dev;
851 port->idx = index;
852 port->fe_type = (index == 0) ? dev->info->fe_0 : dev->info->fe_1;
853 dmachs = (index == 0) ? dev->info->ts_0 : dev->info->ts_1;
854 /* port init.*/
855 ret = smi_port_init(port, dmachs);
856 if (ret < 0)
857 return ret;
858 /* dvb init.*/
859 ret = smi_dvb_init(port);
860 if (ret < 0)
861 goto err_del_port_init;
862 /* fe init.*/
863 ret = smi_fe_init(port);
864 if (ret < 0)
865 goto err_del_dvb_init;
866 return 0;
867err_del_dvb_init:
868 smi_dvb_exit(port);
869err_del_port_init:
870 smi_port_exit(port);
871 return ret;
872}
873
874static void smi_port_detach(struct smi_port *port)
875{
876 smi_fe_exit(port);
877 smi_dvb_exit(port);
878 smi_port_exit(port);
879}
880
881static int smi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
882{
883 struct smi_dev *dev;
884 int ret = -ENOMEM;
885
886 if (pci_enable_device(pdev) < 0)
887 return -ENODEV;
888
889 dev = kzalloc(sizeof(struct smi_dev), GFP_KERNEL);
890 if (!dev) {
891 ret = -ENOMEM;
892 goto err_pci_disable_device;
893 }
894
895 dev->pci_dev = pdev;
896 pci_set_drvdata(pdev, dev);
897 dev->info = (struct smi_cfg_info *) id->driver_data;
898 dev_info(&dev->pci_dev->dev,
899 "card detected: %s\n", dev->info->name);
900
901 dev->nr = dev->info->type;
902 dev->lmmio = ioremap(pci_resource_start(dev->pci_dev, 0),
903 pci_resource_len(dev->pci_dev, 0));
904 if (!dev->lmmio) {
905 ret = -ENOMEM;
906 goto err_kfree;
907 }
908
909 /* should we set to 32bit DMA? */
910 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
911 if (ret < 0)
912 goto err_pci_iounmap;
913
914 pci_set_master(pdev);
915
916 ret = smi_hw_init(dev);
917 if (ret < 0)
918 goto err_pci_iounmap;
919
920 ret = smi_i2c_init(dev);
921 if (ret < 0)
922 goto err_pci_iounmap;
923
924 if (dev->info->ts_0) {
925 ret = smi_port_attach(dev, &dev->ts_port[0], 0);
926 if (ret < 0)
927 goto err_del_i2c_adaptor;
928 }
929
930 if (dev->info->ts_1) {
931 ret = smi_port_attach(dev, &dev->ts_port[1], 1);
932 if (ret < 0)
933 goto err_del_port0_attach;
934 }
935
936#ifdef CONFIG_PCI_MSI /* to do msi interrupt.???*/
937 if (pci_msi_enabled())
938 ret = pci_enable_msi(dev->pci_dev);
939 if (ret)
940 dev_info(&dev->pci_dev->dev, "MSI not available.\n");
941#endif
942
943 ret = request_irq(dev->pci_dev->irq, smi_irq_handler,
944 IRQF_SHARED, "SMI_PCIE", dev);
945 if (ret < 0)
946 goto err_del_port1_attach;
947
948 return 0;
949
950err_del_port1_attach:
951 if (dev->info->ts_1)
952 smi_port_detach(&dev->ts_port[1]);
953err_del_port0_attach:
954 if (dev->info->ts_0)
955 smi_port_detach(&dev->ts_port[0]);
956err_del_i2c_adaptor:
957 smi_i2c_exit(dev);
958err_pci_iounmap:
959 iounmap(dev->lmmio);
960err_kfree:
Hans Verkuil358486c2014-11-05 04:52:10 -0300961 pci_set_drvdata(pdev, NULL);
nibble.maxd32f9ff2014-10-08 04:31:10 -0300962 kfree(dev);
963err_pci_disable_device:
964 pci_disable_device(pdev);
965 return ret;
966}
967
968static void smi_remove(struct pci_dev *pdev)
969{
970 struct smi_dev *dev = pci_get_drvdata(pdev);
971
972 smi_write(MSI_INT_ENA_CLR, ALL_INT);
973 free_irq(dev->pci_dev->irq, dev);
974#ifdef CONFIG_PCI_MSI
975 pci_disable_msi(dev->pci_dev);
976#endif
977 if (dev->info->ts_1)
978 smi_port_detach(&dev->ts_port[1]);
979 if (dev->info->ts_0)
980 smi_port_detach(&dev->ts_port[0]);
981
982 smi_i2c_exit(dev);
983 iounmap(dev->lmmio);
Hans Verkuil358486c2014-11-05 04:52:10 -0300984 pci_set_drvdata(pdev, NULL);
nibble.maxd32f9ff2014-10-08 04:31:10 -0300985 pci_disable_device(pdev);
986 kfree(dev);
987}
988
989/* DVBSky cards */
990static struct smi_cfg_info dvbsky_s950_cfg = {
991 .type = SMI_DVBSKY_S950,
992 .name = "DVBSky S950 V3",
993 .ts_0 = SMI_TS_NULL,
994 .ts_1 = SMI_TS_DMA_BOTH,
995 .fe_0 = DVBSKY_FE_NULL,
996 .fe_1 = DVBSKY_FE_M88DS3103,
997};
998
nibble.max5eedd8d2014-11-04 11:45:58 -0300999static struct smi_cfg_info dvbsky_s952_cfg = {
1000 .type = SMI_DVBSKY_S952,
1001 .name = "DVBSky S952 V3",
1002 .ts_0 = SMI_TS_DMA_BOTH,
1003 .ts_1 = SMI_TS_DMA_BOTH,
1004 .fe_0 = DVBSKY_FE_M88RS6000,
1005 .fe_1 = DVBSKY_FE_M88RS6000,
1006};
1007
nibble.maxd32f9ff2014-10-08 04:31:10 -03001008/* PCI IDs */
1009#define SMI_ID(_subvend, _subdev, _driverdata) { \
1010 .vendor = SMI_VID, .device = SMI_PID, \
1011 .subvendor = _subvend, .subdevice = _subdev, \
1012 .driver_data = (unsigned long)&_driverdata }
1013
1014static const struct pci_device_id smi_id_table[] = {
1015 SMI_ID(0x4254, 0x0550, dvbsky_s950_cfg),
nibble.max5eedd8d2014-11-04 11:45:58 -03001016 SMI_ID(0x4254, 0x0552, dvbsky_s952_cfg),
nibble.maxd32f9ff2014-10-08 04:31:10 -03001017 {0}
1018};
1019MODULE_DEVICE_TABLE(pci, smi_id_table);
1020
1021static struct pci_driver smipcie_driver = {
1022 .name = "SMI PCIe driver",
1023 .id_table = smi_id_table,
1024 .probe = smi_probe,
1025 .remove = smi_remove,
1026};
1027
1028module_pci_driver(smipcie_driver);
1029
1030MODULE_AUTHOR("Max nibble <nibble.max@gmail.com>");
1031MODULE_DESCRIPTION("SMI PCIe driver");
1032MODULE_LICENSE("GPL");