Eric Huang | aabcb7c | 2015-08-26 16:52:28 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2015 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/slab.h> |
| 25 | #include <linux/fb.h> |
| 26 | #include "linux/delay.h" |
| 27 | |
| 28 | #include "hwmgr.h" |
| 29 | #include "fiji_smumgr.h" |
| 30 | #include "atombios.h" |
| 31 | #include "hardwaremanager.h" |
| 32 | #include "ppatomctrl.h" |
| 33 | #include "atombios.h" |
| 34 | #include "cgs_common.h" |
| 35 | #include "fiji_dyn_defaults.h" |
| 36 | #include "fiji_powertune.h" |
| 37 | #include "smu73.h" |
| 38 | #include "smu/smu_7_1_3_d.h" |
| 39 | #include "smu/smu_7_1_3_sh_mask.h" |
| 40 | #include "gmc/gmc_8_1_d.h" |
| 41 | #include "gmc/gmc_8_1_sh_mask.h" |
| 42 | #include "bif/bif_5_0_d.h" |
| 43 | #include "bif/bif_5_0_sh_mask.h" |
| 44 | #include "dce/dce_10_0_d.h" |
| 45 | #include "dce/dce_10_0_sh_mask.h" |
| 46 | #include "pppcielanes.h" |
| 47 | #include "fiji_hwmgr.h" |
| 48 | #include "tonga_processpptables.h" |
| 49 | #include "tonga_pptable.h" |
| 50 | #include "pp_debug.h" |
| 51 | #include "pp_acpi.h" |
Alex Deucher | 16881da | 2015-11-11 20:18:52 -0500 | [diff] [blame] | 52 | #include "amd_pcie_helpers.h" |
Eric Huang | aabcb7c | 2015-08-26 16:52:28 -0400 | [diff] [blame] | 53 | |
| 54 | #define VOLTAGE_SCALE 4 |
| 55 | #define SMC_RAM_END 0x40000 |
| 56 | #define VDDC_VDDCI_DELTA 300 |
| 57 | |
| 58 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28 |
| 59 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 |
| 60 | #define MC_SEQ_MISC0_GDDR5_VALUE 5 |
| 61 | |
| 62 | #define MC_CG_ARB_FREQ_F0 0x0a /* boot-up default */ |
| 63 | #define MC_CG_ARB_FREQ_F1 0x0b |
| 64 | #define MC_CG_ARB_FREQ_F2 0x0c |
| 65 | #define MC_CG_ARB_FREQ_F3 0x0d |
| 66 | |
| 67 | /* From smc_reg.h */ |
| 68 | #define SMC_CG_IND_START 0xc0030000 |
| 69 | #define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND */ |
| 70 | |
| 71 | #define VOLTAGE_SCALE 4 |
| 72 | #define VOLTAGE_VID_OFFSET_SCALE1 625 |
| 73 | #define VOLTAGE_VID_OFFSET_SCALE2 100 |
| 74 | |
| 75 | #define VDDC_VDDCI_DELTA 300 |
| 76 | |
| 77 | #define ixSWRST_COMMAND_1 0x1400103 |
| 78 | #define MC_SEQ_CNTL__CAC_EN_MASK 0x40000000 |
| 79 | |
| 80 | /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ |
| 81 | enum DPM_EVENT_SRC { |
| 82 | DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */ |
| 83 | DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */ |
| 84 | DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */ |
| 85 | DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */ |
| 86 | DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */ |
| 87 | }; |
| 88 | |
| 89 | enum DISPLAY_GAP { |
| 90 | DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */ |
| 91 | DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */ |
| 92 | DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. */ |
| 93 | DISPLAY_GAP_IGNORE = 3 /* Do not wait. */ |
| 94 | }; |
| 95 | |
| 96 | /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs |
| 97 | * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] |
| 98 | */ |
| 99 | uint16_t fiji_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0}, |
| 100 | {600, 1050, 6, 1} }; |
| 101 | |
| 102 | /* [FF, SS] type, [] 4 voltage ranges, and |
| 103 | * [Floor Freq, Boundary Freq, VID min , VID max] |
| 104 | */ |
| 105 | uint32_t fiji_clock_stretcher_ddt_table[2][4][4] = |
| 106 | { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} }, |
| 107 | { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } }; |
| 108 | |
| 109 | /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] |
| 110 | * (coming from PWR_CKS_CNTL.stretch_amount reg spec) |
| 111 | */ |
| 112 | uint8_t fiji_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5}, |
| 113 | {0, 2, 4, 5, 6, 5} }; |
| 114 | |
| 115 | const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic); |
| 116 | |
| 117 | struct fiji_power_state *cast_phw_fiji_power_state( |
| 118 | struct pp_hw_power_state *hw_ps) |
| 119 | { |
| 120 | PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic), |
| 121 | "Invalid Powerstate Type!", |
| 122 | return NULL;); |
| 123 | |
| 124 | return (struct fiji_power_state *)hw_ps; |
| 125 | } |
| 126 | |
| 127 | const struct fiji_power_state *cast_const_phw_fiji_power_state( |
| 128 | const struct pp_hw_power_state *hw_ps) |
| 129 | { |
| 130 | PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic), |
| 131 | "Invalid Powerstate Type!", |
| 132 | return NULL;); |
| 133 | |
| 134 | return (const struct fiji_power_state *)hw_ps; |
| 135 | } |
| 136 | |
| 137 | static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr) |
| 138 | { |
| 139 | return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, |
| 140 | CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) |
| 141 | ? true : false; |
| 142 | } |
| 143 | |
| 144 | static void fiji_init_dpm_defaults(struct pp_hwmgr *hwmgr) |
| 145 | { |
| 146 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 147 | struct fiji_ulv_parm *ulv = &data->ulv; |
| 148 | |
| 149 | ulv->cg_ulv_parameter = PPFIJI_CGULVPARAMETER_DFLT; |
| 150 | data->voting_rights_clients0 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0; |
| 151 | data->voting_rights_clients1 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1; |
| 152 | data->voting_rights_clients2 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2; |
| 153 | data->voting_rights_clients3 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3; |
| 154 | data->voting_rights_clients4 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4; |
| 155 | data->voting_rights_clients5 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5; |
| 156 | data->voting_rights_clients6 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6; |
| 157 | data->voting_rights_clients7 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7; |
| 158 | |
| 159 | data->static_screen_threshold_unit = |
| 160 | PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT; |
| 161 | data->static_screen_threshold = |
| 162 | PPFIJI_STATICSCREENTHRESHOLD_DFLT; |
| 163 | |
| 164 | /* Unset ABM cap as it moved to DAL. |
| 165 | * Add PHM_PlatformCaps_NonABMSupportInPPLib |
| 166 | * for re-direct ABM related request to DAL |
| 167 | */ |
| 168 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 169 | PHM_PlatformCaps_ABM); |
| 170 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 171 | PHM_PlatformCaps_NonABMSupportInPPLib); |
| 172 | |
| 173 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 174 | PHM_PlatformCaps_DynamicACTiming); |
| 175 | |
| 176 | fiji_initialize_power_tune_defaults(hwmgr); |
| 177 | |
| 178 | data->mclk_stutter_mode_threshold = 60000; |
| 179 | data->pcie_gen_performance.max = PP_PCIEGen1; |
| 180 | data->pcie_gen_performance.min = PP_PCIEGen3; |
| 181 | data->pcie_gen_power_saving.max = PP_PCIEGen1; |
| 182 | data->pcie_gen_power_saving.min = PP_PCIEGen3; |
| 183 | data->pcie_lane_performance.max = 0; |
| 184 | data->pcie_lane_performance.min = 16; |
| 185 | data->pcie_lane_power_saving.max = 0; |
| 186 | data->pcie_lane_power_saving.min = 16; |
| 187 | |
| 188 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 189 | PHM_PlatformCaps_DynamicUVDState); |
| 190 | } |
| 191 | |
| 192 | static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, |
| 193 | phm_ppt_v1_voltage_lookup_table *lookup_table, |
| 194 | uint16_t virtual_voltage_id, int32_t *sclk) |
| 195 | { |
| 196 | uint8_t entryId; |
| 197 | uint8_t voltageId; |
| 198 | struct phm_ppt_v1_information *table_info = |
| 199 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 200 | |
| 201 | PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL); |
| 202 | |
| 203 | /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */ |
| 204 | for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) { |
| 205 | voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd; |
| 206 | if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id) |
| 207 | break; |
| 208 | } |
| 209 | |
| 210 | PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count, |
| 211 | "Can't find requested voltage id in vdd_dep_on_sclk table!", |
| 212 | return -EINVAL; |
| 213 | ); |
| 214 | |
| 215 | *sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk; |
| 216 | |
| 217 | return 0; |
| 218 | } |
| 219 | |
| 220 | /** |
| 221 | * Get Leakage VDDC based on leakage ID. |
| 222 | * |
| 223 | * @param hwmgr the address of the powerplay hardware manager. |
| 224 | * @return always 0 |
| 225 | */ |
| 226 | static int fiji_get_evv_voltages(struct pp_hwmgr *hwmgr) |
| 227 | { |
| 228 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 229 | uint16_t vv_id; |
| 230 | uint16_t vddc = 0; |
| 231 | uint16_t evv_default = 1150; |
| 232 | uint16_t i, j; |
| 233 | uint32_t sclk = 0; |
| 234 | struct phm_ppt_v1_information *table_info = |
| 235 | (struct phm_ppt_v1_information *)hwmgr->pptable; |
| 236 | struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = |
| 237 | table_info->vdd_dep_on_sclk; |
| 238 | int result; |
| 239 | |
| 240 | for (i = 0; i < FIJI_MAX_LEAKAGE_COUNT; i++) { |
| 241 | vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; |
| 242 | if (!fiji_get_sclk_for_voltage_evv(hwmgr, |
| 243 | table_info->vddc_lookup_table, vv_id, &sclk)) { |
| 244 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 245 | PHM_PlatformCaps_ClockStretcher)) { |
| 246 | for (j = 1; j < sclk_table->count; j++) { |
| 247 | if (sclk_table->entries[j].clk == sclk && |
| 248 | sclk_table->entries[j].cks_enable == 0) { |
| 249 | sclk += 5000; |
| 250 | break; |
| 251 | } |
| 252 | } |
| 253 | } |
| 254 | |
| 255 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 256 | PHM_PlatformCaps_EnableDriverEVV)) |
| 257 | result = atomctrl_calculate_voltage_evv_on_sclk(hwmgr, |
| 258 | VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc, i, true); |
| 259 | else |
| 260 | result = -EINVAL; |
| 261 | |
| 262 | if (result) |
| 263 | result = atomctrl_get_voltage_evv_on_sclk(hwmgr, |
| 264 | VOLTAGE_TYPE_VDDC, sclk,vv_id, &vddc); |
| 265 | |
| 266 | /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ |
| 267 | PP_ASSERT_WITH_CODE((vddc < 2000), |
| 268 | "Invalid VDDC value, greater than 2v!", result = -EINVAL;); |
| 269 | |
| 270 | if (result) |
| 271 | /* 1.15V is the default safe value for Fiji */ |
| 272 | vddc = evv_default; |
| 273 | |
| 274 | /* the voltage should not be zero nor equal to leakage ID */ |
| 275 | if (vddc != 0 && vddc != vv_id) { |
| 276 | data->vddc_leakage.actual_voltage |
| 277 | [data->vddc_leakage.count] = vddc; |
| 278 | data->vddc_leakage.leakage_id |
| 279 | [data->vddc_leakage.count] = vv_id; |
| 280 | data->vddc_leakage.count++; |
| 281 | } |
| 282 | } |
| 283 | } |
| 284 | return 0; |
| 285 | } |
| 286 | |
| 287 | /** |
| 288 | * Change virtual leakage voltage to actual value. |
| 289 | * |
| 290 | * @param hwmgr the address of the powerplay hardware manager. |
| 291 | * @param pointer to changing voltage |
| 292 | * @param pointer to leakage table |
| 293 | */ |
| 294 | static void fiji_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, |
| 295 | uint16_t *voltage, struct fiji_leakage_voltage *leakage_table) |
| 296 | { |
| 297 | uint32_t index; |
| 298 | |
| 299 | /* search for leakage voltage ID 0xff01 ~ 0xff08 */ |
| 300 | for (index = 0; index < leakage_table->count; index++) { |
| 301 | /* if this voltage matches a leakage voltage ID */ |
| 302 | /* patch with actual leakage voltage */ |
| 303 | if (leakage_table->leakage_id[index] == *voltage) { |
| 304 | *voltage = leakage_table->actual_voltage[index]; |
| 305 | break; |
| 306 | } |
| 307 | } |
| 308 | |
| 309 | if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) |
| 310 | printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n"); |
| 311 | } |
| 312 | |
| 313 | /** |
| 314 | * Patch voltage lookup table by EVV leakages. |
| 315 | * |
| 316 | * @param hwmgr the address of the powerplay hardware manager. |
| 317 | * @param pointer to voltage lookup table |
| 318 | * @param pointer to leakage table |
| 319 | * @return always 0 |
| 320 | */ |
| 321 | static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, |
| 322 | phm_ppt_v1_voltage_lookup_table *lookup_table, |
| 323 | struct fiji_leakage_voltage *leakage_table) |
| 324 | { |
| 325 | uint32_t i; |
| 326 | |
| 327 | for (i = 0; i < lookup_table->count; i++) |
| 328 | fiji_patch_with_vdd_leakage(hwmgr, |
| 329 | &lookup_table->entries[i].us_vdd, leakage_table); |
| 330 | |
| 331 | return 0; |
| 332 | } |
| 333 | |
| 334 | static int fiji_patch_clock_voltage_limits_with_vddc_leakage( |
| 335 | struct pp_hwmgr *hwmgr, struct fiji_leakage_voltage *leakage_table, |
| 336 | uint16_t *vddc) |
| 337 | { |
| 338 | struct phm_ppt_v1_information *table_info = |
| 339 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 340 | fiji_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); |
| 341 | hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = |
| 342 | table_info->max_clock_voltage_on_dc.vddc; |
| 343 | return 0; |
| 344 | } |
| 345 | |
| 346 | static int fiji_patch_voltage_dependency_tables_with_lookup_table( |
| 347 | struct pp_hwmgr *hwmgr) |
| 348 | { |
| 349 | uint8_t entryId; |
| 350 | uint8_t voltageId; |
| 351 | struct phm_ppt_v1_information *table_info = |
| 352 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 353 | |
| 354 | struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = |
| 355 | table_info->vdd_dep_on_sclk; |
| 356 | struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = |
| 357 | table_info->vdd_dep_on_mclk; |
| 358 | struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = |
| 359 | table_info->mm_dep_table; |
| 360 | |
| 361 | for (entryId = 0; entryId < sclk_table->count; ++entryId) { |
| 362 | voltageId = sclk_table->entries[entryId].vddInd; |
| 363 | sclk_table->entries[entryId].vddc = |
| 364 | table_info->vddc_lookup_table->entries[voltageId].us_vdd; |
| 365 | } |
| 366 | |
| 367 | for (entryId = 0; entryId < mclk_table->count; ++entryId) { |
| 368 | voltageId = mclk_table->entries[entryId].vddInd; |
| 369 | mclk_table->entries[entryId].vddc = |
| 370 | table_info->vddc_lookup_table->entries[voltageId].us_vdd; |
| 371 | } |
| 372 | |
| 373 | for (entryId = 0; entryId < mm_table->count; ++entryId) { |
| 374 | voltageId = mm_table->entries[entryId].vddcInd; |
| 375 | mm_table->entries[entryId].vddc = |
| 376 | table_info->vddc_lookup_table->entries[voltageId].us_vdd; |
| 377 | } |
| 378 | |
| 379 | return 0; |
| 380 | |
| 381 | } |
| 382 | |
| 383 | static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) |
| 384 | { |
| 385 | /* Need to determine if we need calculated voltage. */ |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) |
| 390 | { |
| 391 | /* Need to determine if we need calculated voltage from mm table. */ |
| 392 | return 0; |
| 393 | } |
| 394 | |
| 395 | static int fiji_sort_lookup_table(struct pp_hwmgr *hwmgr, |
| 396 | struct phm_ppt_v1_voltage_lookup_table *lookup_table) |
| 397 | { |
| 398 | uint32_t table_size, i, j; |
| 399 | struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record; |
| 400 | table_size = lookup_table->count; |
| 401 | |
| 402 | PP_ASSERT_WITH_CODE(0 != lookup_table->count, |
| 403 | "Lookup table is empty", return -EINVAL); |
| 404 | |
| 405 | /* Sorting voltages */ |
| 406 | for (i = 0; i < table_size - 1; i++) { |
| 407 | for (j = i + 1; j > 0; j--) { |
| 408 | if (lookup_table->entries[j].us_vdd < |
| 409 | lookup_table->entries[j - 1].us_vdd) { |
| 410 | tmp_voltage_lookup_record = lookup_table->entries[j - 1]; |
| 411 | lookup_table->entries[j - 1] = lookup_table->entries[j]; |
| 412 | lookup_table->entries[j] = tmp_voltage_lookup_record; |
| 413 | } |
| 414 | } |
| 415 | } |
| 416 | |
| 417 | return 0; |
| 418 | } |
| 419 | |
| 420 | static int fiji_complete_dependency_tables(struct pp_hwmgr *hwmgr) |
| 421 | { |
| 422 | int result = 0; |
| 423 | int tmp_result; |
| 424 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 425 | struct phm_ppt_v1_information *table_info = |
| 426 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 427 | |
| 428 | tmp_result = fiji_patch_lookup_table_with_leakage(hwmgr, |
| 429 | table_info->vddc_lookup_table, &(data->vddc_leakage)); |
| 430 | if (tmp_result) |
| 431 | result = tmp_result; |
| 432 | |
| 433 | tmp_result = fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, |
| 434 | &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); |
| 435 | if (tmp_result) |
| 436 | result = tmp_result; |
| 437 | |
| 438 | tmp_result = fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr); |
| 439 | if (tmp_result) |
| 440 | result = tmp_result; |
| 441 | |
| 442 | tmp_result = fiji_calc_voltage_dependency_tables(hwmgr); |
| 443 | if (tmp_result) |
| 444 | result = tmp_result; |
| 445 | |
| 446 | tmp_result = fiji_calc_mm_voltage_dependency_table(hwmgr); |
| 447 | if (tmp_result) |
| 448 | result = tmp_result; |
| 449 | |
| 450 | tmp_result = fiji_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); |
| 451 | if(tmp_result) |
| 452 | result = tmp_result; |
| 453 | |
| 454 | return result; |
| 455 | } |
| 456 | |
| 457 | static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) |
| 458 | { |
| 459 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 460 | struct phm_ppt_v1_information *table_info = |
| 461 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 462 | |
| 463 | struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = |
| 464 | table_info->vdd_dep_on_sclk; |
| 465 | struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = |
| 466 | table_info->vdd_dep_on_mclk; |
| 467 | |
| 468 | PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, |
| 469 | "VDD dependency on SCLK table is missing. \ |
| 470 | This table is mandatory", return -EINVAL); |
| 471 | PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, |
| 472 | "VDD dependency on SCLK table has to have is missing. \ |
| 473 | This table is mandatory", return -EINVAL); |
| 474 | |
| 475 | PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, |
| 476 | "VDD dependency on MCLK table is missing. \ |
| 477 | This table is mandatory", return -EINVAL); |
| 478 | PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, |
| 479 | "VDD dependency on MCLK table has to have is missing. \ |
| 480 | This table is mandatory", return -EINVAL); |
| 481 | |
| 482 | data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc; |
| 483 | data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table-> |
| 484 | entries[allowed_sclk_vdd_table->count - 1].vddc; |
| 485 | |
| 486 | table_info->max_clock_voltage_on_ac.sclk = |
| 487 | allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; |
| 488 | table_info->max_clock_voltage_on_ac.mclk = |
| 489 | allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; |
| 490 | table_info->max_clock_voltage_on_ac.vddc = |
| 491 | allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; |
| 492 | table_info->max_clock_voltage_on_ac.vddci = |
| 493 | allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; |
| 494 | |
| 495 | hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = |
| 496 | table_info->max_clock_voltage_on_ac.sclk; |
| 497 | hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = |
| 498 | table_info->max_clock_voltage_on_ac.mclk; |
| 499 | hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = |
| 500 | table_info->max_clock_voltage_on_ac.vddc; |
| 501 | hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = |
| 502 | table_info->max_clock_voltage_on_ac.vddci; |
| 503 | |
| 504 | return 0; |
| 505 | } |
| 506 | |
| 507 | static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr *hwmgr) |
| 508 | { |
| 509 | uint32_t speedCntl = 0; |
| 510 | |
| 511 | /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ |
| 512 | speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, |
| 513 | ixPCIE_LC_SPEED_CNTL); |
| 514 | return((uint16_t)PHM_GET_FIELD(speedCntl, |
| 515 | PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); |
| 516 | } |
| 517 | |
| 518 | static int fiji_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) |
| 519 | { |
| 520 | uint32_t link_width; |
| 521 | |
| 522 | /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ |
| 523 | link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, |
| 524 | PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD); |
| 525 | |
| 526 | PP_ASSERT_WITH_CODE((7 >= link_width), |
| 527 | "Invalid PCIe lane width!", return 0); |
| 528 | |
| 529 | return decode_pcie_lane_width(link_width); |
| 530 | } |
| 531 | |
| 532 | /** Patch the Boot State to match VBIOS boot clocks and voltage. |
| 533 | * |
| 534 | * @param hwmgr Pointer to the hardware manager. |
| 535 | * @param pPowerState The address of the PowerState instance being created. |
| 536 | * |
| 537 | */ |
| 538 | static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr, |
| 539 | struct pp_hw_power_state *hw_ps) |
| 540 | { |
| 541 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 542 | struct fiji_power_state *ps = (struct fiji_power_state *)hw_ps; |
| 543 | ATOM_FIRMWARE_INFO_V2_2 *fw_info; |
| 544 | uint16_t size; |
| 545 | uint8_t frev, crev; |
| 546 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
| 547 | |
| 548 | /* First retrieve the Boot clocks and VDDC from the firmware info table. |
| 549 | * We assume here that fw_info is unchanged if this call fails. |
| 550 | */ |
| 551 | fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table( |
| 552 | hwmgr->device, index, |
| 553 | &size, &frev, &crev); |
| 554 | if (!fw_info) |
| 555 | /* During a test, there is no firmware info table. */ |
| 556 | return 0; |
| 557 | |
| 558 | /* Patch the state. */ |
| 559 | data->vbios_boot_state.sclk_bootup_value = |
| 560 | le32_to_cpu(fw_info->ulDefaultEngineClock); |
| 561 | data->vbios_boot_state.mclk_bootup_value = |
| 562 | le32_to_cpu(fw_info->ulDefaultMemoryClock); |
| 563 | data->vbios_boot_state.mvdd_bootup_value = |
| 564 | le16_to_cpu(fw_info->usBootUpMVDDCVoltage); |
| 565 | data->vbios_boot_state.vddc_bootup_value = |
| 566 | le16_to_cpu(fw_info->usBootUpVDDCVoltage); |
| 567 | data->vbios_boot_state.vddci_bootup_value = |
| 568 | le16_to_cpu(fw_info->usBootUpVDDCIVoltage); |
| 569 | data->vbios_boot_state.pcie_gen_bootup_value = |
| 570 | fiji_get_current_pcie_speed(hwmgr); |
| 571 | data->vbios_boot_state.pcie_lane_bootup_value = |
| 572 | (uint16_t)fiji_get_current_pcie_lane_number(hwmgr); |
| 573 | |
| 574 | /* set boot power state */ |
| 575 | ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; |
| 576 | ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; |
| 577 | ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; |
| 578 | ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; |
| 579 | |
| 580 | return 0; |
| 581 | } |
| 582 | |
| 583 | static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr) |
| 584 | { |
| 585 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 586 | uint32_t i; |
| 587 | struct phm_ppt_v1_information *table_info = |
| 588 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 589 | bool stay_in_boot; |
| 590 | int result; |
| 591 | |
| 592 | data->dll_default_on = false; |
| 593 | data->sram_end = SMC_RAM_END; |
| 594 | |
| 595 | for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++) |
| 596 | data->activity_target[i] = FIJI_AT_DFLT; |
| 597 | |
| 598 | data->vddc_vddci_delta = VDDC_VDDCI_DELTA; |
| 599 | |
| 600 | data->mclk_activity_target = PPFIJI_MCLK_TARGETACTIVITY_DFLT; |
| 601 | data->mclk_dpm0_activity_target = 0xa; |
| 602 | |
| 603 | data->sclk_dpm_key_disabled = 0; |
| 604 | data->mclk_dpm_key_disabled = 0; |
| 605 | data->pcie_dpm_key_disabled = 0; |
| 606 | |
| 607 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 608 | PHM_PlatformCaps_UnTabledHardwareInterface); |
| 609 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 610 | PHM_PlatformCaps_TablelessHardwareInterface); |
| 611 | |
| 612 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 613 | PHM_PlatformCaps_SclkDeepSleep); |
| 614 | |
| 615 | data->gpio_debug = 0; |
| 616 | |
| 617 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 618 | PHM_PlatformCaps_DynamicPatchPowerState); |
| 619 | |
| 620 | /* need to set voltage control types before EVV patching */ |
| 621 | data->voltage_control = FIJI_VOLTAGE_CONTROL_NONE; |
| 622 | data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE; |
| 623 | data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE; |
| 624 | |
| 625 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
| 626 | VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) |
| 627 | data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2; |
| 628 | |
| 629 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 630 | PHM_PlatformCaps_EnableMVDDControl)) |
| 631 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
| 632 | VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) |
| 633 | data->mvdd_control = FIJI_VOLTAGE_CONTROL_BY_GPIO; |
| 634 | |
| 635 | if (data->mvdd_control == FIJI_VOLTAGE_CONTROL_NONE) |
| 636 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 637 | PHM_PlatformCaps_EnableMVDDControl); |
| 638 | |
| 639 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 640 | PHM_PlatformCaps_ControlVDDCI)) { |
| 641 | if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
| 642 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) |
| 643 | data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_GPIO; |
| 644 | else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, |
| 645 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) |
| 646 | data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_SVID2; |
| 647 | } |
| 648 | |
| 649 | if (data->vddci_control == FIJI_VOLTAGE_CONTROL_NONE) |
| 650 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 651 | PHM_PlatformCaps_ControlVDDCI); |
| 652 | |
| 653 | if (table_info && table_info->cac_dtp_table->usClockStretchAmount) |
| 654 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 655 | PHM_PlatformCaps_ClockStretcher); |
| 656 | |
| 657 | fiji_init_dpm_defaults(hwmgr); |
| 658 | |
| 659 | /* Get leakage voltage based on leakage ID. */ |
| 660 | fiji_get_evv_voltages(hwmgr); |
| 661 | |
| 662 | /* Patch our voltage dependency table with actual leakage voltage |
| 663 | * We need to perform leakage translation before it's used by other functions |
| 664 | */ |
| 665 | fiji_complete_dependency_tables(hwmgr); |
| 666 | |
| 667 | /* Parse pptable data read from VBIOS */ |
| 668 | fiji_set_private_data_based_on_pptable(hwmgr); |
| 669 | |
| 670 | /* ULV Support */ |
| 671 | data->ulv.ulv_supported = true; /* ULV feature is enabled by default */ |
| 672 | |
| 673 | /* Initalize Dynamic State Adjustment Rule Settings */ |
| 674 | result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr); |
| 675 | |
| 676 | if (!result) { |
| 677 | data->uvd_enabled = false; |
| 678 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 679 | PHM_PlatformCaps_EnableSMU7ThermalManagement); |
| 680 | data->vddc_phase_shed_control = false; |
| 681 | } |
| 682 | |
| 683 | stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 684 | PHM_PlatformCaps_StayInBootState); |
| 685 | |
| 686 | if (0 == result) { |
Alex Deucher | 464cea3 | 2015-11-11 21:02:16 -0500 | [diff] [blame^] | 687 | struct cgs_system_info sys_info = {0}; |
| 688 | |
Eric Huang | aabcb7c | 2015-08-26 16:52:28 -0400 | [diff] [blame] | 689 | data->is_tlu_enabled = 0; |
| 690 | hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = |
| 691 | FIJI_MAX_HARDWARE_POWERLEVELS; |
| 692 | hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; |
| 693 | hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; |
| 694 | |
Alex Deucher | 464cea3 | 2015-11-11 21:02:16 -0500 | [diff] [blame^] | 695 | sys_info.size = sizeof(struct cgs_system_info); |
| 696 | sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; |
| 697 | result = cgs_query_system_info(hwmgr->device, &sys_info); |
| 698 | if (result) |
| 699 | data->pcie_gen_cap = 0x30007; |
| 700 | else |
| 701 | data->pcie_gen_cap = (uint32_t)sys_info.value; |
| 702 | if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) |
| 703 | data->pcie_spc_cap = 20; |
| 704 | sys_info.size = sizeof(struct cgs_system_info); |
| 705 | sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; |
| 706 | result = cgs_query_system_info(hwmgr->device, &sys_info); |
| 707 | if (result) |
| 708 | data->pcie_lane_cap = 0x2f0000; |
| 709 | else |
| 710 | data->pcie_lane_cap = (uint32_t)sys_info.value; |
Eric Huang | aabcb7c | 2015-08-26 16:52:28 -0400 | [diff] [blame] | 711 | } else { |
| 712 | /* Ignore return value in here, we are cleaning up a mess. */ |
| 713 | tonga_hwmgr_backend_fini(hwmgr); |
| 714 | } |
| 715 | |
| 716 | return 0; |
| 717 | } |
| 718 | |
| 719 | /** |
| 720 | * Read clock related registers. |
| 721 | * |
| 722 | * @param hwmgr the address of the powerplay hardware manager. |
| 723 | * @return always 0 |
| 724 | */ |
| 725 | static int fiji_read_clock_registers(struct pp_hwmgr *hwmgr) |
| 726 | { |
| 727 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 728 | |
| 729 | data->clock_registers.vCG_SPLL_FUNC_CNTL = |
| 730 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 731 | ixCG_SPLL_FUNC_CNTL); |
| 732 | data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = |
| 733 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 734 | ixCG_SPLL_FUNC_CNTL_2); |
| 735 | data->clock_registers.vCG_SPLL_FUNC_CNTL_3 = |
| 736 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 737 | ixCG_SPLL_FUNC_CNTL_3); |
| 738 | data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = |
| 739 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 740 | ixCG_SPLL_FUNC_CNTL_4); |
| 741 | data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM = |
| 742 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 743 | ixCG_SPLL_SPREAD_SPECTRUM); |
| 744 | data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 = |
| 745 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 746 | ixCG_SPLL_SPREAD_SPECTRUM_2); |
| 747 | |
| 748 | return 0; |
| 749 | } |
| 750 | |
| 751 | /** |
| 752 | * Find out if memory is GDDR5. |
| 753 | * |
| 754 | * @param hwmgr the address of the powerplay hardware manager. |
| 755 | * @return always 0 |
| 756 | */ |
| 757 | static int fiji_get_memory_type(struct pp_hwmgr *hwmgr) |
| 758 | { |
| 759 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 760 | uint32_t temp; |
| 761 | |
| 762 | temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0); |
| 763 | |
| 764 | data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == |
| 765 | ((temp & MC_SEQ_MISC0_GDDR5_MASK) >> |
| 766 | MC_SEQ_MISC0_GDDR5_SHIFT)); |
| 767 | |
| 768 | return 0; |
| 769 | } |
| 770 | |
| 771 | /** |
| 772 | * Enables Dynamic Power Management by SMC |
| 773 | * |
| 774 | * @param hwmgr the address of the powerplay hardware manager. |
| 775 | * @return always 0 |
| 776 | */ |
| 777 | static int fiji_enable_acpi_power_management(struct pp_hwmgr *hwmgr) |
| 778 | { |
| 779 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 780 | GENERAL_PWRMGT, STATIC_PM_EN, 1); |
| 781 | |
| 782 | return 0; |
| 783 | } |
| 784 | |
| 785 | /** |
| 786 | * Initialize PowerGating States for different engines |
| 787 | * |
| 788 | * @param hwmgr the address of the powerplay hardware manager. |
| 789 | * @return always 0 |
| 790 | */ |
| 791 | static int fiji_init_power_gate_state(struct pp_hwmgr *hwmgr) |
| 792 | { |
| 793 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 794 | |
| 795 | data->uvd_power_gated = false; |
| 796 | data->vce_power_gated = false; |
| 797 | data->samu_power_gated = false; |
| 798 | data->acp_power_gated = false; |
| 799 | data->pg_acp_init = true; |
| 800 | |
| 801 | return 0; |
| 802 | } |
| 803 | |
| 804 | static int fiji_init_sclk_threshold(struct pp_hwmgr *hwmgr) |
| 805 | { |
| 806 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 807 | data->low_sclk_interrupt_threshold = 0; |
| 808 | |
| 809 | return 0; |
| 810 | } |
| 811 | |
| 812 | static int fiji_setup_asic_task(struct pp_hwmgr *hwmgr) |
| 813 | { |
| 814 | int tmp_result, result = 0; |
| 815 | |
| 816 | tmp_result = fiji_read_clock_registers(hwmgr); |
| 817 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 818 | "Failed to read clock registers!", result = tmp_result); |
| 819 | |
| 820 | tmp_result = fiji_get_memory_type(hwmgr); |
| 821 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 822 | "Failed to get memory type!", result = tmp_result); |
| 823 | |
| 824 | tmp_result = fiji_enable_acpi_power_management(hwmgr); |
| 825 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 826 | "Failed to enable ACPI power management!", result = tmp_result); |
| 827 | |
| 828 | tmp_result = fiji_init_power_gate_state(hwmgr); |
| 829 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 830 | "Failed to init power gate state!", result = tmp_result); |
| 831 | |
| 832 | tmp_result = tonga_get_mc_microcode_version(hwmgr); |
| 833 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 834 | "Failed to get MC microcode version!", result = tmp_result); |
| 835 | |
| 836 | tmp_result = fiji_init_sclk_threshold(hwmgr); |
| 837 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 838 | "Failed to init sclk threshold!", result = tmp_result); |
| 839 | |
| 840 | return result; |
| 841 | } |
| 842 | |
| 843 | /** |
| 844 | * Checks if we want to support voltage control |
| 845 | * |
| 846 | * @param hwmgr the address of the powerplay hardware manager. |
| 847 | */ |
| 848 | static bool fiji_voltage_control(const struct pp_hwmgr *hwmgr) |
| 849 | { |
| 850 | const struct fiji_hwmgr *data = |
| 851 | (const struct fiji_hwmgr *)(hwmgr->backend); |
| 852 | |
| 853 | return (FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control); |
| 854 | } |
| 855 | |
| 856 | /** |
| 857 | * Enable voltage control |
| 858 | * |
| 859 | * @param hwmgr the address of the powerplay hardware manager. |
| 860 | * @return always 0 |
| 861 | */ |
| 862 | static int fiji_enable_voltage_control(struct pp_hwmgr *hwmgr) |
| 863 | { |
| 864 | /* enable voltage control */ |
| 865 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 866 | GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); |
| 867 | |
| 868 | return 0; |
| 869 | } |
| 870 | |
| 871 | /** |
| 872 | * Remove repeated voltage values and create table with unique values. |
| 873 | * |
| 874 | * @param hwmgr the address of the powerplay hardware manager. |
| 875 | * @param vol_table the pointer to changing voltage table |
| 876 | * @return 0 in success |
| 877 | */ |
| 878 | |
| 879 | static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr, |
| 880 | struct pp_atomctrl_voltage_table *vol_table) |
| 881 | { |
| 882 | uint32_t i, j; |
| 883 | uint16_t vvalue; |
| 884 | bool found = false; |
| 885 | struct pp_atomctrl_voltage_table *table; |
| 886 | |
| 887 | PP_ASSERT_WITH_CODE((NULL != vol_table), |
| 888 | "Voltage Table empty.", return -EINVAL); |
| 889 | table = kzalloc(sizeof(struct pp_atomctrl_voltage_table), |
| 890 | GFP_KERNEL); |
| 891 | |
| 892 | if (NULL == table) |
| 893 | return -EINVAL; |
| 894 | |
| 895 | table->mask_low = vol_table->mask_low; |
| 896 | table->phase_delay = vol_table->phase_delay; |
| 897 | |
| 898 | for (i = 0; i < vol_table->count; i++) { |
| 899 | vvalue = vol_table->entries[i].value; |
| 900 | found = false; |
| 901 | |
| 902 | for (j = 0; j < table->count; j++) { |
| 903 | if (vvalue == table->entries[j].value) { |
| 904 | found = true; |
| 905 | break; |
| 906 | } |
| 907 | } |
| 908 | |
| 909 | if (!found) { |
| 910 | table->entries[table->count].value = vvalue; |
| 911 | table->entries[table->count].smio_low = |
| 912 | vol_table->entries[i].smio_low; |
| 913 | table->count++; |
| 914 | } |
| 915 | } |
| 916 | |
| 917 | memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table)); |
| 918 | kfree(table); |
| 919 | |
| 920 | return 0; |
| 921 | } |
| 922 | static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr, |
| 923 | phm_ppt_v1_clock_voltage_dependency_table *dep_table) |
| 924 | { |
| 925 | uint32_t i; |
| 926 | int result; |
| 927 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 928 | struct pp_atomctrl_voltage_table *vol_table = &(data->mvdd_voltage_table); |
| 929 | |
| 930 | PP_ASSERT_WITH_CODE((0 != dep_table->count), |
| 931 | "Voltage Dependency Table empty.", return -EINVAL); |
| 932 | |
| 933 | vol_table->mask_low = 0; |
| 934 | vol_table->phase_delay = 0; |
| 935 | vol_table->count = dep_table->count; |
| 936 | |
| 937 | for (i = 0; i < dep_table->count; i++) { |
| 938 | vol_table->entries[i].value = dep_table->entries[i].mvdd; |
| 939 | vol_table->entries[i].smio_low = 0; |
| 940 | } |
| 941 | |
| 942 | result = fiji_trim_voltage_table(hwmgr, vol_table); |
| 943 | PP_ASSERT_WITH_CODE((0 == result), |
| 944 | "Failed to trim MVDD table.", return result); |
| 945 | |
| 946 | return 0; |
| 947 | } |
| 948 | |
| 949 | static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr *hwmgr, |
| 950 | phm_ppt_v1_clock_voltage_dependency_table *dep_table) |
| 951 | { |
| 952 | uint32_t i; |
| 953 | int result; |
| 954 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 955 | struct pp_atomctrl_voltage_table *vol_table = &(data->vddci_voltage_table); |
| 956 | |
| 957 | PP_ASSERT_WITH_CODE((0 != dep_table->count), |
| 958 | "Voltage Dependency Table empty.", return -EINVAL); |
| 959 | |
| 960 | vol_table->mask_low = 0; |
| 961 | vol_table->phase_delay = 0; |
| 962 | vol_table->count = dep_table->count; |
| 963 | |
| 964 | for (i = 0; i < dep_table->count; i++) { |
| 965 | vol_table->entries[i].value = dep_table->entries[i].vddci; |
| 966 | vol_table->entries[i].smio_low = 0; |
| 967 | } |
| 968 | |
| 969 | result = fiji_trim_voltage_table(hwmgr, vol_table); |
| 970 | PP_ASSERT_WITH_CODE((0 == result), |
| 971 | "Failed to trim VDDCI table.", return result); |
| 972 | |
| 973 | return 0; |
| 974 | } |
| 975 | |
| 976 | static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr *hwmgr, |
| 977 | phm_ppt_v1_voltage_lookup_table *lookup_table) |
| 978 | { |
| 979 | int i = 0; |
| 980 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 981 | struct pp_atomctrl_voltage_table *vol_table = &(data->vddc_voltage_table); |
| 982 | |
| 983 | PP_ASSERT_WITH_CODE((0 != lookup_table->count), |
| 984 | "Voltage Lookup Table empty.", return -EINVAL); |
| 985 | |
| 986 | vol_table->mask_low = 0; |
| 987 | vol_table->phase_delay = 0; |
| 988 | |
| 989 | vol_table->count = lookup_table->count; |
| 990 | |
| 991 | for (i = 0; i < vol_table->count; i++) { |
| 992 | vol_table->entries[i].value = lookup_table->entries[i].us_vdd; |
| 993 | vol_table->entries[i].smio_low = 0; |
| 994 | } |
| 995 | |
| 996 | return 0; |
| 997 | } |
| 998 | |
| 999 | /* ---- Voltage Tables ---- |
| 1000 | * If the voltage table would be bigger than |
| 1001 | * what will fit into the state table on |
| 1002 | * the SMC keep only the higher entries. |
| 1003 | */ |
| 1004 | static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr *hwmgr, |
| 1005 | uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table) |
| 1006 | { |
| 1007 | unsigned int i, diff; |
| 1008 | |
| 1009 | if (vol_table->count <= max_vol_steps) |
| 1010 | return; |
| 1011 | |
| 1012 | diff = vol_table->count - max_vol_steps; |
| 1013 | |
| 1014 | for (i = 0; i < max_vol_steps; i++) |
| 1015 | vol_table->entries[i] = vol_table->entries[i + diff]; |
| 1016 | |
| 1017 | vol_table->count = max_vol_steps; |
| 1018 | |
| 1019 | return; |
| 1020 | } |
| 1021 | |
| 1022 | /** |
| 1023 | * Create Voltage Tables. |
| 1024 | * |
| 1025 | * @param hwmgr the address of the powerplay hardware manager. |
| 1026 | * @return always 0 |
| 1027 | */ |
| 1028 | static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr) |
| 1029 | { |
| 1030 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1031 | struct phm_ppt_v1_information *table_info = |
| 1032 | (struct phm_ppt_v1_information *)hwmgr->pptable; |
| 1033 | int result; |
| 1034 | |
| 1035 | if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { |
| 1036 | result = atomctrl_get_voltage_table_v3(hwmgr, |
| 1037 | VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, |
| 1038 | &(data->mvdd_voltage_table)); |
| 1039 | PP_ASSERT_WITH_CODE((0 == result), |
| 1040 | "Failed to retrieve MVDD table.", |
| 1041 | return result); |
| 1042 | } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { |
| 1043 | result = fiji_get_svi2_mvdd_voltage_table(hwmgr, |
| 1044 | table_info->vdd_dep_on_mclk); |
| 1045 | PP_ASSERT_WITH_CODE((0 == result), |
| 1046 | "Failed to retrieve SVI2 MVDD table from dependancy table.", |
| 1047 | return result;); |
| 1048 | } |
| 1049 | |
| 1050 | if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { |
| 1051 | result = atomctrl_get_voltage_table_v3(hwmgr, |
| 1052 | VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, |
| 1053 | &(data->vddci_voltage_table)); |
| 1054 | PP_ASSERT_WITH_CODE((0 == result), |
| 1055 | "Failed to retrieve VDDCI table.", |
| 1056 | return result); |
| 1057 | } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { |
| 1058 | result = fiji_get_svi2_vddci_voltage_table(hwmgr, |
| 1059 | table_info->vdd_dep_on_mclk); |
| 1060 | PP_ASSERT_WITH_CODE((0 == result), |
| 1061 | "Failed to retrieve SVI2 VDDCI table from dependancy table.", |
| 1062 | return result); |
| 1063 | } |
| 1064 | |
| 1065 | if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { |
| 1066 | result = fiji_get_svi2_vdd_voltage_table(hwmgr, |
| 1067 | table_info->vddc_lookup_table); |
| 1068 | PP_ASSERT_WITH_CODE((0 == result), |
| 1069 | "Failed to retrieve SVI2 VDDC table from lookup table.", |
| 1070 | return result); |
| 1071 | } |
| 1072 | |
| 1073 | PP_ASSERT_WITH_CODE( |
| 1074 | (data->vddc_voltage_table.count <= (SMU73_MAX_LEVELS_VDDC)), |
| 1075 | "Too many voltage values for VDDC. Trimming to fit state table.", |
| 1076 | fiji_trim_voltage_table_to_fit_state_table(hwmgr, |
| 1077 | SMU73_MAX_LEVELS_VDDC, &(data->vddc_voltage_table))); |
| 1078 | |
| 1079 | PP_ASSERT_WITH_CODE( |
| 1080 | (data->vddci_voltage_table.count <= (SMU73_MAX_LEVELS_VDDCI)), |
| 1081 | "Too many voltage values for VDDCI. Trimming to fit state table.", |
| 1082 | fiji_trim_voltage_table_to_fit_state_table(hwmgr, |
| 1083 | SMU73_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table))); |
| 1084 | |
| 1085 | PP_ASSERT_WITH_CODE( |
| 1086 | (data->mvdd_voltage_table.count <= (SMU73_MAX_LEVELS_MVDD)), |
| 1087 | "Too many voltage values for MVDD. Trimming to fit state table.", |
| 1088 | fiji_trim_voltage_table_to_fit_state_table(hwmgr, |
| 1089 | SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table))); |
| 1090 | |
| 1091 | return 0; |
| 1092 | } |
| 1093 | |
| 1094 | static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) |
| 1095 | { |
| 1096 | /* Program additional LP registers |
| 1097 | * that are no longer programmed by VBIOS |
| 1098 | */ |
| 1099 | cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, |
| 1100 | cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING)); |
| 1101 | cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, |
| 1102 | cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING)); |
| 1103 | cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, |
| 1104 | cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2)); |
| 1105 | cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, |
| 1106 | cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1)); |
| 1107 | cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, |
| 1108 | cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0)); |
| 1109 | cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, |
| 1110 | cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1)); |
| 1111 | cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, |
| 1112 | cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING)); |
| 1113 | |
| 1114 | return 0; |
| 1115 | } |
| 1116 | |
| 1117 | /** |
| 1118 | * Programs static screed detection parameters |
| 1119 | * |
| 1120 | * @param hwmgr the address of the powerplay hardware manager. |
| 1121 | * @return always 0 |
| 1122 | */ |
| 1123 | static int fiji_program_static_screen_threshold_parameters( |
| 1124 | struct pp_hwmgr *hwmgr) |
| 1125 | { |
| 1126 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1127 | |
| 1128 | /* Set static screen threshold unit */ |
| 1129 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 1130 | CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, |
| 1131 | data->static_screen_threshold_unit); |
| 1132 | /* Set static screen threshold */ |
| 1133 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 1134 | CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, |
| 1135 | data->static_screen_threshold); |
| 1136 | |
| 1137 | return 0; |
| 1138 | } |
| 1139 | |
| 1140 | /** |
| 1141 | * Setup display gap for glitch free memory clock switching. |
| 1142 | * |
| 1143 | * @param hwmgr the address of the powerplay hardware manager. |
| 1144 | * @return always 0 |
| 1145 | */ |
| 1146 | static int fiji_enable_display_gap(struct pp_hwmgr *hwmgr) |
| 1147 | { |
| 1148 | uint32_t displayGap = |
| 1149 | cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 1150 | ixCG_DISPLAY_GAP_CNTL); |
| 1151 | |
| 1152 | displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL, |
| 1153 | DISP_GAP, DISPLAY_GAP_IGNORE); |
| 1154 | |
| 1155 | displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL, |
| 1156 | DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); |
| 1157 | |
| 1158 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 1159 | ixCG_DISPLAY_GAP_CNTL, displayGap); |
| 1160 | |
| 1161 | return 0; |
| 1162 | } |
| 1163 | |
| 1164 | /** |
| 1165 | * Programs activity state transition voting clients |
| 1166 | * |
| 1167 | * @param hwmgr the address of the powerplay hardware manager. |
| 1168 | * @return always 0 |
| 1169 | */ |
| 1170 | static int fiji_program_voting_clients(struct pp_hwmgr *hwmgr) |
| 1171 | { |
| 1172 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1173 | |
| 1174 | /* Clear reset for voting clients before enabling DPM */ |
| 1175 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 1176 | SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); |
| 1177 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 1178 | SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); |
| 1179 | |
| 1180 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 1181 | ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0); |
| 1182 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 1183 | ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1); |
| 1184 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 1185 | ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2); |
| 1186 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 1187 | ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3); |
| 1188 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 1189 | ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4); |
| 1190 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 1191 | ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5); |
| 1192 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 1193 | ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6); |
| 1194 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 1195 | ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7); |
| 1196 | |
| 1197 | return 0; |
| 1198 | } |
| 1199 | |
| 1200 | /** |
| 1201 | * Get the location of various tables inside the FW image. |
| 1202 | * |
| 1203 | * @param hwmgr the address of the powerplay hardware manager. |
| 1204 | * @return always 0 |
| 1205 | */ |
| 1206 | static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) |
| 1207 | { |
| 1208 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1209 | struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); |
| 1210 | uint32_t tmp; |
| 1211 | int result; |
| 1212 | bool error = false; |
| 1213 | |
| 1214 | result = fiji_read_smc_sram_dword(hwmgr->smumgr, |
| 1215 | SMU7_FIRMWARE_HEADER_LOCATION + |
| 1216 | offsetof(SMU73_Firmware_Header, DpmTable), |
| 1217 | &tmp, data->sram_end); |
| 1218 | |
| 1219 | if (0 == result) |
| 1220 | data->dpm_table_start = tmp; |
| 1221 | |
| 1222 | error |= (0 != result); |
| 1223 | |
| 1224 | result = fiji_read_smc_sram_dword(hwmgr->smumgr, |
| 1225 | SMU7_FIRMWARE_HEADER_LOCATION + |
| 1226 | offsetof(SMU73_Firmware_Header, SoftRegisters), |
| 1227 | &tmp, data->sram_end); |
| 1228 | |
| 1229 | if (!result) { |
| 1230 | data->soft_regs_start = tmp; |
| 1231 | smu_data->soft_regs_start = tmp; |
| 1232 | } |
| 1233 | |
| 1234 | error |= (0 != result); |
| 1235 | |
| 1236 | result = fiji_read_smc_sram_dword(hwmgr->smumgr, |
| 1237 | SMU7_FIRMWARE_HEADER_LOCATION + |
| 1238 | offsetof(SMU73_Firmware_Header, mcRegisterTable), |
| 1239 | &tmp, data->sram_end); |
| 1240 | |
| 1241 | if (!result) |
| 1242 | data->mc_reg_table_start = tmp; |
| 1243 | |
| 1244 | result = fiji_read_smc_sram_dword(hwmgr->smumgr, |
| 1245 | SMU7_FIRMWARE_HEADER_LOCATION + |
| 1246 | offsetof(SMU73_Firmware_Header, FanTable), |
| 1247 | &tmp, data->sram_end); |
| 1248 | |
| 1249 | if (!result) |
| 1250 | data->fan_table_start = tmp; |
| 1251 | |
| 1252 | error |= (0 != result); |
| 1253 | |
| 1254 | result = fiji_read_smc_sram_dword(hwmgr->smumgr, |
| 1255 | SMU7_FIRMWARE_HEADER_LOCATION + |
| 1256 | offsetof(SMU73_Firmware_Header, mcArbDramTimingTable), |
| 1257 | &tmp, data->sram_end); |
| 1258 | |
| 1259 | if (!result) |
| 1260 | data->arb_table_start = tmp; |
| 1261 | |
| 1262 | error |= (0 != result); |
| 1263 | |
| 1264 | result = fiji_read_smc_sram_dword(hwmgr->smumgr, |
| 1265 | SMU7_FIRMWARE_HEADER_LOCATION + |
| 1266 | offsetof(SMU73_Firmware_Header, Version), |
| 1267 | &tmp, data->sram_end); |
| 1268 | |
| 1269 | if (!result) |
| 1270 | hwmgr->microcode_version_info.SMC = tmp; |
| 1271 | |
| 1272 | error |= (0 != result); |
| 1273 | |
| 1274 | return error ? -1 : 0; |
| 1275 | } |
| 1276 | |
| 1277 | /* Copy one arb setting to another and then switch the active set. |
| 1278 | * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants. |
| 1279 | */ |
| 1280 | static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, |
| 1281 | uint32_t arb_src, uint32_t arb_dest) |
| 1282 | { |
| 1283 | uint32_t mc_arb_dram_timing; |
| 1284 | uint32_t mc_arb_dram_timing2; |
| 1285 | uint32_t burst_time; |
| 1286 | uint32_t mc_cg_config; |
| 1287 | |
| 1288 | switch (arb_src) { |
| 1289 | case MC_CG_ARB_FREQ_F0: |
| 1290 | mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); |
| 1291 | mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); |
| 1292 | burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); |
| 1293 | break; |
| 1294 | case MC_CG_ARB_FREQ_F1: |
| 1295 | mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); |
| 1296 | mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); |
| 1297 | burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); |
| 1298 | break; |
| 1299 | default: |
| 1300 | return -EINVAL; |
| 1301 | } |
| 1302 | |
| 1303 | switch (arb_dest) { |
| 1304 | case MC_CG_ARB_FREQ_F0: |
| 1305 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); |
| 1306 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); |
| 1307 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); |
| 1308 | break; |
| 1309 | case MC_CG_ARB_FREQ_F1: |
| 1310 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); |
| 1311 | cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); |
| 1312 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); |
| 1313 | break; |
| 1314 | default: |
| 1315 | return -EINVAL; |
| 1316 | } |
| 1317 | |
| 1318 | mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); |
| 1319 | mc_cg_config |= 0x0000000F; |
| 1320 | cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); |
| 1321 | PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest); |
| 1322 | |
| 1323 | return 0; |
| 1324 | } |
| 1325 | |
| 1326 | /** |
| 1327 | * Initial switch from ARB F0->F1 |
| 1328 | * |
| 1329 | * @param hwmgr the address of the powerplay hardware manager. |
| 1330 | * @return always 0 |
| 1331 | * This function is to be called from the SetPowerState table. |
| 1332 | */ |
| 1333 | static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) |
| 1334 | { |
| 1335 | return fiji_copy_and_switch_arb_sets(hwmgr, |
| 1336 | MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); |
| 1337 | } |
| 1338 | |
| 1339 | static int fiji_reset_single_dpm_table(struct pp_hwmgr *hwmgr, |
| 1340 | struct fiji_single_dpm_table *dpm_table, uint32_t count) |
| 1341 | { |
| 1342 | int i; |
| 1343 | PP_ASSERT_WITH_CODE(count <= MAX_REGULAR_DPM_NUMBER, |
| 1344 | "Fatal error, can not set up single DPM table entries " |
| 1345 | "to exceed max number!",); |
| 1346 | |
| 1347 | dpm_table->count = count; |
| 1348 | for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) |
| 1349 | dpm_table->dpm_levels[i].enabled = false; |
| 1350 | |
| 1351 | return 0; |
| 1352 | } |
| 1353 | |
| 1354 | static void fiji_setup_pcie_table_entry( |
| 1355 | struct fiji_single_dpm_table *dpm_table, |
| 1356 | uint32_t index, uint32_t pcie_gen, |
| 1357 | uint32_t pcie_lanes) |
| 1358 | { |
| 1359 | dpm_table->dpm_levels[index].value = pcie_gen; |
| 1360 | dpm_table->dpm_levels[index].param1 = pcie_lanes; |
| 1361 | dpm_table->dpm_levels[index].enabled = 1; |
| 1362 | } |
| 1363 | |
| 1364 | static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr) |
| 1365 | { |
| 1366 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1367 | struct phm_ppt_v1_information *table_info = |
| 1368 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1369 | struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; |
| 1370 | uint32_t i, max_entry; |
| 1371 | |
| 1372 | PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels || |
| 1373 | data->use_pcie_power_saving_levels), "No pcie performance levels!", |
| 1374 | return -EINVAL); |
| 1375 | |
| 1376 | if (data->use_pcie_performance_levels && |
| 1377 | !data->use_pcie_power_saving_levels) { |
| 1378 | data->pcie_gen_power_saving = data->pcie_gen_performance; |
| 1379 | data->pcie_lane_power_saving = data->pcie_lane_performance; |
| 1380 | } else if (!data->use_pcie_performance_levels && |
| 1381 | data->use_pcie_power_saving_levels) { |
| 1382 | data->pcie_gen_performance = data->pcie_gen_power_saving; |
| 1383 | data->pcie_lane_performance = data->pcie_lane_power_saving; |
| 1384 | } |
| 1385 | |
| 1386 | fiji_reset_single_dpm_table(hwmgr, |
| 1387 | &data->dpm_table.pcie_speed_table, SMU73_MAX_LEVELS_LINK); |
| 1388 | |
| 1389 | if (pcie_table != NULL) { |
| 1390 | /* max_entry is used to make sure we reserve one PCIE level |
| 1391 | * for boot level (fix for A+A PSPP issue). |
| 1392 | * If PCIE table from PPTable have ULV entry + 8 entries, |
| 1393 | * then ignore the last entry.*/ |
| 1394 | max_entry = (SMU73_MAX_LEVELS_LINK < pcie_table->count) ? |
| 1395 | SMU73_MAX_LEVELS_LINK : pcie_table->count; |
| 1396 | for (i = 1; i < max_entry; i++) { |
| 1397 | fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, |
| 1398 | get_pcie_gen_support(data->pcie_gen_cap, |
| 1399 | pcie_table->entries[i].gen_speed), |
| 1400 | get_pcie_lane_support(data->pcie_lane_cap, |
| 1401 | pcie_table->entries[i].lane_width)); |
| 1402 | } |
| 1403 | data->dpm_table.pcie_speed_table.count = max_entry - 1; |
| 1404 | } else { |
| 1405 | /* Hardcode Pcie Table */ |
| 1406 | fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, |
| 1407 | get_pcie_gen_support(data->pcie_gen_cap, |
| 1408 | PP_Min_PCIEGen), |
| 1409 | get_pcie_lane_support(data->pcie_lane_cap, |
| 1410 | PP_Max_PCIELane)); |
| 1411 | fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, |
| 1412 | get_pcie_gen_support(data->pcie_gen_cap, |
| 1413 | PP_Min_PCIEGen), |
| 1414 | get_pcie_lane_support(data->pcie_lane_cap, |
| 1415 | PP_Max_PCIELane)); |
| 1416 | fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, |
| 1417 | get_pcie_gen_support(data->pcie_gen_cap, |
| 1418 | PP_Max_PCIEGen), |
| 1419 | get_pcie_lane_support(data->pcie_lane_cap, |
| 1420 | PP_Max_PCIELane)); |
| 1421 | fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, |
| 1422 | get_pcie_gen_support(data->pcie_gen_cap, |
| 1423 | PP_Max_PCIEGen), |
| 1424 | get_pcie_lane_support(data->pcie_lane_cap, |
| 1425 | PP_Max_PCIELane)); |
| 1426 | fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, |
| 1427 | get_pcie_gen_support(data->pcie_gen_cap, |
| 1428 | PP_Max_PCIEGen), |
| 1429 | get_pcie_lane_support(data->pcie_lane_cap, |
| 1430 | PP_Max_PCIELane)); |
| 1431 | fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, |
| 1432 | get_pcie_gen_support(data->pcie_gen_cap, |
| 1433 | PP_Max_PCIEGen), |
| 1434 | get_pcie_lane_support(data->pcie_lane_cap, |
| 1435 | PP_Max_PCIELane)); |
| 1436 | |
| 1437 | data->dpm_table.pcie_speed_table.count = 6; |
| 1438 | } |
| 1439 | /* Populate last level for boot PCIE level, but do not increment count. */ |
| 1440 | fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, |
| 1441 | data->dpm_table.pcie_speed_table.count, |
| 1442 | get_pcie_gen_support(data->pcie_gen_cap, |
| 1443 | PP_Min_PCIEGen), |
| 1444 | get_pcie_lane_support(data->pcie_lane_cap, |
| 1445 | PP_Max_PCIELane)); |
| 1446 | |
| 1447 | return 0; |
| 1448 | } |
| 1449 | |
| 1450 | /* |
| 1451 | * This function is to initalize all DPM state tables |
| 1452 | * for SMU7 based on the dependency table. |
| 1453 | * Dynamic state patching function will then trim these |
| 1454 | * state tables to the allowed range based |
| 1455 | * on the power policy or external client requests, |
| 1456 | * such as UVD request, etc. |
| 1457 | */ |
| 1458 | static int fiji_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) |
| 1459 | { |
| 1460 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1461 | struct phm_ppt_v1_information *table_info = |
| 1462 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1463 | uint32_t i; |
| 1464 | |
| 1465 | struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = |
| 1466 | table_info->vdd_dep_on_sclk; |
| 1467 | struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = |
| 1468 | table_info->vdd_dep_on_mclk; |
| 1469 | |
| 1470 | PP_ASSERT_WITH_CODE(dep_sclk_table != NULL, |
| 1471 | "SCLK dependency table is missing. This table is mandatory", |
| 1472 | return -EINVAL); |
| 1473 | PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1, |
| 1474 | "SCLK dependency table has to have is missing. " |
| 1475 | "This table is mandatory", |
| 1476 | return -EINVAL); |
| 1477 | |
| 1478 | PP_ASSERT_WITH_CODE(dep_mclk_table != NULL, |
| 1479 | "MCLK dependency table is missing. This table is mandatory", |
| 1480 | return -EINVAL); |
| 1481 | PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, |
| 1482 | "MCLK dependency table has to have is missing. " |
| 1483 | "This table is mandatory", |
| 1484 | return -EINVAL); |
| 1485 | |
| 1486 | /* clear the state table to reset everything to default */ |
| 1487 | fiji_reset_single_dpm_table(hwmgr, |
| 1488 | &data->dpm_table.sclk_table, SMU73_MAX_LEVELS_GRAPHICS); |
| 1489 | fiji_reset_single_dpm_table(hwmgr, |
| 1490 | &data->dpm_table.mclk_table, SMU73_MAX_LEVELS_MEMORY); |
| 1491 | |
| 1492 | /* Initialize Sclk DPM table based on allow Sclk values */ |
| 1493 | data->dpm_table.sclk_table.count = 0; |
| 1494 | for (i = 0; i < dep_sclk_table->count; i++) { |
| 1495 | if (i == 0 || data->dpm_table.sclk_table.dpm_levels |
| 1496 | [data->dpm_table.sclk_table.count - 1].value != |
| 1497 | dep_sclk_table->entries[i].clk) { |
| 1498 | data->dpm_table.sclk_table.dpm_levels |
| 1499 | [data->dpm_table.sclk_table.count].value = |
| 1500 | dep_sclk_table->entries[i].clk; |
| 1501 | data->dpm_table.sclk_table.dpm_levels |
| 1502 | [data->dpm_table.sclk_table.count].enabled = |
| 1503 | (i == 0) ? true : false; |
| 1504 | data->dpm_table.sclk_table.count++; |
| 1505 | } |
| 1506 | } |
| 1507 | |
| 1508 | /* Initialize Mclk DPM table based on allow Mclk values */ |
| 1509 | data->dpm_table.mclk_table.count = 0; |
| 1510 | for (i=0; i<dep_mclk_table->count; i++) { |
| 1511 | if ( i==0 || data->dpm_table.mclk_table.dpm_levels |
| 1512 | [data->dpm_table.mclk_table.count - 1].value != |
| 1513 | dep_mclk_table->entries[i].clk) { |
| 1514 | data->dpm_table.mclk_table.dpm_levels |
| 1515 | [data->dpm_table.mclk_table.count].value = |
| 1516 | dep_mclk_table->entries[i].clk; |
| 1517 | data->dpm_table.mclk_table.dpm_levels |
| 1518 | [data->dpm_table.mclk_table.count].enabled = |
| 1519 | (i == 0) ? true : false; |
| 1520 | data->dpm_table.mclk_table.count++; |
| 1521 | } |
| 1522 | } |
| 1523 | |
| 1524 | /* setup PCIE gen speed levels */ |
| 1525 | fiji_setup_default_pcie_table(hwmgr); |
| 1526 | |
| 1527 | /* save a copy of the default DPM table */ |
| 1528 | memcpy(&(data->golden_dpm_table), &(data->dpm_table), |
| 1529 | sizeof(struct fiji_dpm_table)); |
| 1530 | |
| 1531 | return 0; |
| 1532 | } |
| 1533 | |
| 1534 | /** |
| 1535 | * @brief PhwFiji_GetVoltageOrder |
| 1536 | * Returns index of requested voltage record in lookup(table) |
| 1537 | * @param lookup_table - lookup list to search in |
| 1538 | * @param voltage - voltage to look for |
| 1539 | * @return 0 on success |
| 1540 | */ |
| 1541 | uint8_t fiji_get_voltage_index( |
| 1542 | struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage) |
| 1543 | { |
| 1544 | uint8_t count = (uint8_t) (lookup_table->count); |
| 1545 | uint8_t i; |
| 1546 | |
| 1547 | PP_ASSERT_WITH_CODE((NULL != lookup_table), |
| 1548 | "Lookup Table empty.", return 0); |
| 1549 | PP_ASSERT_WITH_CODE((0 != count), |
| 1550 | "Lookup Table empty.", return 0); |
| 1551 | |
| 1552 | for (i = 0; i < lookup_table->count; i++) { |
| 1553 | /* find first voltage equal or bigger than requested */ |
| 1554 | if (lookup_table->entries[i].us_vdd >= voltage) |
| 1555 | return i; |
| 1556 | } |
| 1557 | /* voltage is bigger than max voltage in the table */ |
| 1558 | return i - 1; |
| 1559 | } |
| 1560 | |
| 1561 | /** |
| 1562 | * Preparation of vddc and vddgfx CAC tables for SMC. |
| 1563 | * |
| 1564 | * @param hwmgr the address of the hardware manager |
| 1565 | * @param table the SMC DPM table structure to be populated |
| 1566 | * @return always 0 |
| 1567 | */ |
| 1568 | static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr, |
| 1569 | struct SMU73_Discrete_DpmTable *table) |
| 1570 | { |
| 1571 | uint32_t count; |
| 1572 | uint8_t index; |
| 1573 | int result = 0; |
| 1574 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1575 | struct phm_ppt_v1_information *table_info = |
| 1576 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1577 | struct phm_ppt_v1_voltage_lookup_table *lookup_table = |
| 1578 | table_info->vddc_lookup_table; |
| 1579 | /* tables is already swapped, so in order to use the value from it, |
| 1580 | * we need to swap it back. |
| 1581 | * We are populating vddc CAC data to BapmVddc table |
| 1582 | * in split and merged mode |
| 1583 | */ |
| 1584 | for( count = 0; count<lookup_table->count; count++) { |
| 1585 | index = fiji_get_voltage_index(lookup_table, |
| 1586 | data->vddc_voltage_table.entries[count].value); |
| 1587 | table->BapmVddcVidLoSidd[count] = (uint8_t) ((6200 - |
| 1588 | (lookup_table->entries[index].us_cac_low * |
| 1589 | VOLTAGE_SCALE)) / 25); |
| 1590 | table->BapmVddcVidHiSidd[count] = (uint8_t) ((6200 - |
| 1591 | (lookup_table->entries[index].us_cac_high * |
| 1592 | VOLTAGE_SCALE)) / 25); |
| 1593 | } |
| 1594 | |
| 1595 | return result; |
| 1596 | } |
| 1597 | |
| 1598 | /** |
| 1599 | * Preparation of voltage tables for SMC. |
| 1600 | * |
| 1601 | * @param hwmgr the address of the hardware manager |
| 1602 | * @param table the SMC DPM table structure to be populated |
| 1603 | * @return always 0 |
| 1604 | */ |
| 1605 | |
| 1606 | int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, |
| 1607 | struct SMU73_Discrete_DpmTable *table) |
| 1608 | { |
| 1609 | int result; |
| 1610 | |
| 1611 | result = fiji_populate_cac_table(hwmgr, table); |
| 1612 | PP_ASSERT_WITH_CODE(0 == result, |
| 1613 | "can not populate CAC voltage tables to SMC", |
| 1614 | return -EINVAL); |
| 1615 | |
| 1616 | return 0; |
| 1617 | } |
| 1618 | |
| 1619 | static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr, |
| 1620 | struct SMU73_Discrete_Ulv *state) |
| 1621 | { |
| 1622 | int result = 0; |
| 1623 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1624 | struct phm_ppt_v1_information *table_info = |
| 1625 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1626 | |
| 1627 | state->CcPwrDynRm = 0; |
| 1628 | state->CcPwrDynRm1 = 0; |
| 1629 | |
| 1630 | state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset; |
| 1631 | state->VddcOffsetVid = (uint8_t)( table_info->us_ulv_voltage_offset * |
| 1632 | VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1 ); |
| 1633 | |
| 1634 | state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; |
| 1635 | |
| 1636 | if (!result) { |
| 1637 | CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm); |
| 1638 | CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1); |
| 1639 | CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset); |
| 1640 | } |
| 1641 | return result; |
| 1642 | } |
| 1643 | |
| 1644 | static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr, |
| 1645 | struct SMU73_Discrete_DpmTable *table) |
| 1646 | { |
| 1647 | return fiji_populate_ulv_level(hwmgr, &table->Ulv); |
| 1648 | } |
| 1649 | |
| 1650 | static int32_t fiji_get_dpm_level_enable_mask_value( |
| 1651 | struct fiji_single_dpm_table* dpm_table) |
| 1652 | { |
| 1653 | int32_t i; |
| 1654 | int32_t mask = 0; |
| 1655 | |
| 1656 | for (i = dpm_table->count; i > 0; i--) { |
| 1657 | mask = mask << 1; |
| 1658 | if (dpm_table->dpm_levels[i - 1].enabled) |
| 1659 | mask |= 0x1; |
| 1660 | else |
| 1661 | mask &= 0xFFFFFFFE; |
| 1662 | } |
| 1663 | return mask; |
| 1664 | } |
| 1665 | |
| 1666 | static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr, |
| 1667 | struct SMU73_Discrete_DpmTable *table) |
| 1668 | { |
| 1669 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1670 | struct fiji_dpm_table *dpm_table = &data->dpm_table; |
| 1671 | int i; |
| 1672 | |
| 1673 | /* Index (dpm_table->pcie_speed_table.count) |
| 1674 | * is reserved for PCIE boot level. */ |
| 1675 | for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { |
| 1676 | table->LinkLevel[i].PcieGenSpeed = |
| 1677 | (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; |
| 1678 | table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( |
| 1679 | dpm_table->pcie_speed_table.dpm_levels[i].param1); |
| 1680 | table->LinkLevel[i].EnabledForActivity = 1; |
| 1681 | table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); |
| 1682 | table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); |
| 1683 | table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); |
| 1684 | } |
| 1685 | |
| 1686 | data->smc_state_table.LinkLevelCount = |
| 1687 | (uint8_t)dpm_table->pcie_speed_table.count; |
| 1688 | data->dpm_level_enable_mask.pcie_dpm_enable_mask = |
| 1689 | fiji_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); |
| 1690 | |
| 1691 | return 0; |
| 1692 | } |
| 1693 | |
| 1694 | /** |
| 1695 | * Calculates the SCLK dividers using the provided engine clock |
| 1696 | * |
| 1697 | * @param hwmgr the address of the hardware manager |
| 1698 | * @param clock the engine clock to use to populate the structure |
| 1699 | * @param sclk the SMC SCLK structure to be populated |
| 1700 | */ |
| 1701 | static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr, |
| 1702 | uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk) |
| 1703 | { |
| 1704 | const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1705 | struct pp_atomctrl_clock_dividers_vi dividers; |
| 1706 | uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; |
| 1707 | uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; |
| 1708 | uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; |
| 1709 | uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; |
| 1710 | uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; |
| 1711 | uint32_t ref_clock; |
| 1712 | uint32_t ref_divider; |
| 1713 | uint32_t fbdiv; |
| 1714 | int result; |
| 1715 | |
| 1716 | /* get the engine clock dividers for this clock value */ |
| 1717 | result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); |
| 1718 | |
| 1719 | PP_ASSERT_WITH_CODE(result == 0, |
| 1720 | "Error retrieving Engine Clock dividers from VBIOS.", |
| 1721 | return result); |
| 1722 | |
| 1723 | /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */ |
| 1724 | ref_clock = atomctrl_get_reference_clock(hwmgr); |
| 1725 | ref_divider = 1 + dividers.uc_pll_ref_div; |
| 1726 | |
| 1727 | /* low 14 bits is fraction and high 12 bits is divider */ |
| 1728 | fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; |
| 1729 | |
| 1730 | /* SPLL_FUNC_CNTL setup */ |
| 1731 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, |
| 1732 | SPLL_REF_DIV, dividers.uc_pll_ref_div); |
| 1733 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, |
| 1734 | SPLL_PDIV_A, dividers.uc_pll_post_div); |
| 1735 | |
| 1736 | /* SPLL_FUNC_CNTL_3 setup*/ |
| 1737 | spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3, |
| 1738 | SPLL_FB_DIV, fbdiv); |
| 1739 | |
| 1740 | /* set to use fractional accumulation*/ |
| 1741 | spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3, |
| 1742 | SPLL_DITHEN, 1); |
| 1743 | |
| 1744 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 1745 | PHM_PlatformCaps_EngineSpreadSpectrumSupport)) { |
| 1746 | struct pp_atomctrl_internal_ss_info ssInfo; |
| 1747 | |
| 1748 | uint32_t vco_freq = clock * dividers.uc_pll_post_div; |
| 1749 | if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr, |
| 1750 | vco_freq, &ssInfo)) { |
| 1751 | /* |
| 1752 | * ss_info.speed_spectrum_percentage -- in unit of 0.01% |
| 1753 | * ss_info.speed_spectrum_rate -- in unit of khz |
| 1754 | * |
| 1755 | * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 |
| 1756 | */ |
| 1757 | uint32_t clk_s = ref_clock * 5 / |
| 1758 | (ref_divider * ssInfo.speed_spectrum_rate); |
| 1759 | /* clkv = 2 * D * fbdiv / NS */ |
| 1760 | uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage * |
| 1761 | fbdiv / (clk_s * 10000); |
| 1762 | |
| 1763 | cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum, |
| 1764 | CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s); |
| 1765 | cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum, |
| 1766 | CG_SPLL_SPREAD_SPECTRUM, SSEN, 1); |
| 1767 | cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2, |
| 1768 | CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v); |
| 1769 | } |
| 1770 | } |
| 1771 | |
| 1772 | sclk->SclkFrequency = clock; |
| 1773 | sclk->CgSpllFuncCntl3 = spll_func_cntl_3; |
| 1774 | sclk->CgSpllFuncCntl4 = spll_func_cntl_4; |
| 1775 | sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; |
| 1776 | sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; |
| 1777 | sclk->SclkDid = (uint8_t)dividers.pll_post_divider; |
| 1778 | |
| 1779 | return 0; |
| 1780 | } |
| 1781 | |
| 1782 | static uint16_t fiji_find_closest_vddci(struct pp_hwmgr *hwmgr, uint16_t vddci) |
| 1783 | { |
| 1784 | uint32_t i; |
| 1785 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1786 | struct pp_atomctrl_voltage_table *vddci_table = |
| 1787 | &(data->vddci_voltage_table); |
| 1788 | |
| 1789 | for (i = 0; i < vddci_table->count; i++) { |
| 1790 | if (vddci_table->entries[i].value >= vddci) |
| 1791 | return vddci_table->entries[i].value; |
| 1792 | } |
| 1793 | |
| 1794 | PP_ASSERT_WITH_CODE(false, |
| 1795 | "VDDCI is larger than max VDDCI in VDDCI Voltage Table!", |
| 1796 | return vddci_table->entries[i].value); |
| 1797 | } |
| 1798 | |
| 1799 | static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, |
| 1800 | struct phm_ppt_v1_clock_voltage_dependency_table* dep_table, |
| 1801 | uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) |
| 1802 | { |
| 1803 | uint32_t i; |
| 1804 | uint16_t vddci; |
| 1805 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1806 | |
| 1807 | *voltage = *mvdd = 0; |
| 1808 | |
| 1809 | /* clock - voltage dependency table is empty table */ |
| 1810 | if (dep_table->count == 0) |
| 1811 | return -EINVAL; |
| 1812 | |
| 1813 | for (i = 0; i < dep_table->count; i++) { |
| 1814 | /* find first sclk bigger than request */ |
| 1815 | if (dep_table->entries[i].clk >= clock) { |
| 1816 | *voltage |= (dep_table->entries[i].vddc * |
| 1817 | VOLTAGE_SCALE) << VDDC_SHIFT; |
| 1818 | if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control) |
| 1819 | *voltage |= (data->vbios_boot_state.vddci_bootup_value * |
| 1820 | VOLTAGE_SCALE) << VDDCI_SHIFT; |
| 1821 | else if (dep_table->entries[i].vddci) |
| 1822 | *voltage |= (dep_table->entries[i].vddci * |
| 1823 | VOLTAGE_SCALE) << VDDCI_SHIFT; |
| 1824 | else { |
| 1825 | vddci = fiji_find_closest_vddci(hwmgr, |
| 1826 | (dep_table->entries[i].vddc - |
| 1827 | (uint16_t)data->vddc_vddci_delta)); |
| 1828 | *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; |
| 1829 | } |
| 1830 | |
| 1831 | if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) |
| 1832 | *mvdd = data->vbios_boot_state.mvdd_bootup_value * |
| 1833 | VOLTAGE_SCALE; |
| 1834 | else if (dep_table->entries[i].mvdd) |
| 1835 | *mvdd = (uint32_t) dep_table->entries[i].mvdd * |
| 1836 | VOLTAGE_SCALE; |
| 1837 | |
| 1838 | *voltage |= 1 << PHASES_SHIFT; |
| 1839 | return 0; |
| 1840 | } |
| 1841 | } |
| 1842 | |
| 1843 | /* sclk is bigger than max sclk in the dependence table */ |
| 1844 | *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; |
| 1845 | |
| 1846 | if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control) |
| 1847 | *voltage |= (data->vbios_boot_state.vddci_bootup_value * |
| 1848 | VOLTAGE_SCALE) << VDDCI_SHIFT; |
| 1849 | else if (dep_table->entries[i-1].vddci) { |
| 1850 | vddci = fiji_find_closest_vddci(hwmgr, |
| 1851 | (dep_table->entries[i].vddc - |
| 1852 | (uint16_t)data->vddc_vddci_delta)); |
| 1853 | *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; |
| 1854 | } |
| 1855 | |
| 1856 | if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) |
| 1857 | *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE; |
| 1858 | else if (dep_table->entries[i].mvdd) |
| 1859 | *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE; |
| 1860 | |
| 1861 | return 0; |
| 1862 | } |
| 1863 | /** |
| 1864 | * Populates single SMC SCLK structure using the provided engine clock |
| 1865 | * |
| 1866 | * @param hwmgr the address of the hardware manager |
| 1867 | * @param clock the engine clock to use to populate the structure |
| 1868 | * @param sclk the SMC SCLK structure to be populated |
| 1869 | */ |
| 1870 | |
| 1871 | static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr, |
| 1872 | uint32_t clock, uint16_t sclk_al_threshold, |
| 1873 | struct SMU73_Discrete_GraphicsLevel *level) |
| 1874 | { |
| 1875 | int result; |
| 1876 | /* PP_Clocks minClocks; */ |
| 1877 | uint32_t threshold, mvdd; |
| 1878 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1879 | struct phm_ppt_v1_information *table_info = |
| 1880 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1881 | |
| 1882 | result = fiji_calculate_sclk_params(hwmgr, clock, level); |
| 1883 | |
| 1884 | /* populate graphics levels */ |
| 1885 | result = fiji_get_dependency_volt_by_clk(hwmgr, |
| 1886 | table_info->vdd_dep_on_sclk, clock, |
| 1887 | &level->MinVoltage, &mvdd); |
| 1888 | PP_ASSERT_WITH_CODE((0 == result), |
| 1889 | "can not find VDDC voltage value for " |
| 1890 | "VDDC engine clock dependency table", |
| 1891 | return result); |
| 1892 | |
| 1893 | level->SclkFrequency = clock; |
| 1894 | level->ActivityLevel = sclk_al_threshold; |
| 1895 | level->CcPwrDynRm = 0; |
| 1896 | level->CcPwrDynRm1 = 0; |
| 1897 | level->EnabledForActivity = 0; |
| 1898 | level->EnabledForThrottle = 1; |
| 1899 | level->UpHyst = 10; |
| 1900 | level->DownHyst = 0; |
| 1901 | level->VoltageDownHyst = 0; |
| 1902 | level->PowerThrottle = 0; |
| 1903 | |
| 1904 | threshold = clock * data->fast_watermark_threshold / 100; |
| 1905 | |
| 1906 | /* |
| 1907 | * TODO: get minimum clocks from dal configaration |
| 1908 | * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks); |
| 1909 | */ |
| 1910 | /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */ |
| 1911 | |
| 1912 | /* get level->DeepSleepDivId |
| 1913 | if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) |
| 1914 | { |
| 1915 | level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR); |
| 1916 | } */ |
| 1917 | |
| 1918 | /* Default to slow, highest DPM level will be |
| 1919 | * set to PPSMC_DISPLAY_WATERMARK_LOW later. |
| 1920 | */ |
| 1921 | level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; |
| 1922 | |
| 1923 | CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage); |
| 1924 | CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency); |
| 1925 | CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel); |
| 1926 | CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3); |
| 1927 | CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4); |
| 1928 | CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum); |
| 1929 | CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2); |
| 1930 | CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm); |
| 1931 | CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1); |
| 1932 | |
| 1933 | return 0; |
| 1934 | } |
| 1935 | /** |
| 1936 | * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states |
| 1937 | * |
| 1938 | * @param hwmgr the address of the hardware manager |
| 1939 | */ |
| 1940 | static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) |
| 1941 | { |
| 1942 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 1943 | struct fiji_dpm_table *dpm_table = &data->dpm_table; |
| 1944 | struct phm_ppt_v1_information *table_info = |
| 1945 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 1946 | struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; |
| 1947 | uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count; |
| 1948 | int result = 0; |
| 1949 | uint32_t array = data->dpm_table_start + |
| 1950 | offsetof(SMU73_Discrete_DpmTable, GraphicsLevel); |
| 1951 | uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) * |
| 1952 | SMU73_MAX_LEVELS_GRAPHICS; |
| 1953 | struct SMU73_Discrete_GraphicsLevel *levels = |
| 1954 | data->smc_state_table.GraphicsLevel; |
| 1955 | uint32_t i, max_entry; |
| 1956 | uint8_t hightest_pcie_level_enabled = 0, |
| 1957 | lowest_pcie_level_enabled = 0, |
| 1958 | mid_pcie_level_enabled = 0, |
| 1959 | count = 0; |
| 1960 | |
| 1961 | for (i = 0; i < dpm_table->sclk_table.count; i++) { |
| 1962 | result = fiji_populate_single_graphic_level(hwmgr, |
| 1963 | dpm_table->sclk_table.dpm_levels[i].value, |
| 1964 | (uint16_t)data->activity_target[i], |
| 1965 | &levels[i]); |
| 1966 | if (result) |
| 1967 | return result; |
| 1968 | |
| 1969 | /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ |
| 1970 | if (i > 1) |
| 1971 | levels[i].DeepSleepDivId = 0; |
| 1972 | } |
| 1973 | |
| 1974 | /* Only enable level 0 for now.*/ |
| 1975 | levels[0].EnabledForActivity = 1; |
| 1976 | |
| 1977 | /* set highest level watermark to high */ |
| 1978 | levels[dpm_table->sclk_table.count - 1].DisplayWatermark = |
| 1979 | PPSMC_DISPLAY_WATERMARK_HIGH; |
| 1980 | |
| 1981 | data->smc_state_table.GraphicsDpmLevelCount = |
| 1982 | (uint8_t)dpm_table->sclk_table.count; |
| 1983 | data->dpm_level_enable_mask.sclk_dpm_enable_mask = |
| 1984 | fiji_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); |
| 1985 | |
| 1986 | if (pcie_table != NULL) { |
| 1987 | PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt), |
| 1988 | "There must be 1 or more PCIE levels defined in PPTable.", |
| 1989 | return -EINVAL); |
| 1990 | max_entry = pcie_entry_cnt - 1; |
| 1991 | for (i = 0; i < dpm_table->sclk_table.count; i++) |
| 1992 | levels[i].pcieDpmLevel = |
| 1993 | (uint8_t) ((i < max_entry)? i : max_entry); |
| 1994 | } else { |
| 1995 | while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && |
| 1996 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & |
| 1997 | (1 << (hightest_pcie_level_enabled + 1))) != 0 )) |
| 1998 | hightest_pcie_level_enabled++; |
| 1999 | |
| 2000 | while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && |
| 2001 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & |
| 2002 | (1 << lowest_pcie_level_enabled)) == 0 )) |
| 2003 | lowest_pcie_level_enabled++; |
| 2004 | |
| 2005 | while ((count < hightest_pcie_level_enabled) && |
| 2006 | ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & |
| 2007 | (1 << (lowest_pcie_level_enabled + 1 + count))) == 0 )) |
| 2008 | count++; |
| 2009 | |
| 2010 | mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1+ count) < |
| 2011 | hightest_pcie_level_enabled? |
| 2012 | (lowest_pcie_level_enabled + 1 + count) : |
| 2013 | hightest_pcie_level_enabled; |
| 2014 | |
| 2015 | /* set pcieDpmLevel to hightest_pcie_level_enabled */ |
| 2016 | for(i = 2; i < dpm_table->sclk_table.count; i++) |
| 2017 | levels[i].pcieDpmLevel = hightest_pcie_level_enabled; |
| 2018 | |
| 2019 | /* set pcieDpmLevel to lowest_pcie_level_enabled */ |
| 2020 | levels[0].pcieDpmLevel = lowest_pcie_level_enabled; |
| 2021 | |
| 2022 | /* set pcieDpmLevel to mid_pcie_level_enabled */ |
| 2023 | levels[1].pcieDpmLevel = mid_pcie_level_enabled; |
| 2024 | } |
| 2025 | /* level count will send to smc once at init smc table and never change */ |
| 2026 | result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, |
| 2027 | (uint32_t)array_size, data->sram_end); |
| 2028 | |
| 2029 | return result; |
| 2030 | } |
| 2031 | |
| 2032 | /** |
| 2033 | * MCLK Frequency Ratio |
| 2034 | * SEQ_CG_RESP Bit[31:24] - 0x0 |
| 2035 | * Bit[27:24] \96 DDR3 Frequency ratio |
| 2036 | * 0x0 <= 100MHz, 450 < 0x8 <= 500MHz |
| 2037 | * 100 < 0x1 <= 150MHz, 500 < 0x9 <= 550MHz |
| 2038 | * 150 < 0x2 <= 200MHz, 550 < 0xA <= 600MHz |
| 2039 | * 200 < 0x3 <= 250MHz, 600 < 0xB <= 650MHz |
| 2040 | * 250 < 0x4 <= 300MHz, 650 < 0xC <= 700MHz |
| 2041 | * 300 < 0x5 <= 350MHz, 700 < 0xD <= 750MHz |
| 2042 | * 350 < 0x6 <= 400MHz, 750 < 0xE <= 800MHz |
| 2043 | * 400 < 0x7 <= 450MHz, 800 < 0xF |
| 2044 | */ |
| 2045 | static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock) |
| 2046 | { |
| 2047 | if (mem_clock <= 10000) return 0x0; |
| 2048 | if (mem_clock <= 15000) return 0x1; |
| 2049 | if (mem_clock <= 20000) return 0x2; |
| 2050 | if (mem_clock <= 25000) return 0x3; |
| 2051 | if (mem_clock <= 30000) return 0x4; |
| 2052 | if (mem_clock <= 35000) return 0x5; |
| 2053 | if (mem_clock <= 40000) return 0x6; |
| 2054 | if (mem_clock <= 45000) return 0x7; |
| 2055 | if (mem_clock <= 50000) return 0x8; |
| 2056 | if (mem_clock <= 55000) return 0x9; |
| 2057 | if (mem_clock <= 60000) return 0xa; |
| 2058 | if (mem_clock <= 65000) return 0xb; |
| 2059 | if (mem_clock <= 70000) return 0xc; |
| 2060 | if (mem_clock <= 75000) return 0xd; |
| 2061 | if (mem_clock <= 80000) return 0xe; |
| 2062 | /* mem_clock > 800MHz */ |
| 2063 | return 0xf; |
| 2064 | } |
| 2065 | |
| 2066 | /** |
| 2067 | * Populates the SMC MCLK structure using the provided memory clock |
| 2068 | * |
| 2069 | * @param hwmgr the address of the hardware manager |
| 2070 | * @param clock the memory clock to use to populate the structure |
| 2071 | * @param sclk the SMC SCLK structure to be populated |
| 2072 | */ |
| 2073 | static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr, |
| 2074 | uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk) |
| 2075 | { |
| 2076 | struct pp_atomctrl_memory_clock_param mem_param; |
| 2077 | int result; |
| 2078 | |
| 2079 | result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param); |
| 2080 | PP_ASSERT_WITH_CODE((0 == result), |
| 2081 | "Failed to get Memory PLL Dividers.",); |
| 2082 | |
| 2083 | /* Save the result data to outpupt memory level structure */ |
| 2084 | mclk->MclkFrequency = clock; |
| 2085 | mclk->MclkDivider = (uint8_t)mem_param.mpll_post_divider; |
| 2086 | mclk->FreqRange = fiji_get_mclk_frequency_ratio(clock); |
| 2087 | |
| 2088 | return result; |
| 2089 | } |
| 2090 | |
| 2091 | static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr, |
| 2092 | uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level) |
| 2093 | { |
| 2094 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2095 | struct phm_ppt_v1_information *table_info = |
| 2096 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2097 | int result = 0; |
| 2098 | |
| 2099 | if (table_info->vdd_dep_on_mclk) { |
| 2100 | result = fiji_get_dependency_volt_by_clk(hwmgr, |
| 2101 | table_info->vdd_dep_on_mclk, clock, |
| 2102 | &mem_level->MinVoltage, &mem_level->MinMvdd); |
| 2103 | PP_ASSERT_WITH_CODE((0 == result), |
| 2104 | "can not find MinVddc voltage value from memory " |
| 2105 | "VDDC voltage dependency table", return result); |
| 2106 | } |
| 2107 | |
| 2108 | mem_level->EnabledForThrottle = 1; |
| 2109 | mem_level->EnabledForActivity = 0; |
| 2110 | mem_level->UpHyst = 0; |
| 2111 | mem_level->DownHyst = 100; |
| 2112 | mem_level->VoltageDownHyst = 0; |
| 2113 | mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target; |
| 2114 | mem_level->StutterEnable = false; |
| 2115 | |
| 2116 | mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; |
| 2117 | |
| 2118 | /* enable stutter mode if all the follow condition applied |
| 2119 | * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI, |
| 2120 | * &(data->DisplayTiming.numExistingDisplays)); |
| 2121 | */ |
| 2122 | data->display_timing.num_existing_displays = 1; |
| 2123 | |
| 2124 | if ((data->mclk_stutter_mode_threshold) && |
| 2125 | (clock <= data->mclk_stutter_mode_threshold) && |
| 2126 | (!data->is_uvd_enabled) && |
| 2127 | (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, |
| 2128 | STUTTER_ENABLE) & 0x1)) |
| 2129 | mem_level->StutterEnable = true; |
| 2130 | |
| 2131 | result = fiji_calculate_mclk_params(hwmgr, clock, mem_level); |
| 2132 | if (!result) { |
| 2133 | CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd); |
| 2134 | CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency); |
| 2135 | CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel); |
| 2136 | CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage); |
| 2137 | } |
| 2138 | return result; |
| 2139 | } |
| 2140 | |
| 2141 | /** |
| 2142 | * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states |
| 2143 | * |
| 2144 | * @param hwmgr the address of the hardware manager |
| 2145 | */ |
| 2146 | static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr) |
| 2147 | { |
| 2148 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2149 | struct fiji_dpm_table *dpm_table = &data->dpm_table; |
| 2150 | int result; |
| 2151 | /* populate MCLK dpm table to SMU7 */ |
| 2152 | uint32_t array = data->dpm_table_start + |
| 2153 | offsetof(SMU73_Discrete_DpmTable, MemoryLevel); |
| 2154 | uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) * |
| 2155 | SMU73_MAX_LEVELS_MEMORY; |
| 2156 | struct SMU73_Discrete_MemoryLevel *levels = |
| 2157 | data->smc_state_table.MemoryLevel; |
| 2158 | uint32_t i; |
| 2159 | |
| 2160 | for (i = 0; i < dpm_table->mclk_table.count; i++) { |
| 2161 | PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), |
| 2162 | "can not populate memory level as memory clock is zero", |
| 2163 | return -EINVAL); |
| 2164 | result = fiji_populate_single_memory_level(hwmgr, |
| 2165 | dpm_table->mclk_table.dpm_levels[i].value, |
| 2166 | &levels[i]); |
| 2167 | if (result) |
| 2168 | return result; |
| 2169 | } |
| 2170 | |
| 2171 | /* Only enable level 0 for now. */ |
| 2172 | levels[0].EnabledForActivity = 1; |
| 2173 | |
| 2174 | /* in order to prevent MC activity from stutter mode to push DPM up. |
| 2175 | * the UVD change complements this by putting the MCLK in |
| 2176 | * a higher state by default such that we are not effected by |
| 2177 | * up threshold or and MCLK DPM latency. |
| 2178 | */ |
| 2179 | levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target; |
| 2180 | CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel); |
| 2181 | |
| 2182 | data->smc_state_table.MemoryDpmLevelCount = |
| 2183 | (uint8_t)dpm_table->mclk_table.count; |
| 2184 | data->dpm_level_enable_mask.mclk_dpm_enable_mask = |
| 2185 | fiji_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); |
| 2186 | /* set highest level watermark to high */ |
| 2187 | levels[dpm_table->mclk_table.count - 1].DisplayWatermark = |
| 2188 | PPSMC_DISPLAY_WATERMARK_HIGH; |
| 2189 | |
| 2190 | /* level count will send to smc once at init smc table and never change */ |
| 2191 | result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, |
| 2192 | (uint32_t)array_size, data->sram_end); |
| 2193 | |
| 2194 | return result; |
| 2195 | } |
| 2196 | |
| 2197 | /** |
| 2198 | * Populates the SMC MVDD structure using the provided memory clock. |
| 2199 | * |
| 2200 | * @param hwmgr the address of the hardware manager |
| 2201 | * @param mclk the MCLK value to be used in the decision if MVDD should be high or low. |
| 2202 | * @param voltage the SMC VOLTAGE structure to be populated |
| 2203 | */ |
| 2204 | int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr, |
| 2205 | uint32_t mclk, SMIO_Pattern *smio_pat) |
| 2206 | { |
| 2207 | const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2208 | struct phm_ppt_v1_information *table_info = |
| 2209 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2210 | uint32_t i = 0; |
| 2211 | |
| 2212 | if (FIJI_VOLTAGE_CONTROL_NONE != data->mvdd_control) { |
| 2213 | /* find mvdd value which clock is more than request */ |
| 2214 | for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) { |
| 2215 | if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) { |
| 2216 | smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value; |
| 2217 | break; |
| 2218 | } |
| 2219 | } |
| 2220 | PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, |
| 2221 | "MVDD Voltage is outside the supported range.", |
| 2222 | return -EINVAL); |
| 2223 | } else |
| 2224 | return -EINVAL; |
| 2225 | |
| 2226 | return 0; |
| 2227 | } |
| 2228 | |
| 2229 | static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, |
| 2230 | SMU73_Discrete_DpmTable *table) |
| 2231 | { |
| 2232 | int result = 0; |
| 2233 | const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2234 | struct phm_ppt_v1_information *table_info = |
| 2235 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2236 | struct pp_atomctrl_clock_dividers_vi dividers; |
| 2237 | SMIO_Pattern vol_level; |
| 2238 | uint32_t mvdd; |
| 2239 | uint16_t us_mvdd; |
| 2240 | uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; |
| 2241 | uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; |
| 2242 | |
| 2243 | table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; |
| 2244 | |
| 2245 | if (!data->sclk_dpm_key_disabled) { |
| 2246 | /* Get MinVoltage and Frequency from DPM0, |
| 2247 | * already converted to SMC_UL */ |
| 2248 | table->ACPILevel.SclkFrequency = |
| 2249 | data->dpm_table.sclk_table.dpm_levels[0].value; |
| 2250 | result = fiji_get_dependency_volt_by_clk(hwmgr, |
| 2251 | table_info->vdd_dep_on_sclk, |
| 2252 | table->ACPILevel.SclkFrequency, |
| 2253 | &table->ACPILevel.MinVoltage, &mvdd); |
| 2254 | PP_ASSERT_WITH_CODE((0 == result), |
| 2255 | "Cannot find ACPI VDDC voltage value " |
| 2256 | "in Clock Dependency Table",); |
| 2257 | } else { |
| 2258 | table->ACPILevel.SclkFrequency = |
| 2259 | data->vbios_boot_state.sclk_bootup_value; |
| 2260 | table->ACPILevel.MinVoltage = |
| 2261 | data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE; |
| 2262 | } |
| 2263 | |
| 2264 | /* get the engine clock dividers for this clock value */ |
| 2265 | result = atomctrl_get_engine_pll_dividers_vi(hwmgr, |
| 2266 | table->ACPILevel.SclkFrequency, ÷rs); |
| 2267 | PP_ASSERT_WITH_CODE(result == 0, |
| 2268 | "Error retrieving Engine Clock dividers from VBIOS.", |
| 2269 | return result); |
| 2270 | |
| 2271 | table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; |
| 2272 | table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; |
| 2273 | table->ACPILevel.DeepSleepDivId = 0; |
| 2274 | |
| 2275 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, |
| 2276 | SPLL_PWRON, 0); |
| 2277 | spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, |
| 2278 | SPLL_RESET, 1); |
| 2279 | spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2, |
| 2280 | SCLK_MUX_SEL, 4); |
| 2281 | |
| 2282 | table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; |
| 2283 | table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; |
| 2284 | table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; |
| 2285 | table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; |
| 2286 | table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; |
| 2287 | table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; |
| 2288 | table->ACPILevel.CcPwrDynRm = 0; |
| 2289 | table->ACPILevel.CcPwrDynRm1 = 0; |
| 2290 | |
| 2291 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); |
| 2292 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency); |
| 2293 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage); |
| 2294 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl); |
| 2295 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2); |
| 2296 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3); |
| 2297 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4); |
| 2298 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum); |
| 2299 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2); |
| 2300 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); |
| 2301 | CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); |
| 2302 | |
| 2303 | if (!data->mclk_dpm_key_disabled) { |
| 2304 | /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */ |
| 2305 | table->MemoryACPILevel.MclkFrequency = |
| 2306 | data->dpm_table.mclk_table.dpm_levels[0].value; |
| 2307 | result = fiji_get_dependency_volt_by_clk(hwmgr, |
| 2308 | table_info->vdd_dep_on_mclk, |
| 2309 | table->MemoryACPILevel.MclkFrequency, |
| 2310 | &table->MemoryACPILevel.MinVoltage, &mvdd); |
| 2311 | PP_ASSERT_WITH_CODE((0 == result), |
| 2312 | "Cannot find ACPI VDDCI voltage value " |
| 2313 | "in Clock Dependency Table",); |
| 2314 | } else { |
| 2315 | table->MemoryACPILevel.MclkFrequency = |
| 2316 | data->vbios_boot_state.mclk_bootup_value; |
| 2317 | table->MemoryACPILevel.MinVoltage = |
| 2318 | data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE; |
| 2319 | } |
| 2320 | |
| 2321 | us_mvdd = 0; |
| 2322 | if ((FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) || |
| 2323 | (data->mclk_dpm_key_disabled)) |
| 2324 | us_mvdd = data->vbios_boot_state.mvdd_bootup_value; |
| 2325 | else { |
| 2326 | if (!fiji_populate_mvdd_value(hwmgr, |
| 2327 | data->dpm_table.mclk_table.dpm_levels[0].value, |
| 2328 | &vol_level)) |
| 2329 | us_mvdd = vol_level.Voltage; |
| 2330 | } |
| 2331 | |
| 2332 | table->MemoryACPILevel.MinMvdd = |
| 2333 | PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE); |
| 2334 | |
| 2335 | table->MemoryACPILevel.EnabledForThrottle = 0; |
| 2336 | table->MemoryACPILevel.EnabledForActivity = 0; |
| 2337 | table->MemoryACPILevel.UpHyst = 0; |
| 2338 | table->MemoryACPILevel.DownHyst = 100; |
| 2339 | table->MemoryACPILevel.VoltageDownHyst = 0; |
| 2340 | table->MemoryACPILevel.ActivityLevel = |
| 2341 | PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target); |
| 2342 | |
| 2343 | table->MemoryACPILevel.StutterEnable = false; |
| 2344 | CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency); |
| 2345 | CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage); |
| 2346 | |
| 2347 | return result; |
| 2348 | } |
| 2349 | |
| 2350 | static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr, |
| 2351 | SMU73_Discrete_DpmTable *table) |
| 2352 | { |
| 2353 | int result = -EINVAL; |
| 2354 | uint8_t count; |
| 2355 | struct pp_atomctrl_clock_dividers_vi dividers; |
| 2356 | struct phm_ppt_v1_information *table_info = |
| 2357 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2358 | struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = |
| 2359 | table_info->mm_dep_table; |
| 2360 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2361 | |
| 2362 | table->VceLevelCount = (uint8_t)(mm_table->count); |
| 2363 | table->VceBootLevel = 0; |
| 2364 | |
| 2365 | for(count = 0; count < table->VceLevelCount; count++) { |
| 2366 | table->VceLevel[count].Frequency = mm_table->entries[count].eclk; |
| 2367 | table->VceLevel[count].MinVoltage |= |
| 2368 | (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; |
| 2369 | table->VceLevel[count].MinVoltage |= |
| 2370 | ((mm_table->entries[count].vddc - data->vddc_vddci_delta) * |
| 2371 | VOLTAGE_SCALE) << VDDCI_SHIFT; |
| 2372 | table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT; |
| 2373 | |
| 2374 | /*retrieve divider value for VBIOS */ |
| 2375 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 2376 | table->VceLevel[count].Frequency, ÷rs); |
| 2377 | PP_ASSERT_WITH_CODE((0 == result), |
| 2378 | "can not find divide id for VCE engine clock", |
| 2379 | return result); |
| 2380 | |
| 2381 | table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; |
| 2382 | |
| 2383 | CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); |
| 2384 | CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage); |
| 2385 | } |
| 2386 | return result; |
| 2387 | } |
| 2388 | |
| 2389 | static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr, |
| 2390 | SMU73_Discrete_DpmTable *table) |
| 2391 | { |
| 2392 | int result = -EINVAL; |
| 2393 | uint8_t count; |
| 2394 | struct pp_atomctrl_clock_dividers_vi dividers; |
| 2395 | struct phm_ppt_v1_information *table_info = |
| 2396 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2397 | struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = |
| 2398 | table_info->mm_dep_table; |
| 2399 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2400 | |
| 2401 | table->AcpLevelCount = (uint8_t)(mm_table->count); |
| 2402 | table->AcpBootLevel = 0; |
| 2403 | |
| 2404 | for (count = 0; count < table->AcpLevelCount; count++) { |
| 2405 | table->AcpLevel[count].Frequency = mm_table->entries[count].aclk; |
| 2406 | table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc * |
| 2407 | VOLTAGE_SCALE) << VDDC_SHIFT; |
| 2408 | table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - |
| 2409 | data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT; |
| 2410 | table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT; |
| 2411 | |
| 2412 | /* retrieve divider value for VBIOS */ |
| 2413 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 2414 | table->AcpLevel[count].Frequency, ÷rs); |
| 2415 | PP_ASSERT_WITH_CODE((0 == result), |
| 2416 | "can not find divide id for engine clock", return result); |
| 2417 | |
| 2418 | table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; |
| 2419 | |
| 2420 | CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency); |
| 2421 | CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage); |
| 2422 | } |
| 2423 | return result; |
| 2424 | } |
| 2425 | |
| 2426 | static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr, |
| 2427 | SMU73_Discrete_DpmTable *table) |
| 2428 | { |
| 2429 | int result = -EINVAL; |
| 2430 | uint8_t count; |
| 2431 | struct pp_atomctrl_clock_dividers_vi dividers; |
| 2432 | struct phm_ppt_v1_information *table_info = |
| 2433 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2434 | struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = |
| 2435 | table_info->mm_dep_table; |
| 2436 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2437 | |
| 2438 | table->SamuBootLevel = 0; |
| 2439 | table->SamuLevelCount = (uint8_t)(mm_table->count); |
| 2440 | |
| 2441 | for (count = 0; count < table->SamuLevelCount; count++) { |
| 2442 | /* not sure whether we need evclk or not */ |
| 2443 | table->SamuLevel[count].Frequency = mm_table->entries[count].samclock; |
| 2444 | table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc * |
| 2445 | VOLTAGE_SCALE) << VDDC_SHIFT; |
| 2446 | table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - |
| 2447 | data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT; |
| 2448 | table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT; |
| 2449 | |
| 2450 | /* retrieve divider value for VBIOS */ |
| 2451 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 2452 | table->SamuLevel[count].Frequency, ÷rs); |
| 2453 | PP_ASSERT_WITH_CODE((0 == result), |
| 2454 | "can not find divide id for samu clock", return result); |
| 2455 | |
| 2456 | table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; |
| 2457 | |
| 2458 | CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency); |
| 2459 | CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage); |
| 2460 | } |
| 2461 | return result; |
| 2462 | } |
| 2463 | |
| 2464 | static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, |
| 2465 | int32_t eng_clock, int32_t mem_clock, |
| 2466 | struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs) |
| 2467 | { |
| 2468 | uint32_t dram_timing; |
| 2469 | uint32_t dram_timing2; |
| 2470 | uint32_t burstTime; |
| 2471 | ULONG state, trrds, trrdl; |
| 2472 | int result; |
| 2473 | |
| 2474 | result = atomctrl_set_engine_dram_timings_rv770(hwmgr, |
| 2475 | eng_clock, mem_clock); |
| 2476 | PP_ASSERT_WITH_CODE(result == 0, |
| 2477 | "Error calling VBIOS to set DRAM_TIMING.", return result); |
| 2478 | |
| 2479 | dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); |
| 2480 | dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); |
| 2481 | burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME); |
| 2482 | |
| 2483 | state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0); |
| 2484 | trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0); |
| 2485 | trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0); |
| 2486 | |
| 2487 | arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); |
| 2488 | arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); |
| 2489 | arb_regs->McArbBurstTime = (uint8_t)burstTime; |
| 2490 | arb_regs->TRRDS = (uint8_t)trrds; |
| 2491 | arb_regs->TRRDL = (uint8_t)trrdl; |
| 2492 | |
| 2493 | return 0; |
| 2494 | } |
| 2495 | |
| 2496 | static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) |
| 2497 | { |
| 2498 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2499 | struct SMU73_Discrete_MCArbDramTimingTable arb_regs; |
| 2500 | uint32_t i, j; |
| 2501 | int result = 0; |
| 2502 | |
| 2503 | for (i = 0; i < data->dpm_table.sclk_table.count; i++) { |
| 2504 | for (j = 0; j < data->dpm_table.mclk_table.count; j++) { |
| 2505 | result = fiji_populate_memory_timing_parameters(hwmgr, |
| 2506 | data->dpm_table.sclk_table.dpm_levels[i].value, |
| 2507 | data->dpm_table.mclk_table.dpm_levels[j].value, |
| 2508 | &arb_regs.entries[i][j]); |
| 2509 | if (result) |
| 2510 | break; |
| 2511 | } |
| 2512 | } |
| 2513 | |
| 2514 | if (!result) |
| 2515 | result = fiji_copy_bytes_to_smc( |
| 2516 | hwmgr->smumgr, |
| 2517 | data->arb_table_start, |
| 2518 | (uint8_t *)&arb_regs, |
| 2519 | sizeof(SMU73_Discrete_MCArbDramTimingTable), |
| 2520 | data->sram_end); |
| 2521 | return result; |
| 2522 | } |
| 2523 | |
| 2524 | static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, |
| 2525 | struct SMU73_Discrete_DpmTable *table) |
| 2526 | { |
| 2527 | int result = -EINVAL; |
| 2528 | uint8_t count; |
| 2529 | struct pp_atomctrl_clock_dividers_vi dividers; |
| 2530 | struct phm_ppt_v1_information *table_info = |
| 2531 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2532 | struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = |
| 2533 | table_info->mm_dep_table; |
| 2534 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2535 | |
| 2536 | table->UvdLevelCount = (uint8_t)(mm_table->count); |
| 2537 | table->UvdBootLevel = 0; |
| 2538 | |
| 2539 | for (count = 0; count < table->UvdLevelCount; count++) { |
| 2540 | table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; |
| 2541 | table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; |
| 2542 | table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc * |
| 2543 | VOLTAGE_SCALE) << VDDC_SHIFT; |
| 2544 | table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - |
| 2545 | data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT; |
| 2546 | table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT; |
| 2547 | |
| 2548 | /* retrieve divider value for VBIOS */ |
| 2549 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 2550 | table->UvdLevel[count].VclkFrequency, ÷rs); |
| 2551 | PP_ASSERT_WITH_CODE((0 == result), |
| 2552 | "can not find divide id for Vclk clock", return result); |
| 2553 | |
| 2554 | table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; |
| 2555 | |
| 2556 | result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, |
| 2557 | table->UvdLevel[count].DclkFrequency, ÷rs); |
| 2558 | PP_ASSERT_WITH_CODE((0 == result), |
| 2559 | "can not find divide id for Dclk clock", return result); |
| 2560 | |
| 2561 | table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; |
| 2562 | |
| 2563 | CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); |
| 2564 | CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); |
| 2565 | CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage); |
| 2566 | |
| 2567 | } |
| 2568 | return result; |
| 2569 | } |
| 2570 | |
| 2571 | static int fiji_find_boot_level(struct fiji_single_dpm_table *table, |
| 2572 | uint32_t value, uint32_t *boot_level) |
| 2573 | { |
| 2574 | int result = -EINVAL; |
| 2575 | uint32_t i; |
| 2576 | |
| 2577 | for (i = 0; i < table->count; i++) { |
| 2578 | if (value == table->dpm_levels[i].value) { |
| 2579 | *boot_level = i; |
| 2580 | result = 0; |
| 2581 | } |
| 2582 | } |
| 2583 | return result; |
| 2584 | } |
| 2585 | |
| 2586 | static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr, |
| 2587 | struct SMU73_Discrete_DpmTable *table) |
| 2588 | { |
| 2589 | int result = 0; |
| 2590 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2591 | |
| 2592 | table->GraphicsBootLevel = 0; |
| 2593 | table->MemoryBootLevel = 0; |
| 2594 | |
| 2595 | /* find boot level from dpm table */ |
| 2596 | result = fiji_find_boot_level(&(data->dpm_table.sclk_table), |
| 2597 | data->vbios_boot_state.sclk_bootup_value, |
| 2598 | (uint32_t *)&(table->GraphicsBootLevel)); |
| 2599 | |
| 2600 | result = fiji_find_boot_level(&(data->dpm_table.mclk_table), |
| 2601 | data->vbios_boot_state.mclk_bootup_value, |
| 2602 | (uint32_t *)&(table->MemoryBootLevel)); |
| 2603 | |
| 2604 | table->BootVddc = data->vbios_boot_state.vddc_bootup_value * |
| 2605 | VOLTAGE_SCALE; |
| 2606 | table->BootVddci = data->vbios_boot_state.vddci_bootup_value * |
| 2607 | VOLTAGE_SCALE; |
| 2608 | table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value * |
| 2609 | VOLTAGE_SCALE; |
| 2610 | |
| 2611 | CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc); |
| 2612 | CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci); |
| 2613 | CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd); |
| 2614 | |
| 2615 | return 0; |
| 2616 | } |
| 2617 | |
| 2618 | static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) |
| 2619 | { |
| 2620 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2621 | struct phm_ppt_v1_information *table_info = |
| 2622 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2623 | uint8_t count, level; |
| 2624 | |
| 2625 | count = (uint8_t)(table_info->vdd_dep_on_sclk->count); |
| 2626 | for (level = 0; level < count; level++) { |
| 2627 | if(table_info->vdd_dep_on_sclk->entries[level].clk >= |
| 2628 | data->vbios_boot_state.sclk_bootup_value) { |
| 2629 | data->smc_state_table.GraphicsBootLevel = level; |
| 2630 | break; |
| 2631 | } |
| 2632 | } |
| 2633 | |
| 2634 | count = (uint8_t)(table_info->vdd_dep_on_mclk->count); |
| 2635 | for (level = 0; level < count; level++) { |
| 2636 | if(table_info->vdd_dep_on_mclk->entries[level].clk >= |
| 2637 | data->vbios_boot_state.mclk_bootup_value) { |
| 2638 | data->smc_state_table.MemoryBootLevel = level; |
| 2639 | break; |
| 2640 | } |
| 2641 | } |
| 2642 | |
| 2643 | return 0; |
| 2644 | } |
| 2645 | |
| 2646 | static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) |
| 2647 | { |
| 2648 | uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks, |
| 2649 | volt_with_cks, value; |
| 2650 | uint16_t clock_freq_u16; |
| 2651 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2652 | uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, |
| 2653 | volt_offset = 0; |
| 2654 | struct phm_ppt_v1_information *table_info = |
| 2655 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2656 | struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = |
| 2657 | table_info->vdd_dep_on_sclk; |
| 2658 | |
| 2659 | stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount; |
| 2660 | |
| 2661 | /* Read SMU_Eefuse to read and calculate RO and determine |
| 2662 | * if the part is SS or FF. if RO >= 1660MHz, part is FF. |
| 2663 | */ |
| 2664 | efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 2665 | ixSMU_EFUSE_0 + (146 * 4)); |
| 2666 | efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 2667 | ixSMU_EFUSE_0 + (148 * 4)); |
| 2668 | efuse &= 0xFF000000; |
| 2669 | efuse = efuse >> 24; |
| 2670 | efuse2 &= 0xF; |
| 2671 | |
| 2672 | if (efuse2 == 1) |
| 2673 | ro = (2300 - 1350) * efuse / 255 + 1350; |
| 2674 | else |
| 2675 | ro = (2500 - 1000) * efuse / 255 + 1000; |
| 2676 | |
| 2677 | if (ro >= 1660) |
| 2678 | type = 0; |
| 2679 | else |
| 2680 | type = 1; |
| 2681 | |
| 2682 | /* Populate Stretch amount */ |
| 2683 | data->smc_state_table.ClockStretcherAmount = stretch_amount; |
| 2684 | |
| 2685 | /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */ |
| 2686 | for (i = 0; i < sclk_table->count; i++) { |
| 2687 | data->smc_state_table.Sclk_CKS_masterEn0_7 |= |
| 2688 | sclk_table->entries[i].cks_enable << i; |
| 2689 | volt_without_cks = (uint32_t)((14041 * |
| 2690 | (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 / |
| 2691 | (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000))); |
| 2692 | volt_with_cks = (uint32_t)((13946 * |
| 2693 | (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 / |
| 2694 | (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000))); |
| 2695 | if (volt_without_cks >= volt_with_cks) |
| 2696 | volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks + |
| 2697 | sclk_table->entries[i].cks_voffset) * 100 / 625) + 1); |
| 2698 | data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; |
| 2699 | } |
| 2700 | |
| 2701 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, |
| 2702 | STRETCH_ENABLE, 0x0); |
| 2703 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, |
| 2704 | masterReset, 0x1); |
| 2705 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, |
| 2706 | staticEnable, 0x1); |
| 2707 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, |
| 2708 | masterReset, 0x0); |
| 2709 | |
| 2710 | /* Populate CKS Lookup Table */ |
| 2711 | if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5) |
| 2712 | stretch_amount2 = 0; |
| 2713 | else if (stretch_amount == 3 || stretch_amount == 4) |
| 2714 | stretch_amount2 = 1; |
| 2715 | else { |
| 2716 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 2717 | PHM_PlatformCaps_ClockStretcher); |
| 2718 | PP_ASSERT_WITH_CODE(false, |
| 2719 | "Stretch Amount in PPTable not supported\n", |
| 2720 | return -EINVAL); |
| 2721 | } |
| 2722 | |
| 2723 | value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 2724 | ixPWR_CKS_CNTL); |
| 2725 | value &= 0xFFC2FF87; |
| 2726 | data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq = |
| 2727 | fiji_clock_stretcher_lookup_table[stretch_amount2][0]; |
| 2728 | data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq = |
| 2729 | fiji_clock_stretcher_lookup_table[stretch_amount2][1]; |
| 2730 | clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table. |
| 2731 | GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1]. |
| 2732 | SclkFrequency) / 100); |
| 2733 | if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] < |
| 2734 | clock_freq_u16 && |
| 2735 | fiji_clock_stretcher_lookup_table[stretch_amount2][1] > |
| 2736 | clock_freq_u16) { |
| 2737 | /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */ |
| 2738 | value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16; |
| 2739 | /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */ |
| 2740 | value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18; |
| 2741 | /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */ |
| 2742 | value |= (fiji_clock_stretch_amount_conversion |
| 2743 | [fiji_clock_stretcher_lookup_table[stretch_amount2][3]] |
| 2744 | [stretch_amount]) << 3; |
| 2745 | } |
| 2746 | CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable. |
| 2747 | CKS_LOOKUPTableEntry[0].minFreq); |
| 2748 | CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable. |
| 2749 | CKS_LOOKUPTableEntry[0].maxFreq); |
| 2750 | data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting = |
| 2751 | fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F; |
| 2752 | data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |= |
| 2753 | (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7; |
| 2754 | |
| 2755 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 2756 | ixPWR_CKS_CNTL, value); |
| 2757 | |
| 2758 | /* Populate DDT Lookup Table */ |
| 2759 | for (i = 0; i < 4; i++) { |
| 2760 | /* Assign the minimum and maximum VID stored |
| 2761 | * in the last row of Clock Stretcher Voltage Table. |
| 2762 | */ |
| 2763 | data->smc_state_table.ClockStretcherDataTable. |
| 2764 | ClockStretcherDataTableEntry[i].minVID = |
| 2765 | (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2]; |
| 2766 | data->smc_state_table.ClockStretcherDataTable. |
| 2767 | ClockStretcherDataTableEntry[i].maxVID = |
| 2768 | (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3]; |
| 2769 | /* Loop through each SCLK and check the frequency |
| 2770 | * to see if it lies within the frequency for clock stretcher. |
| 2771 | */ |
| 2772 | for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) { |
| 2773 | cks_setting = 0; |
| 2774 | clock_freq = PP_SMC_TO_HOST_UL( |
| 2775 | data->smc_state_table.GraphicsLevel[j].SclkFrequency); |
| 2776 | /* Check the allowed frequency against the sclk level[j]. |
| 2777 | * Sclk's endianness has already been converted, |
| 2778 | * and it's in 10Khz unit, |
| 2779 | * as opposed to Data table, which is in Mhz unit. |
| 2780 | */ |
| 2781 | if (clock_freq >= |
| 2782 | (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) { |
| 2783 | cks_setting |= 0x2; |
| 2784 | if (clock_freq < |
| 2785 | (fiji_clock_stretcher_ddt_table[type][i][1]) * 100) |
| 2786 | cks_setting |= 0x1; |
| 2787 | } |
| 2788 | data->smc_state_table.ClockStretcherDataTable. |
| 2789 | ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2); |
| 2790 | } |
| 2791 | CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table. |
| 2792 | ClockStretcherDataTable. |
| 2793 | ClockStretcherDataTableEntry[i].setting); |
| 2794 | } |
| 2795 | |
| 2796 | value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL); |
| 2797 | value &= 0xFFFFFFFE; |
| 2798 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value); |
| 2799 | |
| 2800 | return 0; |
| 2801 | } |
| 2802 | |
| 2803 | /** |
| 2804 | * Populates the SMC VRConfig field in DPM table. |
| 2805 | * |
| 2806 | * @param hwmgr the address of the hardware manager |
| 2807 | * @param table the SMC DPM table structure to be populated |
| 2808 | * @return always 0 |
| 2809 | */ |
| 2810 | static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr, |
| 2811 | struct SMU73_Discrete_DpmTable *table) |
| 2812 | { |
| 2813 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2814 | uint16_t config; |
| 2815 | |
| 2816 | config = VR_MERGED_WITH_VDDC; |
| 2817 | table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT); |
| 2818 | |
| 2819 | /* Set Vddc Voltage Controller */ |
| 2820 | if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { |
| 2821 | config = VR_SVI2_PLANE_1; |
| 2822 | table->VRConfig |= config; |
| 2823 | } else { |
| 2824 | PP_ASSERT_WITH_CODE(false, |
| 2825 | "VDDC should be on SVI2 control in merged mode!",); |
| 2826 | } |
| 2827 | /* Set Vddci Voltage Controller */ |
| 2828 | if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { |
| 2829 | config = VR_SVI2_PLANE_2; /* only in merged mode */ |
| 2830 | table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); |
| 2831 | } else if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { |
| 2832 | config = VR_SMIO_PATTERN_1; |
| 2833 | table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); |
| 2834 | } else { |
| 2835 | config = VR_STATIC_VOLTAGE; |
| 2836 | table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); |
| 2837 | } |
| 2838 | /* Set Mvdd Voltage Controller */ |
| 2839 | if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { |
| 2840 | config = VR_SVI2_PLANE_2; |
| 2841 | table->VRConfig |= (config << VRCONF_MVDD_SHIFT); |
| 2842 | } else if(FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { |
| 2843 | config = VR_SMIO_PATTERN_2; |
| 2844 | table->VRConfig |= (config << VRCONF_MVDD_SHIFT); |
| 2845 | } else { |
| 2846 | config = VR_STATIC_VOLTAGE; |
| 2847 | table->VRConfig |= (config << VRCONF_MVDD_SHIFT); |
| 2848 | } |
| 2849 | |
| 2850 | return 0; |
| 2851 | } |
| 2852 | |
| 2853 | /** |
| 2854 | * Initializes the SMC table and uploads it |
| 2855 | * |
| 2856 | * @param hwmgr the address of the powerplay hardware manager. |
| 2857 | * @param pInput the pointer to input data (PowerState) |
| 2858 | * @return always 0 |
| 2859 | */ |
| 2860 | static int fiji_init_smc_table(struct pp_hwmgr *hwmgr) |
| 2861 | { |
| 2862 | int result; |
| 2863 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 2864 | struct phm_ppt_v1_information *table_info = |
| 2865 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 2866 | struct SMU73_Discrete_DpmTable *table = &(data->smc_state_table); |
| 2867 | const struct fiji_ulv_parm *ulv = &(data->ulv); |
| 2868 | uint8_t i; |
| 2869 | struct pp_atomctrl_gpio_pin_assignment gpio_pin; |
| 2870 | |
| 2871 | result = fiji_setup_default_dpm_tables(hwmgr); |
| 2872 | PP_ASSERT_WITH_CODE(0 == result, |
| 2873 | "Failed to setup default DPM tables!", return result); |
| 2874 | |
| 2875 | if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control) |
| 2876 | fiji_populate_smc_voltage_tables(hwmgr, table); |
| 2877 | |
| 2878 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2879 | PHM_PlatformCaps_AutomaticDCTransition)) |
| 2880 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; |
| 2881 | |
| 2882 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2883 | PHM_PlatformCaps_StepVddc)) |
| 2884 | table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; |
| 2885 | |
| 2886 | if (data->is_memory_gddr5) |
| 2887 | table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; |
| 2888 | |
| 2889 | if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) { |
| 2890 | result = fiji_populate_ulv_state(hwmgr, table); |
| 2891 | PP_ASSERT_WITH_CODE(0 == result, |
| 2892 | "Failed to initialize ULV state!", return result); |
| 2893 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 2894 | ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter); |
| 2895 | } |
| 2896 | |
| 2897 | result = fiji_populate_smc_link_level(hwmgr, table); |
| 2898 | PP_ASSERT_WITH_CODE(0 == result, |
| 2899 | "Failed to initialize Link Level!", return result); |
| 2900 | |
| 2901 | result = fiji_populate_all_graphic_levels(hwmgr); |
| 2902 | PP_ASSERT_WITH_CODE(0 == result, |
| 2903 | "Failed to initialize Graphics Level!", return result); |
| 2904 | |
| 2905 | result = fiji_populate_all_memory_levels(hwmgr); |
| 2906 | PP_ASSERT_WITH_CODE(0 == result, |
| 2907 | "Failed to initialize Memory Level!", return result); |
| 2908 | |
| 2909 | result = fiji_populate_smc_acpi_level(hwmgr, table); |
| 2910 | PP_ASSERT_WITH_CODE(0 == result, |
| 2911 | "Failed to initialize ACPI Level!", return result); |
| 2912 | |
| 2913 | result = fiji_populate_smc_vce_level(hwmgr, table); |
| 2914 | PP_ASSERT_WITH_CODE(0 == result, |
| 2915 | "Failed to initialize VCE Level!", return result); |
| 2916 | |
| 2917 | result = fiji_populate_smc_acp_level(hwmgr, table); |
| 2918 | PP_ASSERT_WITH_CODE(0 == result, |
| 2919 | "Failed to initialize ACP Level!", return result); |
| 2920 | |
| 2921 | result = fiji_populate_smc_samu_level(hwmgr, table); |
| 2922 | PP_ASSERT_WITH_CODE(0 == result, |
| 2923 | "Failed to initialize SAMU Level!", return result); |
| 2924 | |
| 2925 | /* Since only the initial state is completely set up at this point |
| 2926 | * (the other states are just copies of the boot state) we only |
| 2927 | * need to populate the ARB settings for the initial state. |
| 2928 | */ |
| 2929 | result = fiji_program_memory_timing_parameters(hwmgr); |
| 2930 | PP_ASSERT_WITH_CODE(0 == result, |
| 2931 | "Failed to Write ARB settings for the initial state.", return result); |
| 2932 | |
| 2933 | result = fiji_populate_smc_uvd_level(hwmgr, table); |
| 2934 | PP_ASSERT_WITH_CODE(0 == result, |
| 2935 | "Failed to initialize UVD Level!", return result); |
| 2936 | |
| 2937 | result = fiji_populate_smc_boot_level(hwmgr, table); |
| 2938 | PP_ASSERT_WITH_CODE(0 == result, |
| 2939 | "Failed to initialize Boot Level!", return result); |
| 2940 | |
| 2941 | result = fiji_populate_smc_initailial_state(hwmgr); |
| 2942 | PP_ASSERT_WITH_CODE(0 == result, |
| 2943 | "Failed to initialize Boot State!", return result); |
| 2944 | |
| 2945 | result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr); |
| 2946 | PP_ASSERT_WITH_CODE(0 == result, |
| 2947 | "Failed to populate BAPM Parameters!", return result); |
| 2948 | |
| 2949 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 2950 | PHM_PlatformCaps_ClockStretcher)) { |
| 2951 | result = fiji_populate_clock_stretcher_data_table(hwmgr); |
| 2952 | PP_ASSERT_WITH_CODE(0 == result, |
| 2953 | "Failed to populate Clock Stretcher Data Table!", |
| 2954 | return result); |
| 2955 | } |
| 2956 | |
| 2957 | table->GraphicsVoltageChangeEnable = 1; |
| 2958 | table->GraphicsThermThrottleEnable = 1; |
| 2959 | table->GraphicsInterval = 1; |
| 2960 | table->VoltageInterval = 1; |
| 2961 | table->ThermalInterval = 1; |
| 2962 | table->TemperatureLimitHigh = |
| 2963 | table_info->cac_dtp_table->usTargetOperatingTemp * |
| 2964 | FIJI_Q88_FORMAT_CONVERSION_UNIT; |
| 2965 | table->TemperatureLimitLow = |
| 2966 | (table_info->cac_dtp_table->usTargetOperatingTemp - 1) * |
| 2967 | FIJI_Q88_FORMAT_CONVERSION_UNIT; |
| 2968 | table->MemoryVoltageChangeEnable = 1; |
| 2969 | table->MemoryInterval = 1; |
| 2970 | table->VoltageResponseTime = 0; |
| 2971 | table->PhaseResponseTime = 0; |
| 2972 | table->MemoryThermThrottleEnable = 1; |
| 2973 | table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/ |
| 2974 | table->PCIeGenInterval = 1; |
| 2975 | |
| 2976 | result = fiji_populate_vr_config(hwmgr, table); |
| 2977 | PP_ASSERT_WITH_CODE(0 == result, |
| 2978 | "Failed to populate VRConfig setting!", return result); |
| 2979 | |
| 2980 | table->ThermGpio = 17; |
| 2981 | table->SclkStepSize = 0x4000; |
| 2982 | |
| 2983 | if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) { |
| 2984 | table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift; |
| 2985 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 2986 | PHM_PlatformCaps_RegulatorHot); |
| 2987 | } else { |
| 2988 | table->VRHotGpio = FIJI_UNUSED_GPIO_PIN; |
| 2989 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 2990 | PHM_PlatformCaps_RegulatorHot); |
| 2991 | } |
| 2992 | |
| 2993 | if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID, |
| 2994 | &gpio_pin)) { |
| 2995 | table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift; |
| 2996 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 2997 | PHM_PlatformCaps_AutomaticDCTransition); |
| 2998 | } else { |
| 2999 | table->AcDcGpio = FIJI_UNUSED_GPIO_PIN; |
| 3000 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 3001 | PHM_PlatformCaps_AutomaticDCTransition); |
| 3002 | } |
| 3003 | |
| 3004 | /* Thermal Output GPIO */ |
| 3005 | if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID, |
| 3006 | &gpio_pin)) { |
| 3007 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
| 3008 | PHM_PlatformCaps_ThermalOutGPIO); |
| 3009 | |
| 3010 | table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift; |
| 3011 | |
| 3012 | /* For porlarity read GPIOPAD_A with assigned Gpio pin |
| 3013 | * since VBIOS will program this register to set 'inactive state', |
| 3014 | * driver can then determine 'active state' from this and |
| 3015 | * program SMU with correct polarity |
| 3016 | */ |
| 3017 | table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) & |
| 3018 | (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0; |
| 3019 | table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY; |
| 3020 | |
| 3021 | /* if required, combine VRHot/PCC with thermal out GPIO */ |
| 3022 | if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 3023 | PHM_PlatformCaps_RegulatorHot) && |
| 3024 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 3025 | PHM_PlatformCaps_CombinePCCWithThermalSignal)) |
| 3026 | table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT; |
| 3027 | } else { |
| 3028 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
| 3029 | PHM_PlatformCaps_ThermalOutGPIO); |
| 3030 | table->ThermOutGpio = 17; |
| 3031 | table->ThermOutPolarity = 1; |
| 3032 | table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE; |
| 3033 | } |
| 3034 | |
| 3035 | for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++) |
| 3036 | table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); |
| 3037 | |
| 3038 | CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); |
| 3039 | CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig); |
| 3040 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1); |
| 3041 | CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2); |
| 3042 | CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); |
| 3043 | CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); |
| 3044 | CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); |
| 3045 | CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); |
| 3046 | CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); |
| 3047 | |
| 3048 | /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ |
| 3049 | result = fiji_copy_bytes_to_smc(hwmgr->smumgr, |
| 3050 | data->dpm_table_start + |
| 3051 | offsetof(SMU73_Discrete_DpmTable, SystemFlags), |
| 3052 | (uint8_t *)&(table->SystemFlags), |
| 3053 | sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController), |
| 3054 | data->sram_end); |
| 3055 | PP_ASSERT_WITH_CODE(0 == result, |
| 3056 | "Failed to upload dpm data to SMC memory!", return result); |
| 3057 | |
| 3058 | return 0; |
| 3059 | } |
| 3060 | |
| 3061 | /** |
| 3062 | * Initialize the ARB DRAM timing table's index field. |
| 3063 | * |
| 3064 | * @param hwmgr the address of the powerplay hardware manager. |
| 3065 | * @return always 0 |
| 3066 | */ |
| 3067 | static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr) |
| 3068 | { |
| 3069 | const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 3070 | uint32_t tmp; |
| 3071 | int result; |
| 3072 | |
| 3073 | /* This is a read-modify-write on the first byte of the ARB table. |
| 3074 | * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure |
| 3075 | * is the field 'current'. |
| 3076 | * This solution is ugly, but we never write the whole table only |
| 3077 | * individual fields in it. |
| 3078 | * In reality this field should not be in that structure |
| 3079 | * but in a soft register. |
| 3080 | */ |
| 3081 | result = fiji_read_smc_sram_dword(hwmgr->smumgr, |
| 3082 | data->arb_table_start, &tmp, data->sram_end); |
| 3083 | |
| 3084 | if (result) |
| 3085 | return result; |
| 3086 | |
| 3087 | tmp &= 0x00FFFFFF; |
| 3088 | tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; |
| 3089 | |
| 3090 | return fiji_write_smc_sram_dword(hwmgr->smumgr, |
| 3091 | data->arb_table_start, tmp, data->sram_end); |
| 3092 | } |
| 3093 | |
| 3094 | static int fiji_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) |
| 3095 | { |
| 3096 | if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 3097 | PHM_PlatformCaps_RegulatorHot)) |
| 3098 | return smum_send_msg_to_smc(hwmgr->smumgr, |
| 3099 | PPSMC_MSG_EnableVRHotGPIOInterrupt); |
| 3100 | |
| 3101 | return 0; |
| 3102 | } |
| 3103 | |
| 3104 | static int fiji_enable_sclk_control(struct pp_hwmgr *hwmgr) |
| 3105 | { |
| 3106 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, |
| 3107 | SCLK_PWRMGT_OFF, 0); |
| 3108 | return 0; |
| 3109 | } |
| 3110 | |
| 3111 | static int fiji_enable_ulv(struct pp_hwmgr *hwmgr) |
| 3112 | { |
| 3113 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 3114 | struct fiji_ulv_parm *ulv = &(data->ulv); |
| 3115 | |
| 3116 | if (ulv->ulv_supported) |
| 3117 | return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV); |
| 3118 | |
| 3119 | return 0; |
| 3120 | } |
| 3121 | |
| 3122 | static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) |
| 3123 | { |
| 3124 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 3125 | PHM_PlatformCaps_SclkDeepSleep)) { |
| 3126 | if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON)) |
| 3127 | PP_ASSERT_WITH_CODE(false, |
| 3128 | "Attempt to enable Master Deep Sleep switch failed!", |
| 3129 | return -1); |
| 3130 | } else { |
| 3131 | if (smum_send_msg_to_smc(hwmgr->smumgr, |
| 3132 | PPSMC_MSG_MASTER_DeepSleep_OFF)) { |
| 3133 | PP_ASSERT_WITH_CODE(false, |
| 3134 | "Attempt to disable Master Deep Sleep switch failed!", |
| 3135 | return -1); |
| 3136 | } |
| 3137 | } |
| 3138 | |
| 3139 | return 0; |
| 3140 | } |
| 3141 | |
| 3142 | static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) |
| 3143 | { |
| 3144 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 3145 | uint32_t val, val0, val2; |
| 3146 | uint32_t i, cpl_cntl, cpl_threshold, mc_threshold; |
| 3147 | |
| 3148 | /* enable SCLK dpm */ |
| 3149 | if(!data->sclk_dpm_key_disabled) |
| 3150 | PP_ASSERT_WITH_CODE( |
| 3151 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)), |
| 3152 | "Failed to enable SCLK DPM during DPM Start Function!", |
| 3153 | return -1); |
| 3154 | |
| 3155 | /* enable MCLK dpm */ |
| 3156 | if(0 == data->mclk_dpm_key_disabled) { |
| 3157 | cpl_threshold = 0; |
| 3158 | mc_threshold = 0; |
| 3159 | |
| 3160 | /* Read per MCD tile (0 - 7) */ |
| 3161 | for (i = 0; i < 8; i++) { |
| 3162 | PHM_WRITE_FIELD(hwmgr->device, MC_CONFIG_MCD, MC_RD_ENABLE, i); |
| 3163 | val = cgs_read_register(hwmgr->device, mmMC_SEQ_RESERVE_0_S) & 0xf0000000; |
| 3164 | if (0xf0000000 != val) { |
| 3165 | /* count number of MCQ that has channel(s) enabled */ |
| 3166 | cpl_threshold++; |
| 3167 | /* only harvest 3 or full 4 supported */ |
| 3168 | mc_threshold = val ? 3 : 4; |
| 3169 | } |
| 3170 | } |
| 3171 | PP_ASSERT_WITH_CODE(0 != cpl_threshold, |
| 3172 | "Number of MCQ is zero!", return -EINVAL;); |
| 3173 | |
| 3174 | mc_threshold = ((mc_threshold & LCAC_MC0_CNTL__MC0_THRESHOLD_MASK) << |
| 3175 | LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT) | |
| 3176 | LCAC_MC0_CNTL__MC0_ENABLE_MASK; |
| 3177 | cpl_cntl = ((cpl_threshold & LCAC_CPL_CNTL__CPL_THRESHOLD_MASK) << |
| 3178 | LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT) | |
| 3179 | LCAC_CPL_CNTL__CPL_ENABLE_MASK; |
| 3180 | cpl_cntl = (cpl_cntl | (8 << LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT)); |
| 3181 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3182 | ixLCAC_MC0_CNTL, mc_threshold); |
| 3183 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3184 | ixLCAC_MC1_CNTL, mc_threshold); |
| 3185 | if (8 == cpl_threshold) { |
| 3186 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3187 | ixLCAC_MC2_CNTL, mc_threshold); |
| 3188 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3189 | ixLCAC_MC3_CNTL, mc_threshold); |
| 3190 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3191 | ixLCAC_MC4_CNTL, mc_threshold); |
| 3192 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3193 | ixLCAC_MC5_CNTL, mc_threshold); |
| 3194 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3195 | ixLCAC_MC6_CNTL, mc_threshold); |
| 3196 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3197 | ixLCAC_MC7_CNTL, mc_threshold); |
| 3198 | } |
| 3199 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3200 | ixLCAC_CPL_CNTL, cpl_cntl); |
| 3201 | |
| 3202 | udelay(5); |
| 3203 | |
| 3204 | mc_threshold = mc_threshold | |
| 3205 | (1 << LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT); |
| 3206 | cpl_cntl = cpl_cntl | (1 << LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT); |
| 3207 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3208 | ixLCAC_MC0_CNTL, mc_threshold); |
| 3209 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3210 | ixLCAC_MC1_CNTL, mc_threshold); |
| 3211 | if (8 == cpl_threshold) { |
| 3212 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3213 | ixLCAC_MC2_CNTL, mc_threshold); |
| 3214 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3215 | ixLCAC_MC3_CNTL, mc_threshold); |
| 3216 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3217 | ixLCAC_MC4_CNTL, mc_threshold); |
| 3218 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3219 | ixLCAC_MC5_CNTL, mc_threshold); |
| 3220 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3221 | ixLCAC_MC6_CNTL, mc_threshold); |
| 3222 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3223 | ixLCAC_MC7_CNTL, mc_threshold); |
| 3224 | } |
| 3225 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3226 | ixLCAC_CPL_CNTL, cpl_cntl); |
| 3227 | |
| 3228 | /* Program CAC_EN per MCD (0-7) Tile */ |
| 3229 | val0 = val = cgs_read_register(hwmgr->device, mmMC_CONFIG_MCD); |
| 3230 | val &= ~(MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK | |
| 3231 | MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK | |
| 3232 | MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK | |
| 3233 | MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK | |
| 3234 | MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK | |
| 3235 | MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK | |
| 3236 | MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK | |
| 3237 | MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK | |
| 3238 | MC_CONFIG_MCD__MC_RD_ENABLE_MASK); |
| 3239 | |
| 3240 | for (i = 0; i < 8; i++) { |
| 3241 | /* Enable MCD i Tile read & write */ |
| 3242 | val2 = (val | (i << MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT) | |
| 3243 | (1 << i)); |
| 3244 | cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val2); |
| 3245 | /* Enbale CAC_ON MCD i Tile */ |
| 3246 | val2 = cgs_read_register(hwmgr->device, mmMC_SEQ_CNTL); |
| 3247 | val2 |= MC_SEQ_CNTL__CAC_EN_MASK; |
| 3248 | cgs_write_register(hwmgr->device, mmMC_SEQ_CNTL, val2); |
| 3249 | } |
| 3250 | /* Set MC_CONFIG_MCD back to its default setting val0 */ |
| 3251 | cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val0); |
| 3252 | |
| 3253 | PP_ASSERT_WITH_CODE( |
| 3254 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 3255 | PPSMC_MSG_MCLKDPM_Enable)), |
| 3256 | "Failed to enable MCLK DPM during DPM Start Function!", |
| 3257 | return -1); |
| 3258 | } |
| 3259 | return 0; |
| 3260 | } |
| 3261 | |
| 3262 | static int fiji_start_dpm(struct pp_hwmgr *hwmgr) |
| 3263 | { |
| 3264 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 3265 | |
| 3266 | /*enable general power management */ |
| 3267 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, |
| 3268 | GLOBAL_PWRMGT_EN, 1); |
| 3269 | /* enable sclk deep sleep */ |
| 3270 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, |
| 3271 | DYNAMIC_PM_EN, 1); |
| 3272 | /* prepare for PCIE DPM */ |
| 3273 | cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, |
| 3274 | data->soft_regs_start + offsetof(SMU73_SoftRegisters, |
| 3275 | VoltageChangeTimeout), 0x1000); |
| 3276 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, |
| 3277 | SWRST_COMMAND_1, RESETLC, 0x0); |
| 3278 | |
| 3279 | PP_ASSERT_WITH_CODE( |
| 3280 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 3281 | PPSMC_MSG_Voltage_Cntl_Enable)), |
| 3282 | "Failed to enable voltage DPM during DPM Start Function!", |
| 3283 | return -1); |
| 3284 | |
| 3285 | if (fiji_enable_sclk_mclk_dpm(hwmgr)) { |
| 3286 | printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!"); |
| 3287 | return -1; |
| 3288 | } |
| 3289 | |
| 3290 | /* enable PCIE dpm */ |
| 3291 | if(!data->pcie_dpm_key_disabled) { |
| 3292 | PP_ASSERT_WITH_CODE( |
| 3293 | (0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 3294 | PPSMC_MSG_PCIeDPM_Enable)), |
| 3295 | "Failed to enable pcie DPM during DPM Start Function!", |
| 3296 | return -1); |
| 3297 | } |
| 3298 | |
| 3299 | return 0; |
| 3300 | } |
| 3301 | |
| 3302 | static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr, |
| 3303 | uint32_t sources) |
| 3304 | { |
| 3305 | bool protection; |
| 3306 | enum DPM_EVENT_SRC src; |
| 3307 | |
| 3308 | switch (sources) { |
| 3309 | default: |
| 3310 | printk(KERN_ERR "Unknown throttling event sources."); |
| 3311 | /* fall through */ |
| 3312 | case 0: |
| 3313 | protection = false; |
| 3314 | /* src is unused */ |
| 3315 | break; |
| 3316 | case (1 << PHM_AutoThrottleSource_Thermal): |
| 3317 | protection = true; |
| 3318 | src = DPM_EVENT_SRC_DIGITAL; |
| 3319 | break; |
| 3320 | case (1 << PHM_AutoThrottleSource_External): |
| 3321 | protection = true; |
| 3322 | src = DPM_EVENT_SRC_EXTERNAL; |
| 3323 | break; |
| 3324 | case (1 << PHM_AutoThrottleSource_External) | |
| 3325 | (1 << PHM_AutoThrottleSource_Thermal): |
| 3326 | protection = true; |
| 3327 | src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL; |
| 3328 | break; |
| 3329 | } |
| 3330 | /* Order matters - don't enable thermal protection for the wrong source. */ |
| 3331 | if (protection) { |
| 3332 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, |
| 3333 | DPM_EVENT_SRC, src); |
| 3334 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, |
| 3335 | THERMAL_PROTECTION_DIS, |
| 3336 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 3337 | PHM_PlatformCaps_ThermalController)); |
| 3338 | } else |
| 3339 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, |
| 3340 | THERMAL_PROTECTION_DIS, 1); |
| 3341 | } |
| 3342 | |
| 3343 | static int fiji_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, |
| 3344 | PHM_AutoThrottleSource source) |
| 3345 | { |
| 3346 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 3347 | |
| 3348 | if (!(data->active_auto_throttle_sources & (1 << source))) { |
| 3349 | data->active_auto_throttle_sources |= 1 << source; |
| 3350 | fiji_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); |
| 3351 | } |
| 3352 | return 0; |
| 3353 | } |
| 3354 | |
| 3355 | static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) |
| 3356 | { |
| 3357 | return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); |
| 3358 | } |
| 3359 | |
| 3360 | static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr) |
| 3361 | { |
| 3362 | int tmp_result, result = 0; |
| 3363 | |
| 3364 | tmp_result = (!fiji_is_dpm_running(hwmgr))? 0 : -1; |
| 3365 | PP_ASSERT_WITH_CODE(result == 0, |
| 3366 | "DPM is already running right now, no need to enable DPM!", |
| 3367 | return 0); |
| 3368 | |
| 3369 | if (fiji_voltage_control(hwmgr)) { |
| 3370 | tmp_result = fiji_enable_voltage_control(hwmgr); |
| 3371 | PP_ASSERT_WITH_CODE(tmp_result == 0, |
| 3372 | "Failed to enable voltage control!", |
| 3373 | result = tmp_result); |
| 3374 | } |
| 3375 | |
| 3376 | if (fiji_voltage_control(hwmgr)) { |
| 3377 | tmp_result = fiji_construct_voltage_tables(hwmgr); |
| 3378 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3379 | "Failed to contruct voltage tables!", |
| 3380 | result = tmp_result); |
| 3381 | } |
| 3382 | |
| 3383 | tmp_result = fiji_initialize_mc_reg_table(hwmgr); |
| 3384 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3385 | "Failed to initialize MC reg table!", result = tmp_result); |
| 3386 | |
| 3387 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 3388 | PHM_PlatformCaps_EngineSpreadSpectrumSupport)) |
| 3389 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 3390 | GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1); |
| 3391 | |
| 3392 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 3393 | PHM_PlatformCaps_ThermalController)) |
| 3394 | PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, |
| 3395 | GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0); |
| 3396 | |
| 3397 | tmp_result = fiji_program_static_screen_threshold_parameters(hwmgr); |
| 3398 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3399 | "Failed to program static screen threshold parameters!", |
| 3400 | result = tmp_result); |
| 3401 | |
| 3402 | tmp_result = fiji_enable_display_gap(hwmgr); |
| 3403 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3404 | "Failed to enable display gap!", result = tmp_result); |
| 3405 | |
| 3406 | tmp_result = fiji_program_voting_clients(hwmgr); |
| 3407 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3408 | "Failed to program voting clients!", result = tmp_result); |
| 3409 | |
| 3410 | tmp_result = fiji_process_firmware_header(hwmgr); |
| 3411 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3412 | "Failed to process firmware header!", result = tmp_result); |
| 3413 | |
| 3414 | tmp_result = fiji_initial_switch_from_arbf0_to_f1(hwmgr); |
| 3415 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3416 | "Failed to initialize switch from ArbF0 to F1!", |
| 3417 | result = tmp_result); |
| 3418 | |
| 3419 | tmp_result = fiji_init_smc_table(hwmgr); |
| 3420 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3421 | "Failed to initialize SMC table!", result = tmp_result); |
| 3422 | |
| 3423 | tmp_result = fiji_init_arb_table_index(hwmgr); |
| 3424 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3425 | "Failed to initialize ARB table index!", result = tmp_result); |
| 3426 | |
| 3427 | tmp_result = fiji_populate_pm_fuses(hwmgr); |
| 3428 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3429 | "Failed to populate PM fuses!", result = tmp_result); |
| 3430 | |
| 3431 | tmp_result = fiji_enable_vrhot_gpio_interrupt(hwmgr); |
| 3432 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3433 | "Failed to enable VR hot GPIO interrupt!", result = tmp_result); |
| 3434 | |
| 3435 | tmp_result = fiji_enable_sclk_control(hwmgr); |
| 3436 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3437 | "Failed to enable SCLK control!", result = tmp_result); |
| 3438 | |
| 3439 | tmp_result = fiji_enable_ulv(hwmgr); |
| 3440 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3441 | "Failed to enable ULV!", result = tmp_result); |
| 3442 | |
| 3443 | tmp_result = fiji_enable_deep_sleep_master_switch(hwmgr); |
| 3444 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3445 | "Failed to enable deep sleep master switch!", result = tmp_result); |
| 3446 | |
| 3447 | tmp_result = fiji_start_dpm(hwmgr); |
| 3448 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3449 | "Failed to start DPM!", result = tmp_result); |
| 3450 | |
| 3451 | tmp_result = fiji_enable_smc_cac(hwmgr); |
| 3452 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3453 | "Failed to enable SMC CAC!", result = tmp_result); |
| 3454 | |
| 3455 | tmp_result = fiji_enable_power_containment(hwmgr); |
| 3456 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3457 | "Failed to enable power containment!", result = tmp_result); |
| 3458 | |
| 3459 | tmp_result = fiji_power_control_set_level(hwmgr); |
| 3460 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3461 | "Failed to power control set level!", result = tmp_result); |
| 3462 | |
| 3463 | tmp_result = fiji_enable_thermal_auto_throttle(hwmgr); |
| 3464 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 3465 | "Failed to enable thermal auto throttle!", result = tmp_result); |
| 3466 | |
| 3467 | return result; |
| 3468 | } |
| 3469 | |
| 3470 | static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr) |
| 3471 | { |
| 3472 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 3473 | uint32_t level, tmp; |
| 3474 | |
| 3475 | if (!data->sclk_dpm_key_disabled) { |
| 3476 | if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { |
| 3477 | level = 0; |
| 3478 | tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; |
| 3479 | while (tmp >>= 1) |
| 3480 | level++; |
| 3481 | if (level) |
| 3482 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 3483 | PPSMC_MSG_SCLKDPM_SetEnabledMask, |
| 3484 | (1 << level)); |
| 3485 | } |
| 3486 | } |
| 3487 | |
| 3488 | if (!data->mclk_dpm_key_disabled) { |
| 3489 | if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { |
| 3490 | level = 0; |
| 3491 | tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; |
| 3492 | while (tmp >>= 1) |
| 3493 | level++; |
| 3494 | if (level) |
| 3495 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 3496 | PPSMC_MSG_MCLKDPM_SetEnabledMask, |
| 3497 | (1 << level)); |
| 3498 | } |
| 3499 | } |
| 3500 | |
| 3501 | if (!data->pcie_dpm_key_disabled) { |
| 3502 | if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { |
| 3503 | level = 0; |
| 3504 | tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; |
| 3505 | while (tmp >>= 1) |
| 3506 | level++; |
| 3507 | if (level) |
| 3508 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 3509 | PPSMC_MSG_PCIeDPM_ForceLevel, |
| 3510 | (1 << level)); |
| 3511 | } |
| 3512 | } |
| 3513 | return 0; |
| 3514 | } |
| 3515 | |
| 3516 | static void fiji_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr) |
| 3517 | { |
| 3518 | struct phm_ppt_v1_information *table_info = |
| 3519 | (struct phm_ppt_v1_information *)hwmgr->pptable; |
| 3520 | struct phm_clock_voltage_dependency_table *table = |
| 3521 | table_info->vddc_dep_on_dal_pwrl; |
| 3522 | struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table; |
| 3523 | enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level; |
| 3524 | uint32_t req_vddc = 0, req_volt, i; |
| 3525 | |
| 3526 | if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW && |
| 3527 | dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE)) |
| 3528 | return; |
| 3529 | |
| 3530 | for (i= 0; i < table->count; i++) { |
| 3531 | if (dal_power_level == table->entries[i].clk) { |
| 3532 | req_vddc = table->entries[i].v; |
| 3533 | break; |
| 3534 | } |
| 3535 | } |
| 3536 | |
| 3537 | vddc_table = table_info->vdd_dep_on_sclk; |
| 3538 | for (i= 0; i < vddc_table->count; i++) { |
| 3539 | if (req_vddc <= vddc_table->entries[i].vddc) { |
| 3540 | req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE) |
| 3541 | << VDDC_SHIFT; |
| 3542 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 3543 | PPSMC_MSG_VddC_Request, req_volt); |
| 3544 | return; |
| 3545 | } |
| 3546 | } |
| 3547 | printk(KERN_ERR "DAL requested level can not" |
| 3548 | " found a available voltage in VDDC DPM Table \n"); |
| 3549 | } |
| 3550 | |
| 3551 | static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr *hwmgr) |
| 3552 | { |
| 3553 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 3554 | |
| 3555 | fiji_apply_dal_min_voltage_request(hwmgr); |
| 3556 | |
| 3557 | if (!data->sclk_dpm_key_disabled) { |
| 3558 | if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) |
| 3559 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 3560 | PPSMC_MSG_SCLKDPM_SetEnabledMask, |
| 3561 | data->dpm_level_enable_mask.sclk_dpm_enable_mask); |
| 3562 | } |
| 3563 | return 0; |
| 3564 | } |
| 3565 | |
| 3566 | static int fiji_unforce_dpm_levels(struct pp_hwmgr *hwmgr) |
| 3567 | { |
| 3568 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 3569 | |
| 3570 | if (!fiji_is_dpm_running(hwmgr)) |
| 3571 | return -EINVAL; |
| 3572 | |
| 3573 | if (!data->pcie_dpm_key_disabled) { |
| 3574 | smum_send_msg_to_smc(hwmgr->smumgr, |
| 3575 | PPSMC_MSG_PCIeDPM_UnForceLevel); |
| 3576 | } |
| 3577 | |
| 3578 | return fiji_upload_dpmlevel_enable_mask(hwmgr); |
| 3579 | } |
| 3580 | |
| 3581 | static uint32_t fiji_get_lowest_enabled_level( |
| 3582 | struct pp_hwmgr *hwmgr, uint32_t mask) |
| 3583 | { |
| 3584 | uint32_t level = 0; |
| 3585 | |
| 3586 | while(0 == (mask & (1 << level))) |
| 3587 | level++; |
| 3588 | |
| 3589 | return level; |
| 3590 | } |
| 3591 | |
| 3592 | static int fiji_force_dpm_lowest(struct pp_hwmgr *hwmgr) |
| 3593 | { |
| 3594 | struct fiji_hwmgr *data = |
| 3595 | (struct fiji_hwmgr *)(hwmgr->backend); |
Alex Deucher | 74c577b | 2015-11-11 00:31:00 -0500 | [diff] [blame] | 3596 | uint32_t level; |
Eric Huang | aabcb7c | 2015-08-26 16:52:28 -0400 | [diff] [blame] | 3597 | |
Eric Huang | aabcb7c | 2015-08-26 16:52:28 -0400 | [diff] [blame] | 3598 | if (!data->sclk_dpm_key_disabled) |
| 3599 | if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { |
| 3600 | level = fiji_get_lowest_enabled_level(hwmgr, |
Alex Deucher | 74c577b | 2015-11-11 00:31:00 -0500 | [diff] [blame] | 3601 | data->dpm_level_enable_mask.sclk_dpm_enable_mask); |
Eric Huang | aabcb7c | 2015-08-26 16:52:28 -0400 | [diff] [blame] | 3602 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
Alex Deucher | 74c577b | 2015-11-11 00:31:00 -0500 | [diff] [blame] | 3603 | PPSMC_MSG_SCLKDPM_SetEnabledMask, |
| 3604 | (1 << level)); |
Eric Huang | aabcb7c | 2015-08-26 16:52:28 -0400 | [diff] [blame] | 3605 | |
| 3606 | } |
Alex Deucher | 74c577b | 2015-11-11 00:31:00 -0500 | [diff] [blame] | 3607 | |
| 3608 | if (!data->mclk_dpm_key_disabled) { |
| 3609 | if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { |
| 3610 | level = fiji_get_lowest_enabled_level(hwmgr, |
| 3611 | data->dpm_level_enable_mask.mclk_dpm_enable_mask); |
| 3612 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 3613 | PPSMC_MSG_MCLKDPM_SetEnabledMask, |
| 3614 | (1 << level)); |
| 3615 | } |
| 3616 | } |
| 3617 | |
| 3618 | if (!data->pcie_dpm_key_disabled) { |
| 3619 | if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { |
| 3620 | level = fiji_get_lowest_enabled_level(hwmgr, |
| 3621 | data->dpm_level_enable_mask.pcie_dpm_enable_mask); |
| 3622 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 3623 | PPSMC_MSG_PCIeDPM_ForceLevel, |
| 3624 | (1 << level)); |
| 3625 | } |
| 3626 | } |
| 3627 | |
Eric Huang | aabcb7c | 2015-08-26 16:52:28 -0400 | [diff] [blame] | 3628 | return 0; |
| 3629 | |
| 3630 | } |
| 3631 | static int fiji_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, |
| 3632 | enum amd_dpm_forced_level level) |
| 3633 | { |
| 3634 | int ret = 0; |
| 3635 | |
| 3636 | switch (level) { |
| 3637 | case AMD_DPM_FORCED_LEVEL_HIGH: |
| 3638 | ret = fiji_force_dpm_highest(hwmgr); |
| 3639 | if (ret) |
| 3640 | return ret; |
| 3641 | break; |
| 3642 | case AMD_DPM_FORCED_LEVEL_LOW: |
| 3643 | ret = fiji_force_dpm_lowest(hwmgr); |
| 3644 | if (ret) |
| 3645 | return ret; |
| 3646 | break; |
| 3647 | case AMD_DPM_FORCED_LEVEL_AUTO: |
| 3648 | ret = fiji_unforce_dpm_levels(hwmgr); |
| 3649 | if (ret) |
| 3650 | return ret; |
| 3651 | break; |
| 3652 | default: |
| 3653 | break; |
| 3654 | } |
| 3655 | |
| 3656 | hwmgr->dpm_level = level; |
| 3657 | |
| 3658 | return ret; |
| 3659 | } |
| 3660 | |
| 3661 | static int fiji_get_power_state_size(struct pp_hwmgr *hwmgr) |
| 3662 | { |
| 3663 | return sizeof(struct fiji_power_state); |
| 3664 | } |
| 3665 | |
| 3666 | static int fiji_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, |
| 3667 | void *state, struct pp_power_state *power_state, |
| 3668 | void *pp_table, uint32_t classification_flag) |
| 3669 | { |
| 3670 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 3671 | struct fiji_power_state *fiji_power_state = |
| 3672 | (struct fiji_power_state *)(&(power_state->hardware)); |
| 3673 | struct fiji_performance_level *performance_level; |
| 3674 | ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; |
| 3675 | ATOM_Tonga_POWERPLAYTABLE *powerplay_table = |
| 3676 | (ATOM_Tonga_POWERPLAYTABLE *)pp_table; |
| 3677 | ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = |
| 3678 | (ATOM_Tonga_SCLK_Dependency_Table *) |
| 3679 | (((unsigned long)powerplay_table) + |
| 3680 | le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); |
| 3681 | ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = |
| 3682 | (ATOM_Tonga_MCLK_Dependency_Table *) |
| 3683 | (((unsigned long)powerplay_table) + |
| 3684 | le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); |
| 3685 | |
| 3686 | /* The following fields are not initialized here: id orderedList allStatesList */ |
| 3687 | power_state->classification.ui_label = |
| 3688 | (le16_to_cpu(state_entry->usClassification) & |
| 3689 | ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> |
| 3690 | ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; |
| 3691 | power_state->classification.flags = classification_flag; |
| 3692 | /* NOTE: There is a classification2 flag in BIOS that is not being used right now */ |
| 3693 | |
| 3694 | power_state->classification.temporary_state = false; |
| 3695 | power_state->classification.to_be_deleted = false; |
| 3696 | |
| 3697 | power_state->validation.disallowOnDC = |
| 3698 | (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & |
| 3699 | ATOM_Tonga_DISALLOW_ON_DC)); |
| 3700 | |
| 3701 | power_state->pcie.lanes = 0; |
| 3702 | |
| 3703 | power_state->display.disableFrameModulation = false; |
| 3704 | power_state->display.limitRefreshrate = false; |
| 3705 | power_state->display.enableVariBright = |
| 3706 | (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & |
| 3707 | ATOM_Tonga_ENABLE_VARIBRIGHT)); |
| 3708 | |
| 3709 | power_state->validation.supportedPowerLevels = 0; |
| 3710 | power_state->uvd_clocks.VCLK = 0; |
| 3711 | power_state->uvd_clocks.DCLK = 0; |
| 3712 | power_state->temperatures.min = 0; |
| 3713 | power_state->temperatures.max = 0; |
| 3714 | |
| 3715 | performance_level = &(fiji_power_state->performance_levels |
| 3716 | [fiji_power_state->performance_level_count++]); |
| 3717 | |
| 3718 | PP_ASSERT_WITH_CODE( |
| 3719 | (fiji_power_state->performance_level_count < SMU73_MAX_LEVELS_GRAPHICS), |
| 3720 | "Performance levels exceeds SMC limit!", |
| 3721 | return -1); |
| 3722 | |
| 3723 | PP_ASSERT_WITH_CODE( |
| 3724 | (fiji_power_state->performance_level_count <= |
| 3725 | hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), |
| 3726 | "Performance levels exceeds Driver limit!", |
| 3727 | return -1); |
| 3728 | |
| 3729 | /* Performance levels are arranged from low to high. */ |
| 3730 | performance_level->memory_clock = mclk_dep_table->entries |
| 3731 | [state_entry->ucMemoryClockIndexLow].ulMclk; |
| 3732 | performance_level->engine_clock = sclk_dep_table->entries |
| 3733 | [state_entry->ucEngineClockIndexLow].ulSclk; |
| 3734 | performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, |
| 3735 | state_entry->ucPCIEGenLow); |
| 3736 | performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, |
| 3737 | state_entry->ucPCIELaneHigh); |
| 3738 | |
| 3739 | performance_level = &(fiji_power_state->performance_levels |
| 3740 | [fiji_power_state->performance_level_count++]); |
| 3741 | performance_level->memory_clock = mclk_dep_table->entries |
| 3742 | [state_entry->ucMemoryClockIndexHigh].ulMclk; |
| 3743 | performance_level->engine_clock = sclk_dep_table->entries |
| 3744 | [state_entry->ucEngineClockIndexHigh].ulSclk; |
| 3745 | performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, |
| 3746 | state_entry->ucPCIEGenHigh); |
| 3747 | performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, |
| 3748 | state_entry->ucPCIELaneHigh); |
| 3749 | |
| 3750 | return 0; |
| 3751 | } |
| 3752 | |
| 3753 | static int fiji_get_pp_table_entry(struct pp_hwmgr *hwmgr, |
| 3754 | unsigned long entry_index, struct pp_power_state *state) |
| 3755 | { |
| 3756 | int result; |
| 3757 | struct fiji_power_state *ps; |
| 3758 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 3759 | struct phm_ppt_v1_information *table_info = |
| 3760 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3761 | struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = |
| 3762 | table_info->vdd_dep_on_mclk; |
| 3763 | |
| 3764 | state->hardware.magic = PHM_VIslands_Magic; |
| 3765 | |
| 3766 | ps = (struct fiji_power_state *)(&state->hardware); |
| 3767 | |
| 3768 | result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state, |
| 3769 | fiji_get_pp_table_entry_callback_func); |
| 3770 | |
| 3771 | /* This is the earliest time we have all the dependency table and the VBIOS boot state |
| 3772 | * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state |
| 3773 | * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state |
| 3774 | */ |
| 3775 | if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { |
| 3776 | if (dep_mclk_table->entries[0].clk != |
| 3777 | data->vbios_boot_state.mclk_bootup_value) |
| 3778 | printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table " |
| 3779 | "does not match VBIOS boot MCLK level"); |
| 3780 | if (dep_mclk_table->entries[0].vddci != |
| 3781 | data->vbios_boot_state.vddci_bootup_value) |
| 3782 | printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table " |
| 3783 | "does not match VBIOS boot VDDCI level"); |
| 3784 | } |
| 3785 | |
| 3786 | /* set DC compatible flag if this state supports DC */ |
| 3787 | if (!state->validation.disallowOnDC) |
| 3788 | ps->dc_compatible = true; |
| 3789 | |
| 3790 | if (state->classification.flags & PP_StateClassificationFlag_ACPI) |
| 3791 | data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; |
| 3792 | |
| 3793 | ps->uvd_clks.vclk = state->uvd_clocks.VCLK; |
| 3794 | ps->uvd_clks.dclk = state->uvd_clocks.DCLK; |
| 3795 | |
| 3796 | if (!result) { |
| 3797 | uint32_t i; |
| 3798 | |
| 3799 | switch (state->classification.ui_label) { |
| 3800 | case PP_StateUILabel_Performance: |
| 3801 | data->use_pcie_performance_levels = true; |
| 3802 | |
| 3803 | for (i = 0; i < ps->performance_level_count; i++) { |
| 3804 | if (data->pcie_gen_performance.max < |
| 3805 | ps->performance_levels[i].pcie_gen) |
| 3806 | data->pcie_gen_performance.max = |
| 3807 | ps->performance_levels[i].pcie_gen; |
| 3808 | |
| 3809 | if (data->pcie_gen_performance.min > |
| 3810 | ps->performance_levels[i].pcie_gen) |
| 3811 | data->pcie_gen_performance.min = |
| 3812 | ps->performance_levels[i].pcie_gen; |
| 3813 | |
| 3814 | if (data->pcie_lane_performance.max < |
| 3815 | ps->performance_levels[i].pcie_lane) |
| 3816 | data->pcie_lane_performance.max = |
| 3817 | ps->performance_levels[i].pcie_lane; |
| 3818 | |
| 3819 | if (data->pcie_lane_performance.min > |
| 3820 | ps->performance_levels[i].pcie_lane) |
| 3821 | data->pcie_lane_performance.min = |
| 3822 | ps->performance_levels[i].pcie_lane; |
| 3823 | } |
| 3824 | break; |
| 3825 | case PP_StateUILabel_Battery: |
| 3826 | data->use_pcie_power_saving_levels = true; |
| 3827 | |
| 3828 | for (i = 0; i < ps->performance_level_count; i++) { |
| 3829 | if (data->pcie_gen_power_saving.max < |
| 3830 | ps->performance_levels[i].pcie_gen) |
| 3831 | data->pcie_gen_power_saving.max = |
| 3832 | ps->performance_levels[i].pcie_gen; |
| 3833 | |
| 3834 | if (data->pcie_gen_power_saving.min > |
| 3835 | ps->performance_levels[i].pcie_gen) |
| 3836 | data->pcie_gen_power_saving.min = |
| 3837 | ps->performance_levels[i].pcie_gen; |
| 3838 | |
| 3839 | if (data->pcie_lane_power_saving.max < |
| 3840 | ps->performance_levels[i].pcie_lane) |
| 3841 | data->pcie_lane_power_saving.max = |
| 3842 | ps->performance_levels[i].pcie_lane; |
| 3843 | |
| 3844 | if (data->pcie_lane_power_saving.min > |
| 3845 | ps->performance_levels[i].pcie_lane) |
| 3846 | data->pcie_lane_power_saving.min = |
| 3847 | ps->performance_levels[i].pcie_lane; |
| 3848 | } |
| 3849 | break; |
| 3850 | default: |
| 3851 | break; |
| 3852 | } |
| 3853 | } |
| 3854 | return 0; |
| 3855 | } |
| 3856 | |
| 3857 | static int fiji_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, |
| 3858 | struct pp_power_state *request_ps, |
| 3859 | const struct pp_power_state *current_ps) |
| 3860 | { |
| 3861 | struct fiji_power_state *fiji_ps = |
| 3862 | cast_phw_fiji_power_state(&request_ps->hardware); |
| 3863 | uint32_t sclk; |
| 3864 | uint32_t mclk; |
| 3865 | struct PP_Clocks minimum_clocks = {0}; |
| 3866 | bool disable_mclk_switching; |
| 3867 | bool disable_mclk_switching_for_frame_lock; |
| 3868 | struct cgs_display_info info = {0}; |
| 3869 | const struct phm_clock_and_voltage_limits *max_limits; |
| 3870 | uint32_t i; |
| 3871 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 3872 | struct phm_ppt_v1_information *table_info = |
| 3873 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 3874 | int32_t count; |
| 3875 | int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; |
| 3876 | |
| 3877 | data->battery_state = (PP_StateUILabel_Battery == |
| 3878 | request_ps->classification.ui_label); |
| 3879 | |
| 3880 | PP_ASSERT_WITH_CODE(fiji_ps->performance_level_count == 2, |
| 3881 | "VI should always have 2 performance levels",); |
| 3882 | |
| 3883 | max_limits = (PP_PowerSource_AC == hwmgr->power_source) ? |
| 3884 | &(hwmgr->dyn_state.max_clock_voltage_on_ac) : |
| 3885 | &(hwmgr->dyn_state.max_clock_voltage_on_dc); |
| 3886 | |
| 3887 | /* Cap clock DPM tables at DC MAX if it is in DC. */ |
| 3888 | if (PP_PowerSource_DC == hwmgr->power_source) { |
| 3889 | for (i = 0; i < fiji_ps->performance_level_count; i++) { |
| 3890 | if (fiji_ps->performance_levels[i].memory_clock > max_limits->mclk) |
| 3891 | fiji_ps->performance_levels[i].memory_clock = max_limits->mclk; |
| 3892 | if (fiji_ps->performance_levels[i].engine_clock > max_limits->sclk) |
| 3893 | fiji_ps->performance_levels[i].engine_clock = max_limits->sclk; |
| 3894 | } |
| 3895 | } |
| 3896 | |
| 3897 | fiji_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk; |
| 3898 | fiji_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk; |
| 3899 | |
| 3900 | fiji_ps->acp_clk = hwmgr->acp_arbiter.acpclk; |
| 3901 | |
| 3902 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 3903 | |
| 3904 | /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ |
| 3905 | |
| 3906 | /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */ |
| 3907 | |
| 3908 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 3909 | PHM_PlatformCaps_StablePState)) { |
| 3910 | max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); |
| 3911 | stable_pstate_sclk = (max_limits->sclk * 75) / 100; |
| 3912 | |
| 3913 | for (count = table_info->vdd_dep_on_sclk->count - 1; |
| 3914 | count >= 0; count--) { |
| 3915 | if (stable_pstate_sclk >= |
| 3916 | table_info->vdd_dep_on_sclk->entries[count].clk) { |
| 3917 | stable_pstate_sclk = |
| 3918 | table_info->vdd_dep_on_sclk->entries[count].clk; |
| 3919 | break; |
| 3920 | } |
| 3921 | } |
| 3922 | |
| 3923 | if (count < 0) |
| 3924 | stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; |
| 3925 | |
| 3926 | stable_pstate_mclk = max_limits->mclk; |
| 3927 | |
| 3928 | minimum_clocks.engineClock = stable_pstate_sclk; |
| 3929 | minimum_clocks.memoryClock = stable_pstate_mclk; |
| 3930 | } |
| 3931 | |
| 3932 | if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk) |
| 3933 | minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk; |
| 3934 | |
| 3935 | if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk) |
| 3936 | minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk; |
| 3937 | |
| 3938 | fiji_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; |
| 3939 | |
| 3940 | if (0 != hwmgr->gfx_arbiter.sclk_over_drive) { |
| 3941 | PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= |
| 3942 | hwmgr->platform_descriptor.overdriveLimit.engineClock), |
| 3943 | "Overdrive sclk exceeds limit", |
| 3944 | hwmgr->gfx_arbiter.sclk_over_drive = |
| 3945 | hwmgr->platform_descriptor.overdriveLimit.engineClock); |
| 3946 | |
| 3947 | if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) |
| 3948 | fiji_ps->performance_levels[1].engine_clock = |
| 3949 | hwmgr->gfx_arbiter.sclk_over_drive; |
| 3950 | } |
| 3951 | |
| 3952 | if (0 != hwmgr->gfx_arbiter.mclk_over_drive) { |
| 3953 | PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= |
| 3954 | hwmgr->platform_descriptor.overdriveLimit.memoryClock), |
| 3955 | "Overdrive mclk exceeds limit", |
| 3956 | hwmgr->gfx_arbiter.mclk_over_drive = |
| 3957 | hwmgr->platform_descriptor.overdriveLimit.memoryClock); |
| 3958 | |
| 3959 | if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) |
| 3960 | fiji_ps->performance_levels[1].memory_clock = |
| 3961 | hwmgr->gfx_arbiter.mclk_over_drive; |
| 3962 | } |
| 3963 | |
| 3964 | disable_mclk_switching_for_frame_lock = phm_cap_enabled( |
| 3965 | hwmgr->platform_descriptor.platformCaps, |
| 3966 | PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); |
| 3967 | |
| 3968 | disable_mclk_switching = (1 < info.display_count) || |
| 3969 | disable_mclk_switching_for_frame_lock; |
| 3970 | |
| 3971 | sclk = fiji_ps->performance_levels[0].engine_clock; |
| 3972 | mclk = fiji_ps->performance_levels[0].memory_clock; |
| 3973 | |
| 3974 | if (disable_mclk_switching) |
| 3975 | mclk = fiji_ps->performance_levels |
| 3976 | [fiji_ps->performance_level_count - 1].memory_clock; |
| 3977 | |
| 3978 | if (sclk < minimum_clocks.engineClock) |
| 3979 | sclk = (minimum_clocks.engineClock > max_limits->sclk) ? |
| 3980 | max_limits->sclk : minimum_clocks.engineClock; |
| 3981 | |
| 3982 | if (mclk < minimum_clocks.memoryClock) |
| 3983 | mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? |
| 3984 | max_limits->mclk : minimum_clocks.memoryClock; |
| 3985 | |
| 3986 | fiji_ps->performance_levels[0].engine_clock = sclk; |
| 3987 | fiji_ps->performance_levels[0].memory_clock = mclk; |
| 3988 | |
| 3989 | fiji_ps->performance_levels[1].engine_clock = |
| 3990 | (fiji_ps->performance_levels[1].engine_clock >= |
| 3991 | fiji_ps->performance_levels[0].engine_clock) ? |
| 3992 | fiji_ps->performance_levels[1].engine_clock : |
| 3993 | fiji_ps->performance_levels[0].engine_clock; |
| 3994 | |
| 3995 | if (disable_mclk_switching) { |
| 3996 | if (mclk < fiji_ps->performance_levels[1].memory_clock) |
| 3997 | mclk = fiji_ps->performance_levels[1].memory_clock; |
| 3998 | |
| 3999 | fiji_ps->performance_levels[0].memory_clock = mclk; |
| 4000 | fiji_ps->performance_levels[1].memory_clock = mclk; |
| 4001 | } else { |
| 4002 | if (fiji_ps->performance_levels[1].memory_clock < |
| 4003 | fiji_ps->performance_levels[0].memory_clock) |
| 4004 | fiji_ps->performance_levels[1].memory_clock = |
| 4005 | fiji_ps->performance_levels[0].memory_clock; |
| 4006 | } |
| 4007 | |
| 4008 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4009 | PHM_PlatformCaps_StablePState)) { |
| 4010 | for (i = 0; i < fiji_ps->performance_level_count; i++) { |
| 4011 | fiji_ps->performance_levels[i].engine_clock = stable_pstate_sclk; |
| 4012 | fiji_ps->performance_levels[i].memory_clock = stable_pstate_mclk; |
| 4013 | fiji_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; |
| 4014 | fiji_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; |
| 4015 | } |
| 4016 | } |
| 4017 | |
| 4018 | return 0; |
| 4019 | } |
| 4020 | |
| 4021 | static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) |
| 4022 | { |
| 4023 | const struct phm_set_power_state_input *states = |
| 4024 | (const struct phm_set_power_state_input *)input; |
| 4025 | const struct fiji_power_state *fiji_ps = |
| 4026 | cast_const_phw_fiji_power_state(states->pnew_state); |
| 4027 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4028 | struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); |
| 4029 | uint32_t sclk = fiji_ps->performance_levels |
| 4030 | [fiji_ps->performance_level_count - 1].engine_clock; |
| 4031 | struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); |
| 4032 | uint32_t mclk = fiji_ps->performance_levels |
| 4033 | [fiji_ps->performance_level_count - 1].memory_clock; |
| 4034 | struct PP_Clocks min_clocks = {0}; |
| 4035 | uint32_t i; |
| 4036 | struct cgs_display_info info = {0}; |
| 4037 | |
| 4038 | data->need_update_smu7_dpm_table = 0; |
| 4039 | |
| 4040 | for (i = 0; i < sclk_table->count; i++) { |
| 4041 | if (sclk == sclk_table->dpm_levels[i].value) |
| 4042 | break; |
| 4043 | } |
| 4044 | |
| 4045 | if (i >= sclk_table->count) |
| 4046 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; |
| 4047 | else { |
| 4048 | /* TODO: Check SCLK in DAL's minimum clocks |
| 4049 | * in case DeepSleep divider update is required. |
| 4050 | */ |
| 4051 | if(data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR) |
| 4052 | data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; |
| 4053 | } |
| 4054 | |
| 4055 | for (i = 0; i < mclk_table->count; i++) { |
| 4056 | if (mclk == mclk_table->dpm_levels[i].value) |
| 4057 | break; |
| 4058 | } |
| 4059 | |
| 4060 | if (i >= mclk_table->count) |
| 4061 | data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; |
| 4062 | |
| 4063 | cgs_get_active_displays_info(hwmgr->device, &info); |
| 4064 | |
| 4065 | if (data->display_timing.num_existing_displays != info.display_count) |
| 4066 | data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; |
| 4067 | |
| 4068 | return 0; |
| 4069 | } |
| 4070 | |
| 4071 | static uint16_t fiji_get_maximum_link_speed(struct pp_hwmgr *hwmgr, |
| 4072 | const struct fiji_power_state *fiji_ps) |
| 4073 | { |
| 4074 | uint32_t i; |
| 4075 | uint32_t sclk, max_sclk = 0; |
| 4076 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4077 | struct fiji_dpm_table *dpm_table = &data->dpm_table; |
| 4078 | |
| 4079 | for (i = 0; i < fiji_ps->performance_level_count; i++) { |
| 4080 | sclk = fiji_ps->performance_levels[i].engine_clock; |
| 4081 | if (max_sclk < sclk) |
| 4082 | max_sclk = sclk; |
| 4083 | } |
| 4084 | |
| 4085 | for (i = 0; i < dpm_table->sclk_table.count; i++) { |
| 4086 | if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk) |
| 4087 | return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ? |
| 4088 | dpm_table->pcie_speed_table.dpm_levels |
| 4089 | [dpm_table->pcie_speed_table.count - 1].value : |
| 4090 | dpm_table->pcie_speed_table.dpm_levels[i].value); |
| 4091 | } |
| 4092 | |
| 4093 | return 0; |
| 4094 | } |
| 4095 | |
| 4096 | static int fiji_request_link_speed_change_before_state_change( |
| 4097 | struct pp_hwmgr *hwmgr, const void *input) |
| 4098 | { |
| 4099 | const struct phm_set_power_state_input *states = |
| 4100 | (const struct phm_set_power_state_input *)input; |
| 4101 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4102 | const struct fiji_power_state *fiji_nps = |
| 4103 | cast_const_phw_fiji_power_state(states->pnew_state); |
| 4104 | const struct fiji_power_state *fiji_cps = |
| 4105 | cast_const_phw_fiji_power_state(states->pcurrent_state); |
| 4106 | |
| 4107 | uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_nps); |
| 4108 | uint16_t current_link_speed; |
| 4109 | |
| 4110 | if (data->force_pcie_gen == PP_PCIEGenInvalid) |
| 4111 | current_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_cps); |
| 4112 | else |
| 4113 | current_link_speed = data->force_pcie_gen; |
| 4114 | |
| 4115 | data->force_pcie_gen = PP_PCIEGenInvalid; |
| 4116 | data->pspp_notify_required = false; |
| 4117 | if (target_link_speed > current_link_speed) { |
| 4118 | switch(target_link_speed) { |
| 4119 | case PP_PCIEGen3: |
| 4120 | if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false)) |
| 4121 | break; |
| 4122 | data->force_pcie_gen = PP_PCIEGen2; |
| 4123 | if (current_link_speed == PP_PCIEGen2) |
| 4124 | break; |
| 4125 | case PP_PCIEGen2: |
| 4126 | if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false)) |
| 4127 | break; |
| 4128 | default: |
| 4129 | data->force_pcie_gen = fiji_get_current_pcie_speed(hwmgr); |
| 4130 | break; |
| 4131 | } |
| 4132 | } else { |
| 4133 | if (target_link_speed < current_link_speed) |
| 4134 | data->pspp_notify_required = true; |
| 4135 | } |
| 4136 | |
| 4137 | return 0; |
| 4138 | } |
| 4139 | |
| 4140 | static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) |
| 4141 | { |
| 4142 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4143 | |
| 4144 | if (0 == data->need_update_smu7_dpm_table) |
| 4145 | return 0; |
| 4146 | |
| 4147 | if ((0 == data->sclk_dpm_key_disabled) && |
| 4148 | (data->need_update_smu7_dpm_table & |
| 4149 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { |
| 4150 | PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr), |
| 4151 | "Trying to freeze SCLK DPM when DPM is disabled",); |
| 4152 | PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 4153 | PPSMC_MSG_SCLKDPM_FreezeLevel), |
| 4154 | "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", |
| 4155 | return -1); |
| 4156 | } |
| 4157 | |
| 4158 | if ((0 == data->mclk_dpm_key_disabled) && |
| 4159 | (data->need_update_smu7_dpm_table & |
| 4160 | DPMTABLE_OD_UPDATE_MCLK)) { |
| 4161 | PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr), |
| 4162 | "Trying to freeze MCLK DPM when DPM is disabled",); |
| 4163 | PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 4164 | PPSMC_MSG_MCLKDPM_FreezeLevel), |
| 4165 | "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", |
| 4166 | return -1); |
| 4167 | } |
| 4168 | |
| 4169 | return 0; |
| 4170 | } |
| 4171 | |
| 4172 | static int fiji_populate_and_upload_sclk_mclk_dpm_levels( |
| 4173 | struct pp_hwmgr *hwmgr, const void *input) |
| 4174 | { |
| 4175 | int result = 0; |
| 4176 | const struct phm_set_power_state_input *states = |
| 4177 | (const struct phm_set_power_state_input *)input; |
| 4178 | const struct fiji_power_state *fiji_ps = |
| 4179 | cast_const_phw_fiji_power_state(states->pnew_state); |
| 4180 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4181 | uint32_t sclk = fiji_ps->performance_levels |
| 4182 | [fiji_ps->performance_level_count - 1].engine_clock; |
| 4183 | uint32_t mclk = fiji_ps->performance_levels |
| 4184 | [fiji_ps->performance_level_count - 1].memory_clock; |
| 4185 | struct fiji_dpm_table *dpm_table = &data->dpm_table; |
| 4186 | |
| 4187 | struct fiji_dpm_table *golden_dpm_table = &data->golden_dpm_table; |
| 4188 | uint32_t dpm_count, clock_percent; |
| 4189 | uint32_t i; |
| 4190 | |
| 4191 | if (0 == data->need_update_smu7_dpm_table) |
| 4192 | return 0; |
| 4193 | |
| 4194 | if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { |
| 4195 | dpm_table->sclk_table.dpm_levels |
| 4196 | [dpm_table->sclk_table.count - 1].value = sclk; |
| 4197 | |
| 4198 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4199 | PHM_PlatformCaps_OD6PlusinACSupport) || |
| 4200 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4201 | PHM_PlatformCaps_OD6PlusinDCSupport)) { |
| 4202 | /* Need to do calculation based on the golden DPM table |
| 4203 | * as the Heatmap GPU Clock axis is also based on the default values |
| 4204 | */ |
| 4205 | PP_ASSERT_WITH_CODE( |
| 4206 | (golden_dpm_table->sclk_table.dpm_levels |
| 4207 | [golden_dpm_table->sclk_table.count - 1].value != 0), |
| 4208 | "Divide by 0!", |
| 4209 | return -1); |
| 4210 | dpm_count = dpm_table->sclk_table.count < 2 ? |
| 4211 | 0 : dpm_table->sclk_table.count - 2; |
| 4212 | for (i = dpm_count; i > 1; i--) { |
| 4213 | if (sclk > golden_dpm_table->sclk_table.dpm_levels |
| 4214 | [golden_dpm_table->sclk_table.count-1].value) { |
| 4215 | clock_percent = |
| 4216 | ((sclk - golden_dpm_table->sclk_table.dpm_levels |
| 4217 | [golden_dpm_table->sclk_table.count-1].value) * 100) / |
| 4218 | golden_dpm_table->sclk_table.dpm_levels |
| 4219 | [golden_dpm_table->sclk_table.count-1].value; |
| 4220 | |
| 4221 | dpm_table->sclk_table.dpm_levels[i].value = |
| 4222 | golden_dpm_table->sclk_table.dpm_levels[i].value + |
| 4223 | (golden_dpm_table->sclk_table.dpm_levels[i].value * |
| 4224 | clock_percent)/100; |
| 4225 | |
| 4226 | } else if (golden_dpm_table->sclk_table.dpm_levels |
| 4227 | [dpm_table->sclk_table.count-1].value > sclk) { |
| 4228 | clock_percent = |
| 4229 | ((golden_dpm_table->sclk_table.dpm_levels |
| 4230 | [golden_dpm_table->sclk_table.count - 1].value - sclk) * |
| 4231 | 100) / |
| 4232 | golden_dpm_table->sclk_table.dpm_levels |
| 4233 | [golden_dpm_table->sclk_table.count-1].value; |
| 4234 | |
| 4235 | dpm_table->sclk_table.dpm_levels[i].value = |
| 4236 | golden_dpm_table->sclk_table.dpm_levels[i].value - |
| 4237 | (golden_dpm_table->sclk_table.dpm_levels[i].value * |
| 4238 | clock_percent) / 100; |
| 4239 | } else |
| 4240 | dpm_table->sclk_table.dpm_levels[i].value = |
| 4241 | golden_dpm_table->sclk_table.dpm_levels[i].value; |
| 4242 | } |
| 4243 | } |
| 4244 | } |
| 4245 | |
| 4246 | if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { |
| 4247 | dpm_table->mclk_table.dpm_levels |
| 4248 | [dpm_table->mclk_table.count - 1].value = mclk; |
| 4249 | |
| 4250 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4251 | PHM_PlatformCaps_OD6PlusinACSupport) || |
| 4252 | phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4253 | PHM_PlatformCaps_OD6PlusinDCSupport)) { |
| 4254 | |
| 4255 | PP_ASSERT_WITH_CODE( |
| 4256 | (golden_dpm_table->mclk_table.dpm_levels |
| 4257 | [golden_dpm_table->mclk_table.count-1].value != 0), |
| 4258 | "Divide by 0!", |
| 4259 | return -1); |
| 4260 | dpm_count = dpm_table->mclk_table.count < 2 ? |
| 4261 | 0 : dpm_table->mclk_table.count - 2; |
| 4262 | for (i = dpm_count; i > 1; i--) { |
| 4263 | if (mclk > golden_dpm_table->mclk_table.dpm_levels |
| 4264 | [golden_dpm_table->mclk_table.count-1].value) { |
| 4265 | clock_percent = ((mclk - |
| 4266 | golden_dpm_table->mclk_table.dpm_levels |
| 4267 | [golden_dpm_table->mclk_table.count-1].value) * 100) / |
| 4268 | golden_dpm_table->mclk_table.dpm_levels |
| 4269 | [golden_dpm_table->mclk_table.count-1].value; |
| 4270 | |
| 4271 | dpm_table->mclk_table.dpm_levels[i].value = |
| 4272 | golden_dpm_table->mclk_table.dpm_levels[i].value + |
| 4273 | (golden_dpm_table->mclk_table.dpm_levels[i].value * |
| 4274 | clock_percent) / 100; |
| 4275 | |
| 4276 | } else if (golden_dpm_table->mclk_table.dpm_levels |
| 4277 | [dpm_table->mclk_table.count-1].value > mclk) { |
| 4278 | clock_percent = ((golden_dpm_table->mclk_table.dpm_levels |
| 4279 | [golden_dpm_table->mclk_table.count-1].value - mclk) * 100) / |
| 4280 | golden_dpm_table->mclk_table.dpm_levels |
| 4281 | [golden_dpm_table->mclk_table.count-1].value; |
| 4282 | |
| 4283 | dpm_table->mclk_table.dpm_levels[i].value = |
| 4284 | golden_dpm_table->mclk_table.dpm_levels[i].value - |
| 4285 | (golden_dpm_table->mclk_table.dpm_levels[i].value * |
| 4286 | clock_percent) / 100; |
| 4287 | } else |
| 4288 | dpm_table->mclk_table.dpm_levels[i].value = |
| 4289 | golden_dpm_table->mclk_table.dpm_levels[i].value; |
| 4290 | } |
| 4291 | } |
| 4292 | } |
| 4293 | |
| 4294 | if (data->need_update_smu7_dpm_table & |
| 4295 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) { |
| 4296 | result = fiji_populate_all_memory_levels(hwmgr); |
| 4297 | PP_ASSERT_WITH_CODE((0 == result), |
| 4298 | "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", |
| 4299 | return result); |
| 4300 | } |
| 4301 | |
| 4302 | if (data->need_update_smu7_dpm_table & |
| 4303 | (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { |
| 4304 | /*populate MCLK dpm table to SMU7 */ |
| 4305 | result = fiji_populate_all_memory_levels(hwmgr); |
| 4306 | PP_ASSERT_WITH_CODE((0 == result), |
| 4307 | "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", |
| 4308 | return result); |
| 4309 | } |
| 4310 | |
| 4311 | return result; |
| 4312 | } |
| 4313 | |
| 4314 | static int fiji_trim_single_dpm_states(struct pp_hwmgr *hwmgr, |
| 4315 | struct fiji_single_dpm_table * dpm_table, |
| 4316 | uint32_t low_limit, uint32_t high_limit) |
| 4317 | { |
| 4318 | uint32_t i; |
| 4319 | |
| 4320 | for (i = 0; i < dpm_table->count; i++) { |
| 4321 | if ((dpm_table->dpm_levels[i].value < low_limit) || |
| 4322 | (dpm_table->dpm_levels[i].value > high_limit)) |
| 4323 | dpm_table->dpm_levels[i].enabled = false; |
| 4324 | else |
| 4325 | dpm_table->dpm_levels[i].enabled = true; |
| 4326 | } |
| 4327 | return 0; |
| 4328 | } |
| 4329 | |
| 4330 | static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr, |
| 4331 | const struct fiji_power_state *fiji_ps) |
| 4332 | { |
| 4333 | int result = 0; |
| 4334 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4335 | uint32_t high_limit_count; |
| 4336 | |
| 4337 | PP_ASSERT_WITH_CODE((fiji_ps->performance_level_count >= 1), |
| 4338 | "power state did not have any performance level", |
| 4339 | return -1); |
| 4340 | |
| 4341 | high_limit_count = (1 == fiji_ps->performance_level_count) ? 0 : 1; |
| 4342 | |
| 4343 | fiji_trim_single_dpm_states(hwmgr, |
| 4344 | &(data->dpm_table.sclk_table), |
| 4345 | fiji_ps->performance_levels[0].engine_clock, |
| 4346 | fiji_ps->performance_levels[high_limit_count].engine_clock); |
| 4347 | |
| 4348 | fiji_trim_single_dpm_states(hwmgr, |
| 4349 | &(data->dpm_table.mclk_table), |
| 4350 | fiji_ps->performance_levels[0].memory_clock, |
| 4351 | fiji_ps->performance_levels[high_limit_count].memory_clock); |
| 4352 | |
| 4353 | return result; |
| 4354 | } |
| 4355 | |
| 4356 | static int fiji_generate_dpm_level_enable_mask( |
| 4357 | struct pp_hwmgr *hwmgr, const void *input) |
| 4358 | { |
| 4359 | int result; |
| 4360 | const struct phm_set_power_state_input *states = |
| 4361 | (const struct phm_set_power_state_input *)input; |
| 4362 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4363 | const struct fiji_power_state *fiji_ps = |
| 4364 | cast_const_phw_fiji_power_state(states->pnew_state); |
| 4365 | |
| 4366 | result = fiji_trim_dpm_states(hwmgr, fiji_ps); |
| 4367 | if (result) |
| 4368 | return result; |
| 4369 | |
| 4370 | data->dpm_level_enable_mask.sclk_dpm_enable_mask = |
| 4371 | fiji_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); |
| 4372 | data->dpm_level_enable_mask.mclk_dpm_enable_mask = |
| 4373 | fiji_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); |
| 4374 | data->last_mclk_dpm_enable_mask = |
| 4375 | data->dpm_level_enable_mask.mclk_dpm_enable_mask; |
| 4376 | |
| 4377 | if (data->uvd_enabled) { |
| 4378 | if (data->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) |
| 4379 | data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; |
| 4380 | } |
| 4381 | |
| 4382 | data->dpm_level_enable_mask.pcie_dpm_enable_mask = |
| 4383 | fiji_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); |
| 4384 | |
| 4385 | return 0; |
| 4386 | } |
| 4387 | |
| 4388 | static int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) |
| 4389 | { |
| 4390 | return smum_send_msg_to_smc(hwmgr->smumgr, enable? |
| 4391 | PPSMC_MSG_VCEDPM_Enable : |
| 4392 | PPSMC_MSG_VCEDPM_Disable); |
| 4393 | } |
| 4394 | |
| 4395 | static int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) |
| 4396 | { |
| 4397 | const struct phm_set_power_state_input *states = |
| 4398 | (const struct phm_set_power_state_input *)input; |
| 4399 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4400 | const struct fiji_power_state *fiji_nps = |
| 4401 | cast_const_phw_fiji_power_state(states->pnew_state); |
| 4402 | const struct fiji_power_state *fiji_cps = |
| 4403 | cast_const_phw_fiji_power_state(states->pcurrent_state); |
| 4404 | |
| 4405 | uint32_t mm_boot_level_offset, mm_boot_level_value; |
| 4406 | struct phm_ppt_v1_information *table_info = |
| 4407 | (struct phm_ppt_v1_information *)(hwmgr->pptable); |
| 4408 | |
| 4409 | if (fiji_nps->vce_clks.evclk >0 && |
| 4410 | (fiji_cps == NULL || fiji_cps->vce_clks.evclk == 0)) { |
| 4411 | data->smc_state_table.VceBootLevel = |
| 4412 | (uint8_t) (table_info->mm_dep_table->count - 1); |
| 4413 | |
| 4414 | mm_boot_level_offset = data->dpm_table_start + |
| 4415 | offsetof(SMU73_Discrete_DpmTable, VceBootLevel); |
| 4416 | mm_boot_level_offset /= 4; |
| 4417 | mm_boot_level_offset *= 4; |
| 4418 | mm_boot_level_value = cgs_read_ind_register(hwmgr->device, |
| 4419 | CGS_IND_REG__SMC, mm_boot_level_offset); |
| 4420 | mm_boot_level_value &= 0xFF00FFFF; |
| 4421 | mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16; |
| 4422 | cgs_write_ind_register(hwmgr->device, |
| 4423 | CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); |
| 4424 | |
| 4425 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4426 | PHM_PlatformCaps_StablePState)) { |
| 4427 | smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 4428 | PPSMC_MSG_VCEDPM_SetEnabledMask, |
| 4429 | (uint32_t)1 << data->smc_state_table.VceBootLevel); |
| 4430 | |
| 4431 | fiji_enable_disable_vce_dpm(hwmgr, true); |
| 4432 | } else if (fiji_nps->vce_clks.evclk == 0 && |
| 4433 | fiji_cps != NULL && |
| 4434 | fiji_cps->vce_clks.evclk > 0) |
| 4435 | fiji_enable_disable_vce_dpm(hwmgr, false); |
| 4436 | } |
| 4437 | |
| 4438 | return 0; |
| 4439 | } |
| 4440 | |
| 4441 | static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr) |
| 4442 | { |
| 4443 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4444 | |
| 4445 | int result = 0; |
| 4446 | uint32_t low_sclk_interrupt_threshold = 0; |
| 4447 | |
| 4448 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4449 | PHM_PlatformCaps_SclkThrottleLowNotification) |
| 4450 | && (hwmgr->gfx_arbiter.sclk_threshold != |
| 4451 | data->low_sclk_interrupt_threshold)) { |
| 4452 | data->low_sclk_interrupt_threshold = |
| 4453 | hwmgr->gfx_arbiter.sclk_threshold; |
| 4454 | low_sclk_interrupt_threshold = |
| 4455 | data->low_sclk_interrupt_threshold; |
| 4456 | |
| 4457 | CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); |
| 4458 | |
| 4459 | result = fiji_copy_bytes_to_smc( |
| 4460 | hwmgr->smumgr, |
| 4461 | data->dpm_table_start + |
| 4462 | offsetof(SMU73_Discrete_DpmTable, |
| 4463 | LowSclkInterruptThreshold), |
| 4464 | (uint8_t *)&low_sclk_interrupt_threshold, |
| 4465 | sizeof(uint32_t), |
| 4466 | data->sram_end); |
| 4467 | } |
| 4468 | |
| 4469 | return result; |
| 4470 | } |
| 4471 | |
| 4472 | static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) |
| 4473 | { |
| 4474 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4475 | |
| 4476 | if (data->need_update_smu7_dpm_table & |
| 4477 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) |
| 4478 | return fiji_program_memory_timing_parameters(hwmgr); |
| 4479 | |
| 4480 | return 0; |
| 4481 | } |
| 4482 | |
| 4483 | static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) |
| 4484 | { |
| 4485 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4486 | |
| 4487 | if (0 == data->need_update_smu7_dpm_table) |
| 4488 | return 0; |
| 4489 | |
| 4490 | if ((0 == data->sclk_dpm_key_disabled) && |
| 4491 | (data->need_update_smu7_dpm_table & |
| 4492 | (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { |
| 4493 | |
| 4494 | PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr), |
| 4495 | "Trying to Unfreeze SCLK DPM when DPM is disabled",); |
| 4496 | PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 4497 | PPSMC_MSG_SCLKDPM_UnfreezeLevel), |
| 4498 | "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", |
| 4499 | return -1); |
| 4500 | } |
| 4501 | |
| 4502 | if ((0 == data->mclk_dpm_key_disabled) && |
| 4503 | (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { |
| 4504 | |
| 4505 | PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr), |
| 4506 | "Trying to Unfreeze MCLK DPM when DPM is disabled",); |
| 4507 | PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, |
| 4508 | PPSMC_MSG_SCLKDPM_UnfreezeLevel), |
| 4509 | "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", |
| 4510 | return -1); |
| 4511 | } |
| 4512 | |
| 4513 | data->need_update_smu7_dpm_table = 0; |
| 4514 | |
| 4515 | return 0; |
| 4516 | } |
| 4517 | |
| 4518 | /* Look up the voltaged based on DAL's requested level. |
| 4519 | * and then send the requested VDDC voltage to SMC |
| 4520 | */ |
| 4521 | static void fiji_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr) |
| 4522 | { |
| 4523 | return; |
| 4524 | } |
| 4525 | |
| 4526 | int fiji_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) |
| 4527 | { |
| 4528 | int result; |
| 4529 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4530 | |
| 4531 | /* Apply minimum voltage based on DAL's request level */ |
| 4532 | fiji_apply_dal_minimum_voltage_request(hwmgr); |
| 4533 | |
| 4534 | if (0 == data->sclk_dpm_key_disabled) { |
| 4535 | /* Checking if DPM is running. If we discover hang because of this, |
| 4536 | * we should skip this message. |
| 4537 | */ |
| 4538 | if (!fiji_is_dpm_running(hwmgr)) |
| 4539 | printk(KERN_ERR "[ powerplay ] " |
| 4540 | "Trying to set Enable Mask when DPM is disabled \n"); |
| 4541 | |
| 4542 | if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { |
| 4543 | result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 4544 | PPSMC_MSG_SCLKDPM_SetEnabledMask, |
| 4545 | data->dpm_level_enable_mask.sclk_dpm_enable_mask); |
| 4546 | PP_ASSERT_WITH_CODE((0 == result), |
| 4547 | "Set Sclk Dpm enable Mask failed", return -1); |
| 4548 | } |
| 4549 | } |
| 4550 | |
| 4551 | if (0 == data->mclk_dpm_key_disabled) { |
| 4552 | /* Checking if DPM is running. If we discover hang because of this, |
| 4553 | * we should skip this message. |
| 4554 | */ |
| 4555 | if (!fiji_is_dpm_running(hwmgr)) |
| 4556 | printk(KERN_ERR "[ powerplay ]" |
| 4557 | " Trying to set Enable Mask when DPM is disabled \n"); |
| 4558 | |
| 4559 | if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { |
| 4560 | result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, |
| 4561 | PPSMC_MSG_MCLKDPM_SetEnabledMask, |
| 4562 | data->dpm_level_enable_mask.mclk_dpm_enable_mask); |
| 4563 | PP_ASSERT_WITH_CODE((0 == result), |
| 4564 | "Set Mclk Dpm enable Mask failed", return -1); |
| 4565 | } |
| 4566 | } |
| 4567 | |
| 4568 | return 0; |
| 4569 | } |
| 4570 | |
| 4571 | static int fiji_notify_link_speed_change_after_state_change( |
| 4572 | struct pp_hwmgr *hwmgr, const void *input) |
| 4573 | { |
| 4574 | const struct phm_set_power_state_input *states = |
| 4575 | (const struct phm_set_power_state_input *)input; |
| 4576 | struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); |
| 4577 | const struct fiji_power_state *fiji_ps = |
| 4578 | cast_const_phw_fiji_power_state(states->pnew_state); |
| 4579 | uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_ps); |
| 4580 | uint8_t request; |
| 4581 | |
| 4582 | if (data->pspp_notify_required) { |
| 4583 | if (target_link_speed == PP_PCIEGen3) |
| 4584 | request = PCIE_PERF_REQ_GEN3; |
| 4585 | else if (target_link_speed == PP_PCIEGen2) |
| 4586 | request = PCIE_PERF_REQ_GEN2; |
| 4587 | else |
| 4588 | request = PCIE_PERF_REQ_GEN1; |
| 4589 | |
| 4590 | if(request == PCIE_PERF_REQ_GEN1 && |
| 4591 | fiji_get_current_pcie_speed(hwmgr) > 0) |
| 4592 | return 0; |
| 4593 | |
| 4594 | if (acpi_pcie_perf_request(hwmgr->device, request, false)) { |
| 4595 | if (PP_PCIEGen2 == target_link_speed) |
| 4596 | printk("PSPP request to switch to Gen2 from Gen3 Failed!"); |
| 4597 | else |
| 4598 | printk("PSPP request to switch to Gen1 from Gen2 Failed!"); |
| 4599 | } |
| 4600 | } |
| 4601 | |
| 4602 | return 0; |
| 4603 | } |
| 4604 | |
| 4605 | static int fiji_set_power_state_tasks(struct pp_hwmgr *hwmgr, |
| 4606 | const void *input) |
| 4607 | { |
| 4608 | int tmp_result, result = 0; |
| 4609 | |
| 4610 | tmp_result = fiji_find_dpm_states_clocks_in_dpm_table(hwmgr, input); |
| 4611 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4612 | "Failed to find DPM states clocks in DPM table!", |
| 4613 | result = tmp_result); |
| 4614 | |
| 4615 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4616 | PHM_PlatformCaps_PCIEPerformanceRequest)) { |
| 4617 | tmp_result = |
| 4618 | fiji_request_link_speed_change_before_state_change(hwmgr, input); |
| 4619 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4620 | "Failed to request link speed change before state change!", |
| 4621 | result = tmp_result); |
| 4622 | } |
| 4623 | |
| 4624 | tmp_result = fiji_freeze_sclk_mclk_dpm(hwmgr); |
| 4625 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4626 | "Failed to freeze SCLK MCLK DPM!", result = tmp_result); |
| 4627 | |
| 4628 | tmp_result = fiji_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); |
| 4629 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4630 | "Failed to populate and upload SCLK MCLK DPM levels!", |
| 4631 | result = tmp_result); |
| 4632 | |
| 4633 | tmp_result = fiji_generate_dpm_level_enable_mask(hwmgr, input); |
| 4634 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4635 | "Failed to generate DPM level enabled mask!", |
| 4636 | result = tmp_result); |
| 4637 | |
| 4638 | tmp_result = fiji_update_vce_dpm(hwmgr, input); |
| 4639 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4640 | "Failed to update VCE DPM!", |
| 4641 | result = tmp_result); |
| 4642 | |
| 4643 | tmp_result = fiji_update_sclk_threshold(hwmgr); |
| 4644 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4645 | "Failed to update SCLK threshold!", |
| 4646 | result = tmp_result); |
| 4647 | |
| 4648 | tmp_result = fiji_program_mem_timing_parameters(hwmgr); |
| 4649 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4650 | "Failed to program memory timing parameters!", |
| 4651 | result = tmp_result); |
| 4652 | |
| 4653 | tmp_result = fiji_unfreeze_sclk_mclk_dpm(hwmgr); |
| 4654 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4655 | "Failed to unfreeze SCLK MCLK DPM!", |
| 4656 | result = tmp_result); |
| 4657 | |
| 4658 | tmp_result = fiji_upload_dpm_level_enable_mask(hwmgr); |
| 4659 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4660 | "Failed to upload DPM level enabled mask!", |
| 4661 | result = tmp_result); |
| 4662 | |
| 4663 | if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, |
| 4664 | PHM_PlatformCaps_PCIEPerformanceRequest)) { |
| 4665 | tmp_result = |
| 4666 | fiji_notify_link_speed_change_after_state_change(hwmgr, input); |
| 4667 | PP_ASSERT_WITH_CODE((0 == tmp_result), |
| 4668 | "Failed to notify link speed change after state change!", |
| 4669 | result = tmp_result); |
| 4670 | } |
| 4671 | |
| 4672 | return result; |
| 4673 | } |
| 4674 | |
| 4675 | static int fiji_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) |
| 4676 | { |
| 4677 | struct pp_power_state *ps; |
| 4678 | struct fiji_power_state *fiji_ps; |
| 4679 | |
| 4680 | if (hwmgr == NULL) |
| 4681 | return -EINVAL; |
| 4682 | |
| 4683 | ps = hwmgr->request_ps; |
| 4684 | |
| 4685 | if (ps == NULL) |
| 4686 | return -EINVAL; |
| 4687 | |
| 4688 | fiji_ps = cast_phw_fiji_power_state(&ps->hardware); |
| 4689 | |
| 4690 | if (low) |
| 4691 | return fiji_ps->performance_levels[0].engine_clock; |
| 4692 | else |
| 4693 | return fiji_ps->performance_levels |
| 4694 | [fiji_ps->performance_level_count-1].engine_clock; |
| 4695 | } |
| 4696 | |
| 4697 | static int fiji_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) |
| 4698 | { |
| 4699 | struct pp_power_state *ps; |
| 4700 | struct fiji_power_state *fiji_ps; |
| 4701 | |
| 4702 | if (hwmgr == NULL) |
| 4703 | return -EINVAL; |
| 4704 | |
| 4705 | ps = hwmgr->request_ps; |
| 4706 | |
| 4707 | if (ps == NULL) |
| 4708 | return -EINVAL; |
| 4709 | |
| 4710 | fiji_ps = cast_phw_fiji_power_state(&ps->hardware); |
| 4711 | |
| 4712 | if (low) |
| 4713 | return fiji_ps->performance_levels[0].memory_clock; |
| 4714 | else |
| 4715 | return fiji_ps->performance_levels |
| 4716 | [fiji_ps->performance_level_count-1].memory_clock; |
| 4717 | } |
| 4718 | |
| 4719 | static void fiji_print_current_perforce_level( |
| 4720 | struct pp_hwmgr *hwmgr, struct seq_file *m) |
| 4721 | { |
| 4722 | uint32_t sclk, mclk; |
| 4723 | |
| 4724 | smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); |
| 4725 | |
| 4726 | sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); |
| 4727 | |
| 4728 | smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); |
| 4729 | |
| 4730 | mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); |
| 4731 | seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", |
| 4732 | mclk / 100, sclk / 100); |
| 4733 | } |
| 4734 | |
| 4735 | static const struct pp_hwmgr_func fiji_hwmgr_funcs = { |
| 4736 | .backend_init = &fiji_hwmgr_backend_init, |
| 4737 | .backend_fini = &tonga_hwmgr_backend_fini, |
| 4738 | .asic_setup = &fiji_setup_asic_task, |
| 4739 | .dynamic_state_management_enable = &fiji_enable_dpm_tasks, |
| 4740 | .force_dpm_level = &fiji_dpm_force_dpm_level, |
| 4741 | .get_num_of_pp_table_entries = &tonga_get_number_of_powerplay_table_entries, |
| 4742 | .get_power_state_size = &fiji_get_power_state_size, |
| 4743 | .get_pp_table_entry = &fiji_get_pp_table_entry, |
| 4744 | .patch_boot_state = &fiji_patch_boot_state, |
| 4745 | .apply_state_adjust_rules = &fiji_apply_state_adjust_rules, |
| 4746 | .power_state_set = &fiji_set_power_state_tasks, |
| 4747 | .get_sclk = &fiji_dpm_get_sclk, |
| 4748 | .get_mclk = &fiji_dpm_get_mclk, |
| 4749 | .print_current_perforce_level = &fiji_print_current_perforce_level, |
| 4750 | }; |
| 4751 | |
| 4752 | int fiji_hwmgr_init(struct pp_hwmgr *hwmgr) |
| 4753 | { |
| 4754 | struct fiji_hwmgr *data; |
| 4755 | int ret = 0; |
| 4756 | |
| 4757 | data = kzalloc(sizeof(struct fiji_hwmgr), GFP_KERNEL); |
| 4758 | if (data == NULL) |
| 4759 | return -ENOMEM; |
| 4760 | |
| 4761 | hwmgr->backend = data; |
| 4762 | hwmgr->hwmgr_func = &fiji_hwmgr_funcs; |
| 4763 | hwmgr->pptable_func = &tonga_pptable_funcs; |
| 4764 | return ret; |
| 4765 | } |