blob: 5c697f162579db1f5465c8c78d0983658dbe11a7 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*****************************************************************************/
2
3/*
4 * es1371.c -- Creative Ensoniq ES1371.
5 *
6 * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Special thanks to Ensoniq
23 *
24 * Supported devices:
25 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
26 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
27 * /dev/dsp1 additional DAC, like /dev/dsp, but outputs to mixer "SYNTH" setting
28 * /dev/midi simple MIDI UART interface, no ioctl
29 *
30 * NOTE: the card does not have any FM/Wavetable synthesizer, it is supposed
31 * to be done in software. That is what /dev/dac is for. By now (Q2 1998)
32 * there are several MIDI to PCM (WAV) packages, one of them is timidity.
33 *
34 * Revision history
35 * 04.06.1998 0.1 Initial release
36 * Mixer stuff should be overhauled; especially optional AC97 mixer bits
37 * should be detected. This results in strange behaviour of some mixer
38 * settings, like master volume and mic.
39 * 08.06.1998 0.2 First release using Alan Cox' soundcore instead of miscdevice
40 * 03.08.1998 0.3 Do not include modversions.h
41 * Now mixer behaviour can basically be selected between
42 * "OSS documented" and "OSS actual" behaviour
43 * 31.08.1998 0.4 Fix realplayer problems - dac.count issues
44 * 27.10.1998 0.5 Fix joystick support
45 * -- Oliver Neukum (c188@org.chemie.uni-muenchen.de)
46 * 10.12.1998 0.6 Fix drain_dac trying to wait on not yet initialized DMA
47 * 23.12.1998 0.7 Fix a few f_file & FMODE_ bugs
48 * Don't wake up app until there are fragsize bytes to read/write
49 * 06.01.1999 0.8 remove the silly SA_INTERRUPT flag.
50 * hopefully killed the egcs section type conflict
51 * 12.03.1999 0.9 cinfo.blocks should be reset after GETxPTR ioctl.
52 * reported by Johan Maes <joma@telindus.be>
53 * 22.03.1999 0.10 return EAGAIN instead of EBUSY when O_NONBLOCK
54 * read/write cannot be executed
55 * 07.04.1999 0.11 implemented the following ioctl's: SOUND_PCM_READ_RATE,
56 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
57 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
58 * Another Alpha fix (wait_src_ready in init routine)
59 * reported by "Ivan N. Kokshaysky" <ink@jurassic.park.msu.ru>
60 * Note: joystick address handling might still be wrong on archs
61 * other than i386
62 * 15.06.1999 0.12 Fix bad allocation bug.
63 * Thanks to Deti Fliegl <fliegl@in.tum.de>
64 * 28.06.1999 0.13 Add pci_set_master
65 * 03.08.1999 0.14 adapt to Linus' new __setup/__initcall
66 * added kernel command line option "es1371=joystickaddr"
67 * removed CONFIG_SOUND_ES1371_JOYPORT_BOOT kludge
68 * 10.08.1999 0.15 (Re)added S/PDIF module option for cards revision >= 4.
69 * Initial version by Dave Platt <dplatt@snulbug.mtview.ca.us>.
70 * module_init/__setup fixes
71 * 08.16.1999 0.16 Joe Cotellese <joec@ensoniq.com>
72 * Added detection for ES1371 revision ID so that we can
73 * detect the ES1373 and later parts.
74 * added AC97 #defines for readability
75 * added a /proc file system for dumping hardware state
76 * updated SRC and CODEC w/r functions to accommodate bugs
77 * in some versions of the ES137x chips.
78 * 31.08.1999 0.17 add spin_lock_init
79 * replaced current->state = x with set_current_state(x)
80 * 03.09.1999 0.18 change read semantics for MIDI to match
81 * OSS more closely; remove possible wakeup race
82 * 21.10.1999 0.19 Round sampling rates, requested by
83 * Kasamatsu Kenichi <t29w0267@ip.media.kyoto-u.ac.jp>
84 * 27.10.1999 0.20 Added SigmaTel 3D enhancement string
85 * Codec ID printing changes
86 * 28.10.1999 0.21 More waitqueue races fixed
87 * Joe Cotellese <joec@ensoniq.com>
88 * Changed PCI detection routine so we can more easily
89 * detect ES137x chip and derivatives.
90 * 05.01.2000 0.22 Should now work with rev7 boards; patch by
91 * Eric Lemar, elemar@cs.washington.edu
92 * 08.01.2000 0.23 Prevent some ioctl's from returning bad count values on underrun/overrun;
93 * Tim Janik's BSE (Bedevilled Sound Engine) found this
94 * 07.02.2000 0.24 Use pci_alloc_consistent and pci_register_driver
95 * 07.02.2000 0.25 Use ac97_codec
96 * 01.03.2000 0.26 SPDIF patch by Mikael Bouillot <mikael.bouillot@bigfoot.com>
97 * Use pci_module_init
98 * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
99 * 12.12.2000 0.28 More dma buffer initializations, patch from
100 * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
101 * 05.01.2001 0.29 Hopefully updates will not be required anymore when Creative bumps
102 * the CT5880 revision.
103 * suggested by Stephan Müller <smueller@chronox.de>
104 * 31.01.2001 0.30 Register/Unregister gameport
105 * Fix SETTRIGGER non OSS API conformity
106 * 14.07.2001 0.31 Add list of laptops needing amplifier control
107 * 03.01.2003 0.32 open_mode fixes from Georg Acher <acher@in.tum.de>
108 */
109
110/*****************************************************************************/
111
112#include <linux/interrupt.h>
113#include <linux/module.h>
114#include <linux/string.h>
115#include <linux/ioport.h>
116#include <linux/sched.h>
117#include <linux/delay.h>
118#include <linux/sound.h>
119#include <linux/slab.h>
120#include <linux/soundcard.h>
121#include <linux/pci.h>
122#include <linux/init.h>
123#include <linux/poll.h>
124#include <linux/bitops.h>
125#include <linux/proc_fs.h>
126#include <linux/spinlock.h>
127#include <linux/smp_lock.h>
128#include <linux/ac97_codec.h>
129#include <linux/gameport.h>
130#include <linux/wait.h>
Tobias Klauser3ee538a2005-06-25 14:59:26 -0700131#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
133#include <asm/io.h>
134#include <asm/page.h>
135#include <asm/uaccess.h>
136
Dmitry Torokhov5d503e52005-06-01 02:39:04 -0500137#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
138#define SUPPORT_JOYSTICK
139#endif
140
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141/* --------------------------------------------------------------------- */
142
143#undef OSS_DOCUMENTED_MIXER_SEMANTICS
144#define ES1371_DEBUG
145#define DBG(x) {}
146/*#define DBG(x) {x}*/
147
148/* --------------------------------------------------------------------- */
149
150#ifndef PCI_VENDOR_ID_ENSONIQ
151#define PCI_VENDOR_ID_ENSONIQ 0x1274
152#endif
153
154#ifndef PCI_VENDOR_ID_ECTIVA
155#define PCI_VENDOR_ID_ECTIVA 0x1102
156#endif
157
158#ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
159#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
160#endif
161
162#ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
163#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
164#endif
165
166#ifndef PCI_DEVICE_ID_ECTIVA_EV1938
167#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
168#endif
169
170/* ES1371 chip ID */
171/* This is a little confusing because all ES1371 compatible chips have the
172 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
173 This is only significant if you want to enable features on the later parts.
174 Yes, I know it's stupid and why didn't we use the sub IDs?
175*/
176#define ES1371REV_ES1373_A 0x04
177#define ES1371REV_ES1373_B 0x06
178#define ES1371REV_CT5880_A 0x07
179#define CT5880REV_CT5880_C 0x02
180#define CT5880REV_CT5880_D 0x03
181#define ES1371REV_ES1371_B 0x09
182#define EV1938REV_EV1938_A 0x00
183#define ES1371REV_ES1373_8 0x08
184
185#define ES1371_MAGIC ((PCI_VENDOR_ID_ENSONIQ<<16)|PCI_DEVICE_ID_ENSONIQ_ES1371)
186
187#define ES1371_EXTENT 0x40
188#define JOY_EXTENT 8
189
190#define ES1371_REG_CONTROL 0x00
191#define ES1371_REG_STATUS 0x04 /* on the 5880 it is control/status */
192#define ES1371_REG_UART_DATA 0x08
193#define ES1371_REG_UART_STATUS 0x09
194#define ES1371_REG_UART_CONTROL 0x09
195#define ES1371_REG_UART_TEST 0x0a
196#define ES1371_REG_MEMPAGE 0x0c
197#define ES1371_REG_SRCONV 0x10
198#define ES1371_REG_CODEC 0x14
199#define ES1371_REG_LEGACY 0x18
200#define ES1371_REG_SERIAL_CONTROL 0x20
201#define ES1371_REG_DAC1_SCOUNT 0x24
202#define ES1371_REG_DAC2_SCOUNT 0x28
203#define ES1371_REG_ADC_SCOUNT 0x2c
204
205#define ES1371_REG_DAC1_FRAMEADR 0xc30
206#define ES1371_REG_DAC1_FRAMECNT 0xc34
207#define ES1371_REG_DAC2_FRAMEADR 0xc38
208#define ES1371_REG_DAC2_FRAMECNT 0xc3c
209#define ES1371_REG_ADC_FRAMEADR 0xd30
210#define ES1371_REG_ADC_FRAMECNT 0xd34
211
212#define ES1371_FMT_U8_MONO 0
213#define ES1371_FMT_U8_STEREO 1
214#define ES1371_FMT_S16_MONO 2
215#define ES1371_FMT_S16_STEREO 3
216#define ES1371_FMT_STEREO 1
217#define ES1371_FMT_S16 2
218#define ES1371_FMT_MASK 3
219
220static const unsigned sample_size[] = { 1, 2, 2, 4 };
221static const unsigned sample_shift[] = { 0, 1, 1, 2 };
222
223#define CTRL_RECEN_B 0x08000000 /* 1 = don't mix analog in to digital out */
224#define CTRL_SPDIFEN_B 0x04000000
225#define CTRL_JOY_SHIFT 24
226#define CTRL_JOY_MASK 3
227#define CTRL_JOY_200 0x00000000 /* joystick base address */
228#define CTRL_JOY_208 0x01000000
229#define CTRL_JOY_210 0x02000000
230#define CTRL_JOY_218 0x03000000
231#define CTRL_GPIO_IN0 0x00100000 /* general purpose inputs/outputs */
232#define CTRL_GPIO_IN1 0x00200000
233#define CTRL_GPIO_IN2 0x00400000
234#define CTRL_GPIO_IN3 0x00800000
235#define CTRL_GPIO_OUT0 0x00010000
236#define CTRL_GPIO_OUT1 0x00020000
237#define CTRL_GPIO_OUT2 0x00040000
238#define CTRL_GPIO_OUT3 0x00080000
239#define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
240#define CTRL_SYNCRES 0x00004000 /* AC97 warm reset */
241#define CTRL_ADCSTOP 0x00002000 /* stop ADC transfers */
242#define CTRL_PWR_INTRM 0x00001000 /* 1 = power level ints enabled */
243#define CTRL_M_CB 0x00000800 /* recording source: 0 = ADC, 1 = MPEG */
244#define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
245#define CTRL_PDLEV0 0x00000000 /* power down level */
246#define CTRL_PDLEV1 0x00000100
247#define CTRL_PDLEV2 0x00000200
248#define CTRL_PDLEV3 0x00000300
249#define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
250#define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
251#define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
252#define CTRL_ADC_EN 0x00000010 /* enable ADC */
253#define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
254#define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port */
255#define CTRL_XTALCLKDIS 0x00000002 /* 1 = disable crystal clock input */
256#define CTRL_PCICLKDIS 0x00000001 /* 1 = disable PCI clock distribution */
257
258
259#define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
260#define CSTAT_5880_AC97_RST 0x20000000 /* CT5880 Reset bit */
261#define STAT_EN_SPDIF 0x00040000 /* enable S/PDIF circuitry */
262#define STAT_TS_SPDIF 0x00020000 /* test S/PDIF circuitry */
263#define STAT_TESTMODE 0x00010000 /* test ASIC */
264#define STAT_SYNC_ERR 0x00000100 /* 1 = codec sync error */
265#define STAT_VC 0x000000c0 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
266#define STAT_SH_VC 6
267#define STAT_MPWR 0x00000020 /* power level interrupt */
268#define STAT_MCCB 0x00000010 /* CCB int pending */
269#define STAT_UART 0x00000008 /* UART int pending */
270#define STAT_DAC1 0x00000004 /* DAC1 int pending */
271#define STAT_DAC2 0x00000002 /* DAC2 int pending */
272#define STAT_ADC 0x00000001 /* ADC int pending */
273
274#define USTAT_RXINT 0x80 /* UART rx int pending */
275#define USTAT_TXINT 0x04 /* UART tx int pending */
276#define USTAT_TXRDY 0x02 /* UART tx ready */
277#define USTAT_RXRDY 0x01 /* UART rx ready */
278
279#define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
280#define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
281#define UCTRL_ENA_TXINT 0x20 /* enable TX int */
282#define UCTRL_CNTRL 0x03 /* control field */
283#define UCTRL_CNTRL_SWR 0x03 /* software reset command */
284
285/* sample rate converter */
286#define SRC_OKSTATE 1
287
288#define SRC_RAMADDR_MASK 0xfe000000
289#define SRC_RAMADDR_SHIFT 25
290#define SRC_DAC1FREEZE (1UL << 21)
291#define SRC_DAC2FREEZE (1UL << 20)
292#define SRC_ADCFREEZE (1UL << 19)
293
294
295#define SRC_WE 0x01000000 /* read/write control for SRC RAM */
296#define SRC_BUSY 0x00800000 /* SRC busy */
297#define SRC_DIS 0x00400000 /* 1 = disable SRC */
298#define SRC_DDAC1 0x00200000 /* 1 = disable accum update for DAC1 */
299#define SRC_DDAC2 0x00100000 /* 1 = disable accum update for DAC2 */
300#define SRC_DADC 0x00080000 /* 1 = disable accum update for ADC2 */
301#define SRC_CTLMASK 0x00780000
302#define SRC_RAMDATA_MASK 0x0000ffff
303#define SRC_RAMDATA_SHIFT 0
304
305#define SRCREG_ADC 0x78
306#define SRCREG_DAC1 0x70
307#define SRCREG_DAC2 0x74
308#define SRCREG_VOL_ADC 0x6c
309#define SRCREG_VOL_DAC1 0x7c
310#define SRCREG_VOL_DAC2 0x7e
311
312#define SRCREG_TRUNC_N 0x00
313#define SRCREG_INT_REGS 0x01
314#define SRCREG_ACCUM_FRAC 0x02
315#define SRCREG_VFREQ_FRAC 0x03
316
317#define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
318#define CODEC_PIADD_MASK 0x007f0000
319#define CODEC_PIADD_SHIFT 16
320#define CODEC_PIDAT_MASK 0x0000ffff
321#define CODEC_PIDAT_SHIFT 0
322
323#define CODEC_RDY 0x80000000 /* AC97 read data valid */
324#define CODEC_WIP 0x40000000 /* AC97 write in progress */
325#define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
326#define CODEC_POADD_MASK 0x007f0000
327#define CODEC_POADD_SHIFT 16
328#define CODEC_PODAT_MASK 0x0000ffff
329#define CODEC_PODAT_SHIFT 0
330
331
332#define LEGACY_JFAST 0x80000000 /* fast joystick timing */
333#define LEGACY_FIRQ 0x01000000 /* force IRQ */
334
335#define SCTRL_DACTEST 0x00400000 /* 1 = DAC test, test vector generation purposes */
336#define SCTRL_P2ENDINC 0x00380000 /* */
337#define SCTRL_SH_P2ENDINC 19
338#define SCTRL_P2STINC 0x00070000 /* */
339#define SCTRL_SH_P2STINC 16
340#define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
341#define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
342#define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
343#define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
344#define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
345#define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
346#define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
347#define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
348#define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
349#define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
350#define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
351#define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
352#define SCTRL_R1FMT 0x00000030 /* format mask */
353#define SCTRL_SH_R1FMT 4
354#define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
355#define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
356#define SCTRL_P2FMT 0x0000000c /* format mask */
357#define SCTRL_SH_P2FMT 2
358#define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
359#define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
360#define SCTRL_P1FMT 0x00000003 /* format mask */
361#define SCTRL_SH_P1FMT 0
362
363
364/* misc stuff */
365#define POLL_COUNT 0x1000
366#define FMODE_DAC 4 /* slight misuse of mode_t */
367
368/* MIDI buffer sizes */
369
370#define MIDIINBUF 256
371#define MIDIOUTBUF 256
372
373#define FMODE_MIDI_SHIFT 3
374#define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
375#define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
376
377#define ES1371_MODULE_NAME "es1371"
378#define PFX ES1371_MODULE_NAME ": "
379
380/* --------------------------------------------------------------------- */
381
382struct es1371_state {
383 /* magic */
384 unsigned int magic;
385
386 /* list of es1371 devices */
387 struct list_head devs;
388
389 /* the corresponding pci_dev structure */
390 struct pci_dev *dev;
391
392 /* soundcore stuff */
393 int dev_audio;
394 int dev_dac;
395 int dev_midi;
396
397 /* hardware resources */
398 unsigned long io; /* long for SPARC */
399 unsigned int irq;
400
401 /* PCI ID's */
402 u16 vendor;
403 u16 device;
404 u8 rev; /* the chip revision */
405
406 /* options */
407 int spdif_volume; /* S/PDIF output is enabled if != -1 */
408
409#ifdef ES1371_DEBUG
410 /* debug /proc entry */
411 struct proc_dir_entry *ps;
412#endif /* ES1371_DEBUG */
413
414 struct ac97_codec *codec;
415
416 /* wave stuff */
417 unsigned ctrl;
418 unsigned sctrl;
419 unsigned dac1rate, dac2rate, adcrate;
420
421 spinlock_t lock;
422 struct semaphore open_sem;
423 mode_t open_mode;
424 wait_queue_head_t open_wait;
425
426 struct dmabuf {
427 void *rawbuf;
428 dma_addr_t dmaaddr;
429 unsigned buforder;
430 unsigned numfrag;
431 unsigned fragshift;
432 unsigned hwptr, swptr;
433 unsigned total_bytes;
434 int count;
435 unsigned error; /* over/underrun */
436 wait_queue_head_t wait;
437 /* redundant, but makes calculations easier */
438 unsigned fragsize;
439 unsigned dmasize;
440 unsigned fragsamples;
441 /* OSS stuff */
442 unsigned mapped:1;
443 unsigned ready:1;
444 unsigned endcleared:1;
445 unsigned enabled:1;
446 unsigned ossfragshift;
447 int ossmaxfrags;
448 unsigned subdivision;
449 } dma_dac1, dma_dac2, dma_adc;
450
451 /* midi stuff */
452 struct {
453 unsigned ird, iwr, icnt;
454 unsigned ord, owr, ocnt;
455 wait_queue_head_t iwait;
456 wait_queue_head_t owait;
457 unsigned char ibuf[MIDIINBUF];
458 unsigned char obuf[MIDIOUTBUF];
459 } midi;
460
Dmitry Torokhov5d503e52005-06-01 02:39:04 -0500461#ifdef SUPPORT_JOYSTICK
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462 struct gameport *gameport;
Dmitry Torokhov5d503e52005-06-01 02:39:04 -0500463#endif
464
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465 struct semaphore sem;
466};
467
468/* --------------------------------------------------------------------- */
469
470static LIST_HEAD(devs);
471
472/* --------------------------------------------------------------------- */
473
474static inline unsigned ld2(unsigned int x)
475{
476 unsigned r = 0;
477
478 if (x >= 0x10000) {
479 x >>= 16;
480 r += 16;
481 }
482 if (x >= 0x100) {
483 x >>= 8;
484 r += 8;
485 }
486 if (x >= 0x10) {
487 x >>= 4;
488 r += 4;
489 }
490 if (x >= 4) {
491 x >>= 2;
492 r += 2;
493 }
494 if (x >= 2)
495 r++;
496 return r;
497}
498
499/* --------------------------------------------------------------------- */
500
501static unsigned wait_src_ready(struct es1371_state *s)
502{
503 unsigned int t, r;
504
505 for (t = 0; t < POLL_COUNT; t++) {
506 if (!((r = inl(s->io + ES1371_REG_SRCONV)) & SRC_BUSY))
507 return r;
508 udelay(1);
509 }
510 printk(KERN_DEBUG PFX "sample rate converter timeout r = 0x%08x\n", r);
511 return r;
512}
513
514static unsigned src_read(struct es1371_state *s, unsigned reg)
515{
516 unsigned int temp,i,orig;
517
518 /* wait for ready */
519 temp = wait_src_ready (s);
520
521 /* we can only access the SRC at certain times, make sure
522 we're allowed to before we read */
523
524 orig = temp;
525 /* expose the SRC state bits */
526 outl ( (temp & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT) | 0x10000UL,
527 s->io + ES1371_REG_SRCONV);
528
529 /* now, wait for busy and the correct time to read */
530 temp = wait_src_ready (s);
531
532 if ( (temp & 0x00870000UL ) != ( SRC_OKSTATE << 16 )){
533 /* wait for the right state */
534 for (i=0; i<POLL_COUNT; i++){
535 temp = inl (s->io + ES1371_REG_SRCONV);
536 if ( (temp & 0x00870000UL ) == ( SRC_OKSTATE << 16 ))
537 break;
538 }
539 }
540
541 /* hide the state bits */
542 outl ((orig & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT), s->io + ES1371_REG_SRCONV);
543 return temp;
544
545
546}
547
548static void src_write(struct es1371_state *s, unsigned reg, unsigned data)
549{
550
551 unsigned int r;
552
553 r = wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC);
554 r |= (reg << SRC_RAMADDR_SHIFT) & SRC_RAMADDR_MASK;
555 r |= (data << SRC_RAMDATA_SHIFT) & SRC_RAMDATA_MASK;
556 outl(r | SRC_WE, s->io + ES1371_REG_SRCONV);
557
558}
559
560/* --------------------------------------------------------------------- */
561
562/* most of the following here is black magic */
563static void set_adc_rate(struct es1371_state *s, unsigned rate)
564{
565 unsigned long flags;
566 unsigned int n, truncm, freq;
567
568 if (rate > 48000)
569 rate = 48000;
570 if (rate < 4000)
571 rate = 4000;
572 n = rate / 3000;
573 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
574 n--;
575 truncm = (21 * n - 1) | 1;
576 freq = ((48000UL << 15) / rate) * n;
577 s->adcrate = (48000UL << 15) / (freq / n);
578 spin_lock_irqsave(&s->lock, flags);
579 if (rate >= 24000) {
580 if (truncm > 239)
581 truncm = 239;
582 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
583 (((239 - truncm) >> 1) << 9) | (n << 4));
584 } else {
585 if (truncm > 119)
586 truncm = 119;
587 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
588 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
589 }
590 src_write(s, SRCREG_ADC+SRCREG_INT_REGS,
591 (src_read(s, SRCREG_ADC+SRCREG_INT_REGS) & 0x00ff) |
592 ((freq >> 5) & 0xfc00));
593 src_write(s, SRCREG_ADC+SRCREG_VFREQ_FRAC, freq & 0x7fff);
594 src_write(s, SRCREG_VOL_ADC, n << 8);
595 src_write(s, SRCREG_VOL_ADC+1, n << 8);
596 spin_unlock_irqrestore(&s->lock, flags);
597}
598
599
600static void set_dac1_rate(struct es1371_state *s, unsigned rate)
601{
602 unsigned long flags;
603 unsigned int freq, r;
604
605 if (rate > 48000)
606 rate = 48000;
607 if (rate < 4000)
608 rate = 4000;
609 freq = ((rate << 15) + 1500) / 3000;
610 s->dac1rate = (freq * 3000 + 16384) >> 15;
611 spin_lock_irqsave(&s->lock, flags);
612 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)) | SRC_DDAC1;
613 outl(r, s->io + ES1371_REG_SRCONV);
614 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS,
615 (src_read(s, SRCREG_DAC1+SRCREG_INT_REGS) & 0x00ff) |
616 ((freq >> 5) & 0xfc00));
617 src_write(s, SRCREG_DAC1+SRCREG_VFREQ_FRAC, freq & 0x7fff);
618 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC));
619 outl(r, s->io + ES1371_REG_SRCONV);
620 spin_unlock_irqrestore(&s->lock, flags);
621}
622
623static void set_dac2_rate(struct es1371_state *s, unsigned rate)
624{
625 unsigned long flags;
626 unsigned int freq, r;
627
628 if (rate > 48000)
629 rate = 48000;
630 if (rate < 4000)
631 rate = 4000;
632 freq = ((rate << 15) + 1500) / 3000;
633 s->dac2rate = (freq * 3000 + 16384) >> 15;
634 spin_lock_irqsave(&s->lock, flags);
635 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)) | SRC_DDAC2;
636 outl(r, s->io + ES1371_REG_SRCONV);
637 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS,
638 (src_read(s, SRCREG_DAC2+SRCREG_INT_REGS) & 0x00ff) |
639 ((freq >> 5) & 0xfc00));
640 src_write(s, SRCREG_DAC2+SRCREG_VFREQ_FRAC, freq & 0x7fff);
641 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC));
642 outl(r, s->io + ES1371_REG_SRCONV);
643 spin_unlock_irqrestore(&s->lock, flags);
644}
645
646/* --------------------------------------------------------------------- */
647
648static void __devinit src_init(struct es1371_state *s)
649{
650 unsigned int i;
651
652 /* before we enable or disable the SRC we need
653 to wait for it to become ready */
654 wait_src_ready(s);
655
656 outl(SRC_DIS, s->io + ES1371_REG_SRCONV);
657
658 for (i = 0; i < 0x80; i++)
659 src_write(s, i, 0);
660
661 src_write(s, SRCREG_DAC1+SRCREG_TRUNC_N, 16 << 4);
662 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 16 << 10);
663 src_write(s, SRCREG_DAC2+SRCREG_TRUNC_N, 16 << 4);
664 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 16 << 10);
665 src_write(s, SRCREG_VOL_ADC, 1 << 12);
666 src_write(s, SRCREG_VOL_ADC+1, 1 << 12);
667 src_write(s, SRCREG_VOL_DAC1, 1 << 12);
668 src_write(s, SRCREG_VOL_DAC1+1, 1 << 12);
669 src_write(s, SRCREG_VOL_DAC2, 1 << 12);
670 src_write(s, SRCREG_VOL_DAC2+1, 1 << 12);
671 set_adc_rate(s, 22050);
672 set_dac1_rate(s, 22050);
673 set_dac2_rate(s, 22050);
674
675 /* WARNING:
676 * enabling the sample rate converter without properly programming
677 * its parameters causes the chip to lock up (the SRC busy bit will
678 * be stuck high, and I've found no way to rectify this other than
679 * power cycle)
680 */
681 wait_src_ready(s);
682 outl(0, s->io+ES1371_REG_SRCONV);
683}
684
685/* --------------------------------------------------------------------- */
686
687static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
688{
689 struct es1371_state *s = (struct es1371_state *)codec->private_data;
690 unsigned long flags;
691 unsigned t, x;
692
693 spin_lock_irqsave(&s->lock, flags);
694 for (t = 0; t < POLL_COUNT; t++)
695 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
696 break;
697
698 /* save the current state for later */
699 x = wait_src_ready(s);
700
701 /* enable SRC state data in SRC mux */
702 outl((x & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)) | 0x00010000,
703 s->io+ES1371_REG_SRCONV);
704
705 /* wait for not busy (state 0) first to avoid
706 transition states */
707 for (t=0; t<POLL_COUNT; t++){
708 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
709 break;
710 udelay(1);
711 }
712
713 /* wait for a SAFE time to write addr/data and then do it, dammit */
714 for (t=0; t<POLL_COUNT; t++){
715 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
716 break;
717 udelay(1);
718 }
719
720 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
721 ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), s->io+ES1371_REG_CODEC);
722
723 /* restore SRC reg */
724 wait_src_ready(s);
725 outl(x, s->io+ES1371_REG_SRCONV);
726 spin_unlock_irqrestore(&s->lock, flags);
727}
728
729static u16 rdcodec(struct ac97_codec *codec, u8 addr)
730{
731 struct es1371_state *s = (struct es1371_state *)codec->private_data;
732 unsigned long flags;
733 unsigned t, x;
734
735 spin_lock_irqsave(&s->lock, flags);
736
737 /* wait for WIP to go away */
738 for (t = 0; t < 0x1000; t++)
739 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
740 break;
741
742 /* save the current state for later */
743 x = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC));
744
745 /* enable SRC state data in SRC mux */
746 outl( x | 0x00010000,
747 s->io+ES1371_REG_SRCONV);
748
749 /* wait for not busy (state 0) first to avoid
750 transition states */
751 for (t=0; t<POLL_COUNT; t++){
752 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
753 break;
754 udelay(1);
755 }
756
757 /* wait for a SAFE time to write addr/data and then do it, dammit */
758 for (t=0; t<POLL_COUNT; t++){
759 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
760 break;
761 udelay(1);
762 }
763
764 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD, s->io+ES1371_REG_CODEC);
765 /* restore SRC reg */
766 wait_src_ready(s);
767 outl(x, s->io+ES1371_REG_SRCONV);
768
769 /* wait for WIP again */
770 for (t = 0; t < 0x1000; t++)
771 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
772 break;
773
774 /* now wait for the stinkin' data (RDY) */
775 for (t = 0; t < POLL_COUNT; t++)
776 if ((x = inl(s->io+ES1371_REG_CODEC)) & CODEC_RDY)
777 break;
778
779 spin_unlock_irqrestore(&s->lock, flags);
780 return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT);
781}
782
783/* --------------------------------------------------------------------- */
784
785static inline void stop_adc(struct es1371_state *s)
786{
787 unsigned long flags;
788
789 spin_lock_irqsave(&s->lock, flags);
790 s->ctrl &= ~CTRL_ADC_EN;
791 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
792 spin_unlock_irqrestore(&s->lock, flags);
793}
794
795static inline void stop_dac1(struct es1371_state *s)
796{
797 unsigned long flags;
798
799 spin_lock_irqsave(&s->lock, flags);
800 s->ctrl &= ~CTRL_DAC1_EN;
801 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
802 spin_unlock_irqrestore(&s->lock, flags);
803}
804
805static inline void stop_dac2(struct es1371_state *s)
806{
807 unsigned long flags;
808
809 spin_lock_irqsave(&s->lock, flags);
810 s->ctrl &= ~CTRL_DAC2_EN;
811 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
812 spin_unlock_irqrestore(&s->lock, flags);
813}
814
815static void start_dac1(struct es1371_state *s)
816{
817 unsigned long flags;
818 unsigned fragremain, fshift;
819
820 spin_lock_irqsave(&s->lock, flags);
821 if (!(s->ctrl & CTRL_DAC1_EN) && (s->dma_dac1.mapped || s->dma_dac1.count > 0)
822 && s->dma_dac1.ready) {
823 s->ctrl |= CTRL_DAC1_EN;
824 s->sctrl = (s->sctrl & ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD)) | SCTRL_P1INTEN;
825 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
826 fragremain = ((- s->dma_dac1.hwptr) & (s->dma_dac1.fragsize-1));
827 fshift = sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
828 if (fragremain < 2*fshift)
829 fragremain = s->dma_dac1.fragsize;
830 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
831 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
832 outl((s->dma_dac1.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
833 }
834 spin_unlock_irqrestore(&s->lock, flags);
835}
836
837static void start_dac2(struct es1371_state *s)
838{
839 unsigned long flags;
840 unsigned fragremain, fshift;
841
842 spin_lock_irqsave(&s->lock, flags);
843 if (!(s->ctrl & CTRL_DAC2_EN) && (s->dma_dac2.mapped || s->dma_dac2.count > 0)
844 && s->dma_dac2.ready) {
845 s->ctrl |= CTRL_DAC2_EN;
846 s->sctrl = (s->sctrl & ~(SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN |
847 SCTRL_P2ENDINC | SCTRL_P2STINC)) | SCTRL_P2INTEN |
848 (((s->sctrl & SCTRL_P2FMT) ? 2 : 1) << SCTRL_SH_P2ENDINC) |
849 (0 << SCTRL_SH_P2STINC);
850 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
851 fragremain = ((- s->dma_dac2.hwptr) & (s->dma_dac2.fragsize-1));
852 fshift = sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
853 if (fragremain < 2*fshift)
854 fragremain = s->dma_dac2.fragsize;
855 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
856 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
857 outl((s->dma_dac2.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
858 }
859 spin_unlock_irqrestore(&s->lock, flags);
860}
861
862static void start_adc(struct es1371_state *s)
863{
864 unsigned long flags;
865 unsigned fragremain, fshift;
866
867 spin_lock_irqsave(&s->lock, flags);
868 if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
869 && s->dma_adc.ready) {
870 s->ctrl |= CTRL_ADC_EN;
871 s->sctrl = (s->sctrl & ~SCTRL_R1LOOPSEL) | SCTRL_R1INTEN;
872 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
873 fragremain = ((- s->dma_adc.hwptr) & (s->dma_adc.fragsize-1));
874 fshift = sample_shift[(s->sctrl & SCTRL_R1FMT) >> SCTRL_SH_R1FMT];
875 if (fragremain < 2*fshift)
876 fragremain = s->dma_adc.fragsize;
877 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
878 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
879 outl((s->dma_adc.fragsize >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
880 }
881 spin_unlock_irqrestore(&s->lock, flags);
882}
883
884/* --------------------------------------------------------------------- */
885
886#define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
887#define DMABUF_MINORDER 1
888
889
890static inline void dealloc_dmabuf(struct es1371_state *s, struct dmabuf *db)
891{
892 struct page *page, *pend;
893
894 if (db->rawbuf) {
895 /* undo marking the pages as reserved */
896 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
897 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
898 ClearPageReserved(page);
899 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
900 }
901 db->rawbuf = NULL;
902 db->mapped = db->ready = 0;
903}
904
905static int prog_dmabuf(struct es1371_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg)
906{
907 int order;
908 unsigned bytepersec;
909 unsigned bufs;
910 struct page *page, *pend;
911
912 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
913 if (!db->rawbuf) {
914 db->ready = db->mapped = 0;
915 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
916 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
917 break;
918 if (!db->rawbuf)
919 return -ENOMEM;
920 db->buforder = order;
921 /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
922 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
923 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
924 SetPageReserved(page);
925 }
926 fmt &= ES1371_FMT_MASK;
927 bytepersec = rate << sample_shift[fmt];
928 bufs = PAGE_SIZE << db->buforder;
929 if (db->ossfragshift) {
930 if ((1000 << db->ossfragshift) < bytepersec)
931 db->fragshift = ld2(bytepersec/1000);
932 else
933 db->fragshift = db->ossfragshift;
934 } else {
935 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
936 if (db->fragshift < 3)
937 db->fragshift = 3;
938 }
939 db->numfrag = bufs >> db->fragshift;
940 while (db->numfrag < 4 && db->fragshift > 3) {
941 db->fragshift--;
942 db->numfrag = bufs >> db->fragshift;
943 }
944 db->fragsize = 1 << db->fragshift;
945 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
946 db->numfrag = db->ossmaxfrags;
947 db->fragsamples = db->fragsize >> sample_shift[fmt];
948 db->dmasize = db->numfrag << db->fragshift;
949 memset(db->rawbuf, (fmt & ES1371_FMT_S16) ? 0 : 0x80, db->dmasize);
950 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
951 outl(db->dmaaddr, s->io+(reg & 0xff));
952 outl((db->dmasize >> 2)-1, s->io+((reg + 4) & 0xff));
953 db->enabled = 1;
954 db->ready = 1;
955 return 0;
956}
957
958static inline int prog_dmabuf_adc(struct es1371_state *s)
959{
960 stop_adc(s);
961 return prog_dmabuf(s, &s->dma_adc, s->adcrate, (s->sctrl >> SCTRL_SH_R1FMT) & ES1371_FMT_MASK,
962 ES1371_REG_ADC_FRAMEADR);
963}
964
965static inline int prog_dmabuf_dac2(struct es1371_state *s)
966{
967 stop_dac2(s);
968 return prog_dmabuf(s, &s->dma_dac2, s->dac2rate, (s->sctrl >> SCTRL_SH_P2FMT) & ES1371_FMT_MASK,
969 ES1371_REG_DAC2_FRAMEADR);
970}
971
972static inline int prog_dmabuf_dac1(struct es1371_state *s)
973{
974 stop_dac1(s);
975 return prog_dmabuf(s, &s->dma_dac1, s->dac1rate, (s->sctrl >> SCTRL_SH_P1FMT) & ES1371_FMT_MASK,
976 ES1371_REG_DAC1_FRAMEADR);
977}
978
979static inline unsigned get_hwptr(struct es1371_state *s, struct dmabuf *db, unsigned reg)
980{
981 unsigned hwptr, diff;
982
983 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
984 hwptr = (inl(s->io+(reg & 0xff)) >> 14) & 0x3fffc;
985 diff = (db->dmasize + hwptr - db->hwptr) % db->dmasize;
986 db->hwptr = hwptr;
987 return diff;
988}
989
990static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
991{
992 if (bptr + len > bsize) {
993 unsigned x = bsize - bptr;
994 memset(((char *)buf) + bptr, c, x);
995 bptr = 0;
996 len -= x;
997 }
998 memset(((char *)buf) + bptr, c, len);
999}
1000
1001/* call with spinlock held! */
1002static void es1371_update_ptr(struct es1371_state *s)
1003{
1004 int diff;
1005
1006 /* update ADC pointer */
1007 if (s->ctrl & CTRL_ADC_EN) {
1008 diff = get_hwptr(s, &s->dma_adc, ES1371_REG_ADC_FRAMECNT);
1009 s->dma_adc.total_bytes += diff;
1010 s->dma_adc.count += diff;
1011 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1012 wake_up(&s->dma_adc.wait);
1013 if (!s->dma_adc.mapped) {
1014 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1015 s->ctrl &= ~CTRL_ADC_EN;
1016 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1017 s->dma_adc.error++;
1018 }
1019 }
1020 }
1021 /* update DAC1 pointer */
1022 if (s->ctrl & CTRL_DAC1_EN) {
1023 diff = get_hwptr(s, &s->dma_dac1, ES1371_REG_DAC1_FRAMECNT);
1024 s->dma_dac1.total_bytes += diff;
1025 if (s->dma_dac1.mapped) {
1026 s->dma_dac1.count += diff;
1027 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
1028 wake_up(&s->dma_dac1.wait);
1029 } else {
1030 s->dma_dac1.count -= diff;
1031 if (s->dma_dac1.count <= 0) {
1032 s->ctrl &= ~CTRL_DAC1_EN;
1033 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1034 s->dma_dac1.error++;
1035 } else if (s->dma_dac1.count <= (signed)s->dma_dac1.fragsize && !s->dma_dac1.endcleared) {
1036 clear_advance(s->dma_dac1.rawbuf, s->dma_dac1.dmasize, s->dma_dac1.swptr,
1037 s->dma_dac1.fragsize, (s->sctrl & SCTRL_P1SEB) ? 0 : 0x80);
1038 s->dma_dac1.endcleared = 1;
1039 }
1040 if (s->dma_dac1.count + (signed)s->dma_dac1.fragsize <= (signed)s->dma_dac1.dmasize)
1041 wake_up(&s->dma_dac1.wait);
1042 }
1043 }
1044 /* update DAC2 pointer */
1045 if (s->ctrl & CTRL_DAC2_EN) {
1046 diff = get_hwptr(s, &s->dma_dac2, ES1371_REG_DAC2_FRAMECNT);
1047 s->dma_dac2.total_bytes += diff;
1048 if (s->dma_dac2.mapped) {
1049 s->dma_dac2.count += diff;
1050 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1051 wake_up(&s->dma_dac2.wait);
1052 } else {
1053 s->dma_dac2.count -= diff;
1054 if (s->dma_dac2.count <= 0) {
1055 s->ctrl &= ~CTRL_DAC2_EN;
1056 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1057 s->dma_dac2.error++;
1058 } else if (s->dma_dac2.count <= (signed)s->dma_dac2.fragsize && !s->dma_dac2.endcleared) {
1059 clear_advance(s->dma_dac2.rawbuf, s->dma_dac2.dmasize, s->dma_dac2.swptr,
1060 s->dma_dac2.fragsize, (s->sctrl & SCTRL_P2SEB) ? 0 : 0x80);
1061 s->dma_dac2.endcleared = 1;
1062 }
1063 if (s->dma_dac2.count + (signed)s->dma_dac2.fragsize <= (signed)s->dma_dac2.dmasize)
1064 wake_up(&s->dma_dac2.wait);
1065 }
1066 }
1067}
1068
1069/* hold spinlock for the following! */
1070static void es1371_handle_midi(struct es1371_state *s)
1071{
1072 unsigned char ch;
1073 int wake;
1074
1075 if (!(s->ctrl & CTRL_UART_EN))
1076 return;
1077 wake = 0;
1078 while (inb(s->io+ES1371_REG_UART_STATUS) & USTAT_RXRDY) {
1079 ch = inb(s->io+ES1371_REG_UART_DATA);
1080 if (s->midi.icnt < MIDIINBUF) {
1081 s->midi.ibuf[s->midi.iwr] = ch;
1082 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
1083 s->midi.icnt++;
1084 }
1085 wake = 1;
1086 }
1087 if (wake)
1088 wake_up(&s->midi.iwait);
1089 wake = 0;
1090 while ((inb(s->io+ES1371_REG_UART_STATUS) & USTAT_TXRDY) && s->midi.ocnt > 0) {
1091 outb(s->midi.obuf[s->midi.ord], s->io+ES1371_REG_UART_DATA);
1092 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
1093 s->midi.ocnt--;
1094 if (s->midi.ocnt < MIDIOUTBUF-16)
1095 wake = 1;
1096 }
1097 if (wake)
1098 wake_up(&s->midi.owait);
1099 outb((s->midi.ocnt > 0) ? UCTRL_RXINTEN | UCTRL_ENA_TXINT : UCTRL_RXINTEN, s->io+ES1371_REG_UART_CONTROL);
1100}
1101
1102static irqreturn_t es1371_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1103{
1104 struct es1371_state *s = (struct es1371_state *)dev_id;
1105 unsigned int intsrc, sctl;
1106
1107 /* fastpath out, to ease interrupt sharing */
1108 intsrc = inl(s->io+ES1371_REG_STATUS);
1109 if (!(intsrc & 0x80000000))
1110 return IRQ_NONE;
1111 spin_lock(&s->lock);
1112 /* clear audio interrupts first */
1113 sctl = s->sctrl;
1114 if (intsrc & STAT_ADC)
1115 sctl &= ~SCTRL_R1INTEN;
1116 if (intsrc & STAT_DAC1)
1117 sctl &= ~SCTRL_P1INTEN;
1118 if (intsrc & STAT_DAC2)
1119 sctl &= ~SCTRL_P2INTEN;
1120 outl(sctl, s->io+ES1371_REG_SERIAL_CONTROL);
1121 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1122 es1371_update_ptr(s);
1123 es1371_handle_midi(s);
1124 spin_unlock(&s->lock);
1125 return IRQ_HANDLED;
1126}
1127
1128/* --------------------------------------------------------------------- */
1129
1130static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value\n";
1131
1132#define VALIDATE_STATE(s) \
1133({ \
1134 if (!(s) || (s)->magic != ES1371_MAGIC) { \
1135 printk(invalid_magic); \
1136 return -ENXIO; \
1137 } \
1138})
1139
1140/* --------------------------------------------------------------------- */
1141
1142/* Conversion table for S/PDIF PCM volume emulation through the SRC */
1143/* dB-linear table of DAC vol values; -0dB to -46.5dB with mute */
1144static const unsigned short DACVolTable[101] =
1145{
1146 0x1000, 0x0f2a, 0x0e60, 0x0da0, 0x0cea, 0x0c3e, 0x0b9a, 0x0aff,
1147 0x0a6d, 0x09e1, 0x095e, 0x08e1, 0x086a, 0x07fa, 0x078f, 0x072a,
1148 0x06cb, 0x0670, 0x061a, 0x05c9, 0x057b, 0x0532, 0x04ed, 0x04ab,
1149 0x046d, 0x0432, 0x03fa, 0x03c5, 0x0392, 0x0363, 0x0335, 0x030b,
1150 0x02e2, 0x02bc, 0x0297, 0x0275, 0x0254, 0x0235, 0x0217, 0x01fb,
1151 0x01e1, 0x01c8, 0x01b0, 0x0199, 0x0184, 0x0170, 0x015d, 0x014b,
1152 0x0139, 0x0129, 0x0119, 0x010b, 0x00fd, 0x00f0, 0x00e3, 0x00d7,
1153 0x00cc, 0x00c1, 0x00b7, 0x00ae, 0x00a5, 0x009c, 0x0094, 0x008c,
1154 0x0085, 0x007e, 0x0077, 0x0071, 0x006b, 0x0066, 0x0060, 0x005b,
1155 0x0057, 0x0052, 0x004e, 0x004a, 0x0046, 0x0042, 0x003f, 0x003c,
1156 0x0038, 0x0036, 0x0033, 0x0030, 0x002e, 0x002b, 0x0029, 0x0027,
1157 0x0025, 0x0023, 0x0021, 0x001f, 0x001e, 0x001c, 0x001b, 0x0019,
1158 0x0018, 0x0017, 0x0016, 0x0014, 0x0000
1159};
1160
1161/*
1162 * when we are in S/PDIF mode, we want to disable any analog output so
1163 * we filter the mixer ioctls
1164 */
1165static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, unsigned long arg)
1166{
1167 struct es1371_state *s = (struct es1371_state *)codec->private_data;
1168 int val;
1169 unsigned long flags;
1170 unsigned int left, right;
1171
1172 VALIDATE_STATE(s);
1173 /* filter mixer ioctls to catch PCM and MASTER volume when in S/PDIF mode */
1174 if (s->spdif_volume == -1)
1175 return codec->mixer_ioctl(codec, cmd, arg);
1176 switch (cmd) {
1177 case SOUND_MIXER_WRITE_VOLUME:
1178 return 0;
1179
1180 case SOUND_MIXER_WRITE_PCM: /* use SRC for PCM volume */
1181 if (get_user(val, (int __user *)arg))
1182 return -EFAULT;
1183 right = ((val >> 8) & 0xff);
1184 left = (val & 0xff);
1185 if (right > 100)
1186 right = 100;
1187 if (left > 100)
1188 left = 100;
1189 s->spdif_volume = (right << 8) | left;
1190 spin_lock_irqsave(&s->lock, flags);
1191 src_write(s, SRCREG_VOL_DAC2, DACVolTable[100 - left]);
1192 src_write(s, SRCREG_VOL_DAC2+1, DACVolTable[100 - right]);
1193 spin_unlock_irqrestore(&s->lock, flags);
1194 return 0;
1195
1196 case SOUND_MIXER_READ_PCM:
1197 return put_user(s->spdif_volume, (int __user *)arg);
1198 }
1199 return codec->mixer_ioctl(codec, cmd, arg);
1200}
1201
1202/* --------------------------------------------------------------------- */
1203
1204/*
1205 * AC97 Mixer Register to Connections mapping of the Concert 97 board
1206 *
1207 * AC97_MASTER_VOL_STEREO Line Out
1208 * AC97_MASTER_VOL_MONO TAD Output
1209 * AC97_PCBEEP_VOL none
1210 * AC97_PHONE_VOL TAD Input (mono)
1211 * AC97_MIC_VOL MIC Input (mono)
1212 * AC97_LINEIN_VOL Line Input (stereo)
1213 * AC97_CD_VOL CD Input (stereo)
1214 * AC97_VIDEO_VOL none
1215 * AC97_AUX_VOL Aux Input (stereo)
1216 * AC97_PCMOUT_VOL Wave Output (stereo)
1217 */
1218
1219static int es1371_open_mixdev(struct inode *inode, struct file *file)
1220{
1221 int minor = iminor(inode);
1222 struct list_head *list;
1223 struct es1371_state *s;
1224
1225 for (list = devs.next; ; list = list->next) {
1226 if (list == &devs)
1227 return -ENODEV;
1228 s = list_entry(list, struct es1371_state, devs);
1229 if (s->codec->dev_mixer == minor)
1230 break;
1231 }
1232 VALIDATE_STATE(s);
1233 file->private_data = s;
1234 return nonseekable_open(inode, file);
1235}
1236
1237static int es1371_release_mixdev(struct inode *inode, struct file *file)
1238{
1239 struct es1371_state *s = (struct es1371_state *)file->private_data;
1240
1241 VALIDATE_STATE(s);
1242 return 0;
1243}
1244
1245static int es1371_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1246{
1247 struct es1371_state *s = (struct es1371_state *)file->private_data;
1248 struct ac97_codec *codec = s->codec;
1249
1250 return mixdev_ioctl(codec, cmd, arg);
1251}
1252
1253static /*const*/ struct file_operations es1371_mixer_fops = {
1254 .owner = THIS_MODULE,
1255 .llseek = no_llseek,
1256 .ioctl = es1371_ioctl_mixdev,
1257 .open = es1371_open_mixdev,
1258 .release = es1371_release_mixdev,
1259};
1260
1261/* --------------------------------------------------------------------- */
1262
1263static int drain_dac1(struct es1371_state *s, int nonblock)
1264{
1265 DECLARE_WAITQUEUE(wait, current);
1266 unsigned long flags;
1267 int count, tmo;
1268
1269 if (s->dma_dac1.mapped || !s->dma_dac1.ready)
1270 return 0;
1271 add_wait_queue(&s->dma_dac1.wait, &wait);
1272 for (;;) {
1273 __set_current_state(TASK_INTERRUPTIBLE);
1274 spin_lock_irqsave(&s->lock, flags);
1275 count = s->dma_dac1.count;
1276 spin_unlock_irqrestore(&s->lock, flags);
1277 if (count <= 0)
1278 break;
1279 if (signal_pending(current))
1280 break;
1281 if (nonblock) {
1282 remove_wait_queue(&s->dma_dac1.wait, &wait);
1283 set_current_state(TASK_RUNNING);
1284 return -EBUSY;
1285 }
1286 tmo = 3 * HZ * (count + s->dma_dac1.fragsize) / 2 / s->dac1rate;
1287 tmo >>= sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
1288 if (!schedule_timeout(tmo + 1))
1289 DBG(printk(KERN_DEBUG PFX "dac1 dma timed out??\n");)
1290 }
1291 remove_wait_queue(&s->dma_dac1.wait, &wait);
1292 set_current_state(TASK_RUNNING);
1293 if (signal_pending(current))
1294 return -ERESTARTSYS;
1295 return 0;
1296}
1297
1298static int drain_dac2(struct es1371_state *s, int nonblock)
1299{
1300 DECLARE_WAITQUEUE(wait, current);
1301 unsigned long flags;
1302 int count, tmo;
1303
1304 if (s->dma_dac2.mapped || !s->dma_dac2.ready)
1305 return 0;
1306 add_wait_queue(&s->dma_dac2.wait, &wait);
1307 for (;;) {
1308 __set_current_state(TASK_UNINTERRUPTIBLE);
1309 spin_lock_irqsave(&s->lock, flags);
1310 count = s->dma_dac2.count;
1311 spin_unlock_irqrestore(&s->lock, flags);
1312 if (count <= 0)
1313 break;
1314 if (signal_pending(current))
1315 break;
1316 if (nonblock) {
1317 remove_wait_queue(&s->dma_dac2.wait, &wait);
1318 set_current_state(TASK_RUNNING);
1319 return -EBUSY;
1320 }
1321 tmo = 3 * HZ * (count + s->dma_dac2.fragsize) / 2 / s->dac2rate;
1322 tmo >>= sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
1323 if (!schedule_timeout(tmo + 1))
1324 DBG(printk(KERN_DEBUG PFX "dac2 dma timed out??\n");)
1325 }
1326 remove_wait_queue(&s->dma_dac2.wait, &wait);
1327 set_current_state(TASK_RUNNING);
1328 if (signal_pending(current))
1329 return -ERESTARTSYS;
1330 return 0;
1331}
1332
1333/* --------------------------------------------------------------------- */
1334
1335static ssize_t es1371_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1336{
1337 struct es1371_state *s = (struct es1371_state *)file->private_data;
1338 DECLARE_WAITQUEUE(wait, current);
1339 ssize_t ret = 0;
1340 unsigned long flags;
1341 unsigned swptr;
1342 int cnt;
1343
1344 VALIDATE_STATE(s);
1345 if (s->dma_adc.mapped)
1346 return -ENXIO;
1347 if (!access_ok(VERIFY_WRITE, buffer, count))
1348 return -EFAULT;
1349 down(&s->sem);
1350 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1351 goto out2;
1352
1353 add_wait_queue(&s->dma_adc.wait, &wait);
1354 while (count > 0) {
1355 spin_lock_irqsave(&s->lock, flags);
1356 swptr = s->dma_adc.swptr;
1357 cnt = s->dma_adc.dmasize-swptr;
1358 if (s->dma_adc.count < cnt)
1359 cnt = s->dma_adc.count;
1360 if (cnt <= 0)
1361 __set_current_state(TASK_INTERRUPTIBLE);
1362 spin_unlock_irqrestore(&s->lock, flags);
1363 if (cnt > count)
1364 cnt = count;
1365 if (cnt <= 0) {
1366 if (s->dma_adc.enabled)
1367 start_adc(s);
1368 if (file->f_flags & O_NONBLOCK) {
1369 if (!ret)
1370 ret = -EAGAIN;
1371 goto out;
1372 }
1373 up(&s->sem);
1374 schedule();
1375 if (signal_pending(current)) {
1376 if (!ret)
1377 ret = -ERESTARTSYS;
1378 goto out2;
1379 }
1380 down(&s->sem);
1381 if (s->dma_adc.mapped)
1382 {
1383 ret = -ENXIO;
1384 goto out;
1385 }
1386 continue;
1387 }
1388 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1389 if (!ret)
1390 ret = -EFAULT;
1391 goto out;
1392 }
1393 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1394 spin_lock_irqsave(&s->lock, flags);
1395 s->dma_adc.swptr = swptr;
1396 s->dma_adc.count -= cnt;
1397 spin_unlock_irqrestore(&s->lock, flags);
1398 count -= cnt;
1399 buffer += cnt;
1400 ret += cnt;
1401 if (s->dma_adc.enabled)
1402 start_adc(s);
1403 }
1404out:
1405 up(&s->sem);
1406out2:
1407 remove_wait_queue(&s->dma_adc.wait, &wait);
1408 set_current_state(TASK_RUNNING);
1409 return ret;
1410}
1411
1412static ssize_t es1371_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1413{
1414 struct es1371_state *s = (struct es1371_state *)file->private_data;
1415 DECLARE_WAITQUEUE(wait, current);
1416 ssize_t ret;
1417 unsigned long flags;
1418 unsigned swptr;
1419 int cnt;
1420
1421 VALIDATE_STATE(s);
1422 if (s->dma_dac2.mapped)
1423 return -ENXIO;
1424 if (!access_ok(VERIFY_READ, buffer, count))
1425 return -EFAULT;
1426 down(&s->sem);
1427 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1428 goto out3;
1429 ret = 0;
1430 add_wait_queue(&s->dma_dac2.wait, &wait);
1431 while (count > 0) {
1432 spin_lock_irqsave(&s->lock, flags);
1433 if (s->dma_dac2.count < 0) {
1434 s->dma_dac2.count = 0;
1435 s->dma_dac2.swptr = s->dma_dac2.hwptr;
1436 }
1437 swptr = s->dma_dac2.swptr;
1438 cnt = s->dma_dac2.dmasize-swptr;
1439 if (s->dma_dac2.count + cnt > s->dma_dac2.dmasize)
1440 cnt = s->dma_dac2.dmasize - s->dma_dac2.count;
1441 if (cnt <= 0)
1442 __set_current_state(TASK_INTERRUPTIBLE);
1443 spin_unlock_irqrestore(&s->lock, flags);
1444 if (cnt > count)
1445 cnt = count;
1446 if (cnt <= 0) {
1447 if (s->dma_dac2.enabled)
1448 start_dac2(s);
1449 if (file->f_flags & O_NONBLOCK) {
1450 if (!ret)
1451 ret = -EAGAIN;
1452 goto out;
1453 }
1454 up(&s->sem);
1455 schedule();
1456 if (signal_pending(current)) {
1457 if (!ret)
1458 ret = -ERESTARTSYS;
1459 goto out2;
1460 }
1461 down(&s->sem);
1462 if (s->dma_dac2.mapped)
1463 {
1464 ret = -ENXIO;
1465 goto out;
1466 }
1467 continue;
1468 }
1469 if (copy_from_user(s->dma_dac2.rawbuf + swptr, buffer, cnt)) {
1470 if (!ret)
1471 ret = -EFAULT;
1472 goto out;
1473 }
1474 swptr = (swptr + cnt) % s->dma_dac2.dmasize;
1475 spin_lock_irqsave(&s->lock, flags);
1476 s->dma_dac2.swptr = swptr;
1477 s->dma_dac2.count += cnt;
1478 s->dma_dac2.endcleared = 0;
1479 spin_unlock_irqrestore(&s->lock, flags);
1480 count -= cnt;
1481 buffer += cnt;
1482 ret += cnt;
1483 if (s->dma_dac2.enabled)
1484 start_dac2(s);
1485 }
1486out:
1487 up(&s->sem);
1488out2:
1489 remove_wait_queue(&s->dma_dac2.wait, &wait);
1490out3:
1491 set_current_state(TASK_RUNNING);
1492 return ret;
1493}
1494
1495/* No kernel lock - we have our own spinlock */
1496static unsigned int es1371_poll(struct file *file, struct poll_table_struct *wait)
1497{
1498 struct es1371_state *s = (struct es1371_state *)file->private_data;
1499 unsigned long flags;
1500 unsigned int mask = 0;
1501
1502 VALIDATE_STATE(s);
1503 if (file->f_mode & FMODE_WRITE) {
1504 if (!s->dma_dac2.ready && prog_dmabuf_dac2(s))
1505 return 0;
1506 poll_wait(file, &s->dma_dac2.wait, wait);
1507 }
1508 if (file->f_mode & FMODE_READ) {
1509 if (!s->dma_adc.ready && prog_dmabuf_adc(s))
1510 return 0;
1511 poll_wait(file, &s->dma_adc.wait, wait);
1512 }
1513 spin_lock_irqsave(&s->lock, flags);
1514 es1371_update_ptr(s);
1515 if (file->f_mode & FMODE_READ) {
1516 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1517 mask |= POLLIN | POLLRDNORM;
1518 }
1519 if (file->f_mode & FMODE_WRITE) {
1520 if (s->dma_dac2.mapped) {
1521 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1522 mask |= POLLOUT | POLLWRNORM;
1523 } else {
1524 if ((signed)s->dma_dac2.dmasize >= s->dma_dac2.count + (signed)s->dma_dac2.fragsize)
1525 mask |= POLLOUT | POLLWRNORM;
1526 }
1527 }
1528 spin_unlock_irqrestore(&s->lock, flags);
1529 return mask;
1530}
1531
1532static int es1371_mmap(struct file *file, struct vm_area_struct *vma)
1533{
1534 struct es1371_state *s = (struct es1371_state *)file->private_data;
1535 struct dmabuf *db;
1536 int ret = 0;
1537 unsigned long size;
1538
1539 VALIDATE_STATE(s);
1540 lock_kernel();
1541 down(&s->sem);
1542
1543 if (vma->vm_flags & VM_WRITE) {
1544 if ((ret = prog_dmabuf_dac2(s)) != 0) {
1545 goto out;
1546 }
1547 db = &s->dma_dac2;
1548 } else if (vma->vm_flags & VM_READ) {
1549 if ((ret = prog_dmabuf_adc(s)) != 0) {
1550 goto out;
1551 }
1552 db = &s->dma_adc;
1553 } else {
1554 ret = -EINVAL;
1555 goto out;
1556 }
1557 if (vma->vm_pgoff != 0) {
1558 ret = -EINVAL;
1559 goto out;
1560 }
1561 size = vma->vm_end - vma->vm_start;
1562 if (size > (PAGE_SIZE << db->buforder)) {
1563 ret = -EINVAL;
1564 goto out;
1565 }
1566 if (remap_pfn_range(vma, vma->vm_start,
1567 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1568 size, vma->vm_page_prot)) {
1569 ret = -EAGAIN;
1570 goto out;
1571 }
1572 db->mapped = 1;
1573out:
1574 up(&s->sem);
1575 unlock_kernel();
1576 return ret;
1577}
1578
1579static int es1371_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1580{
1581 struct es1371_state *s = (struct es1371_state *)file->private_data;
1582 unsigned long flags;
1583 audio_buf_info abinfo;
1584 count_info cinfo;
1585 int count;
1586 int val, mapped, ret;
1587 void __user *argp = (void __user *)arg;
1588 int __user *p = argp;
1589
1590 VALIDATE_STATE(s);
1591 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac2.mapped) ||
1592 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1593 switch (cmd) {
1594 case OSS_GETVERSION:
1595 return put_user(SOUND_VERSION, p);
1596
1597 case SNDCTL_DSP_SYNC:
1598 if (file->f_mode & FMODE_WRITE)
1599 return drain_dac2(s, 0/*file->f_flags & O_NONBLOCK*/);
1600 return 0;
1601
1602 case SNDCTL_DSP_SETDUPLEX:
1603 return 0;
1604
1605 case SNDCTL_DSP_GETCAPS:
1606 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
1607
1608 case SNDCTL_DSP_RESET:
1609 if (file->f_mode & FMODE_WRITE) {
1610 stop_dac2(s);
1611 synchronize_irq(s->irq);
1612 s->dma_dac2.swptr = s->dma_dac2.hwptr = s->dma_dac2.count = s->dma_dac2.total_bytes = 0;
1613 }
1614 if (file->f_mode & FMODE_READ) {
1615 stop_adc(s);
1616 synchronize_irq(s->irq);
1617 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1618 }
1619 return 0;
1620
1621 case SNDCTL_DSP_SPEED:
1622 if (get_user(val, p))
1623 return -EFAULT;
1624 if (val >= 0) {
1625 if (file->f_mode & FMODE_READ) {
1626 stop_adc(s);
1627 s->dma_adc.ready = 0;
1628 set_adc_rate(s, val);
1629 }
1630 if (file->f_mode & FMODE_WRITE) {
1631 stop_dac2(s);
1632 s->dma_dac2.ready = 0;
1633 set_dac2_rate(s, val);
1634 }
1635 }
1636 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p);
1637
1638 case SNDCTL_DSP_STEREO:
1639 if (get_user(val, p))
1640 return -EFAULT;
1641 if (file->f_mode & FMODE_READ) {
1642 stop_adc(s);
1643 s->dma_adc.ready = 0;
1644 spin_lock_irqsave(&s->lock, flags);
1645 if (val)
1646 s->sctrl |= SCTRL_R1SMB;
1647 else
1648 s->sctrl &= ~SCTRL_R1SMB;
1649 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1650 spin_unlock_irqrestore(&s->lock, flags);
1651 }
1652 if (file->f_mode & FMODE_WRITE) {
1653 stop_dac2(s);
1654 s->dma_dac2.ready = 0;
1655 spin_lock_irqsave(&s->lock, flags);
1656 if (val)
1657 s->sctrl |= SCTRL_P2SMB;
1658 else
1659 s->sctrl &= ~SCTRL_P2SMB;
1660 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1661 spin_unlock_irqrestore(&s->lock, flags);
1662 }
1663 return 0;
1664
1665 case SNDCTL_DSP_CHANNELS:
1666 if (get_user(val, p))
1667 return -EFAULT;
1668 if (val != 0) {
1669 if (file->f_mode & FMODE_READ) {
1670 stop_adc(s);
1671 s->dma_adc.ready = 0;
1672 spin_lock_irqsave(&s->lock, flags);
1673 if (val >= 2)
1674 s->sctrl |= SCTRL_R1SMB;
1675 else
1676 s->sctrl &= ~SCTRL_R1SMB;
1677 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1678 spin_unlock_irqrestore(&s->lock, flags);
1679 }
1680 if (file->f_mode & FMODE_WRITE) {
1681 stop_dac2(s);
1682 s->dma_dac2.ready = 0;
1683 spin_lock_irqsave(&s->lock, flags);
1684 if (val >= 2)
1685 s->sctrl |= SCTRL_P2SMB;
1686 else
1687 s->sctrl &= ~SCTRL_P2SMB;
1688 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1689 spin_unlock_irqrestore(&s->lock, flags);
1690 }
1691 }
1692 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p);
1693
1694 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1695 return put_user(AFMT_S16_LE|AFMT_U8, p);
1696
1697 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1698 if (get_user(val, p))
1699 return -EFAULT;
1700 if (val != AFMT_QUERY) {
1701 if (file->f_mode & FMODE_READ) {
1702 stop_adc(s);
1703 s->dma_adc.ready = 0;
1704 spin_lock_irqsave(&s->lock, flags);
1705 if (val == AFMT_S16_LE)
1706 s->sctrl |= SCTRL_R1SEB;
1707 else
1708 s->sctrl &= ~SCTRL_R1SEB;
1709 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1710 spin_unlock_irqrestore(&s->lock, flags);
1711 }
1712 if (file->f_mode & FMODE_WRITE) {
1713 stop_dac2(s);
1714 s->dma_dac2.ready = 0;
1715 spin_lock_irqsave(&s->lock, flags);
1716 if (val == AFMT_S16_LE)
1717 s->sctrl |= SCTRL_P2SEB;
1718 else
1719 s->sctrl &= ~SCTRL_P2SEB;
1720 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1721 spin_unlock_irqrestore(&s->lock, flags);
1722 }
1723 }
1724 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ?
1725 AFMT_S16_LE : AFMT_U8, p);
1726
1727 case SNDCTL_DSP_POST:
1728 return 0;
1729
1730 case SNDCTL_DSP_GETTRIGGER:
1731 val = 0;
1732 if (file->f_mode & FMODE_READ && s->ctrl & CTRL_ADC_EN)
1733 val |= PCM_ENABLE_INPUT;
1734 if (file->f_mode & FMODE_WRITE && s->ctrl & CTRL_DAC2_EN)
1735 val |= PCM_ENABLE_OUTPUT;
1736 return put_user(val, p);
1737
1738 case SNDCTL_DSP_SETTRIGGER:
1739 if (get_user(val, p))
1740 return -EFAULT;
1741 if (file->f_mode & FMODE_READ) {
1742 if (val & PCM_ENABLE_INPUT) {
1743 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1744 return ret;
1745 s->dma_adc.enabled = 1;
1746 start_adc(s);
1747 } else {
1748 s->dma_adc.enabled = 0;
1749 stop_adc(s);
1750 }
1751 }
1752 if (file->f_mode & FMODE_WRITE) {
1753 if (val & PCM_ENABLE_OUTPUT) {
1754 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1755 return ret;
1756 s->dma_dac2.enabled = 1;
1757 start_dac2(s);
1758 } else {
1759 s->dma_dac2.enabled = 0;
1760 stop_dac2(s);
1761 }
1762 }
1763 return 0;
1764
1765 case SNDCTL_DSP_GETOSPACE:
1766 if (!(file->f_mode & FMODE_WRITE))
1767 return -EINVAL;
1768 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1769 return val;
1770 spin_lock_irqsave(&s->lock, flags);
1771 es1371_update_ptr(s);
1772 abinfo.fragsize = s->dma_dac2.fragsize;
1773 count = s->dma_dac2.count;
1774 if (count < 0)
1775 count = 0;
1776 abinfo.bytes = s->dma_dac2.dmasize - count;
1777 abinfo.fragstotal = s->dma_dac2.numfrag;
1778 abinfo.fragments = abinfo.bytes >> s->dma_dac2.fragshift;
1779 spin_unlock_irqrestore(&s->lock, flags);
1780 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1781
1782 case SNDCTL_DSP_GETISPACE:
1783 if (!(file->f_mode & FMODE_READ))
1784 return -EINVAL;
1785 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1786 return val;
1787 spin_lock_irqsave(&s->lock, flags);
1788 es1371_update_ptr(s);
1789 abinfo.fragsize = s->dma_adc.fragsize;
1790 count = s->dma_adc.count;
1791 if (count < 0)
1792 count = 0;
1793 abinfo.bytes = count;
1794 abinfo.fragstotal = s->dma_adc.numfrag;
1795 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1796 spin_unlock_irqrestore(&s->lock, flags);
1797 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1798
1799 case SNDCTL_DSP_NONBLOCK:
1800 file->f_flags |= O_NONBLOCK;
1801 return 0;
1802
1803 case SNDCTL_DSP_GETODELAY:
1804 if (!(file->f_mode & FMODE_WRITE))
1805 return -EINVAL;
1806 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1807 return val;
1808 spin_lock_irqsave(&s->lock, flags);
1809 es1371_update_ptr(s);
1810 count = s->dma_dac2.count;
1811 spin_unlock_irqrestore(&s->lock, flags);
1812 if (count < 0)
1813 count = 0;
1814 return put_user(count, p);
1815
1816 case SNDCTL_DSP_GETIPTR:
1817 if (!(file->f_mode & FMODE_READ))
1818 return -EINVAL;
1819 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1820 return val;
1821 spin_lock_irqsave(&s->lock, flags);
1822 es1371_update_ptr(s);
1823 cinfo.bytes = s->dma_adc.total_bytes;
1824 count = s->dma_adc.count;
1825 if (count < 0)
1826 count = 0;
1827 cinfo.blocks = count >> s->dma_adc.fragshift;
1828 cinfo.ptr = s->dma_adc.hwptr;
1829 if (s->dma_adc.mapped)
1830 s->dma_adc.count &= s->dma_adc.fragsize-1;
1831 spin_unlock_irqrestore(&s->lock, flags);
1832 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1833 return -EFAULT;
1834 return 0;
1835
1836 case SNDCTL_DSP_GETOPTR:
1837 if (!(file->f_mode & FMODE_WRITE))
1838 return -EINVAL;
1839 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1840 return val;
1841 spin_lock_irqsave(&s->lock, flags);
1842 es1371_update_ptr(s);
1843 cinfo.bytes = s->dma_dac2.total_bytes;
1844 count = s->dma_dac2.count;
1845 if (count < 0)
1846 count = 0;
1847 cinfo.blocks = count >> s->dma_dac2.fragshift;
1848 cinfo.ptr = s->dma_dac2.hwptr;
1849 if (s->dma_dac2.mapped)
1850 s->dma_dac2.count &= s->dma_dac2.fragsize-1;
1851 spin_unlock_irqrestore(&s->lock, flags);
1852 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1853 return -EFAULT;
1854 return 0;
1855
1856 case SNDCTL_DSP_GETBLKSIZE:
1857 if (file->f_mode & FMODE_WRITE) {
1858 if ((val = prog_dmabuf_dac2(s)))
1859 return val;
1860 return put_user(s->dma_dac2.fragsize, p);
1861 }
1862 if ((val = prog_dmabuf_adc(s)))
1863 return val;
1864 return put_user(s->dma_adc.fragsize, p);
1865
1866 case SNDCTL_DSP_SETFRAGMENT:
1867 if (get_user(val, p))
1868 return -EFAULT;
1869 if (file->f_mode & FMODE_READ) {
1870 s->dma_adc.ossfragshift = val & 0xffff;
1871 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1872 if (s->dma_adc.ossfragshift < 4)
1873 s->dma_adc.ossfragshift = 4;
1874 if (s->dma_adc.ossfragshift > 15)
1875 s->dma_adc.ossfragshift = 15;
1876 if (s->dma_adc.ossmaxfrags < 4)
1877 s->dma_adc.ossmaxfrags = 4;
1878 }
1879 if (file->f_mode & FMODE_WRITE) {
1880 s->dma_dac2.ossfragshift = val & 0xffff;
1881 s->dma_dac2.ossmaxfrags = (val >> 16) & 0xffff;
1882 if (s->dma_dac2.ossfragshift < 4)
1883 s->dma_dac2.ossfragshift = 4;
1884 if (s->dma_dac2.ossfragshift > 15)
1885 s->dma_dac2.ossfragshift = 15;
1886 if (s->dma_dac2.ossmaxfrags < 4)
1887 s->dma_dac2.ossmaxfrags = 4;
1888 }
1889 return 0;
1890
1891 case SNDCTL_DSP_SUBDIVIDE:
1892 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1893 (file->f_mode & FMODE_WRITE && s->dma_dac2.subdivision))
1894 return -EINVAL;
1895 if (get_user(val, p))
1896 return -EFAULT;
1897 if (val != 1 && val != 2 && val != 4)
1898 return -EINVAL;
1899 if (file->f_mode & FMODE_READ)
1900 s->dma_adc.subdivision = val;
1901 if (file->f_mode & FMODE_WRITE)
1902 s->dma_dac2.subdivision = val;
1903 return 0;
1904
1905 case SOUND_PCM_READ_RATE:
1906 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p);
1907
1908 case SOUND_PCM_READ_CHANNELS:
1909 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p);
1910
1911 case SOUND_PCM_READ_BITS:
1912 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 16 : 8, p);
1913
1914 case SOUND_PCM_WRITE_FILTER:
1915 case SNDCTL_DSP_SETSYNCRO:
1916 case SOUND_PCM_READ_FILTER:
1917 return -EINVAL;
1918
1919 }
1920 return mixdev_ioctl(s->codec, cmd, arg);
1921}
1922
1923static int es1371_open(struct inode *inode, struct file *file)
1924{
1925 int minor = iminor(inode);
1926 DECLARE_WAITQUEUE(wait, current);
1927 unsigned long flags;
1928 struct list_head *list;
1929 struct es1371_state *s;
1930
1931 for (list = devs.next; ; list = list->next) {
1932 if (list == &devs)
1933 return -ENODEV;
1934 s = list_entry(list, struct es1371_state, devs);
1935 if (!((s->dev_audio ^ minor) & ~0xf))
1936 break;
1937 }
1938 VALIDATE_STATE(s);
1939 file->private_data = s;
1940 /* wait for device to become free */
1941 down(&s->open_sem);
1942 while (s->open_mode & file->f_mode) {
1943 if (file->f_flags & O_NONBLOCK) {
1944 up(&s->open_sem);
1945 return -EBUSY;
1946 }
1947 add_wait_queue(&s->open_wait, &wait);
1948 __set_current_state(TASK_INTERRUPTIBLE);
1949 up(&s->open_sem);
1950 schedule();
1951 remove_wait_queue(&s->open_wait, &wait);
1952 set_current_state(TASK_RUNNING);
1953 if (signal_pending(current))
1954 return -ERESTARTSYS;
1955 down(&s->open_sem);
1956 }
1957 if (file->f_mode & FMODE_READ) {
1958 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1959 s->dma_adc.enabled = 1;
1960 set_adc_rate(s, 8000);
1961 }
1962 if (file->f_mode & FMODE_WRITE) {
1963 s->dma_dac2.ossfragshift = s->dma_dac2.ossmaxfrags = s->dma_dac2.subdivision = 0;
1964 s->dma_dac2.enabled = 1;
1965 set_dac2_rate(s, 8000);
1966 }
1967 spin_lock_irqsave(&s->lock, flags);
1968 if (file->f_mode & FMODE_READ) {
1969 s->sctrl &= ~SCTRL_R1FMT;
1970 if ((minor & 0xf) == SND_DEV_DSP16)
1971 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_R1FMT;
1972 else
1973 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_R1FMT;
1974 }
1975 if (file->f_mode & FMODE_WRITE) {
1976 s->sctrl &= ~SCTRL_P2FMT;
1977 if ((minor & 0xf) == SND_DEV_DSP16)
1978 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P2FMT;
1979 else
1980 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P2FMT;
1981 }
1982 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1983 spin_unlock_irqrestore(&s->lock, flags);
1984 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1985 up(&s->open_sem);
1986 init_MUTEX(&s->sem);
1987 return nonseekable_open(inode, file);
1988}
1989
1990static int es1371_release(struct inode *inode, struct file *file)
1991{
1992 struct es1371_state *s = (struct es1371_state *)file->private_data;
1993
1994 VALIDATE_STATE(s);
1995 lock_kernel();
1996 if (file->f_mode & FMODE_WRITE)
1997 drain_dac2(s, file->f_flags & O_NONBLOCK);
1998 down(&s->open_sem);
1999 if (file->f_mode & FMODE_WRITE) {
2000 stop_dac2(s);
2001 dealloc_dmabuf(s, &s->dma_dac2);
2002 }
2003 if (file->f_mode & FMODE_READ) {
2004 stop_adc(s);
2005 dealloc_dmabuf(s, &s->dma_adc);
2006 }
2007 s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
2008 up(&s->open_sem);
2009 wake_up(&s->open_wait);
2010 unlock_kernel();
2011 return 0;
2012}
2013
2014static /*const*/ struct file_operations es1371_audio_fops = {
2015 .owner = THIS_MODULE,
2016 .llseek = no_llseek,
2017 .read = es1371_read,
2018 .write = es1371_write,
2019 .poll = es1371_poll,
2020 .ioctl = es1371_ioctl,
2021 .mmap = es1371_mmap,
2022 .open = es1371_open,
2023 .release = es1371_release,
2024};
2025
2026/* --------------------------------------------------------------------- */
2027
2028static ssize_t es1371_write_dac(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
2029{
2030 struct es1371_state *s = (struct es1371_state *)file->private_data;
2031 DECLARE_WAITQUEUE(wait, current);
2032 ssize_t ret = 0;
2033 unsigned long flags;
2034 unsigned swptr;
2035 int cnt;
2036
2037 VALIDATE_STATE(s);
2038 if (s->dma_dac1.mapped)
2039 return -ENXIO;
2040 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2041 return ret;
2042 if (!access_ok(VERIFY_READ, buffer, count))
2043 return -EFAULT;
2044 add_wait_queue(&s->dma_dac1.wait, &wait);
2045 while (count > 0) {
2046 spin_lock_irqsave(&s->lock, flags);
2047 if (s->dma_dac1.count < 0) {
2048 s->dma_dac1.count = 0;
2049 s->dma_dac1.swptr = s->dma_dac1.hwptr;
2050 }
2051 swptr = s->dma_dac1.swptr;
2052 cnt = s->dma_dac1.dmasize-swptr;
2053 if (s->dma_dac1.count + cnt > s->dma_dac1.dmasize)
2054 cnt = s->dma_dac1.dmasize - s->dma_dac1.count;
2055 if (cnt <= 0)
2056 __set_current_state(TASK_INTERRUPTIBLE);
2057 spin_unlock_irqrestore(&s->lock, flags);
2058 if (cnt > count)
2059 cnt = count;
2060 if (cnt <= 0) {
2061 if (s->dma_dac1.enabled)
2062 start_dac1(s);
2063 if (file->f_flags & O_NONBLOCK) {
2064 if (!ret)
2065 ret = -EAGAIN;
2066 break;
2067 }
2068 schedule();
2069 if (signal_pending(current)) {
2070 if (!ret)
2071 ret = -ERESTARTSYS;
2072 break;
2073 }
2074 continue;
2075 }
2076 if (copy_from_user(s->dma_dac1.rawbuf + swptr, buffer, cnt)) {
2077 if (!ret)
2078 ret = -EFAULT;
2079 break;
2080 }
2081 swptr = (swptr + cnt) % s->dma_dac1.dmasize;
2082 spin_lock_irqsave(&s->lock, flags);
2083 s->dma_dac1.swptr = swptr;
2084 s->dma_dac1.count += cnt;
2085 s->dma_dac1.endcleared = 0;
2086 spin_unlock_irqrestore(&s->lock, flags);
2087 count -= cnt;
2088 buffer += cnt;
2089 ret += cnt;
2090 if (s->dma_dac1.enabled)
2091 start_dac1(s);
2092 }
2093 remove_wait_queue(&s->dma_dac1.wait, &wait);
2094 set_current_state(TASK_RUNNING);
2095 return ret;
2096}
2097
2098/* No kernel lock - we have our own spinlock */
2099static unsigned int es1371_poll_dac(struct file *file, struct poll_table_struct *wait)
2100{
2101 struct es1371_state *s = (struct es1371_state *)file->private_data;
2102 unsigned long flags;
2103 unsigned int mask = 0;
2104
2105 VALIDATE_STATE(s);
2106 if (!s->dma_dac1.ready && prog_dmabuf_dac1(s))
2107 return 0;
2108 poll_wait(file, &s->dma_dac1.wait, wait);
2109 spin_lock_irqsave(&s->lock, flags);
2110 es1371_update_ptr(s);
2111 if (s->dma_dac1.mapped) {
2112 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
2113 mask |= POLLOUT | POLLWRNORM;
2114 } else {
2115 if ((signed)s->dma_dac1.dmasize >= s->dma_dac1.count + (signed)s->dma_dac1.fragsize)
2116 mask |= POLLOUT | POLLWRNORM;
2117 }
2118 spin_unlock_irqrestore(&s->lock, flags);
2119 return mask;
2120}
2121
2122static int es1371_mmap_dac(struct file *file, struct vm_area_struct *vma)
2123{
2124 struct es1371_state *s = (struct es1371_state *)file->private_data;
2125 int ret;
2126 unsigned long size;
2127
2128 VALIDATE_STATE(s);
2129 if (!(vma->vm_flags & VM_WRITE))
2130 return -EINVAL;
2131 lock_kernel();
2132 if ((ret = prog_dmabuf_dac1(s)) != 0)
2133 goto out;
2134 ret = -EINVAL;
2135 if (vma->vm_pgoff != 0)
2136 goto out;
2137 size = vma->vm_end - vma->vm_start;
2138 if (size > (PAGE_SIZE << s->dma_dac1.buforder))
2139 goto out;
2140 ret = -EAGAIN;
2141 if (remap_pfn_range(vma, vma->vm_start,
2142 virt_to_phys(s->dma_dac1.rawbuf) >> PAGE_SHIFT,
2143 size, vma->vm_page_prot))
2144 goto out;
2145 s->dma_dac1.mapped = 1;
2146 ret = 0;
2147out:
2148 unlock_kernel();
2149 return ret;
2150}
2151
2152static int es1371_ioctl_dac(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2153{
2154 struct es1371_state *s = (struct es1371_state *)file->private_data;
2155 unsigned long flags;
2156 audio_buf_info abinfo;
2157 count_info cinfo;
2158 int count;
2159 int val, ret;
2160 int __user *p = (int __user *)arg;
2161
2162 VALIDATE_STATE(s);
2163 switch (cmd) {
2164 case OSS_GETVERSION:
2165 return put_user(SOUND_VERSION, p);
2166
2167 case SNDCTL_DSP_SYNC:
2168 return drain_dac1(s, 0/*file->f_flags & O_NONBLOCK*/);
2169
2170 case SNDCTL_DSP_SETDUPLEX:
2171 return -EINVAL;
2172
2173 case SNDCTL_DSP_GETCAPS:
2174 return put_user(DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
2175
2176 case SNDCTL_DSP_RESET:
2177 stop_dac1(s);
2178 synchronize_irq(s->irq);
2179 s->dma_dac1.swptr = s->dma_dac1.hwptr = s->dma_dac1.count = s->dma_dac1.total_bytes = 0;
2180 return 0;
2181
2182 case SNDCTL_DSP_SPEED:
2183 if (get_user(val, p))
2184 return -EFAULT;
2185 if (val >= 0) {
2186 stop_dac1(s);
2187 s->dma_dac1.ready = 0;
2188 set_dac1_rate(s, val);
2189 }
2190 return put_user(s->dac1rate, p);
2191
2192 case SNDCTL_DSP_STEREO:
2193 if (get_user(val, p))
2194 return -EFAULT;
2195 stop_dac1(s);
2196 s->dma_dac1.ready = 0;
2197 spin_lock_irqsave(&s->lock, flags);
2198 if (val)
2199 s->sctrl |= SCTRL_P1SMB;
2200 else
2201 s->sctrl &= ~SCTRL_P1SMB;
2202 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2203 spin_unlock_irqrestore(&s->lock, flags);
2204 return 0;
2205
2206 case SNDCTL_DSP_CHANNELS:
2207 if (get_user(val, p))
2208 return -EFAULT;
2209 if (val != 0) {
2210 stop_dac1(s);
2211 s->dma_dac1.ready = 0;
2212 spin_lock_irqsave(&s->lock, flags);
2213 if (val >= 2)
2214 s->sctrl |= SCTRL_P1SMB;
2215 else
2216 s->sctrl &= ~SCTRL_P1SMB;
2217 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2218 spin_unlock_irqrestore(&s->lock, flags);
2219 }
2220 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p);
2221
2222 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2223 return put_user(AFMT_S16_LE|AFMT_U8, p);
2224
2225 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2226 if (get_user(val, p))
2227 return -EFAULT;
2228 if (val != AFMT_QUERY) {
2229 stop_dac1(s);
2230 s->dma_dac1.ready = 0;
2231 spin_lock_irqsave(&s->lock, flags);
2232 if (val == AFMT_S16_LE)
2233 s->sctrl |= SCTRL_P1SEB;
2234 else
2235 s->sctrl &= ~SCTRL_P1SEB;
2236 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2237 spin_unlock_irqrestore(&s->lock, flags);
2238 }
2239 return put_user((s->sctrl & SCTRL_P1SEB) ? AFMT_S16_LE : AFMT_U8, p);
2240
2241 case SNDCTL_DSP_POST:
2242 return 0;
2243
2244 case SNDCTL_DSP_GETTRIGGER:
2245 return put_user((s->ctrl & CTRL_DAC1_EN) ? PCM_ENABLE_OUTPUT : 0, p);
2246
2247 case SNDCTL_DSP_SETTRIGGER:
2248 if (get_user(val, p))
2249 return -EFAULT;
2250 if (val & PCM_ENABLE_OUTPUT) {
2251 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2252 return ret;
2253 s->dma_dac1.enabled = 1;
2254 start_dac1(s);
2255 } else {
2256 s->dma_dac1.enabled = 0;
2257 stop_dac1(s);
2258 }
2259 return 0;
2260
2261 case SNDCTL_DSP_GETOSPACE:
2262 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2263 return val;
2264 spin_lock_irqsave(&s->lock, flags);
2265 es1371_update_ptr(s);
2266 abinfo.fragsize = s->dma_dac1.fragsize;
2267 count = s->dma_dac1.count;
2268 if (count < 0)
2269 count = 0;
2270 abinfo.bytes = s->dma_dac1.dmasize - count;
2271 abinfo.fragstotal = s->dma_dac1.numfrag;
2272 abinfo.fragments = abinfo.bytes >> s->dma_dac1.fragshift;
2273 spin_unlock_irqrestore(&s->lock, flags);
2274 return copy_to_user((void __user *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2275
2276 case SNDCTL_DSP_NONBLOCK:
2277 file->f_flags |= O_NONBLOCK;
2278 return 0;
2279
2280 case SNDCTL_DSP_GETODELAY:
2281 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2282 return val;
2283 spin_lock_irqsave(&s->lock, flags);
2284 es1371_update_ptr(s);
2285 count = s->dma_dac1.count;
2286 spin_unlock_irqrestore(&s->lock, flags);
2287 if (count < 0)
2288 count = 0;
2289 return put_user(count, p);
2290
2291 case SNDCTL_DSP_GETOPTR:
2292 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2293 return val;
2294 spin_lock_irqsave(&s->lock, flags);
2295 es1371_update_ptr(s);
2296 cinfo.bytes = s->dma_dac1.total_bytes;
2297 count = s->dma_dac1.count;
2298 if (count < 0)
2299 count = 0;
2300 cinfo.blocks = count >> s->dma_dac1.fragshift;
2301 cinfo.ptr = s->dma_dac1.hwptr;
2302 if (s->dma_dac1.mapped)
2303 s->dma_dac1.count &= s->dma_dac1.fragsize-1;
2304 spin_unlock_irqrestore(&s->lock, flags);
2305 if (copy_to_user((void __user *)arg, &cinfo, sizeof(cinfo)))
2306 return -EFAULT;
2307 return 0;
2308
2309 case SNDCTL_DSP_GETBLKSIZE:
2310 if ((val = prog_dmabuf_dac1(s)))
2311 return val;
2312 return put_user(s->dma_dac1.fragsize, p);
2313
2314 case SNDCTL_DSP_SETFRAGMENT:
2315 if (get_user(val, p))
2316 return -EFAULT;
2317 s->dma_dac1.ossfragshift = val & 0xffff;
2318 s->dma_dac1.ossmaxfrags = (val >> 16) & 0xffff;
2319 if (s->dma_dac1.ossfragshift < 4)
2320 s->dma_dac1.ossfragshift = 4;
2321 if (s->dma_dac1.ossfragshift > 15)
2322 s->dma_dac1.ossfragshift = 15;
2323 if (s->dma_dac1.ossmaxfrags < 4)
2324 s->dma_dac1.ossmaxfrags = 4;
2325 return 0;
2326
2327 case SNDCTL_DSP_SUBDIVIDE:
2328 if (s->dma_dac1.subdivision)
2329 return -EINVAL;
2330 if (get_user(val, p))
2331 return -EFAULT;
2332 if (val != 1 && val != 2 && val != 4)
2333 return -EINVAL;
2334 s->dma_dac1.subdivision = val;
2335 return 0;
2336
2337 case SOUND_PCM_READ_RATE:
2338 return put_user(s->dac1rate, p);
2339
2340 case SOUND_PCM_READ_CHANNELS:
2341 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p);
2342
2343 case SOUND_PCM_READ_BITS:
2344 return put_user((s->sctrl & SCTRL_P1SEB) ? 16 : 8, p);
2345
2346 case SOUND_PCM_WRITE_FILTER:
2347 case SNDCTL_DSP_SETSYNCRO:
2348 case SOUND_PCM_READ_FILTER:
2349 return -EINVAL;
2350
2351 }
2352 return mixdev_ioctl(s->codec, cmd, arg);
2353}
2354
2355static int es1371_open_dac(struct inode *inode, struct file *file)
2356{
2357 int minor = iminor(inode);
2358 DECLARE_WAITQUEUE(wait, current);
2359 unsigned long flags;
2360 struct list_head *list;
2361 struct es1371_state *s;
2362
2363 for (list = devs.next; ; list = list->next) {
2364 if (list == &devs)
2365 return -ENODEV;
2366 s = list_entry(list, struct es1371_state, devs);
2367 if (!((s->dev_dac ^ minor) & ~0xf))
2368 break;
2369 }
2370 VALIDATE_STATE(s);
2371 /* we allow opening with O_RDWR, most programs do it although they will only write */
2372#if 0
2373 if (file->f_mode & FMODE_READ)
2374 return -EPERM;
2375#endif
2376 if (!(file->f_mode & FMODE_WRITE))
2377 return -EINVAL;
2378 file->private_data = s;
2379 /* wait for device to become free */
2380 down(&s->open_sem);
2381 while (s->open_mode & FMODE_DAC) {
2382 if (file->f_flags & O_NONBLOCK) {
2383 up(&s->open_sem);
2384 return -EBUSY;
2385 }
2386 add_wait_queue(&s->open_wait, &wait);
2387 __set_current_state(TASK_INTERRUPTIBLE);
2388 up(&s->open_sem);
2389 schedule();
2390 remove_wait_queue(&s->open_wait, &wait);
2391 set_current_state(TASK_RUNNING);
2392 if (signal_pending(current))
2393 return -ERESTARTSYS;
2394 down(&s->open_sem);
2395 }
2396 s->dma_dac1.ossfragshift = s->dma_dac1.ossmaxfrags = s->dma_dac1.subdivision = 0;
2397 s->dma_dac1.enabled = 1;
2398 set_dac1_rate(s, 8000);
2399 spin_lock_irqsave(&s->lock, flags);
2400 s->sctrl &= ~SCTRL_P1FMT;
2401 if ((minor & 0xf) == SND_DEV_DSP16)
2402 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P1FMT;
2403 else
2404 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P1FMT;
2405 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2406 spin_unlock_irqrestore(&s->lock, flags);
2407 s->open_mode |= FMODE_DAC;
2408 up(&s->open_sem);
2409 return nonseekable_open(inode, file);
2410}
2411
2412static int es1371_release_dac(struct inode *inode, struct file *file)
2413{
2414 struct es1371_state *s = (struct es1371_state *)file->private_data;
2415
2416 VALIDATE_STATE(s);
2417 lock_kernel();
2418 drain_dac1(s, file->f_flags & O_NONBLOCK);
2419 down(&s->open_sem);
2420 stop_dac1(s);
2421 dealloc_dmabuf(s, &s->dma_dac1);
2422 s->open_mode &= ~FMODE_DAC;
2423 up(&s->open_sem);
2424 wake_up(&s->open_wait);
2425 unlock_kernel();
2426 return 0;
2427}
2428
2429static /*const*/ struct file_operations es1371_dac_fops = {
2430 .owner = THIS_MODULE,
2431 .llseek = no_llseek,
2432 .write = es1371_write_dac,
2433 .poll = es1371_poll_dac,
2434 .ioctl = es1371_ioctl_dac,
2435 .mmap = es1371_mmap_dac,
2436 .open = es1371_open_dac,
2437 .release = es1371_release_dac,
2438};
2439
2440/* --------------------------------------------------------------------- */
2441
2442static ssize_t es1371_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
2443{
2444 struct es1371_state *s = (struct es1371_state *)file->private_data;
2445 DECLARE_WAITQUEUE(wait, current);
2446 ssize_t ret;
2447 unsigned long flags;
2448 unsigned ptr;
2449 int cnt;
2450
2451 VALIDATE_STATE(s);
2452 if (!access_ok(VERIFY_WRITE, buffer, count))
2453 return -EFAULT;
2454 if (count == 0)
2455 return 0;
2456 ret = 0;
2457 add_wait_queue(&s->midi.iwait, &wait);
2458 while (count > 0) {
2459 spin_lock_irqsave(&s->lock, flags);
2460 ptr = s->midi.ird;
2461 cnt = MIDIINBUF - ptr;
2462 if (s->midi.icnt < cnt)
2463 cnt = s->midi.icnt;
2464 if (cnt <= 0)
2465 __set_current_state(TASK_INTERRUPTIBLE);
2466 spin_unlock_irqrestore(&s->lock, flags);
2467 if (cnt > count)
2468 cnt = count;
2469 if (cnt <= 0) {
2470 if (file->f_flags & O_NONBLOCK) {
2471 if (!ret)
2472 ret = -EAGAIN;
2473 break;
2474 }
2475 schedule();
2476 if (signal_pending(current)) {
2477 if (!ret)
2478 ret = -ERESTARTSYS;
2479 break;
2480 }
2481 continue;
2482 }
2483 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
2484 if (!ret)
2485 ret = -EFAULT;
2486 break;
2487 }
2488 ptr = (ptr + cnt) % MIDIINBUF;
2489 spin_lock_irqsave(&s->lock, flags);
2490 s->midi.ird = ptr;
2491 s->midi.icnt -= cnt;
2492 spin_unlock_irqrestore(&s->lock, flags);
2493 count -= cnt;
2494 buffer += cnt;
2495 ret += cnt;
2496 break;
2497 }
2498 __set_current_state(TASK_RUNNING);
2499 remove_wait_queue(&s->midi.iwait, &wait);
2500 return ret;
2501}
2502
2503static ssize_t es1371_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
2504{
2505 struct es1371_state *s = (struct es1371_state *)file->private_data;
2506 DECLARE_WAITQUEUE(wait, current);
2507 ssize_t ret;
2508 unsigned long flags;
2509 unsigned ptr;
2510 int cnt;
2511
2512 VALIDATE_STATE(s);
2513 if (!access_ok(VERIFY_READ, buffer, count))
2514 return -EFAULT;
2515 if (count == 0)
2516 return 0;
2517 ret = 0;
2518 add_wait_queue(&s->midi.owait, &wait);
2519 while (count > 0) {
2520 spin_lock_irqsave(&s->lock, flags);
2521 ptr = s->midi.owr;
2522 cnt = MIDIOUTBUF - ptr;
2523 if (s->midi.ocnt + cnt > MIDIOUTBUF)
2524 cnt = MIDIOUTBUF - s->midi.ocnt;
2525 if (cnt <= 0) {
2526 __set_current_state(TASK_INTERRUPTIBLE);
2527 es1371_handle_midi(s);
2528 }
2529 spin_unlock_irqrestore(&s->lock, flags);
2530 if (cnt > count)
2531 cnt = count;
2532 if (cnt <= 0) {
2533 if (file->f_flags & O_NONBLOCK) {
2534 if (!ret)
2535 ret = -EAGAIN;
2536 break;
2537 }
2538 schedule();
2539 if (signal_pending(current)) {
2540 if (!ret)
2541 ret = -ERESTARTSYS;
2542 break;
2543 }
2544 continue;
2545 }
2546 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
2547 if (!ret)
2548 ret = -EFAULT;
2549 break;
2550 }
2551 ptr = (ptr + cnt) % MIDIOUTBUF;
2552 spin_lock_irqsave(&s->lock, flags);
2553 s->midi.owr = ptr;
2554 s->midi.ocnt += cnt;
2555 spin_unlock_irqrestore(&s->lock, flags);
2556 count -= cnt;
2557 buffer += cnt;
2558 ret += cnt;
2559 spin_lock_irqsave(&s->lock, flags);
2560 es1371_handle_midi(s);
2561 spin_unlock_irqrestore(&s->lock, flags);
2562 }
2563 __set_current_state(TASK_RUNNING);
2564 remove_wait_queue(&s->midi.owait, &wait);
2565 return ret;
2566}
2567
2568/* No kernel lock - we have our own spinlock */
2569static unsigned int es1371_midi_poll(struct file *file, struct poll_table_struct *wait)
2570{
2571 struct es1371_state *s = (struct es1371_state *)file->private_data;
2572 unsigned long flags;
2573 unsigned int mask = 0;
2574
2575 VALIDATE_STATE(s);
2576 if (file->f_mode & FMODE_WRITE)
2577 poll_wait(file, &s->midi.owait, wait);
2578 if (file->f_mode & FMODE_READ)
2579 poll_wait(file, &s->midi.iwait, wait);
2580 spin_lock_irqsave(&s->lock, flags);
2581 if (file->f_mode & FMODE_READ) {
2582 if (s->midi.icnt > 0)
2583 mask |= POLLIN | POLLRDNORM;
2584 }
2585 if (file->f_mode & FMODE_WRITE) {
2586 if (s->midi.ocnt < MIDIOUTBUF)
2587 mask |= POLLOUT | POLLWRNORM;
2588 }
2589 spin_unlock_irqrestore(&s->lock, flags);
2590 return mask;
2591}
2592
2593static int es1371_midi_open(struct inode *inode, struct file *file)
2594{
2595 int minor = iminor(inode);
2596 DECLARE_WAITQUEUE(wait, current);
2597 unsigned long flags;
2598 struct list_head *list;
2599 struct es1371_state *s;
2600
2601 for (list = devs.next; ; list = list->next) {
2602 if (list == &devs)
2603 return -ENODEV;
2604 s = list_entry(list, struct es1371_state, devs);
2605 if (s->dev_midi == minor)
2606 break;
2607 }
2608 VALIDATE_STATE(s);
2609 file->private_data = s;
2610 /* wait for device to become free */
2611 down(&s->open_sem);
2612 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
2613 if (file->f_flags & O_NONBLOCK) {
2614 up(&s->open_sem);
2615 return -EBUSY;
2616 }
2617 add_wait_queue(&s->open_wait, &wait);
2618 __set_current_state(TASK_INTERRUPTIBLE);
2619 up(&s->open_sem);
2620 schedule();
2621 remove_wait_queue(&s->open_wait, &wait);
2622 set_current_state(TASK_RUNNING);
2623 if (signal_pending(current))
2624 return -ERESTARTSYS;
2625 down(&s->open_sem);
2626 }
2627 spin_lock_irqsave(&s->lock, flags);
2628 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2629 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2630 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2631 outb(UCTRL_CNTRL_SWR, s->io+ES1371_REG_UART_CONTROL);
2632 outb(0, s->io+ES1371_REG_UART_CONTROL);
2633 outb(0, s->io+ES1371_REG_UART_TEST);
2634 }
2635 if (file->f_mode & FMODE_READ) {
2636 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2637 }
2638 if (file->f_mode & FMODE_WRITE) {
2639 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2640 }
2641 s->ctrl |= CTRL_UART_EN;
2642 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2643 es1371_handle_midi(s);
2644 spin_unlock_irqrestore(&s->lock, flags);
2645 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
2646 up(&s->open_sem);
2647 return nonseekable_open(inode, file);
2648}
2649
2650static int es1371_midi_release(struct inode *inode, struct file *file)
2651{
2652 struct es1371_state *s = (struct es1371_state *)file->private_data;
2653 DECLARE_WAITQUEUE(wait, current);
2654 unsigned long flags;
2655 unsigned count, tmo;
2656
2657 VALIDATE_STATE(s);
2658 lock_kernel();
2659 if (file->f_mode & FMODE_WRITE) {
2660 add_wait_queue(&s->midi.owait, &wait);
2661 for (;;) {
2662 __set_current_state(TASK_INTERRUPTIBLE);
2663 spin_lock_irqsave(&s->lock, flags);
2664 count = s->midi.ocnt;
2665 spin_unlock_irqrestore(&s->lock, flags);
2666 if (count <= 0)
2667 break;
2668 if (signal_pending(current))
2669 break;
2670 if (file->f_flags & O_NONBLOCK)
2671 break;
2672 tmo = (count * HZ) / 3100;
2673 if (!schedule_timeout(tmo ? : 1) && tmo)
2674 printk(KERN_DEBUG PFX "midi timed out??\n");
2675 }
2676 remove_wait_queue(&s->midi.owait, &wait);
2677 set_current_state(TASK_RUNNING);
2678 }
2679 down(&s->open_sem);
2680 s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
2681 spin_lock_irqsave(&s->lock, flags);
2682 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2683 s->ctrl &= ~CTRL_UART_EN;
2684 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2685 }
2686 spin_unlock_irqrestore(&s->lock, flags);
2687 up(&s->open_sem);
2688 wake_up(&s->open_wait);
2689 unlock_kernel();
2690 return 0;
2691}
2692
2693static /*const*/ struct file_operations es1371_midi_fops = {
2694 .owner = THIS_MODULE,
2695 .llseek = no_llseek,
2696 .read = es1371_midi_read,
2697 .write = es1371_midi_write,
2698 .poll = es1371_midi_poll,
2699 .open = es1371_midi_open,
2700 .release = es1371_midi_release,
2701};
2702
2703/* --------------------------------------------------------------------- */
2704
2705/*
2706 * for debugging purposes, we'll create a proc device that dumps the
2707 * CODEC chipstate
2708 */
2709
2710#ifdef ES1371_DEBUG
2711static int proc_es1371_dump (char *buf, char **start, off_t fpos, int length, int *eof, void *data)
2712{
2713 struct es1371_state *s;
2714 int cnt, len = 0;
2715
2716 if (list_empty(&devs))
2717 return 0;
2718 s = list_entry(devs.next, struct es1371_state, devs);
2719 /* print out header */
2720 len += sprintf(buf + len, "\t\tCreative ES137x Debug Dump-o-matic\n");
2721
2722 /* print out CODEC state */
2723 len += sprintf (buf + len, "AC97 CODEC state\n");
2724 for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
2725 len+= sprintf (buf + len, "reg:0x%02x val:0x%04x\n", cnt, rdcodec(s->codec, cnt));
2726
2727 if (fpos >=len){
2728 *start = buf;
2729 *eof =1;
2730 return 0;
2731 }
2732 *start = buf + fpos;
2733 if ((len -= fpos) > length)
2734 return length;
2735 *eof =1;
2736 return len;
2737
2738}
2739#endif /* ES1371_DEBUG */
2740
2741/* --------------------------------------------------------------------- */
2742
2743/* maximum number of devices; only used for command line params */
2744#define NR_DEVICE 5
2745
2746static int spdif[NR_DEVICE];
2747static int nomix[NR_DEVICE];
2748static int amplifier[NR_DEVICE];
2749
2750static unsigned int devindex;
2751
2752module_param_array(spdif, bool, NULL, 0);
2753MODULE_PARM_DESC(spdif, "if 1 the output is in S/PDIF digital mode");
2754module_param_array(nomix, bool, NULL, 0);
2755MODULE_PARM_DESC(nomix, "if 1 no analog audio is mixed to the digital output");
2756module_param_array(amplifier, bool, NULL, 0);
2757MODULE_PARM_DESC(amplifier, "Set to 1 if the machine needs the amp control enabling (many laptops)");
2758
2759MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2760MODULE_DESCRIPTION("ES1371 AudioPCI97 Driver");
2761MODULE_LICENSE("GPL");
2762
2763
2764/* --------------------------------------------------------------------- */
2765
2766static struct initvol {
2767 int mixch;
2768 int vol;
2769} initvol[] __devinitdata = {
2770 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2771 { SOUND_MIXER_WRITE_CD, 0x4040 },
2772 { MIXER_WRITE(SOUND_MIXER_VIDEO), 0x4040 },
2773 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2774 { SOUND_MIXER_WRITE_PCM, 0x4040 },
2775 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2776 { MIXER_WRITE(SOUND_MIXER_PHONEOUT), 0x4040 },
2777 { SOUND_MIXER_WRITE_OGAIN, 0x4040 },
2778 { MIXER_WRITE(SOUND_MIXER_PHONEIN), 0x4040 },
2779 { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
2780 { SOUND_MIXER_WRITE_MIC, 0x4040 },
2781 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2782 { SOUND_MIXER_WRITE_IGAIN, 0x4040 }
2783};
2784
2785static struct
2786{
2787 short svid, sdid;
2788} amplifier_needed[] =
2789{
2790 { 0x107B, 0x2150 }, /* Gateway Solo 2150 */
2791 { 0x13BD, 0x100C }, /* Mebius PC-MJ100V */
2792 { 0x1102, 0x5938 }, /* Targa Xtender 300 */
2793 { 0x1102, 0x8938 }, /* IPC notebook */
2794 { PCI_ANY_ID, PCI_ANY_ID }
2795};
2796
Dmitry Torokhov5d503e52005-06-01 02:39:04 -05002797#ifdef SUPPORT_JOYSTICK
2798
2799static int __devinit es1371_register_gameport(struct es1371_state *s)
2800{
2801 struct gameport *gp;
2802 int gpio;
2803
2804 for (gpio = 0x218; gpio >= 0x200; gpio -= 0x08)
2805 if (request_region(gpio, JOY_EXTENT, "es1371"))
2806 break;
2807
2808 if (gpio < 0x200) {
2809 printk(KERN_ERR PFX "no free joystick address found\n");
2810 return -EBUSY;
2811 }
2812
2813 s->gameport = gp = gameport_allocate_port();
2814 if (!gp) {
2815 printk(KERN_ERR PFX "can not allocate memory for gameport\n");
2816 release_region(gpio, JOY_EXTENT);
2817 return -ENOMEM;
2818 }
2819
2820 gameport_set_name(gp, "ESS1371 Gameport");
2821 gameport_set_phys(gp, "isa%04x/gameport0", gpio);
2822 gp->dev.parent = &s->dev->dev;
2823 gp->io = gpio;
2824
2825 s->ctrl |= CTRL_JYSTK_EN | (((gpio >> 3) & CTRL_JOY_MASK) << CTRL_JOY_SHIFT);
2826 outl(s->ctrl, s->io + ES1371_REG_CONTROL);
2827
2828 gameport_register_port(gp);
2829
2830 return 0;
2831}
2832
2833static inline void es1371_unregister_gameport(struct es1371_state *s)
2834{
2835 if (s->gameport) {
2836 int gpio = s->gameport->io;
2837 gameport_unregister_port(s->gameport);
2838 release_region(gpio, JOY_EXTENT);
2839
2840 }
2841}
2842
2843#else
2844static inline int es1371_register_gameport(struct es1371_state *s) { return -ENOSYS; }
2845static inline void es1371_unregister_gameport(struct es1371_state *s) { }
2846#endif /* SUPPORT_JOYSTICK */
2847
2848
Linus Torvalds1da177e2005-04-16 15:20:36 -07002849static int __devinit es1371_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2850{
2851 struct es1371_state *s;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002852 mm_segment_t fs;
Dmitry Torokhov5d503e52005-06-01 02:39:04 -05002853 int i, val, res = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002854 int idx;
2855 unsigned long tmo;
2856 signed long tmo2;
2857 unsigned int cssr;
2858
2859 if ((res=pci_enable_device(pcidev)))
2860 return res;
2861
2862 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO))
2863 return -ENODEV;
2864 if (pcidev->irq == 0)
2865 return -ENODEV;
Tobias Klauser3ee538a2005-06-25 14:59:26 -07002866 i = pci_set_dma_mask(pcidev, DMA_32BIT_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002867 if (i) {
2868 printk(KERN_WARNING "es1371: architecture does not support 32bit PCI busmaster DMA\n");
2869 return i;
2870 }
2871 if (!(s = kmalloc(sizeof(struct es1371_state), GFP_KERNEL))) {
2872 printk(KERN_WARNING PFX "out of memory\n");
2873 return -ENOMEM;
2874 }
2875 memset(s, 0, sizeof(struct es1371_state));
2876
2877 s->codec = ac97_alloc_codec();
2878 if(s->codec == NULL)
2879 goto err_codec;
2880
2881 init_waitqueue_head(&s->dma_adc.wait);
2882 init_waitqueue_head(&s->dma_dac1.wait);
2883 init_waitqueue_head(&s->dma_dac2.wait);
2884 init_waitqueue_head(&s->open_wait);
2885 init_waitqueue_head(&s->midi.iwait);
2886 init_waitqueue_head(&s->midi.owait);
2887 init_MUTEX(&s->open_sem);
2888 spin_lock_init(&s->lock);
2889 s->magic = ES1371_MAGIC;
2890 s->dev = pcidev;
2891 s->io = pci_resource_start(pcidev, 0);
2892 s->irq = pcidev->irq;
2893 s->vendor = pcidev->vendor;
2894 s->device = pcidev->device;
2895 pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev);
2896 s->codec->private_data = s;
2897 s->codec->id = 0;
2898 s->codec->codec_read = rdcodec;
2899 s->codec->codec_write = wrcodec;
2900 printk(KERN_INFO PFX "found chip, vendor id 0x%04x device id 0x%04x revision 0x%02x\n",
2901 s->vendor, s->device, s->rev);
2902 if (!request_region(s->io, ES1371_EXTENT, "es1371")) {
2903 printk(KERN_ERR PFX "io ports %#lx-%#lx in use\n", s->io, s->io+ES1371_EXTENT-1);
2904 res = -EBUSY;
2905 goto err_region;
2906 }
2907 if ((res=request_irq(s->irq, es1371_interrupt, SA_SHIRQ, "es1371",s))) {
2908 printk(KERN_ERR PFX "irq %u in use\n", s->irq);
2909 goto err_irq;
2910 }
2911 printk(KERN_INFO PFX "found es1371 rev %d at io %#lx irq %u\n",
2912 s->rev, s->io, s->irq);
2913 /* register devices */
2914 if ((res=(s->dev_audio = register_sound_dsp(&es1371_audio_fops,-1)))<0)
2915 goto err_dev1;
2916 if ((res=(s->codec->dev_mixer = register_sound_mixer(&es1371_mixer_fops, -1))) < 0)
2917 goto err_dev2;
2918 if ((res=(s->dev_dac = register_sound_dsp(&es1371_dac_fops, -1))) < 0)
2919 goto err_dev3;
2920 if ((res=(s->dev_midi = register_sound_midi(&es1371_midi_fops, -1)))<0 )
2921 goto err_dev4;
2922#ifdef ES1371_DEBUG
2923 /* initialize the debug proc device */
2924 s->ps = create_proc_read_entry("es1371",0,NULL,proc_es1371_dump,NULL);
2925#endif /* ES1371_DEBUG */
2926
2927 /* initialize codec registers */
2928 s->ctrl = 0;
2929
2930 /* Check amplifier requirements */
2931
2932 if (amplifier[devindex])
2933 s->ctrl |= CTRL_GPIO_OUT0;
2934 else for(idx = 0; amplifier_needed[idx].svid != PCI_ANY_ID; idx++)
2935 {
2936 if(pcidev->subsystem_vendor == amplifier_needed[idx].svid &&
2937 pcidev->subsystem_device == amplifier_needed[idx].sdid)
2938 {
2939 s->ctrl |= CTRL_GPIO_OUT0; /* turn internal amplifier on */
2940 printk(KERN_INFO PFX "Enabling internal amplifier.\n");
2941 }
2942 }
2943
Linus Torvalds1da177e2005-04-16 15:20:36 -07002944 s->sctrl = 0;
2945 cssr = 0;
2946 s->spdif_volume = -1;
2947 /* check to see if s/pdif mode is being requested */
2948 if (spdif[devindex]) {
2949 if (s->rev >= 4) {
2950 printk(KERN_INFO PFX "enabling S/PDIF output\n");
2951 s->spdif_volume = 0;
2952 cssr |= STAT_EN_SPDIF;
2953 s->ctrl |= CTRL_SPDIFEN_B;
2954 if (nomix[devindex]) /* don't mix analog inputs to s/pdif output */
2955 s->ctrl |= CTRL_RECEN_B;
2956 } else {
2957 printk(KERN_ERR PFX "revision %d does not support S/PDIF\n", s->rev);
2958 }
2959 }
2960 /* initialize the chips */
2961 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2962 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2963 outl(LEGACY_JFAST, s->io+ES1371_REG_LEGACY);
2964 pci_set_master(pcidev); /* enable bus mastering */
2965 /* if we are a 5880 turn on the AC97 */
2966 if (s->vendor == PCI_VENDOR_ID_ENSONIQ &&
2967 ((s->device == PCI_DEVICE_ID_ENSONIQ_CT5880 && s->rev >= CT5880REV_CT5880_C) ||
2968 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_CT5880_A) ||
2969 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_ES1373_8))) {
2970 cssr |= CSTAT_5880_AC97_RST;
2971 outl(cssr, s->io+ES1371_REG_STATUS);
2972 /* need to delay around 20ms(bleech) to give
2973 some CODECs enough time to wakeup */
2974 tmo = jiffies + (HZ / 50) + 1;
2975 for (;;) {
2976 tmo2 = tmo - jiffies;
2977 if (tmo2 <= 0)
2978 break;
2979 schedule_timeout(tmo2);
2980 }
2981 }
2982 /* AC97 warm reset to start the bitclk */
2983 outl(s->ctrl | CTRL_SYNCRES, s->io+ES1371_REG_CONTROL);
2984 udelay(2);
2985 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2986 /* init the sample rate converter */
2987 src_init(s);
2988 /* codec init */
2989 if (!ac97_probe_codec(s->codec)) {
2990 res = -ENODEV;
2991 goto err_gp;
2992 }
2993 /* set default values */
2994
2995 fs = get_fs();
2996 set_fs(KERNEL_DS);
2997 val = SOUND_MASK_LINE;
2998 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2999 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
3000 val = initvol[i].vol;
3001 mixdev_ioctl(s->codec, initvol[i].mixch, (unsigned long)&val);
3002 }
3003 /* mute master and PCM when in S/PDIF mode */
3004 if (s->spdif_volume != -1) {
3005 val = 0x0000;
3006 s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_VOLUME, (unsigned long)&val);
3007 s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_PCM, (unsigned long)&val);
3008 }
3009 set_fs(fs);
3010 /* turn on S/PDIF output driver if requested */
3011 outl(cssr, s->io+ES1371_REG_STATUS);
3012
Dmitry Torokhov5d503e52005-06-01 02:39:04 -05003013 es1371_register_gameport(s);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003014
3015 /* store it in the driver field */
3016 pci_set_drvdata(pcidev, s);
3017 /* put it into driver list */
3018 list_add_tail(&s->devs, &devs);
3019 /* increment devindex */
3020 if (devindex < NR_DEVICE-1)
3021 devindex++;
Dmitry Torokhov5d503e52005-06-01 02:39:04 -05003022 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003023
3024 err_gp:
Linus Torvalds1da177e2005-04-16 15:20:36 -07003025#ifdef ES1371_DEBUG
3026 if (s->ps)
3027 remove_proc_entry("es1371", NULL);
3028#endif
3029 unregister_sound_midi(s->dev_midi);
3030 err_dev4:
3031 unregister_sound_dsp(s->dev_dac);
3032 err_dev3:
3033 unregister_sound_mixer(s->codec->dev_mixer);
3034 err_dev2:
3035 unregister_sound_dsp(s->dev_audio);
3036 err_dev1:
3037 printk(KERN_ERR PFX "cannot register misc device\n");
3038 free_irq(s->irq, s);
3039 err_irq:
3040 release_region(s->io, ES1371_EXTENT);
3041 err_region:
3042 err_codec:
3043 ac97_release_codec(s->codec);
3044 kfree(s);
3045 return res;
3046}
3047
3048static void __devexit es1371_remove(struct pci_dev *dev)
3049{
3050 struct es1371_state *s = pci_get_drvdata(dev);
3051
3052 if (!s)
3053 return;
3054 list_del(&s->devs);
3055#ifdef ES1371_DEBUG
3056 if (s->ps)
3057 remove_proc_entry("es1371", NULL);
3058#endif /* ES1371_DEBUG */
3059 outl(0, s->io+ES1371_REG_CONTROL); /* switch everything off */
3060 outl(0, s->io+ES1371_REG_SERIAL_CONTROL); /* clear serial interrupts */
3061 synchronize_irq(s->irq);
3062 free_irq(s->irq, s);
Dmitry Torokhov5d503e52005-06-01 02:39:04 -05003063 es1371_unregister_gameport(s);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003064 release_region(s->io, ES1371_EXTENT);
3065 unregister_sound_dsp(s->dev_audio);
3066 unregister_sound_mixer(s->codec->dev_mixer);
3067 unregister_sound_dsp(s->dev_dac);
3068 unregister_sound_midi(s->dev_midi);
3069 ac97_release_codec(s->codec);
3070 kfree(s);
3071 pci_set_drvdata(dev, NULL);
3072}
3073
3074static struct pci_device_id id_table[] = {
3075 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3076 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3077 { PCI_VENDOR_ID_ECTIVA, PCI_DEVICE_ID_ECTIVA_EV1938, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3078 { 0, }
3079};
3080
3081MODULE_DEVICE_TABLE(pci, id_table);
3082
3083static struct pci_driver es1371_driver = {
3084 .name = "es1371",
3085 .id_table = id_table,
3086 .probe = es1371_probe,
3087 .remove = __devexit_p(es1371_remove),
3088};
3089
3090static int __init init_es1371(void)
3091{
3092 printk(KERN_INFO PFX "version v0.32 time " __TIME__ " " __DATE__ "\n");
Greg Kroah-Hartman46654722005-12-06 15:33:15 -08003093 return pci_register_driver(&es1371_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003094}
3095
3096static void __exit cleanup_es1371(void)
3097{
3098 printk(KERN_INFO PFX "unloading\n");
3099 pci_unregister_driver(&es1371_driver);
3100}
3101
3102module_init(init_es1371);
3103module_exit(cleanup_es1371);
3104
3105/* --------------------------------------------------------------------- */
3106
3107#ifndef MODULE
3108
3109/* format is: es1371=[spdif,[nomix,[amplifier]]] */
3110
3111static int __init es1371_setup(char *str)
3112{
3113 static unsigned __initdata nr_dev = 0;
3114
3115 if (nr_dev >= NR_DEVICE)
3116 return 0;
3117
3118 (void)
3119 ((get_option(&str, &spdif[nr_dev]) == 2)
3120 && (get_option(&str, &nomix[nr_dev]) == 2)
3121 && (get_option(&str, &amplifier[nr_dev])));
3122
3123 nr_dev++;
3124 return 1;
3125}
3126
3127__setup("es1371=", es1371_setup);
3128
3129#endif /* MODULE */