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gerrit-public.fairphone.software / kernel / msm-4.9 / 46f92d42ee37e10970e33891b7b61a342bd97aeb / . / drivers / mfd / wm8350-regmap.c
blob: 9efc64750fb68d8a323f2a7241d99cf47d781b0f [file] [log] [blame]
Mark Brown89b40122008-10-10 15:58:10 +0100[diff] [blame]1/*
2 * wm8350-regmap.c -- Wolfson Microelectronics WM8350 register map
3 *
4 * This file splits out the tables describing the defaults and access
5 * status of the WM8350 registers since they are rather large.
6 *
7 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/mfd/wm8350/core.h>
16
Mark Brown89b40122008-10-10 15:58:10 +0100[diff] [blame]17/*
18 * Access masks.
19 */
20
Mark Brown19d57ed2012-06-03 13:37:24 +0100[diff] [blame]21static const struct wm8350_reg_access {
22 u16 readable; /* Mask of readable bits */
23 u16 writable; /* Mask of writable bits */
24 u16 vol; /* Mask of volatile bits */
25} wm8350_reg_io_map[] = {
Mark Brown89b40122008-10-10 15:58:10 +0100[diff] [blame]26 /* read write volatile */
Mark Brown19d57ed2012-06-03 13:37:24 +0100[diff] [blame]27 { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Reset/ID */
28 { 0x7CFF, 0x0C00, 0x0000 }, /* R1 - ID */
Mark Brown422a6a72009-04-22 21:46:51 +0100[diff] [blame]29 { 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */
Mark Brown89b40122008-10-10 15:58:10 +0100[diff] [blame]30 { 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */
Mark Browna39a0212009-02-04 21:10:58 +0100[diff] [blame]31 { 0xFEF7, 0xFEF7, 0xF800 }, /* R4 - System Control 2 */
Mark Brown89b40122008-10-10 15:58:10 +0100[diff] [blame]32 { 0x80FF, 0x80FF, 0x8000 }, /* R5 - System Hibernate */
33 { 0xFB0E, 0xFB0E, 0x0000 }, /* R6 - Interface Control */
34 { 0x0000, 0x0000, 0x0000 }, /* R7 */
35 { 0xE537, 0xE537, 0xFFFF }, /* R8 - Power mgmt (1) */
36 { 0x0FF3, 0x0FF3, 0xFFFF }, /* R9 - Power mgmt (2) */
37 { 0x008F, 0x008F, 0xFFFF }, /* R10 - Power mgmt (3) */
38 { 0x6D3C, 0x6D3C, 0xFFFF }, /* R11 - Power mgmt (4) */
39 { 0x1F8F, 0x1F8F, 0xFFFF }, /* R12 - Power mgmt (5) */
40 { 0x8F3F, 0x8F3F, 0xFFFF }, /* R13 - Power mgmt (6) */
41 { 0x0003, 0x0003, 0xFFFF }, /* R14 - Power mgmt (7) */
42 { 0x0000, 0x0000, 0x0000 }, /* R15 */
43 { 0x7F7F, 0x7F7F, 0xFFFF }, /* R16 - RTC Seconds/Minutes */
44 { 0x073F, 0x073F, 0xFFFF }, /* R17 - RTC Hours/Day */
45 { 0x1F3F, 0x1F3F, 0xFFFF }, /* R18 - RTC Date/Month */
46 { 0x3FFF, 0x00FF, 0xFFFF }, /* R19 - RTC Year */
47 { 0x7F7F, 0x7F7F, 0x0000 }, /* R20 - Alarm Seconds/Minutes */
48 { 0x0F3F, 0x0F3F, 0x0000 }, /* R21 - Alarm Hours/Day */
49 { 0x1F3F, 0x1F3F, 0x0000 }, /* R22 - Alarm Date/Month */
50 { 0xEF7F, 0xEA7F, 0xFFFF }, /* R23 - RTC Time Control */
51 { 0x3BFF, 0x0000, 0xFFFF }, /* R24 - System Interrupts */
52 { 0xFEE7, 0x0000, 0xFFFF }, /* R25 - Interrupt Status 1 */
53 { 0x35FF, 0x0000, 0xFFFF }, /* R26 - Interrupt Status 2 */
54 { 0x0F3F, 0x0000, 0xFFFF }, /* R27 - Power Up Interrupt Status */
55 { 0x0F3F, 0x0000, 0xFFFF }, /* R28 - Under Voltage Interrupt status */
56 { 0x8000, 0x0000, 0xFFFF }, /* R29 - Over Current Interrupt status */
57 { 0x1FFF, 0x0000, 0xFFFF }, /* R30 - GPIO Interrupt Status */
58 { 0xEF7F, 0x0000, 0xFFFF }, /* R31 - Comparator Interrupt Status */
59 { 0x3FFF, 0x3FFF, 0x0000 }, /* R32 - System Interrupts Mask */
60 { 0xFEE7, 0xFEE7, 0x0000 }, /* R33 - Interrupt Status 1 Mask */
61 { 0xF5FF, 0xF5FF, 0x0000 }, /* R34 - Interrupt Status 2 Mask */
62 { 0x0F3F, 0x0F3F, 0x0000 }, /* R35 - Power Up Interrupt Status Mask */
63 { 0x0F3F, 0x0F3F, 0x0000 }, /* R36 - Under Voltage Int status Mask */
64 { 0x8000, 0x8000, 0x0000 }, /* R37 - Over Current Int status Mask */
65 { 0x1FFF, 0x1FFF, 0x0000 }, /* R38 - GPIO Interrupt Status Mask */
66 { 0xEF7F, 0xEF7F, 0x0000 }, /* R39 - Comparator IntStatus Mask */
67 { 0xC9F7, 0xC9F7, 0xFFFF }, /* R40 - Clock Control 1 */
68 { 0x8001, 0x8001, 0x0000 }, /* R41 - Clock Control 2 */
69 { 0xFFF7, 0xFFF7, 0xFFFF }, /* R42 - FLL Control 1 */
70 { 0xFBFF, 0xFBFF, 0x0000 }, /* R43 - FLL Control 2 */
71 { 0xFFFF, 0xFFFF, 0x0000 }, /* R44 - FLL Control 3 */
72 { 0x0033, 0x0033, 0x0000 }, /* R45 - FLL Control 4 */
73 { 0x0000, 0x0000, 0x0000 }, /* R46 */
74 { 0x0000, 0x0000, 0x0000 }, /* R47 */
75 { 0x3033, 0x3033, 0x0000 }, /* R48 - DAC Control */
76 { 0x0000, 0x0000, 0x0000 }, /* R49 */
77 { 0x81FF, 0x81FF, 0xFFFF }, /* R50 - DAC Digital Volume L */
78 { 0x81FF, 0x81FF, 0xFFFF }, /* R51 - DAC Digital Volume R */
79 { 0x0000, 0x0000, 0x0000 }, /* R52 */
80 { 0x0FFF, 0x0FFF, 0xFFFF }, /* R53 - DAC LR Rate */
81 { 0x0017, 0x0017, 0x0000 }, /* R54 - DAC Clock Control */
82 { 0x0000, 0x0000, 0x0000 }, /* R55 */
83 { 0x0000, 0x0000, 0x0000 }, /* R56 */
84 { 0x0000, 0x0000, 0x0000 }, /* R57 */
85 { 0x4000, 0x4000, 0x0000 }, /* R58 - DAC Mute */
86 { 0x7000, 0x7000, 0x0000 }, /* R59 - DAC Mute Volume */
87 { 0x3C00, 0x3C00, 0x0000 }, /* R60 - DAC Side */
88 { 0x0000, 0x0000, 0x0000 }, /* R61 */
89 { 0x0000, 0x0000, 0x0000 }, /* R62 */
90 { 0x0000, 0x0000, 0x0000 }, /* R63 */
91 { 0x8303, 0x8303, 0xFFFF }, /* R64 - ADC Control */
92 { 0x0000, 0x0000, 0x0000 }, /* R65 */
93 { 0x81FF, 0x81FF, 0xFFFF }, /* R66 - ADC Digital Volume L */
94 { 0x81FF, 0x81FF, 0xFFFF }, /* R67 - ADC Digital Volume R */
95 { 0x0FFF, 0x0FFF, 0x0000 }, /* R68 - ADC Divider */
96 { 0x0000, 0x0000, 0x0000 }, /* R69 */
97 { 0x0FFF, 0x0FFF, 0xFFFF }, /* R70 - ADC LR Rate */
98 { 0x0000, 0x0000, 0x0000 }, /* R71 */
99 { 0x0707, 0x0707, 0xFFFF }, /* R72 - Input Control */
100 { 0xC0C0, 0xC0C0, 0xFFFF }, /* R73 - IN3 Input Control */
101 { 0xC09F, 0xC09F, 0xFFFF }, /* R74 - Mic Bias Control */
102 { 0x0000, 0x0000, 0x0000 }, /* R75 */
103 { 0x0F15, 0x0F15, 0xFFFF }, /* R76 - Output Control */
104 { 0xC000, 0xC000, 0xFFFF }, /* R77 - Jack Detect */
105 { 0x03FF, 0x03FF, 0x0000 }, /* R78 - Anti Pop Control */
106 { 0x0000, 0x0000, 0x0000 }, /* R79 */
107 { 0xE1FC, 0xE1FC, 0x8000 }, /* R80 - Left Input Volume */
108 { 0xE1FC, 0xE1FC, 0x8000 }, /* R81 - Right Input Volume */
109 { 0x0000, 0x0000, 0x0000 }, /* R82 */
110 { 0x0000, 0x0000, 0x0000 }, /* R83 */
111 { 0x0000, 0x0000, 0x0000 }, /* R84 */
112 { 0x0000, 0x0000, 0x0000 }, /* R85 */
113 { 0x0000, 0x0000, 0x0000 }, /* R86 */
114 { 0x0000, 0x0000, 0x0000 }, /* R87 */
115 { 0x9807, 0x9807, 0xFFFF }, /* R88 - Left Mixer Control */
116 { 0x980B, 0x980B, 0xFFFF }, /* R89 - Right Mixer Control */
117 { 0x0000, 0x0000, 0x0000 }, /* R90 */
118 { 0x0000, 0x0000, 0x0000 }, /* R91 */
119 { 0x8909, 0x8909, 0xFFFF }, /* R92 - OUT3 Mixer Control */
120 { 0x9E07, 0x9E07, 0xFFFF }, /* R93 - OUT4 Mixer Control */
121 { 0x0000, 0x0000, 0x0000 }, /* R94 */
122 { 0x0000, 0x0000, 0x0000 }, /* R95 */
123 { 0x0EEE, 0x0EEE, 0x0000 }, /* R96 - Output Left Mixer Volume */
124 { 0xE0EE, 0xE0EE, 0x0000 }, /* R97 - Output Right Mixer Volume */
125 { 0x0E0F, 0x0E0F, 0x0000 }, /* R98 - Input Mixer Volume L */
126 { 0xE0E1, 0xE0E1, 0x0000 }, /* R99 - Input Mixer Volume R */
127 { 0x800E, 0x800E, 0x0000 }, /* R100 - Input Mixer Volume */
128 { 0x0000, 0x0000, 0x0000 }, /* R101 */
129 { 0x0000, 0x0000, 0x0000 }, /* R102 */
130 { 0x0000, 0x0000, 0x0000 }, /* R103 */
131 { 0xE1FC, 0xE1FC, 0xFFFF }, /* R104 - LOUT1 Volume */
132 { 0xE1FC, 0xE1FC, 0xFFFF }, /* R105 - ROUT1 Volume */
133 { 0xE1FC, 0xE1FC, 0xFFFF }, /* R106 - LOUT2 Volume */
134 { 0xE7FC, 0xE7FC, 0xFFFF }, /* R107 - ROUT2 Volume */
135 { 0x0000, 0x0000, 0x0000 }, /* R108 */
136 { 0x0000, 0x0000, 0x0000 }, /* R109 */
137 { 0x0000, 0x0000, 0x0000 }, /* R110 */
138 { 0x80E0, 0x80E0, 0xFFFF }, /* R111 - BEEP Volume */
139 { 0xBF00, 0xBF00, 0x0000 }, /* R112 - AI Formating */
140 { 0x00F1, 0x00F1, 0x0000 }, /* R113 - ADC DAC COMP */
141 { 0x00F8, 0x00F8, 0x0000 }, /* R114 - AI ADC Control */
142 { 0x40FB, 0x40FB, 0x0000 }, /* R115 - AI DAC Control */
143 { 0x7C30, 0x7C30, 0x0000 }, /* R116 - AIF Test */
144 { 0x0000, 0x0000, 0x0000 }, /* R117 */
145 { 0x0000, 0x0000, 0x0000 }, /* R118 */
146 { 0x0000, 0x0000, 0x0000 }, /* R119 */
147 { 0x0000, 0x0000, 0x0000 }, /* R120 */
148 { 0x0000, 0x0000, 0x0000 }, /* R121 */
149 { 0x0000, 0x0000, 0x0000 }, /* R122 */
150 { 0x0000, 0x0000, 0x0000 }, /* R123 */
151 { 0x0000, 0x0000, 0x0000 }, /* R124 */
152 { 0x0000, 0x0000, 0x0000 }, /* R125 */
153 { 0x0000, 0x0000, 0x0000 }, /* R126 */
154 { 0x0000, 0x0000, 0x0000 }, /* R127 */
155 { 0x1FFF, 0x1FFF, 0x0000 }, /* R128 - GPIO Debounce */
156 { 0x1FFF, 0x1FFF, 0x0000 }, /* R129 - GPIO Pin pull up Control */
157 { 0x1FFF, 0x1FFF, 0x0000 }, /* R130 - GPIO Pull down Control */
158 { 0x1FFF, 0x1FFF, 0x0000 }, /* R131 - GPIO Interrupt Mode */
159 { 0x0000, 0x0000, 0x0000 }, /* R132 */
160 { 0x00C0, 0x00C0, 0x0000 }, /* R133 - GPIO Control */
161 { 0x1FFF, 0x1FFF, 0x0000 }, /* R134 - GPIO Configuration (i/o) */
162 { 0x1FFF, 0x1FFF, 0x0000 }, /* R135 - GPIO Pin Polarity / Type */
163 { 0x0000, 0x0000, 0x0000 }, /* R136 */
164 { 0x0000, 0x0000, 0x0000 }, /* R137 */
165 { 0x0000, 0x0000, 0x0000 }, /* R138 */
166 { 0x0000, 0x0000, 0x0000 }, /* R139 */
167 { 0xFFFF, 0xFFFF, 0x0000 }, /* R140 - GPIO Function Select 1 */
168 { 0xFFFF, 0xFFFF, 0x0000 }, /* R141 - GPIO Function Select 2 */
169 { 0xFFFF, 0xFFFF, 0x0000 }, /* R142 - GPIO Function Select 3 */
170 { 0x000F, 0x000F, 0x0000 }, /* R143 - GPIO Function Select 4 */
171 { 0xF0FF, 0xF0FF, 0xA000 }, /* R144 - Digitiser Control (1) */
172 { 0x3707, 0x3707, 0x0000 }, /* R145 - Digitiser Control (2) */
173 { 0x0000, 0x0000, 0x0000 }, /* R146 */
174 { 0x0000, 0x0000, 0x0000 }, /* R147 */
175 { 0x0000, 0x0000, 0x0000 }, /* R148 */
176 { 0x0000, 0x0000, 0x0000 }, /* R149 */
177 { 0x0000, 0x0000, 0x0000 }, /* R150 */
178 { 0x0000, 0x0000, 0x0000 }, /* R151 */
179 { 0x7FFF, 0x7000, 0xFFFF }, /* R152 - AUX1 Readback */
180 { 0x7FFF, 0x7000, 0xFFFF }, /* R153 - AUX2 Readback */
181 { 0x7FFF, 0x7000, 0xFFFF }, /* R154 - AUX3 Readback */
182 { 0x7FFF, 0x7000, 0xFFFF }, /* R155 - AUX4 Readback */
183 { 0x0FFF, 0x0000, 0xFFFF }, /* R156 - USB Voltage Readback */
184 { 0x0FFF, 0x0000, 0xFFFF }, /* R157 - LINE Voltage Readback */
185 { 0x0FFF, 0x0000, 0xFFFF }, /* R158 - BATT Voltage Readback */
186 { 0x0FFF, 0x0000, 0xFFFF }, /* R159 - Chip Temp Readback */
187 { 0x0000, 0x0000, 0x0000 }, /* R160 */
188 { 0x0000, 0x0000, 0x0000 }, /* R161 */
189 { 0x0000, 0x0000, 0x0000 }, /* R162 */
190 { 0x000F, 0x000F, 0x0000 }, /* R163 - Generic Comparator Control */
191 { 0xFFFF, 0xFFFF, 0x0000 }, /* R164 - Generic comparator 1 */
192 { 0xFFFF, 0xFFFF, 0x0000 }, /* R165 - Generic comparator 2 */
193 { 0xFFFF, 0xFFFF, 0x0000 }, /* R166 - Generic comparator 3 */
194 { 0xFFFF, 0xFFFF, 0x0000 }, /* R167 - Generic comparator 4 */
195 { 0xBFFF, 0xBFFF, 0x8000 }, /* R168 - Battery Charger Control 1 */
196 { 0xFFFF, 0x4FFF, 0xB000 }, /* R169 - Battery Charger Control 2 */
197 { 0x007F, 0x007F, 0x0000 }, /* R170 - Battery Charger Control 3 */
198 { 0x0000, 0x0000, 0x0000 }, /* R171 */
199 { 0x903F, 0x903F, 0xFFFF }, /* R172 - Current Sink Driver A */
200 { 0xE333, 0xE333, 0xFFFF }, /* R173 - CSA Flash control */
201 { 0x903F, 0x903F, 0xFFFF }, /* R174 - Current Sink Driver B */
202 { 0xE333, 0xE333, 0xFFFF }, /* R175 - CSB Flash control */
203 { 0x8F3F, 0x8F3F, 0xFFFF }, /* R176 - DCDC/LDO requested */
204 { 0x332D, 0x332D, 0x0000 }, /* R177 - DCDC Active options */
205 { 0x002D, 0x002D, 0x0000 }, /* R178 - DCDC Sleep options */
206 { 0x5177, 0x5177, 0x8000 }, /* R179 - Power-check comparator */
207 { 0x047F, 0x047F, 0x0000 }, /* R180 - DCDC1 Control */
208 { 0xFFC0, 0xFFC0, 0x0000 }, /* R181 - DCDC1 Timeouts */
209 { 0x737F, 0x737F, 0x0000 }, /* R182 - DCDC1 Low Power */
210 { 0x535B, 0x535B, 0x0000 }, /* R183 - DCDC2 Control */
211 { 0xFFC0, 0xFFC0, 0x0000 }, /* R184 - DCDC2 Timeouts */
212 { 0x0000, 0x0000, 0x0000 }, /* R185 */
213 { 0x047F, 0x047F, 0x0000 }, /* R186 - DCDC3 Control */
214 { 0xFFC0, 0xFFC0, 0x0000 }, /* R187 - DCDC3 Timeouts */
215 { 0x737F, 0x737F, 0x0000 }, /* R188 - DCDC3 Low Power */
216 { 0x047F, 0x047F, 0x0000 }, /* R189 - DCDC4 Control */
217 { 0xFFC0, 0xFFC0, 0x0000 }, /* R190 - DCDC4 Timeouts */
218 { 0x737F, 0x737F, 0x0000 }, /* R191 - DCDC4 Low Power */
219 { 0x535B, 0x535B, 0x0000 }, /* R192 - DCDC5 Control */
220 { 0xFFC0, 0xFFC0, 0x0000 }, /* R193 - DCDC5 Timeouts */
221 { 0x0000, 0x0000, 0x0000 }, /* R194 */
222 { 0x047F, 0x047F, 0x0000 }, /* R195 - DCDC6 Control */
223 { 0xFFC0, 0xFFC0, 0x0000 }, /* R196 - DCDC6 Timeouts */
224 { 0x737F, 0x737F, 0x0000 }, /* R197 - DCDC6 Low Power */
225 { 0x0000, 0x0000, 0x0000 }, /* R198 */
226 { 0xFFD3, 0xFFD3, 0x0000 }, /* R199 - Limit Switch Control */
227 { 0x441F, 0x441F, 0x0000 }, /* R200 - LDO1 Control */
228 { 0xFFC0, 0xFFC0, 0x0000 }, /* R201 - LDO1 Timeouts */
229 { 0x331F, 0x331F, 0x0000 }, /* R202 - LDO1 Low Power */
230 { 0x441F, 0x441F, 0x0000 }, /* R203 - LDO2 Control */
231 { 0xFFC0, 0xFFC0, 0x0000 }, /* R204 - LDO2 Timeouts */
232 { 0x331F, 0x331F, 0x0000 }, /* R205 - LDO2 Low Power */
233 { 0x441F, 0x441F, 0x0000 }, /* R206 - LDO3 Control */
234 { 0xFFC0, 0xFFC0, 0x0000 }, /* R207 - LDO3 Timeouts */
235 { 0x331F, 0x331F, 0x0000 }, /* R208 - LDO3 Low Power */
236 { 0x441F, 0x441F, 0x0000 }, /* R209 - LDO4 Control */
237 { 0xFFC0, 0xFFC0, 0x0000 }, /* R210 - LDO4 Timeouts */
238 { 0x331F, 0x331F, 0x0000 }, /* R211 - LDO4 Low Power */
239 { 0x0000, 0x0000, 0x0000 }, /* R212 */
240 { 0x0000, 0x0000, 0x0000 }, /* R213 */
241 { 0x0000, 0x0000, 0x0000 }, /* R214 */
242 { 0x8F3F, 0x8F3F, 0x0000 }, /* R215 - VCC_FAULT Masks */
243 { 0xFF3F, 0xE03F, 0x0000 }, /* R216 - Main Bandgap Control */
244 { 0xEF2F, 0xE02F, 0x0000 }, /* R217 - OSC Control */
245 { 0xF3FF, 0xB3FF, 0xc000 }, /* R218 - RTC Tick Control */
Mark Brown6cd99b72008-10-24 19:25:27 +0200[diff] [blame]246 { 0xFFFF, 0xFFFF, 0x0000 }, /* R219 - Security */
Mark Brown89b40122008-10-10 15:58:10 +0100[diff] [blame]247 { 0x09FF, 0x01FF, 0x0000 }, /* R220 - RAM BIST 1 */
248 { 0x0000, 0x0000, 0x0000 }, /* R221 */
249 { 0xFFFF, 0xFFFF, 0xFFFF }, /* R222 */
250 { 0xFFFF, 0xFFFF, 0xFFFF }, /* R223 */
251 { 0x0000, 0x0000, 0x0000 }, /* R224 */
252 { 0x8F3F, 0x0000, 0xFFFF }, /* R225 - DCDC/LDO status */
Mark Brown4008e872008-11-30 22:45:14 +0100[diff] [blame]253 { 0x0000, 0x0000, 0xFFFF }, /* R226 - Charger status */
Mark Brown489bd342009-04-13 14:05:02 +0100[diff] [blame]254 { 0x34FE, 0x0000, 0xFFFF }, /* R227 */
Mark Brown89b40122008-10-10 15:58:10 +0100[diff] [blame]255 { 0x0000, 0x0000, 0x0000 }, /* R228 */
256 { 0x0000, 0x0000, 0x0000 }, /* R229 */
257 { 0xFFFF, 0x1FFF, 0xFFFF }, /* R230 - GPIO Pin Status */
258 { 0xFFFF, 0x1FFF, 0xFFFF }, /* R231 */
259 { 0xFFFF, 0x1FFF, 0xFFFF }, /* R232 */
260 { 0xFFFF, 0x1FFF, 0xFFFF }, /* R233 */
261 { 0x0000, 0x0000, 0x0000 }, /* R234 */
262 { 0x0000, 0x0000, 0x0000 }, /* R235 */
263 { 0x0000, 0x0000, 0x0000 }, /* R236 */
264 { 0x0000, 0x0000, 0x0000 }, /* R237 */
265 { 0x0000, 0x0000, 0x0000 }, /* R238 */
266 { 0x0000, 0x0000, 0x0000 }, /* R239 */
267 { 0x0000, 0x0000, 0x0000 }, /* R240 */
268 { 0x0000, 0x0000, 0x0000 }, /* R241 */
269 { 0x0000, 0x0000, 0x0000 }, /* R242 */
270 { 0x0000, 0x0000, 0x0000 }, /* R243 */
271 { 0x0000, 0x0000, 0x0000 }, /* R244 */
272 { 0x0000, 0x0000, 0x0000 }, /* R245 */
273 { 0x0000, 0x0000, 0x0000 }, /* R246 */
274 { 0x0000, 0x0000, 0x0000 }, /* R247 */
275 { 0xFFFF, 0x0010, 0xFFFF }, /* R248 */
276 { 0x0000, 0x0000, 0x0000 }, /* R249 */
277 { 0xFFFF, 0x0010, 0xFFFF }, /* R250 */
278 { 0xFFFF, 0x0010, 0xFFFF }, /* R251 */
279 { 0x0000, 0x0000, 0x0000 }, /* R252 */
280 { 0xFFFF, 0x0010, 0xFFFF }, /* R253 */
281 { 0x0000, 0x0000, 0x0000 }, /* R254 */
282 { 0x0000, 0x0000, 0x0000 }, /* R255 */
283};
Mark Brown52b461b2012-06-03 13:37:22 +0100[diff] [blame]284
285static bool wm8350_readable(struct device *dev, unsigned int reg)
286{
287 return wm8350_reg_io_map[reg].readable;
288}
289
290static bool wm8350_writeable(struct device *dev, unsigned int reg)
291{
292 struct wm8350 *wm8350 = dev_get_drvdata(dev);
293
294 if (!wm8350->unlocked) {
295 if ((reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
296 reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
297 (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
298 reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
299 return false;
300 }
301
302 return wm8350_reg_io_map[reg].writable;
303}
304
305static bool wm8350_volatile(struct device *dev, unsigned int reg)
306{
307 return wm8350_reg_io_map[reg].vol;
308}
309
310static bool wm8350_precious(struct device *dev, unsigned int reg)
311{
312 switch (reg) {
313 case WM8350_SYSTEM_INTERRUPTS:
314 case WM8350_INT_STATUS_1:
315 case WM8350_INT_STATUS_2:
316 case WM8350_POWER_UP_INT_STATUS:
317 case WM8350_UNDER_VOLTAGE_INT_STATUS:
318 case WM8350_OVER_CURRENT_INT_STATUS:
319 case WM8350_GPIO_INT_STATUS:
320 case WM8350_COMPARATOR_INT_STATUS:
321 return true;
322
323 default:
324 return false;
325 }
326}
327
328const struct regmap_config wm8350_regmap = {
329 .reg_bits = 8,
330 .val_bits = 16,
331
332 .cache_type = REGCACHE_RBTREE,
333
334 .max_register = WM8350_MAX_REGISTER,
335 .readable_reg = wm8350_readable,
336 .writeable_reg = wm8350_writeable,
337 .volatile_reg = wm8350_volatile,
338 .precious_reg = wm8350_precious,
339};