Linus Walleij | dfc8a11 | 2016-02-23 16:51:35 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016 Linaro Ltd |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 5 | * of this software and associated documentation files (the "Software"), to deal |
| 6 | * in the Software without restriction, including without limitation the rights |
| 7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 8 | * copies of the Software, and to permit persons to whom the Software is |
| 9 | * furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 20 | * THE SOFTWARE. |
| 21 | */ |
| 22 | |
| 23 | /dts-v1/; |
| 24 | #include "arm-realview-pbx.dtsi" |
| 25 | |
| 26 | / { |
| 27 | /* |
| 28 | * This is the RealView Platform Baseboard Explore for Cortex-A9 |
| 29 | * (HBI0182 + HBI0183) as described in ARM DUI 0440B |
| 30 | */ |
| 31 | model = "ARM RealView Platform Baseboard Explore for Cortex-A9"; |
| 32 | arm,hbi = <0x182>; |
| 33 | |
| 34 | cpus { |
| 35 | #address-cells = <1>; |
| 36 | #size-cells = <0>; |
| 37 | enable-method = "arm,realview-smp"; |
| 38 | |
| 39 | cpu-map { |
| 40 | cluster0 { |
| 41 | core0 { |
| 42 | cpu = <&CPU0>; |
| 43 | }; |
| 44 | core1 { |
| 45 | cpu = <&CPU1>; |
| 46 | }; |
| 47 | }; |
| 48 | }; |
| 49 | CPU0: cpu@0 { |
| 50 | device_type = "cpu"; |
| 51 | compatible = "arm,cortex-a9"; |
| 52 | reg = <0x0>; |
| 53 | next-level-cache = <&L2>; |
| 54 | }; |
| 55 | CPU1: cpu@1 { |
| 56 | device_type = "cpu"; |
| 57 | compatible = "arm,cortex-a9"; |
| 58 | reg = <0x1>; |
| 59 | next-level-cache = <&L2>; |
| 60 | }; |
| 61 | }; |
| 62 | |
| 63 | L2: l2-cache { |
| 64 | compatible = "arm,pl310-cache"; |
| 65 | reg = <0x1f002000 0x1000>; |
| 66 | cache-unified; |
| 67 | cache-level = <2>; |
| 68 | /* |
| 69 | * Override default cache size, sets and |
| 70 | * associativity as these may be erroneously set |
| 71 | * up by boot loader(s). |
| 72 | */ |
| 73 | cache-size = <1048576>; // 1MB |
| 74 | cache-sets = <4096>; |
| 75 | cache-line-size = <32>; |
| 76 | arm,parity-disable; |
| 77 | arm,tag-latency = <1>; |
| 78 | arm,data-latency = <1 1>; |
| 79 | arm,dirty-latency = <1>; |
| 80 | }; |
| 81 | |
| 82 | scu: scu@1f000000 { |
| 83 | compatible = "arm,cortex-a9-scu"; |
| 84 | reg = <0x1f000000 0x100>; |
| 85 | }; |
| 86 | |
| 87 | twd_timer: timer@1f000600 { |
| 88 | compatible = "arm,cortex-a9-twd-timer"; |
| 89 | reg = <0x1f000600 0x20>; |
| 90 | interrupt-parent = <&intc>; |
| 91 | interrupts = <1 13 0xf04>; |
| 92 | }; |
| 93 | |
| 94 | twd_wdog: watchdog@1f000620 { |
| 95 | compatible = "arm,cortex-a9-twd-wdt"; |
| 96 | reg = <0x1f000620 0x20>; |
| 97 | interrupt-parent = <&intc>; |
| 98 | interrupts = <1 14 0xf04>; |
| 99 | }; |
| 100 | |
| 101 | pmu: pmu@0 { |
| 102 | compatible = "arm,cortex-a9-pmu"; |
| 103 | interrupt-parent = <&intc>; |
| 104 | interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>, |
| 105 | <0 45 IRQ_TYPE_LEVEL_HIGH>; |
| 106 | interrupt-affinity = <&CPU0>, <&CPU1>; |
| 107 | }; |
| 108 | |
| 109 | /* Primary GIC PL390 interrupt controller in the test chip */ |
| 110 | intc: interrupt-controller@1f000000 { |
| 111 | compatible = "arm,cortex-a9-gic"; |
| 112 | #interrupt-cells = <3>; |
| 113 | #address-cells = <1>; |
| 114 | interrupt-controller; |
| 115 | reg = <0x1f001000 0x1000>, |
| 116 | <0x1f000100 0x100>; |
| 117 | }; |
| 118 | }; |
| 119 | |
| 120 | ðernet { |
| 121 | interrupt-parent = <&intc>; |
| 122 | interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; |
| 123 | }; |
| 124 | |
| 125 | &usb { |
| 126 | interrupt-parent = <&intc>; |
| 127 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
| 128 | }; |
| 129 | |
| 130 | &serial0 { |
| 131 | interrupt-parent = <&intc>; |
| 132 | interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; |
| 133 | }; |
| 134 | |
| 135 | &serial1 { |
| 136 | interrupt-parent = <&intc>; |
| 137 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; |
| 138 | }; |
| 139 | |
| 140 | &serial2 { |
| 141 | interrupt-parent = <&intc>; |
| 142 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
| 143 | }; |
| 144 | |
| 145 | &serial3 { |
| 146 | interrupt-parent = <&intc>; |
| 147 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; |
| 148 | }; |
| 149 | |
| 150 | &ssp { |
| 151 | interrupt-parent = <&intc>; |
| 152 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
| 153 | }; |
| 154 | |
| 155 | &wdog0 { |
| 156 | interrupt-parent = <&intc>; |
| 157 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; |
| 158 | }; |
| 159 | |
| 160 | &wdog1 { |
| 161 | interrupt-parent = <&intc>; |
| 162 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
| 163 | }; |
| 164 | |
| 165 | &timer01 { |
| 166 | interrupt-parent = <&intc>; |
| 167 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
| 168 | }; |
| 169 | |
| 170 | &timer23 { |
| 171 | interrupt-parent = <&intc>; |
| 172 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
| 173 | }; |
| 174 | |
| 175 | &gpio0 { |
| 176 | interrupt-parent = <&intc>; |
| 177 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
| 178 | }; |
| 179 | |
| 180 | &gpio1 { |
| 181 | interrupt-parent = <&intc>; |
| 182 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
| 183 | }; |
| 184 | |
| 185 | &gpio2 { |
| 186 | interrupt-parent = <&intc>; |
| 187 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
| 188 | }; |
| 189 | |
| 190 | &rtc { |
| 191 | interrupt-parent = <&intc>; |
| 192 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; |
| 193 | }; |
| 194 | |
| 195 | &timer45 { |
| 196 | interrupt-parent = <&intc>; |
| 197 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
| 198 | }; |
| 199 | |
| 200 | &timer67 { |
| 201 | interrupt-parent = <&intc>; |
| 202 | interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
| 203 | }; |
| 204 | |
| 205 | &aaci { |
| 206 | interrupt-parent = <&intc>; |
| 207 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; |
| 208 | }; |
| 209 | |
| 210 | &mmc { |
| 211 | interrupt-parent = <&intc>; |
| 212 | interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, |
| 213 | <0 18 IRQ_TYPE_LEVEL_HIGH>; |
| 214 | }; |
| 215 | |
| 216 | &kmi0 { |
| 217 | interrupt-parent = <&intc>; |
| 218 | interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; |
| 219 | }; |
| 220 | |
| 221 | &kmi1 { |
| 222 | interrupt-parent = <&intc>; |
| 223 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; |
| 224 | }; |
| 225 | |
| 226 | &clcd { |
| 227 | interrupt-parent = <&intc>; |
| 228 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
| 229 | }; |