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Nicolas Ferre49fe2ba2011-10-10 18:29:24 +02001/*
2 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +080010#include "at91sam9g45.dtsi"
Alexandre Belloni66844c72014-03-19 00:15:41 +010011#include <dt-bindings/pwm/pwm.h>
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020012
13/ {
14 model = "Atmel AT91SAM9M10G45-EK";
15 compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
16
17 chosen {
Alexandre Belloniaa070462015-06-03 14:24:10 +020018 bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2";
19 stdout-path = "serial0:115200n8";
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020020 };
21
Ludovic Desrochesdcce6ce2012-04-02 20:44:20 +020022 memory {
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020023 reg = <0x70000000 0x4000000>;
24 };
25
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +080026 clocks {
Alexandre Belloni4c67a132014-06-13 20:01:51 +020027 slow_xtal {
28 clock-frequency = <32768>;
29 };
30
31 main_xtal {
32 clock-frequency = <12000000>;
33 };
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +080034 };
35
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020036 ahb {
37 apb {
38 dbgu: serial@ffffee00 {
39 status = "okay";
40 };
41
42 usart1: serial@fff90000 {
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +080043 pinctrl-0 =
44 <&pinctrl_usart1
45 &pinctrl_usart1_rts
46 &pinctrl_usart1_cts>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020047 status = "okay";
48 };
Nicolas Ferre0d4f99d2011-12-05 18:03:05 +010049
50 macb0: ethernet@fffbc000 {
51 phy-mode = "rmii";
52 status = "okay";
53 };
Ludovic Desrochesfbc18712012-09-12 08:42:17 +020054
55 i2c0: i2c@fff84000 {
56 status = "okay";
Josh Wu917cdc52015-06-16 18:08:34 +080057 ov2640: camera@30 {
58 compatible = "ovti,ov2640";
59 reg = <0x30>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
62 resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>;
63 pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>;
64 clocks = <&pck1>;
65 clock-names = "xvclk";
66 assigned-clocks = <&pck1>;
67 assigned-clock-rates = <25000000>;
68
69 port {
70 ov2640_0: endpoint {
71 remote-endpoint = <&isi_0>;
72 bus-width = <8>;
73 };
74 };
75 };
Ludovic Desrochesfbc18712012-09-12 08:42:17 +020076 };
77
78 i2c1: i2c@fff88000 {
79 status = "okay";
80 };
Ludovic Desroches4134a452012-11-19 12:24:02 +010081
Wenyou Yangc77bcef2013-05-31 11:11:33 +080082 watchdog@fffffd40 {
83 status = "okay";
84 };
85
Ludovic Desroches4134a452012-11-19 12:24:02 +010086 mmc0: mmc@fff80000 {
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +080087 pinctrl-0 = <
88 &pinctrl_board_mmc0
89 &pinctrl_mmc0_slot0_clk_cmd_dat0
90 &pinctrl_mmc0_slot0_dat1_3>;
Ludovic Desroches4134a452012-11-19 12:24:02 +010091 status = "okay";
92 slot@0 {
93 reg = <0>;
94 bus-width = <4>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +080095 cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>;
Ludovic Desroches4134a452012-11-19 12:24:02 +010096 };
97 };
98
99 mmc1: mmc@fffd0000 {
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800100 pinctrl-0 = <
101 &pinctrl_board_mmc1
102 &pinctrl_mmc1_slot0_clk_cmd_dat0
103 &pinctrl_mmc1_slot0_dat1_3>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100104 status = "okay";
105 slot@0 {
106 reg = <0>;
107 bus-width = <4>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800108 cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>;
109 wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100110 };
111 };
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800112
113 pinctrl@fffff200 {
Josh Wu917cdc52015-06-16 18:08:34 +0800114 camera_sensor {
115 pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 {
116 atmel,pins =
117 <AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;
118 };
119
120 pinctrl_sensor_reset: sensor_reset-0 {
121 atmel,pins =
122 <AT91_PIOD 12 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
123 };
124
125 pinctrl_sensor_power: sensor_power-0 {
126 atmel,pins =
127 <AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
128 };
129 };
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800130 mmc0 {
131 pinctrl_board_mmc0: mmc0-board {
132 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800133 <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD10 gpio CD pin pull up and deglitch */
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800134 };
135 };
136
137 mmc1 {
138 pinctrl_board_mmc1: mmc1-board {
139 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800140 <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PD11 gpio CD pin pull up and deglitch */
141 AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800142 };
143 };
Bo Sheneed97292013-12-19 11:59:18 +0800144
145 pwm0 {
146 pinctrl_pwm_leds: pwm-led {
147 atmel,pins =
148 <AT91_PIOD 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD0 periph B */
149 AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PD31 periph B */
150 };
151 };
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800152 };
Richard Genoudb6811e92013-04-03 14:03:05 +0800153
154 spi0: spi@fffa4000{
155 status = "okay";
156 cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
157 mtd_dataflash@0 {
158 compatible = "atmel,at45", "atmel,dataflash";
159 spi-max-frequency = <13000000>;
160 reg = <0>;
161 };
162 };
Jean-Christophe PLAGNIOL-VILLARD24ce10e2013-05-03 20:56:01 +0800163
164 usb2: gadget@fff78000 {
165 atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
166 status = "okay";
167 };
Bo Sheneed97292013-12-19 11:59:18 +0800168
Alexandre Bellonie10a57e2014-03-19 00:15:40 +0100169 adc0: adc@fffb0000 {
170 pinctrl-names = "default";
171 pinctrl-0 = <
172 &pinctrl_adc0_ad0
173 &pinctrl_adc0_ad1
174 &pinctrl_adc0_ad2
175 &pinctrl_adc0_ad3
176 &pinctrl_adc0_ad4
177 &pinctrl_adc0_ad5
178 &pinctrl_adc0_ad6
179 &pinctrl_adc0_ad7>;
180 atmel,adc-ts-wires = <4>;
181 status = "okay";
182 };
183
Josh Wu917cdc52015-06-16 18:08:34 +0800184 isi@fffb4000 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_isi_data_0_7>;
187 status = "okay";
188 port {
189 isi_0: endpoint {
190 remote-endpoint = <&ov2640_0>;
191 bus-width = <8>;
Josh Wubc81beb2015-09-18 19:28:22 +0800192 vsync-active = <1>;
193 hsync-active = <1>;
Josh Wu917cdc52015-06-16 18:08:34 +0800194 };
195 };
196 };
197
Bo Sheneed97292013-12-19 11:59:18 +0800198 pwm0: pwm@fffb8000 {
199 status = "okay";
200
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_pwm_leds>;
203 };
Erik van Luijk4dd79332014-09-02 12:52:12 +0200204
Boris Brezillon199ec7a2014-11-14 11:08:52 +0100205 rtc@fffffd20 {
206 atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
207 status = "okay";
208 };
209
210 gpbr: syscon@fffffd60 {
211 status = "okay";
212 };
213
Erik van Luijk4dd79332014-09-02 12:52:12 +0200214 rtc@fffffdb0 {
215 status = "okay";
216 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200217 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800218
Jean-Christophe PLAGNIOL-VILLARDf4390a72013-03-29 02:11:22 +0800219 fb0: fb@0x00500000 {
220 display = <&display0>;
221 status = "okay";
222
223 display0: display {
224 bits-per-pixel = <32>;
225 atmel,lcdcon-backlight;
226 atmel,dmacon = <0x1>;
227 atmel,lcdcon2 = <0x80008002>;
228 atmel,guard-time = <9>;
229 atmel,lcd-wiring-mode = "RGB";
230
231 display-timings {
232 native-mode = <&timing0>;
233 timing0: timing0 {
234 clock-frequency = <9000000>;
235 hactive = <480>;
236 vactive = <272>;
237 hback-porch = <1>;
238 hfront-porch = <1>;
239 vback-porch = <40>;
240 vfront-porch = <1>;
241 hsync-len = <45>;
242 vsync-len = <1>;
243 };
244 };
245 };
246 };
247
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800248 nand0: nand@40000000 {
249 nand-bus-width = <8>;
250 nand-ecc-mode = "soft";
251 nand-on-flash-bbt;
252 status = "okay";
253
254 boot@0 {
255 label = "bootstrap/uboot/kernel";
256 reg = <0x0 0x400000>;
257 };
258
259 rootfs@400000 {
260 label = "rootfs";
261 reg = <0x400000 0x3C00000>;
262 };
263
264 data@4000000 {
265 label = "data";
266 reg = <0x4000000 0xC000000>;
267 };
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800268 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800269
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800270 usb0: ohci@00700000 {
271 status = "okay";
272 num-ports = <2>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800273 atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW
274 &pioD 3 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800275 };
Jean-Christophe PLAGNIOL-VILLARD62c55532011-11-22 12:11:13 +0800276
277 usb1: ehci@00800000 {
278 status = "okay";
279 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200280 };
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800281
282 leds {
283 compatible = "gpio-leds";
284
285 d8 {
286 label = "d8";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800287 gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800288 linux,default-trigger = "heartbeat";
289 };
Bo Sheneed97292013-12-19 11:59:18 +0800290 };
291
292 pwmleds {
293 compatible = "pwm-leds";
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800294
295 d6 {
296 label = "d6";
Alexandre Belloni66844c72014-03-19 00:15:41 +0100297 pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>;
Bo Sheneed97292013-12-19 11:59:18 +0800298 max-brightness = <255>;
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800299 linux,default-trigger = "nand-disk";
300 };
301
302 d7 {
303 label = "d7";
Alexandre Belloni66844c72014-03-19 00:15:41 +0100304 pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>;
Bo Sheneed97292013-12-19 11:59:18 +0800305 max-brightness = <255>;
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800306 linux,default-trigger = "mmc0";
307 };
308 };
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800309
310 gpio_keys {
311 compatible = "gpio-keys";
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800312
313 left_click {
314 label = "left_click";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800315 gpios = <&pioB 6 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800316 linux,code = <272>;
Sudeep Holla67ae8b92015-10-21 11:10:07 +0100317 wakeup-source;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800318 };
319
320 right_click {
321 label = "right_click";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800322 gpios = <&pioB 7 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800323 linux,code = <273>;
Sudeep Holla67ae8b92015-10-21 11:10:07 +0100324 wakeup-source;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800325 };
326
327 left {
328 label = "Joystick Left";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800329 gpios = <&pioB 14 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800330 linux,code = <105>;
331 };
332
333 right {
334 label = "Joystick Right";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800335 gpios = <&pioB 15 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800336 linux,code = <106>;
337 };
338
339 up {
340 label = "Joystick Up";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800341 gpios = <&pioB 16 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800342 linux,code = <103>;
343 };
344
345 down {
346 label = "Joystick Down";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800347 gpios = <&pioB 17 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800348 linux,code = <108>;
349 };
350
351 enter {
352 label = "Joystick Press";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800353 gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800354 linux,code = <28>;
355 };
356 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200357};