Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 DENX Software Engineering GmbH |
| 3 | * Heiko Schocher <hs@denx.de> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2 of the License, or (at your |
| 8 | * option) any later version. |
| 9 | */ |
Philip Avinash | a2bcd77 | 2013-06-14 15:15:53 +0530 | [diff] [blame] | 10 | #include "skeleton.dtsi" |
KV Sujith | 2e38b94 | 2013-11-21 23:45:30 +0530 | [diff] [blame] | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 12 | |
| 13 | / { |
| 14 | arm { |
| 15 | #address-cells = <1>; |
| 16 | #size-cells = <1>; |
| 17 | ranges; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 18 | intc: interrupt-controller@fffee000 { |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 19 | compatible = "ti,cp-intc"; |
| 20 | interrupt-controller; |
| 21 | #interrupt-cells = <1>; |
David Lechner | c6d3b5d | 2016-04-16 12:00:20 -0500 | [diff] [blame] | 22 | ti,intc-size = <101>; |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 23 | reg = <0xfffee000 0x2000>; |
| 24 | }; |
| 25 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 26 | soc@1c00000 { |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 27 | compatible = "simple-bus"; |
| 28 | model = "da850"; |
| 29 | #address-cells = <1>; |
| 30 | #size-cells = <1>; |
| 31 | ranges = <0x0 0x01c00000 0x400000>; |
Lad, Prabhakar | c57ff58 | 2013-01-25 16:48:44 +0530 | [diff] [blame] | 32 | interrupt-parent = <&intc>; |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 33 | |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 34 | pmx_core: pinmux@14120 { |
Kumar, Anil | 1faaba3 | 2013-01-16 14:37:39 +0530 | [diff] [blame] | 35 | compatible = "pinctrl-single"; |
| 36 | reg = <0x14120 0x50>; |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <0>; |
| 39 | pinctrl-single,bit-per-mux; |
| 40 | pinctrl-single,register-width = <32>; |
Manjunathappa, Prakash | 055cb2a9 | 2013-05-21 19:38:02 +0530 | [diff] [blame] | 41 | pinctrl-single,function-mask = <0xf>; |
Kumar, Anil | 1faaba3 | 2013-01-16 14:37:39 +0530 | [diff] [blame] | 42 | status = "disabled"; |
Kumar, Anil | 99b8800 | 2013-01-16 14:37:41 +0530 | [diff] [blame] | 43 | |
| 44 | nand_cs3_pins: pinmux_nand_pins { |
| 45 | pinctrl-single,bits = < |
| 46 | /* EMA_OE, EMA_WE */ |
| 47 | 0x1c 0x00110000 0x00ff0000 |
| 48 | /* EMA_CS[4],EMA_CS[3]*/ |
| 49 | 0x1c 0x00000110 0x00000ff0 |
| 50 | /* |
| 51 | * EMA_D[0], EMA_D[1], EMA_D[2], |
| 52 | * EMA_D[3], EMA_D[4], EMA_D[5], |
| 53 | * EMA_D[6], EMA_D[7] |
| 54 | */ |
| 55 | 0x24 0x11111111 0xffffffff |
| 56 | /* EMA_A[1], EMA_A[2] */ |
| 57 | 0x30 0x01100000 0x0ff00000 |
| 58 | >; |
| 59 | }; |
Vishwanathrao Badarkhe, Manish | 01729cc | 2013-02-06 15:06:22 +0530 | [diff] [blame] | 60 | i2c0_pins: pinmux_i2c0_pins { |
| 61 | pinctrl-single,bits = < |
| 62 | /* I2C0_SDA,I2C0_SCL */ |
| 63 | 0x10 0x00002200 0x0000ff00 |
| 64 | >; |
| 65 | }; |
Petr Kulhavy | 92d6464 | 2016-04-01 17:42:04 +0200 | [diff] [blame] | 66 | i2c1_pins: pinmux_i2c1_pins { |
| 67 | pinctrl-single,bits = < |
| 68 | /* I2C1_SDA, I2C1_SCL */ |
| 69 | 0x10 0x00440000 0x00ff0000 |
| 70 | >; |
| 71 | }; |
Manjunathappa, Prakash | 88df412 | 2013-03-28 18:42:01 +0530 | [diff] [blame] | 72 | mmc0_pins: pinmux_mmc_pins { |
| 73 | pinctrl-single,bits = < |
| 74 | /* MMCSD0_DAT[3] MMCSD0_DAT[2] |
| 75 | * MMCSD0_DAT[1] MMCSD0_DAT[0] |
| 76 | * MMCSD0_CMD MMCSD0_CLK |
| 77 | */ |
| 78 | 0x28 0x00222222 0x00ffffff |
| 79 | >; |
| 80 | }; |
Philip Avinash | 64fa59c | 2013-04-10 17:42:41 +0530 | [diff] [blame] | 81 | ehrpwm0a_pins: pinmux_ehrpwm0a_pins { |
| 82 | pinctrl-single,bits = < |
| 83 | /* EPWM0A */ |
| 84 | 0xc 0x00000002 0x0000000f |
| 85 | >; |
| 86 | }; |
| 87 | ehrpwm0b_pins: pinmux_ehrpwm0b_pins { |
| 88 | pinctrl-single,bits = < |
| 89 | /* EPWM0B */ |
| 90 | 0xc 0x00000020 0x000000f0 |
| 91 | >; |
| 92 | }; |
| 93 | ehrpwm1a_pins: pinmux_ehrpwm1a_pins { |
| 94 | pinctrl-single,bits = < |
| 95 | /* EPWM1A */ |
| 96 | 0x14 0x00000002 0x0000000f |
| 97 | >; |
| 98 | }; |
| 99 | ehrpwm1b_pins: pinmux_ehrpwm1b_pins { |
| 100 | pinctrl-single,bits = < |
| 101 | /* EPWM1B */ |
| 102 | 0x14 0x00000020 0x000000f0 |
| 103 | >; |
| 104 | }; |
| 105 | ecap0_pins: pinmux_ecap0_pins { |
| 106 | pinctrl-single,bits = < |
| 107 | /* ECAP0_APWM0 */ |
| 108 | 0x8 0x20000000 0xf0000000 |
| 109 | >; |
| 110 | }; |
| 111 | ecap1_pins: pinmux_ecap1_pins { |
| 112 | pinctrl-single,bits = < |
| 113 | /* ECAP1_APWM1 */ |
| 114 | 0x4 0x40000000 0xf0000000 |
| 115 | >; |
| 116 | }; |
| 117 | ecap2_pins: pinmux_ecap2_pins { |
| 118 | pinctrl-single,bits = < |
| 119 | /* ECAP2_APWM2 */ |
| 120 | 0x4 0x00000004 0x0000000f |
| 121 | >; |
| 122 | }; |
David Lechner | 4be4b28 | 2016-04-16 12:00:17 -0500 | [diff] [blame] | 123 | spi0_pins: pinmux_spi0_pins { |
| 124 | pinctrl-single,bits = < |
| 125 | /* SIMO, SOMI, CLK */ |
| 126 | 0xc 0x00001101 0x0000ff0f |
| 127 | >; |
| 128 | }; |
| 129 | spi0_cs0_pin: pinmux_spi0_cs0 { |
| 130 | pinctrl-single,bits = < |
| 131 | /* CS0 */ |
| 132 | 0x10 0x00000010 0x000000f0 |
| 133 | >; |
| 134 | }; |
| 135 | spi1_pins: pinmux_spi1_pins { |
Manjunathappa, Prakash | c6347e4 | 2013-04-03 19:39:08 +0530 | [diff] [blame] | 136 | pinctrl-single,bits = < |
| 137 | /* SIMO, SOMI, CLK */ |
| 138 | 0x14 0x00110100 0x00ff0f00 |
| 139 | >; |
| 140 | }; |
| 141 | spi1_cs0_pin: pinmux_spi1_cs0 { |
| 142 | pinctrl-single,bits = < |
| 143 | /* CS0 */ |
| 144 | 0x14 0x00000010 0x000000f0 |
| 145 | >; |
| 146 | }; |
Lad, Prabhakar | 609f4bc | 2013-08-15 11:31:34 +0530 | [diff] [blame] | 147 | mdio_pins: pinmux_mdio_pins { |
| 148 | pinctrl-single,bits = < |
| 149 | /* MDIO_CLK, MDIO_D */ |
| 150 | 0x10 0x00000088 0x000000ff |
| 151 | >; |
| 152 | }; |
Lad, Prabhakar | dd7deaf | 2013-08-16 22:37:09 +0530 | [diff] [blame] | 153 | mii_pins: pinmux_mii_pins { |
| 154 | pinctrl-single,bits = < |
| 155 | /* |
| 156 | * MII_TXEN, MII_TXCLK, MII_COL |
| 157 | * MII_TXD_3, MII_TXD_2, MII_TXD_1 |
| 158 | * MII_TXD_0 |
| 159 | */ |
| 160 | 0x8 0x88888880 0xfffffff0 |
| 161 | /* |
| 162 | * MII_RXER, MII_CRS, MII_RXCLK |
| 163 | * MII_RXDV, MII_RXD_3, MII_RXD_2 |
| 164 | * MII_RXD_1, MII_RXD_0 |
| 165 | */ |
| 166 | 0xc 0x88888888 0xffffffff |
| 167 | >; |
| 168 | }; |
Lad, Prabhakar | 609f4bc | 2013-08-15 11:31:34 +0530 | [diff] [blame] | 169 | |
Kumar, Anil | 1faaba3 | 2013-01-16 14:37:39 +0530 | [diff] [blame] | 170 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 171 | edma0: edma@0 { |
Peter Ujfalusi | 7a7faed | 2015-12-17 15:27:48 +0200 | [diff] [blame] | 172 | compatible = "ti,edma3-tpcc"; |
Peter Ujfalusi | dfaebb5 | 2015-12-17 15:27:47 +0200 | [diff] [blame] | 173 | /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ |
| 174 | reg = <0x0 0x8000>; |
Peter Ujfalusi | 7a7faed | 2015-12-17 15:27:48 +0200 | [diff] [blame] | 175 | reg-names = "edma3_cc"; |
| 176 | interrupts = <11 12>; |
| 177 | interrupt-names = "edma3_ccint", "edma3_ccerrint"; |
| 178 | #dma-cells = <2>; |
| 179 | |
| 180 | ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; |
| 181 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 182 | edma0_tptc0: tptc@8000 { |
Peter Ujfalusi | 7a7faed | 2015-12-17 15:27:48 +0200 | [diff] [blame] | 183 | compatible = "ti,edma3-tptc"; |
| 184 | reg = <0x8000 0x400>; |
| 185 | interrupts = <13>; |
| 186 | interrupt-names = "edm3_tcerrint"; |
| 187 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 188 | edma0_tptc1: tptc@8400 { |
Peter Ujfalusi | 7a7faed | 2015-12-17 15:27:48 +0200 | [diff] [blame] | 189 | compatible = "ti,edma3-tptc"; |
| 190 | reg = <0x8400 0x400>; |
| 191 | interrupts = <32>; |
| 192 | interrupt-names = "edm3_tcerrint"; |
Peter Ujfalusi | ee766e4 | 2014-08-01 09:13:26 +0300 | [diff] [blame] | 193 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 194 | edma1: edma@230000 { |
Peter Ujfalusi | b47a856 | 2015-12-17 15:27:49 +0200 | [diff] [blame] | 195 | compatible = "ti,edma3-tpcc"; |
| 196 | /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ |
| 197 | reg = <0x230000 0x8000>; |
| 198 | reg-names = "edma3_cc"; |
| 199 | interrupts = <93 94>; |
| 200 | interrupt-names = "edma3_ccint", "edma3_ccerrint"; |
| 201 | #dma-cells = <2>; |
| 202 | |
| 203 | ti,tptcs = <&edma1_tptc0 7>; |
| 204 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 205 | edma1_tptc0: tptc@238000 { |
Peter Ujfalusi | b47a856 | 2015-12-17 15:27:49 +0200 | [diff] [blame] | 206 | compatible = "ti,edma3-tptc"; |
| 207 | reg = <0x238000 0x400>; |
| 208 | interrupts = <95>; |
| 209 | interrupt-names = "edm3_tcerrint"; |
| 210 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 211 | serial0: serial@42000 { |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 212 | compatible = "ns16550a"; |
| 213 | reg = <0x42000 0x100>; |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 214 | reg-shift = <2>; |
| 215 | interrupts = <25>; |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 216 | status = "disabled"; |
| 217 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 218 | serial1: serial@10c000 { |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 219 | compatible = "ns16550a"; |
| 220 | reg = <0x10c000 0x100>; |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 221 | reg-shift = <2>; |
| 222 | interrupts = <53>; |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 223 | status = "disabled"; |
| 224 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 225 | serial2: serial@10d000 { |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 226 | compatible = "ns16550a"; |
| 227 | reg = <0x10d000 0x100>; |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 228 | reg-shift = <2>; |
| 229 | interrupts = <61>; |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 230 | status = "disabled"; |
| 231 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 232 | rtc0: rtc@23000 { |
Mrugesh Katepallewar | 1661636 | 2013-01-28 13:17:48 +0530 | [diff] [blame] | 233 | compatible = "ti,da830-rtc"; |
| 234 | reg = <0x23000 0x1000>; |
| 235 | interrupts = <19 |
| 236 | 19>; |
| 237 | status = "disabled"; |
| 238 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 239 | i2c0: i2c@22000 { |
Vishwanathrao Badarkhe, Manish | 01729cc | 2013-02-06 15:06:22 +0530 | [diff] [blame] | 240 | compatible = "ti,davinci-i2c"; |
| 241 | reg = <0x22000 0x1000>; |
| 242 | interrupts = <15>; |
| 243 | #address-cells = <1>; |
| 244 | #size-cells = <0>; |
| 245 | status = "disabled"; |
| 246 | }; |
Petr Kulhavy | 92d6464 | 2016-04-01 17:42:04 +0200 | [diff] [blame] | 247 | i2c1: i2c@228000 { |
| 248 | compatible = "ti,davinci-i2c"; |
| 249 | reg = <0x228000 0x1000>; |
| 250 | interrupts = <51>; |
| 251 | #address-cells = <1>; |
| 252 | #size-cells = <0>; |
| 253 | status = "disabled"; |
| 254 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 255 | wdt: wdt@21000 { |
Kumar, Anil | 518f97d | 2013-02-06 09:30:03 +0530 | [diff] [blame] | 256 | compatible = "ti,davinci-wdt"; |
| 257 | reg = <0x21000 0x1000>; |
| 258 | status = "disabled"; |
| 259 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 260 | mmc0: mmc@40000 { |
Manjunathappa, Prakash | 88df412 | 2013-03-28 18:42:01 +0530 | [diff] [blame] | 261 | compatible = "ti,da830-mmc"; |
| 262 | reg = <0x40000 0x1000>; |
| 263 | interrupts = <16>; |
Peter Ujfalusi | 684892a | 2015-12-17 15:27:50 +0200 | [diff] [blame] | 264 | dmas = <&edma0 16 0>, <&edma0 17 0>; |
| 265 | dma-names = "rx", "tx"; |
Manjunathappa, Prakash | 88df412 | 2013-03-28 18:42:01 +0530 | [diff] [blame] | 266 | status = "disabled"; |
| 267 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 268 | mmc1: mmc@21b000 { |
Peter Ujfalusi | 3c49758 | 2015-12-17 15:27:51 +0200 | [diff] [blame] | 269 | compatible = "ti,da830-mmc"; |
| 270 | reg = <0x21b000 0x1000>; |
| 271 | interrupts = <72>; |
| 272 | dmas = <&edma1 28 0>, <&edma1 29 0>; |
| 273 | dma-names = "rx", "tx"; |
| 274 | status = "disabled"; |
| 275 | }; |
Arnd Bergmann | 1ea7c8b | 2016-04-24 23:43:56 +0200 | [diff] [blame] | 276 | ehrpwm0: pwm@300000 { |
Philip Avinash | 64fa59c | 2013-04-10 17:42:41 +0530 | [diff] [blame] | 277 | compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; |
| 278 | #pwm-cells = <3>; |
| 279 | reg = <0x300000 0x2000>; |
| 280 | status = "disabled"; |
| 281 | }; |
Arnd Bergmann | 1ea7c8b | 2016-04-24 23:43:56 +0200 | [diff] [blame] | 282 | ehrpwm1: pwm@302000 { |
Philip Avinash | 64fa59c | 2013-04-10 17:42:41 +0530 | [diff] [blame] | 283 | compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; |
| 284 | #pwm-cells = <3>; |
| 285 | reg = <0x302000 0x2000>; |
| 286 | status = "disabled"; |
| 287 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 288 | ecap0: ecap@306000 { |
Philip Avinash | 64fa59c | 2013-04-10 17:42:41 +0530 | [diff] [blame] | 289 | compatible = "ti,da850-ecap", "ti,am33xx-ecap"; |
| 290 | #pwm-cells = <3>; |
| 291 | reg = <0x306000 0x80>; |
| 292 | status = "disabled"; |
| 293 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 294 | ecap1: ecap@307000 { |
Philip Avinash | 64fa59c | 2013-04-10 17:42:41 +0530 | [diff] [blame] | 295 | compatible = "ti,da850-ecap", "ti,am33xx-ecap"; |
| 296 | #pwm-cells = <3>; |
| 297 | reg = <0x307000 0x80>; |
| 298 | status = "disabled"; |
| 299 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 300 | ecap2: ecap@308000 { |
Philip Avinash | 64fa59c | 2013-04-10 17:42:41 +0530 | [diff] [blame] | 301 | compatible = "ti,da850-ecap", "ti,am33xx-ecap"; |
| 302 | #pwm-cells = <3>; |
| 303 | reg = <0x308000 0x80>; |
| 304 | status = "disabled"; |
| 305 | }; |
David Lechner | 4be4b28 | 2016-04-16 12:00:17 -0500 | [diff] [blame] | 306 | spi0: spi@41000 { |
| 307 | #address-cells = <1>; |
| 308 | #size-cells = <0>; |
| 309 | compatible = "ti,da830-spi"; |
| 310 | reg = <0x41000 0x1000>; |
| 311 | num-cs = <6>; |
| 312 | ti,davinci-spi-intr-line = <1>; |
| 313 | interrupts = <20>; |
| 314 | status = "disabled"; |
| 315 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 316 | spi1: spi@30e000 { |
Manjunathappa, Prakash | c6347e4 | 2013-04-03 19:39:08 +0530 | [diff] [blame] | 317 | #address-cells = <1>; |
| 318 | #size-cells = <0>; |
| 319 | compatible = "ti,da830-spi"; |
| 320 | reg = <0x30e000 0x1000>; |
| 321 | num-cs = <4>; |
| 322 | ti,davinci-spi-intr-line = <1>; |
| 323 | interrupts = <56>; |
Peter Ujfalusi | f0ad435 | 2015-12-17 15:27:52 +0200 | [diff] [blame] | 324 | dmas = <&edma0 18 0>, <&edma0 19 0>; |
| 325 | dma-names = "rx", "tx"; |
Manjunathappa, Prakash | c6347e4 | 2013-04-03 19:39:08 +0530 | [diff] [blame] | 326 | status = "disabled"; |
| 327 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 328 | mdio: mdio@224000 { |
Lad, Prabhakar | 609f4bc | 2013-08-15 11:31:34 +0530 | [diff] [blame] | 329 | compatible = "ti,davinci_mdio"; |
| 330 | #address-cells = <1>; |
| 331 | #size-cells = <0>; |
| 332 | reg = <0x224000 0x1000>; |
David Lechner | 5209a8f | 2016-04-16 12:00:19 -0500 | [diff] [blame] | 333 | status = "disabled"; |
Lad, Prabhakar | 609f4bc | 2013-08-15 11:31:34 +0530 | [diff] [blame] | 334 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 335 | eth0: ethernet@220000 { |
Lad, Prabhakar | dd7deaf | 2013-08-16 22:37:09 +0530 | [diff] [blame] | 336 | compatible = "ti,davinci-dm6467-emac"; |
| 337 | reg = <0x220000 0x4000>; |
| 338 | ti,davinci-ctrl-reg-offset = <0x3000>; |
| 339 | ti,davinci-ctrl-mod-reg-offset = <0x2000>; |
| 340 | ti,davinci-ctrl-ram-offset = <0>; |
| 341 | ti,davinci-ctrl-ram-size = <0x2000>; |
| 342 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 343 | interrupts = <33 |
| 344 | 34 |
| 345 | 35 |
| 346 | 36 |
| 347 | >; |
David Lechner | 5209a8f | 2016-04-16 12:00:19 -0500 | [diff] [blame] | 348 | status = "disabled"; |
Lad, Prabhakar | dd7deaf | 2013-08-16 22:37:09 +0530 | [diff] [blame] | 349 | }; |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 350 | gpio: gpio@226000 { |
KV Sujith | 2e38b94 | 2013-11-21 23:45:30 +0530 | [diff] [blame] | 351 | compatible = "ti,dm6441-gpio"; |
| 352 | gpio-controller; |
Petr Kulhavy | 497762b | 2016-04-05 11:31:37 +0200 | [diff] [blame] | 353 | #gpio-cells = <2>; |
KV Sujith | 2e38b94 | 2013-11-21 23:45:30 +0530 | [diff] [blame] | 354 | reg = <0x226000 0x1000>; |
| 355 | interrupts = <42 IRQ_TYPE_EDGE_BOTH |
| 356 | 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH |
| 357 | 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH |
| 358 | 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH |
| 359 | 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>; |
| 360 | ti,ngpio = <144>; |
| 361 | ti,davinci-gpio-unbanked = <0>; |
| 362 | status = "disabled"; |
| 363 | }; |
Peter Ujfalusi | db74904 | 2014-08-01 09:13:27 +0300 | [diff] [blame] | 364 | |
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 365 | mcasp0: mcasp@100000 { |
Peter Ujfalusi | db74904 | 2014-08-01 09:13:27 +0300 | [diff] [blame] | 366 | compatible = "ti,da830-mcasp-audio"; |
| 367 | reg = <0x100000 0x2000>, |
| 368 | <0x102000 0x400000>; |
| 369 | reg-names = "mpu", "dat"; |
| 370 | interrupts = <54>; |
| 371 | interrupt-names = "common"; |
| 372 | status = "disabled"; |
Peter Ujfalusi | 7a7faed | 2015-12-17 15:27:48 +0200 | [diff] [blame] | 373 | dmas = <&edma0 1 1>, |
| 374 | <&edma0 0 1>; |
Peter Ujfalusi | db74904 | 2014-08-01 09:13:27 +0300 | [diff] [blame] | 375 | dma-names = "tx", "rx"; |
| 376 | }; |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 377 | }; |
Kumar, Anil | 99b8800 | 2013-01-16 14:37:41 +0530 | [diff] [blame] | 378 | nand_cs3@62000000 { |
| 379 | compatible = "ti,davinci-nand"; |
| 380 | reg = <0x62000000 0x807ff |
| 381 | 0x68000000 0x8000>; |
| 382 | ti,davinci-chipselect = <1>; |
| 383 | ti,davinci-mask-ale = <0>; |
| 384 | ti,davinci-mask-cle = <0>; |
| 385 | ti,davinci-mask-chipsel = <0>; |
| 386 | ti,davinci-ecc-mode = "hw"; |
| 387 | ti,davinci-ecc-bits = <4>; |
| 388 | ti,davinci-nand-use-bbt; |
| 389 | status = "disabled"; |
| 390 | }; |
Heiko Schocher | 33085b3 | 2012-08-30 14:21:04 +0530 | [diff] [blame] | 391 | }; |