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Tomasz Figa0f7238a2012-11-06 15:09:04 +09001/*
2 * Samsung's Exynos4412 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
Padmavathi Venna37992792013-06-18 00:02:08 +090020#include "exynos4x12.dtsi"
Tomasz Figa0f7238a2012-11-06 15:09:04 +090021
22/ {
Sachin Kamat8bdb31b2014-03-21 02:17:22 +090023 compatible = "samsung,exynos4412", "samsung,exynos4";
Tomasz Figa0f7238a2012-11-06 15:09:04 +090024
Bartlomiej Zolnierkiewicze5409202014-09-25 17:40:14 +090025 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
Lukasz Majewskibf4a0be2015-01-30 08:26:02 +090029 cpu0: cpu@A00 {
Bartlomiej Zolnierkiewicze5409202014-09-25 17:40:14 +090030 device_type = "cpu";
31 compatible = "arm,cortex-a9";
32 reg = <0xA00>;
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +090033 clocks = <&clock CLK_ARM_CLK>;
34 clock-names = "cpu";
35 operating-points-v2 = <&cpu0_opp_table>;
Lukasz Majewskibf4a0be2015-01-30 08:26:02 +090036 cooling-min-level = <13>;
37 cooling-max-level = <7>;
38 #cooling-cells = <2>; /* min followed by max */
Bartlomiej Zolnierkiewicze5409202014-09-25 17:40:14 +090039 };
40
41 cpu@A01 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a9";
44 reg = <0xA01>;
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +090045 operating-points-v2 = <&cpu0_opp_table>;
Bartlomiej Zolnierkiewicze5409202014-09-25 17:40:14 +090046 };
47
48 cpu@A02 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a9";
51 reg = <0xA02>;
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +090052 operating-points-v2 = <&cpu0_opp_table>;
Bartlomiej Zolnierkiewicze5409202014-09-25 17:40:14 +090053 };
54
55 cpu@A03 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a9";
58 reg = <0xA03>;
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +090059 operating-points-v2 = <&cpu0_opp_table>;
60 };
61 };
62
63 cpu0_opp_table: opp_table0 {
64 compatible = "operating-points-v2";
65 opp-shared;
66
Viresh Kumar2aae9912015-11-11 08:10:58 +053067 opp@200000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +090068 opp-hz = /bits/ 64 <200000000>;
69 opp-microvolt = <900000>;
70 clock-latency-ns = <200000>;
71 };
Viresh Kumar2aae9912015-11-11 08:10:58 +053072 opp@300000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +090073 opp-hz = /bits/ 64 <300000000>;
74 opp-microvolt = <900000>;
75 clock-latency-ns = <200000>;
76 };
Viresh Kumar2aae9912015-11-11 08:10:58 +053077 opp@400000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +090078 opp-hz = /bits/ 64 <400000000>;
79 opp-microvolt = <925000>;
80 clock-latency-ns = <200000>;
81 };
Viresh Kumar2aae9912015-11-11 08:10:58 +053082 opp@500000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +090083 opp-hz = /bits/ 64 <500000000>;
84 opp-microvolt = <950000>;
85 clock-latency-ns = <200000>;
86 };
Viresh Kumar2aae9912015-11-11 08:10:58 +053087 opp@600000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +090088 opp-hz = /bits/ 64 <600000000>;
89 opp-microvolt = <975000>;
90 clock-latency-ns = <200000>;
91 };
Viresh Kumar2aae9912015-11-11 08:10:58 +053092 opp@700000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +090093 opp-hz = /bits/ 64 <700000000>;
94 opp-microvolt = <987500>;
95 clock-latency-ns = <200000>;
96 };
Viresh Kumar2aae9912015-11-11 08:10:58 +053097 opp@800000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +090098 opp-hz = /bits/ 64 <800000000>;
99 opp-microvolt = <1000000>;
100 clock-latency-ns = <200000>;
Bartlomiej Zolnierkiewicz1605b602015-09-17 07:46:28 +0900101 opp-suspend;
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +0900102 };
Viresh Kumar2aae9912015-11-11 08:10:58 +0530103 opp@900000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +0900104 opp-hz = /bits/ 64 <900000000>;
105 opp-microvolt = <1037500>;
106 clock-latency-ns = <200000>;
107 };
Viresh Kumar2aae9912015-11-11 08:10:58 +0530108 opp@1000000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +0900109 opp-hz = /bits/ 64 <1000000000>;
110 opp-microvolt = <1087500>;
111 clock-latency-ns = <200000>;
112 };
Viresh Kumar2aae9912015-11-11 08:10:58 +0530113 opp@1100000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +0900114 opp-hz = /bits/ 64 <1100000000>;
115 opp-microvolt = <1137500>;
116 clock-latency-ns = <200000>;
117 };
Viresh Kumar2aae9912015-11-11 08:10:58 +0530118 opp@1200000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +0900119 opp-hz = /bits/ 64 <1200000000>;
120 opp-microvolt = <1187500>;
121 clock-latency-ns = <200000>;
122 };
Viresh Kumar2aae9912015-11-11 08:10:58 +0530123 opp@1300000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +0900124 opp-hz = /bits/ 64 <1300000000>;
125 opp-microvolt = <1250000>;
126 clock-latency-ns = <200000>;
127 };
Viresh Kumar2aae9912015-11-11 08:10:58 +0530128 opp@1400000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +0900129 opp-hz = /bits/ 64 <1400000000>;
130 opp-microvolt = <1287500>;
131 clock-latency-ns = <200000>;
132 };
Viresh Kumar2aae9912015-11-11 08:10:58 +0530133 opp@1500000000 {
Bartlomiej Zolnierkiewiczf4499742015-08-12 07:38:45 +0900134 opp-hz = /bits/ 64 <1500000000>;
135 opp-microvolt = <1350000>;
136 clock-latency-ns = <200000>;
137 turbo-mode;
Bartlomiej Zolnierkiewicze5409202014-09-25 17:40:14 +0900138 };
139 };
140
Chanho Park6f4b82a2014-07-19 03:11:48 +0900141 pmu {
142 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
143 };
Krzysztof Kozlowski08c4b442015-04-06 21:06:21 +0200144};
Chanho Park6f4b82a2014-07-19 03:11:48 +0900145
Krzysztof Kozlowski08c4b442015-04-06 21:06:21 +0200146&pmu_system_controller {
147 compatible = "samsung,exynos4412-pmu", "syscon";
148};
Chanho Park7b9613a2014-05-23 03:30:20 +0900149
Krzysztof Kozlowski08c4b442015-04-06 21:06:21 +0200150&combiner {
151 samsung,combiner-nr = <20>;
152};
153
154&gic {
155 cpu-offset = <0x4000>;
Tomasz Figa0f7238a2012-11-06 15:09:04 +0900156};