blob: 9bb628f22502972c566744788614e9e34424e431 [file] [log] [blame]
Fabio Estevamebc37462014-03-25 14:47:41 -03001/*
2 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14#include "imx35.dtsi"
15
16/ {
17 model = "Freescale i.MX35 Product Development Kit";
18 compatible = "fsl,imx35-pdk", "fsl,imx35";
19
20 memory {
Fabio Estevamc6f0b872014-05-12 22:04:24 -030021 reg = <0x80000000 0x8000000>,
22 <0x90000000 0x8000000>;
Fabio Estevamebc37462014-03-25 14:47:41 -030023 };
24};
25
26&esdhc1 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_esdhc1>;
29 status = "okay";
30};
31
32&iomuxc {
33 imx35-pdk {
34 pinctrl_esdhc1: esdhc1grp {
35 fsl,pins = <
36 MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
37 MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
38 MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
39 MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
40 MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
41 MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
42 >;
43 };
44
45 pinctrl_uart1: uart1grp {
46 fsl,pins = <
47 MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
48 MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
49 MX35_PAD_CTS1__UART1_CTS 0x1c5
50 MX35_PAD_RTS1__UART1_RTS 0x1c5
51 >;
52 };
53 };
54};
55
56&nfc {
57 nand-bus-width = <16>;
58 nand-ecc-mode = "hw";
59 nand-on-flash-bbt;
60 status = "okay";
61};
62
63&uart1 {
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_uart1>;
Geert Uytterhoeven2e7c4162016-05-31 16:31:51 +020066 uart-has-rtscts;
Fabio Estevamebc37462014-03-25 14:47:41 -030067 status = "okay";
68};