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Josh Coombs5136b2a2012-07-16 11:52:50 +02001/dts-v1/;
2
Ezequiel Garcia0ab61292013-07-26 10:18:02 -03003#include "kirkwood.dtsi"
4#include "kirkwood-6281.dtsi"
Josh Coombs5136b2a2012-07-16 11:52:50 +02005
6/ {
7 model = "Seagate GoFlex Net";
Andrew Lunnf39c1102012-07-18 19:22:54 +02008 compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood";
Josh Coombs5136b2a2012-07-16 11:52:50 +02009
10 memory {
11 device_type = "memory";
12 reg = <0x00000000 0x8000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
Sebastian Hesselbarthab833612014-04-30 14:56:30 +020017 stdout-path = &uart0;
Josh Coombs5136b2a2012-07-16 11:52:50 +020018 };
19
20 ocp@f1000000 {
Sebastian Hesselbartha9483962014-04-30 14:56:32 +020021 pinctrl: pin-controller@10000 {
Andrew Lunn5d183ef2012-11-17 17:00:51 +010022 pmx_usb_power_enable: pmx-usb-power-enable {
23 marvell,pins = "mpp29";
24 marvell,function = "gpio";
25 };
26 pmx_led_right_cap_0: pmx-led_right_cap_0 {
27 marvell,pins = "mpp38";
28 marvell,function = "gpio";
29 };
30 pmx_led_right_cap_1: pmx-led_right_cap_1 {
31 marvell,pins = "mpp39";
32 marvell,function = "gpio";
33 };
34 pmx_led_right_cap_2: pmx-led_right_cap_2 {
35 marvell,pins = "mpp40";
36 marvell,function = "gpio";
37 };
38 pmx_led_right_cap_3: pmx-led_right_cap_3 {
39 marvell,pins = "mpp41";
40 marvell,function = "gpio";
41 };
42 pmx_led_left_cap_0: pmx-led_left_cap_0 {
43 marvell,pins = "mpp42";
44 marvell,function = "gpio";
45 };
46 pmx_led_left_cap_1: pmx-led_left_cap_1 {
47 marvell,pins = "mpp43";
48 marvell,function = "gpio";
49 };
50 pmx_led_left_cap_2: pmx-led_left_cap_2 {
51 marvell,pins = "mpp44";
52 marvell,function = "gpio";
53 };
54 pmx_led_left_cap_3: pmx-led_left_cap_3 {
55 marvell,pins = "mpp45";
56 marvell,function = "gpio";
57 };
58 pmx_led_green: pmx-led_green {
59 marvell,pins = "mpp46";
60 marvell,function = "gpio";
61 };
62 pmx_led_orange: pmx-led_orange {
63 marvell,pins = "mpp47";
64 marvell,function = "gpio";
65 };
66 };
Josh Coombs5136b2a2012-07-16 11:52:50 +020067 serial@12000 {
Josh Coombs5136b2a2012-07-16 11:52:50 +020068 status = "ok";
69 };
70
Andrew Lunnf3af1c72012-07-17 08:05:27 +020071 sata@80000 {
72 status = "okay";
73 nr-ports = <2>;
74 };
75
76 };
77 gpio-leds {
78 compatible = "gpio-leds";
Thomas Petazzoni7cfbb282013-05-24 11:44:42 +020079 pinctrl-0 = < &pmx_led_orange
80 &pmx_led_left_cap_0 &pmx_led_left_cap_1
81 &pmx_led_left_cap_2 &pmx_led_left_cap_3
82 &pmx_led_right_cap_0 &pmx_led_right_cap_1
83 &pmx_led_right_cap_2 &pmx_led_right_cap_3
84 >;
85 pinctrl-names = "default";
Andrew Lunnf3af1c72012-07-17 08:05:27 +020086
87 health {
88 label = "status:green:health";
Andrew Lunn3a31f2d72013-12-04 16:51:39 +010089 gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
Jason Cooperdcdf14c2013-10-14 17:37:55 +000090 default-state = "keep";
Andrew Lunnf3af1c72012-07-17 08:05:27 +020091 };
92 fault {
93 label = "status:orange:fault";
Andrew Lunn3a31f2d72013-12-04 16:51:39 +010094 gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
Andrew Lunnf3af1c72012-07-17 08:05:27 +020095 };
96 left0 {
97 label = "status:white:left0";
Andrew Lunn3a31f2d72013-12-04 16:51:39 +010098 gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
Andrew Lunnf3af1c72012-07-17 08:05:27 +020099 };
100 left1 {
101 label = "status:white:left1";
Andrew Lunn3a31f2d72013-12-04 16:51:39 +0100102 gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
Andrew Lunnf3af1c72012-07-17 08:05:27 +0200103 };
104 left2 {
105 label = "status:white:left2";
Andrew Lunn3a31f2d72013-12-04 16:51:39 +0100106 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
Andrew Lunnf3af1c72012-07-17 08:05:27 +0200107 };
108 left3 {
109 label = "status:white:left3";
Andrew Lunn3a31f2d72013-12-04 16:51:39 +0100110 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
Andrew Lunnf3af1c72012-07-17 08:05:27 +0200111 };
112 right0 {
113 label = "status:white:right0";
Andrew Lunn3a31f2d72013-12-04 16:51:39 +0100114 gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
Andrew Lunnf3af1c72012-07-17 08:05:27 +0200115 };
116 right1 {
117 label = "status:white:right1";
Andrew Lunn3a31f2d72013-12-04 16:51:39 +0100118 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
Andrew Lunnf3af1c72012-07-17 08:05:27 +0200119 };
120 right2 {
121 label = "status:white:right2";
Andrew Lunn3a31f2d72013-12-04 16:51:39 +0100122 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
Andrew Lunnf3af1c72012-07-17 08:05:27 +0200123 };
124 right3 {
125 label = "status:white:right3";
Andrew Lunn3a31f2d72013-12-04 16:51:39 +0100126 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
Andrew Lunnf3af1c72012-07-17 08:05:27 +0200127 };
Josh Coombs5136b2a2012-07-16 11:52:50 +0200128 };
Andrew Lunn280b3482012-11-17 15:46:13 +0100129 regulators {
130 compatible = "simple-bus";
131 #address-cells = <1>;
132 #size-cells = <0>;
Thomas Petazzoni7cfbb282013-05-24 11:44:42 +0200133 pinctrl-0 = <&pmx_usb_power_enable>;
134 pinctrl-names = "default";
Andrew Lunn280b3482012-11-17 15:46:13 +0100135
136 usb_power: regulator@1 {
137 compatible = "regulator-fixed";
138 reg = <1>;
139 regulator-name = "USB Power";
140 regulator-min-microvolt = <5000000>;
141 regulator-max-microvolt = <5000000>;
142 enable-active-high;
143 regulator-always-on;
144 regulator-boot-on;
Andrew Lunn3a31f2d72013-12-04 16:51:39 +0100145 gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
Andrew Lunn280b3482012-11-17 15:46:13 +0100146 };
147 };
Josh Coombs5136b2a2012-07-16 11:52:50 +0200148};
Sebastian Hesselbarth876e2332013-07-07 22:34:56 +0200149
Jason Gunthorpe7045ff52013-09-17 12:44:33 -0600150&nand {
151 chip-delay = <40>;
152 status = "okay";
153
154 partition@0 {
155 label = "u-boot";
156 reg = <0x0000000 0x100000>;
157 read-only;
158 };
159
160 partition@100000 {
161 label = "uImage";
162 reg = <0x0100000 0x400000>;
163 };
164
165 partition@500000 {
166 label = "pogoplug";
167 reg = <0x0500000 0x2000000>;
168 };
169
170 partition@2500000 {
171 label = "root";
172 reg = <0x02500000 0xd800000>;
173 };
174};
175
Sebastian Hesselbarth876e2332013-07-07 22:34:56 +0200176&mdio {
177 status = "okay";
178
179 ethphy0: ethernet-phy@0 {
Sebastian Hesselbarth876e2332013-07-07 22:34:56 +0200180 reg = <0>;
181 };
182};
183
184&eth0 {
185 status = "okay";
186 ethernet0-port@0 {
187 phy-handle = <&ethphy0>;
188 };
189};